Hi,
I wasn't able to get support from other channels, so apologies for asking here.
I wanted to know whether if I need to change any configurations at the UEFI layer for Jetson Orin AGX SoC to be able to use the "off-chip aperture" address region on the SoC to interact with an external device. This isn't documented well in the Orin TRM, nor on the Nvidia forums.
I did see PCIe C5 controller related definitions here, so I was wondering where in the stack the BOM/TOM registers for SCF/MCF need to be configured.
This forum post linked below shows me successfully getting a PCIe device to enumerate when I map it's BAR1 request to a large prefetchable memory region in this "off-chip aperture" address space, but trying to write to that address results in a RAS error, SERR = Illegal address at address 0x5000fef000
Link with more details at the end of the post: https://forums.developer.nvidia.com/t/increase-bar-size-for-pcie-c5-x8-root-port-controller/356933
Hi,
I wasn't able to get support from other channels, so apologies for asking here.
I wanted to know whether if I need to change any configurations at the UEFI layer for Jetson Orin AGX SoC to be able to use the "off-chip aperture" address region on the SoC to interact with an external device. This isn't documented well in the Orin TRM, nor on the Nvidia forums.
I did see PCIe C5 controller related definitions here, so I was wondering where in the stack the BOM/TOM registers for SCF/MCF need to be configured.
This forum post linked below shows me successfully getting a PCIe device to enumerate when I map it's BAR1 request to a large prefetchable memory region in this "off-chip aperture" address space, but trying to write to that address results in a
RAS error, SERR = Illegal address at address 0x5000fef000Link with more details at the end of the post: https://forums.developer.nvidia.com/t/increase-bar-size-for-pcie-c5-x8-root-port-controller/356933