PMIC todos

[akku1139]

#19

• pwrap
• pinctrl (untested)
• pinfunc header
• regulator (ai written)
• rtc
• keys (untested)
• battery (auxadc?)
• interrupts (untested)
• audio codecs
• auxadc (mt6572-mainline)
• clocks (untested, based on chromiumos mt6397)
• led
• power-controller
• efuse (mt6572-mainline)
• thermal (mt6572-mainline)

[akku1139]

clock is required to audio works

[akku1139]

• start-year for RTC, sync with twrp

[akku1139]

clock

https://github.com/mtk09422/chromiumos-third_party-kernel-mediatek/blob/mtk-dev-3.16/drivers/clk/clk-mt6397.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Author: Akari Tsuyukusa <akkun11.open@gmail.com>
 */

#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>

#include "clk-mtk.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mediatek,mt6320-clk.h>
#include <linux/mfd/mt6320/registers.h>

static const struct mtk_gate_regs top_ckpdn_regs = {
	.sta_ofs = MT6320_TOP_CKPDN,
};

static const struct mtk_gate_regs top_ckpdn2_regs = {
	.sta_ofs = MT6320_TOP_CKPDN2,
};

static const struct mtk_gate_regs top_gpio_ckpdn_regs = {
	.sta_ofs = MT6320_TOP_GPIO_CKPDN,
};

static const struct mtk_gate_regs wrp_ckpdn_regs = {
	.sta_ofs = MT6320_WRP_CKPDN,
};

#define GATE_TOP_CKPDN(_id, _name, _parent, _shift)				\
	GATE_MTK(_id, _name, _parent, &top_ckpdn_regs, _shift, &mtk_clk_gate_ops_no_setclr)

#define GATE_TOP_CKPDN2(_id, _name, _parent, _shift)				\
	GATE_MTK(_id, _name, _parent, &top_ckpdn2_regs, _shift, &mtk_clk_gate_ops_no_setclr)

#define GATE_TOP_GPIO_CKPDN(_id, _name, _parent, _shift)				\
	GATE_MTK(_id, _name, _parent, &top_gpio_ckpdn_regs, _shift, &mtk_clk_gate_ops_no_setclr)

#define GATE_WRP_CKPDN(_id, _name, _parent, _shift)				\
	GATE_MTK(_id, _name, _parent, &wrp_ckpdn_regs, _shift, &mtk_clk_gate_ops_no_setclr)

static const struct mtk_gate mt6320_gates[] = {
	GATE_TOP_CKPDN(MT6320_CLK_AUD_26M, "", "", 0),
	GATE_TOP_CKPDN(MT6320_CLK_AUD_13M, "", "", 1),
	GATE_TOP_CKPDN(MT6320_CLK_SPK_CK, "", "", 2),
	GATE_TOP_CKPDN(MT6320_CLK_PWMOC_CK, "", "", 3),
	GATE_TOP_CKPDN(MT6320_CLK_EFUSE_CK, "", "", 4),
	GATE_TOP_CKPDN(MT6320_CLK_FGADC_CK, "", "", 5),
	GATE_TOP_CKPDN(MT6320_CLK_FGADC_ANA_CK, "", "", 6),
	GATE_TOP_CKPDN(MT6320_CLK_BST_DRV_1M_CK, "", "", 7),
	GATE_TOP_CKPDN(MT6320_CLK_RTC_MCLK, "", "", 8),
	GATE_TOP_CKPDN(MT6320_CLK_SPK_PWM_DIV, "", "", 9),
	GATE_TOP_CKPDN(MT6320_CLK_SPK_DIV, "", "", 10),
	GATE_TOP_CKPDN(MT6320_CLK_SMPS_CK_DIV2, "", "", 11),
	GATE_TOP_CKPDN(MT6320_CLK_SMPS_CK_DIV, "", "", 12),
	GATE_TOP_CKPDN(MT6320_CLK_AUXADC_CK, "", "", 13),
	GATE_TOP_CKPDN(MT6320_CLK_ACCDET_CK, "", "", 14),
	GATE_TOP_CKPDN(MT6320_CLK_STRUP_6M, "", "", 15),

	GATE_TOP_CKPDN2(MT6320_CLK_RTC32K_1V8, "", "", 0),
	GATE_TOP_CKPDN2(MT6320_CLK_FQMTR, "", "", 1),
	GATE_TOP_CKPDN2(MT6320_CLK_STRUP_75K_CK, "", "", 2),
	GATE_TOP_CKPDN2(MT6320_CLK_RTC_32K_CK, "", "", 3),
	GATE_TOP_CKPDN2(MT6320_CLK_PCHR_32K_CK, "", "", 4),
	GATE_TOP_CKPDN2(MT6320_CLK_LDOSTB_1M_CK, "", "", 5),
	GATE_TOP_CKPDN2(MT6320_CLK_INTRP_CK, "", "", 6),
	GATE_TOP_CKPDN2(MT6320_CLK_DRV_32K_CK, "", "", 7),
	GATE_TOP_CKPDN2(MT6320_CLK_CHR1M_CK, "", "", 8),
	GATE_TOP_CKPDN2(MT6320_CLK_BUCK_CK, "", "", 9),
	GATE_TOP_CKPDN2(MT6320_CLK_BUCK_ANA_CK, "", "", 10),
	GATE_TOP_CKPDN2(MT6320_CLK_BUCK32K, "", "", 11),
	GATE_TOP_CKPDN2(MT6320_CLK_BUCK_1M_CK, "", "", 12),
	GATE_TOP_CKPDN2(MT6320_CLK_STRUP_32K_CK, "", "", 13),
	GATE_TOP_CKPDN2(MT6320_CLK_RTC_75K_CK, "", "", 14),
	GATE_TOP_CKPDN2(MT6320_CLK_TOP_CKPDN2_RSV_15, "", "", 15),

	GATE_TOP_GPIO_CKPDN(MT6320_CLK_GPIO26M, "", "", 0), /* MUX? */
	GATE_TOP_GPIO_CKPDN(MT6320_CLK_GPIO32K, "", "", 7),
	GATE_TOP_GPIO_CKPDN(MT6320_CLK_TOP_GPIO_CKPDN_RSV_15_14, "", "", 14),

	GATE_WRP_CKPDN(MT6320_CLK_WRP_I2C0, "", "", 0),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_I2C1, "", "", 1),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_I2C2, "", "", 2),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_PWM, "", "", 3),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_KP, "", "", 4),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_EINT, "", "", 5),
	GATE_WRP_CKPDN(MT6320_CLK_WRP_32K, "", "", 6),
	GATE_WRP_CKPDN(MT6320_CLK_WRP, "", "", 7),
};

/*
TOP_CKCON1
TOP_CKCON2
TOP_CKTST1
TOP_CKTST2
 */

static const struct mtk_clk_desc mt6320_clk_desc = {
};

static const struct of_device_id of_match_mt6320_clk[] = {
	{ .compatible = "mediatek,mt6320-clk", .data = &mt6320_clk_desc },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_mt6320_clk);

static struct platform_driver mt6320_clk_drv = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,
	.driver = {
		.name = "mt6320-clk",
		.of_match_table = of_match_mt6320_clk,
	},
};
module_platform_driver(mt6320_clk_drv);

MODULE_DESCRIPTION("MediaTek MT6320 clock driver");
MODULE_LICENSE("GPL");

[akku1139]

• fix Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml

[akku1139]

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Flora Fu <flora.fu@mediatek.com>
 *
 * Author: Akari Tsuyukusa <akkun11.open@gmail.com>
 */

#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6320/registers.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/mediatek,mt6320-clk.h>

struct mt6320_clkpdn {
	struct clk_hw hw;
	struct regmap *regmap;
	u32 enable_reg;
	u32 enable_mask;
	u32 div_reg;
	u32 div_mask;
	u32 div_base;
	u32 div_factor;
	u32 mux_reg;
	u32 mux_mask;
};

#define to_mt6320_clkpdn(_hw) container_of(_hw, struct mt6320_clkpdn, hw)

static int mt6320_clkpdn_prepare(struct clk_hw *hw)
{
	struct mt6320_clkpdn *pdn = to_mt6320_clkpdn(hw);

	return regmap_update_bits(pdn->regmap, pdn->enable_reg,
		pdn->enable_mask, ~pdn->enable_mask);
}

static void mt6320_clkpdn_unprepare(struct clk_hw *hw)
{
	struct mt6320_clkpdn *pdn = to_mt6320_clkpdn(hw);

	regmap_update_bits(pdn->regmap, pdn->enable_reg,
		pdn->enable_mask, pdn->enable_mask);
}

static int mt6320_clkpdn_is_prepared(struct clk_hw *hw)
{
	struct mt6320_clkpdn *pdn = to_mt6320_clkpdn(hw);
	u32 val;

	regmap_read(pdn->regmap, pdn->enable_reg, &val);

	return (val & pdn->enable_mask) == 0;
}

static unsigned long mt6320_clk_recalc_rate(struct clk_hw *hw,
						  unsigned long parent_rate)
{
	struct mt6320_clkpdn *pdn = to_mt6320_clkpdn(hw);
	u32 div, val;

	if (pdn->div_reg == 0) {
		div = 1;
	} else {
		regmap_read(pdn->regmap, pdn->div_reg, &val);
		val &= pdn->div_mask;
		val >>= ffs(pdn->div_mask) - 1;

		if (val)
			div = (1 << val) * pdn->div_base * pdn->div_factor;
		else
			div = pdn->div_base;
	}

	return parent_rate / div;
}

static u8 mt6320_clk_get_parent(struct clk_hw *hw)
{
	struct mt6320_clkpdn *clk = to_mt6320_clkpdn(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	if (num_parents == 1)
		return 0;

	regmap_read(clk->regmap, clk->mux_reg, &val);
	val &= clk->mux_mask;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int mt6320_clk_set_parent(struct clk_hw *hw, u8 index)
{
	struct mt6320_clkpdn *clk = to_mt6320_clkpdn(hw);
	u32 idx;

	idx = index;
	idx <<= ffs(clk->mux_mask) - 1;

	return regmap_update_bits(clk->regmap, clk->mux_reg, clk->mux_mask,
			idx);
}

static const struct clk_ops mt6320_clkpdn_ops = {
	.prepare = mt6320_clkpdn_prepare,
	.unprepare = mt6320_clkpdn_unprepare,
	.is_prepared = mt6320_clkpdn_is_prepared,
};

static const struct clk_ops mt6320_clkcomposite_ops = {
	.prepare = mt6320_clkpdn_prepare,
	.unprepare = mt6320_clkpdn_unprepare,
	.is_prepared = mt6320_clkpdn_is_prepared,
	.recalc_rate = mt6320_clk_recalc_rate,
	.get_parent = mt6320_clk_get_parent,
	.set_parent = mt6320_clk_set_parent,
};

enum {
	AUD26M,	AUD26M_DIV64, AUD13M,
	SMPS24M, SMPS12M, SMPS6M, SMPS3M, SMPS2M, SMPS1M,
	PMU75K, PMU12M,
	FG32K,
	RTC32K,
	CHR1M,
};

static const char *clk_names[] = {
	[AUD26M] = "aud26m",
	[AUD26M_DIV64] = "aud26m_div64",
	[AUD13M] = "aud13m",
	[SMPS24M] = "smps24m",
	[SMPS12M] = "smps12m",
	[SMPS6M] = "smps6m",
	[SMPS3M] = "smps3m",
	[SMPS2M] = "smps2m",
	[SMPS1M] = "smps1m",
	[PMU75K] = "pmu75k",
	[PMU12M] = "pmu12m",
	[FG32K] = "fg32k",
	[RTC32K] = "rtc32k",
	[CHR1M] = "chr1m",
};

static const char *mt6320_accdet_parents[] = {
	"rtc32k",
	"pmu12m",
	"top-accdet",
	"aud26m",
};

static const char *mt6320_fgadc_ana_parents[] = {
	"rtc32k",
	"aud26m_div64",
};

static const char *mt6320_fgmtr_parents[] = {
	"rtc32k",
	"aud26m",
};

#define GATES(id, _name, _reg, _mask, _parent_names)	\
[id] = {						\
	.hw.init = &(struct clk_init_data){		\
		.name = #_name,				\
		.ops = &mt6320_clkpdn_ops,		\
		.flags = CLK_IGNORE_UNUSED,		\
		.parent_names = _parent_names,		\
		.num_parents = 1,			\
	},						\
	.enable_reg = _reg,				\
	.enable_mask = _mask,				\
}

#define COMPOSITE(id, _name, _reg, _mask, _parent_names, _num_parents,	\
	_div_reg, _div_mask, _base, _factor, _mux_reg, _mux_mask)	\
[id] = {								\
	.hw.init = &(struct clk_init_data){				\
		.name = #_name,						\
		.ops = &mt6320_clkcomposite_ops,			\
		.flags = CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE,	\
		.parent_names = _parent_names,				\
		.num_parents = _num_parents,				\
	},								\
	.enable_reg = _reg,						\
	.enable_mask = _mask,						\
	.div_reg = _div_reg,						\
	.div_mask = _div_mask,						\
	.div_base = _base,						\
	.div_factor = _factor,						\
	.mux_reg = _mux_reg,						\
	.mux_mask = _mux_mask,						\
}

static struct mt6320_clkpdn mt6320_clks[MT6320_CLK_MAX] = {
	GATES(MT6320_TOPCKPDN_AUD_26M, "top-aud26m",
		MT6320_TOP_CKPDN, BIT(0), &clk_names[AUD26M]),
	GATES(MT6320_TOPCKPDN_AUD_13M, "top-aud13m",
		MT6320_TOP_CKPDN, BIT(1), &clk_names[AUD13M]),
	GATES(MT6320_TOPCKPDN_SPK_CK, "top-spk",
		MT6320_TOP_CKPDN, BIT(2), &clk_names[SMPS1M]),
	GATES(MT6320_TOPCKPDN_PWMOC_CK, "top-pwmoc",
		MT6320_TOP_CKPDN, BIT(3), &clk_names[SMPS2M]),
	GATES(MT6320_TOPCKPDN_EFUSE_CK, "top-efuse",
		MT6320_TOP_CKPDN, BIT(4), &clk_names[PMU75K]),
	GATES(MT6320_TOPCKPDN_FGADC_CK, "top-fgadc",
		MT6320_TOP_CKPDN, BIT(5), &clk_names[FG32K]),
	COMPOSITE(MT6320_TOPCKPDN_FGADC_ANA_CK, "top-fgadc-ana",
		MT6320_TOP_CKPDN, BIT(6), mt6320_fgadc_ana_parents, 2,
		0, 0, 0, 0, MT6320_TOP_CKCON1, BIT(12)),
	GATES(MT6320_TOPCKPDN_BST_DRV_1M_CK, "top-bstdrv1m",
		MT6320_TOP_CKPDN, BIT(7), &clk_names[SMPS1M]),
	COMPOSITE(MT6320_TOPCKPDN_RTC_MCLK, "top-rtc-mclk",
		MT6320_TOP_CKPDN, BIT(8), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_TOPCKPDN_SPK_PWM_DIV, "top-spkpwm",
		MT6320_TOP_CKPDN, BIT(9), &clk_names[SMPS1M], 1,
		MT6320_TOP_CKCON2, 0x0018, 1, 8, 0, 0),
	COMPOSITE(MT6320_TOPCKPDN_SPK_DIV, "top-spkdiv",
		MT6320_TOP_CKPDN, BIT(10), &clk_names[SMPS1M], 1,
		MT6320_TOP_CKCON2, 0x0060, 1, 1, 0, 0),
	GATES(MT6320_TOPCKPDN_SMPS_CK_DIV2, "top-smpsdiv2",
		MT6320_TOP_CKPDN, BIT(11), &clk_names[SMPS12M]),
	GATES(MT6320_TOPCKPDN_SMPS_CK_DIV, "top-smpsdiv",
		MT6320_TOP_CKPDN, BIT(12), &clk_names[SMPS24M]),
	COMPOSITE(MT6320_TOPCKPDN_AUXADC_CK, "top-auxadc",
		MT6320_TOP_CKPDN, BIT(13), &clk_names[PMU12M], 1,
		MT6320_TOP_CKCON2, 0x0003, 6, 1, 0, 0),
	COMPOSITE(MT6320_TOPCKPDN_ACCDET_CK, "top-accdet",
		MT6320_TOP_CKPDN, BIT(14), mt6320_accdet_parents, 4,
		0, 0, 0, 0, MT6320_TOP_CKCON1, 0x6000),
	GATES(MT6320_TOPCKPDN_STRUP_6M, "top-strup6m",
		MT6320_TOP_CKPDN, BIT(15), &clk_names[SMPS6M]),
	GATES(MT6320_TOPCKPDN2_RTC32K_1V8, "top2-rtc32k1v8",
		MT6320_TOP_CKPDN2, BIT(0), &clk_names[RTC32K]),
	COMPOSITE(MT6320_TOPCKPDN2_FQMTR, "top2-fqmtr",
		MT6320_TOP_CKPDN2, BIT(1), mt6320_fgmtr_parents, 2,
		0, 0, 0, 0, MT6320_TOP_CKCON1, BIT(15)),
	GATES(MT6320_TOPCKPDN2_STRUP_75K_CK, "top2-starup75k",
		MT6320_TOP_CKPDN2, BIT(2), &clk_names[PMU75K]),
	GATES(MT6320_TOPCKPDN2_RTC_32K_CK, "top2-rtc32k",
		MT6320_TOP_CKPDN2, BIT(3), &clk_names[RTC32K]),
	GATES(MT6320_TOPCKPDN2_PCHR_32K_CK, "top2-pchr32k",
		MT6320_TOP_CKPDN2, BIT(4), &clk_names[RTC32K]),
	GATES(MT6320_TOPCKPDN2_LDOSTB_1M_CK, "top2-ldostb1m",
		MT6320_TOP_CKPDN2, BIT(5), &clk_names[SMPS1M]),
	GATES(MT6320_TOPCKPDN2_INTRP_CK, "top2-intr",
		MT6320_TOP_CKPDN2, BIT(6), &clk_names[PMU75K]),
	GATES(MT6320_TOPCKPDN2_DRV_32K_CK, "top2-drv32k",
		MT6320_TOP_CKPDN2, BIT(7), &clk_names[SMPS1M]),
	GATES(MT6320_TOPCKPDN2_CHR1M_CK, "top2-chr1m",
		MT6320_TOP_CKPDN2, BIT(8), &clk_names[CHR1M]),
	GATES(MT6320_TOPCKPDN2_BUCK_CK, "top2-buck",
		MT6320_TOP_CKPDN2, BIT(9), &clk_names[PMU12M]),
	GATES(MT6320_TOPCKPDN2_BUCK_ANA_CK, "top2-buckana",
		MT6320_TOP_CKPDN2, BIT(10), &clk_names[SMPS2M]),
	GATES(MT6320_TOPCKPDN2_BUCK32K, "top2-buck32k",
		MT6320_TOP_CKPDN2, BIT(11), &clk_names[RTC32K]),
	GATES(MT6320_TOPCKPDN2_BUCK_1M_CK, "top2-buck1m",
		MT6320_TOP_CKPDN2, BIT(12), &clk_names[SMPS1M]),
	GATES(MT6320_TOPCKPDN2_STRUP_32K_CK, "top2-starup32k",
		MT6320_TOP_CKPDN2, BIT(13), &clk_names[RTC32K]),
	GATES(MT6320_TOPCKPDN2_RTC_75K_CK, "top2-rtc75k",
		MT6320_TOP_CKPDN2, BIT(14), &clk_names[PMU75K]),
	GATES(MT6320_TOPCKPDN2_RSV_15, "top2-rsv",
		MT6320_TOP_CKPDN2, BIT(15), &clk_names[SMPS24M]),
	COMPOSITE(MT6320_WRPCKPDN_I2C0, "wrap-i2c0",
		MT6320_WRP_CKPDN, BIT(0), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_WRPCKPDN_I2C1, "wrap-i2c1",
		MT6320_WRP_CKPDN, BIT(1), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_WRPCKPDN_I2C2, "wrap-i2c2",
		MT6320_WRP_CKPDN, BIT(2), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_WRPCKPDN_PWM, "wrap-pwm",
		MT6320_WRP_CKPDN, BIT(3), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_WRPCKPDN_KP, "wrap-kp",
		MT6320_WRP_CKPDN, BIT(4), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	COMPOSITE(MT6320_WRPCKPDN_EINT, "wrap-eint",
		MT6320_WRP_CKPDN, BIT(5), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
	GATES(MT6320_WRPCKPDN_32K, "wrap-32k",
		MT6320_WRP_CKPDN, BIT(6), &clk_names[RTC32K]),
	COMPOSITE(MT6320_WRPCKPDN_WRP, "wrap-wrp",
		MT6320_WRP_CKPDN, BIT(7), &clk_names[SMPS24M], 1,
		MT6320_TOP_CKCON2, 0xC000, 1, 1, 0, 0),
};

static const struct of_device_id mt6320_clk_match_table[] = {
	{ .compatible = "mediatek,mt6320-clk" },
	{ }
};
MODULE_DEVICE_TABLE(of, mt6320_clk_match_table);

static int mt6320_clk_probe(struct platform_device *pdev)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct clk **clk;
	size_t num_clks;
	struct mt6397_chip *mt6320 = dev_get_drvdata(pdev->dev.parent);
	struct clk_onecell_data *onecell;

	num_clks = ARRAY_SIZE(mt6320_clks);
	clk = devm_kzalloc(dev, sizeof(struct clk *) * num_clks, GFP_KERNEL);
	if (!clk)
		return -ENOMEM;

	onecell = devm_kzalloc(dev, sizeof(*onecell), GFP_KERNEL);
	if (!onecell)
		return -ENOMEM;

	clk[MT6320_CLK_AUD26M] = clk_register_fixed_rate(&pdev->dev,
			"aud26m", NULL, 0, 26000000);

	clk[MT6320_CLK_AUD13M] = clk_register_fixed_factor(&pdev->dev,
			"aud13m", "aud26m", CLK_SET_RATE_PARENT, 1, 2);

	clk[MT6320_CLK_AUD26M_DIV64] = clk_register_fixed_factor(&pdev->dev,
			"aud26m_div64", "aud26m", CLK_SET_RATE_PARENT, 1, 64);

	clk[MT6320_CLK_SMPS24M] = clk_register_fixed_rate(&pdev->dev,
			"smps24m", NULL, 0, 24000000);

	clk[MT6320_CLK_SMPS12M] = clk_register_fixed_factor(&pdev->dev,
			"smps12m", "smps24m", CLK_SET_RATE_PARENT, 1, 2);

	clk[MT6320_CLK_SMPS6M] = clk_register_fixed_factor(&pdev->dev,
			"smps6m", "smps24m", CLK_SET_RATE_PARENT, 1, 4);

	clk[MT6320_CLK_SMPS3M] = clk_register_fixed_factor(&pdev->dev,
			"smps3m", "smps24m", CLK_SET_RATE_PARENT, 1, 8);

	clk[MT6320_CLK_SMPS2M] = clk_register_fixed_factor(&pdev->dev,
			"smps2m", "smps24m", CLK_SET_RATE_PARENT, 1, 12);

	clk[MT6320_CLK_SMPS1M] = clk_register_fixed_factor(&pdev->dev,
			"smps1m", "smps24m", CLK_SET_RATE_PARENT, 1, 24);

	clk[MT6320_CLK_PMU75K] = clk_register_fixed_rate(&pdev->dev,
			"pmu75k", NULL, 0, 75000);

	clk[MT6320_CLK_PMU12M] = clk_register_fixed_rate(&pdev->dev,
			"pmu12m", NULL, 0, 12000000);

	clk[MT6320_CLK_FG32K] = clk_register_fixed_rate(&pdev->dev,
			"fg32k", NULL, 0, 32000);

	clk[MT6320_CLK_RTC32K] = clk_register_fixed_rate(&pdev->dev,
			"rtc32k", NULL, 0, 32000);

	clk[MT6320_CLK_CHR1M] = clk_register_fixed_rate(&pdev->dev,
			"chr1m", NULL, 0, 1000000);

	for (i = MT6320_TOPCKPDN_AUD_26M; i < num_clks; i++) {
		mt6320_clks[i].regmap = mt6320->regmap;
		clk[i] = devm_clk_register(dev, &mt6320_clks[i].hw);
		if (IS_ERR(clk))
			return PTR_ERR(clk);
	}

	onecell->clk_num = num_clks;
	onecell->clks = clk;
	ret = of_clk_add_provider(dev->of_node,
				  of_clk_src_onecell_get, onecell);
	if (ret) {
		dev_err(dev, "unable to add clk provider\n");
		return ret;
	}

	return 0;
}

static void mt6320_clk_remove(struct platform_device *pdev)
{
	of_clk_del_provider(pdev->dev.of_node);

	return;
}

static struct platform_driver mt6320_clk_driver = {
	.probe = mt6320_clk_probe,
	.remove = mt6320_clk_remove,
	.driver = {
		.name = "mt6320-clk",
		.of_match_table = mt6320_clk_match_table,
	},
};

module_platform_driver(mt6320_clk_driver);

MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
MODULE_DESCRIPTION("Clock Driver for MediaTek MT6320 PMIC");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mt6320-clock");

old style

[akku1139]

i2c 4,5,6 are broken

[akku1139]

wrap-i2c0,1,2 are not 24MHz max?

#define I2C_CLK_WRAPPER_RATE		36000		/* kHz for wrapper I2C work frequency */

https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/drivers/i2c/i2c.c#L49

[akku1139]

&pwrap {
	pmic: mt6397 {
		compatible = "mediatek,mt6397";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;


		rtc: rtc@8000 {
			compatible = "mediatek,mt6397-rtc";
			reg = <0x8000 0x3e>;
			interrupt-parent = <&pmic>;
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
		};


		mt6397codec: mt6397codec {
			compatible = "mediatek,mt6397-codec";
		};


		pinctrl@0x0000C000 {
			compatible = "mediatek,mt6397-pinctrl";
			reg = <0 0x0000C000 0 0x0108>;
			gpio-controller;
		};


		mt6397clock: mt6397clock {
			compatible = "mediatek,mt6397-clk";
			#clock-cells = <1>;
		};


		mt6397regulator: mt6397regulator {
			compatible = "mediatek,mt6397-regulator";


			mt6397_vpca15_reg: buck_vpca15 {
				regulator-compatible = "buck_vpca15";
				regulator-name = "vpca15";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vpca7_reg: buck_vpca7 {
				regulator-compatible = "buck_vpca7";
				regulator-name = "vpca7";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vsramca15_reg: buck_vsramca15 {
				regulator-compatible = "buck_vsramca15";
				regulator-name = "vsramca15";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vsramca7_reg: buck_vsramca7 {
				regulator-compatible = "buck_vsramca7";
				regulator-name = "vsramca7";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vcore_reg: buck_vcore {
				regulator-compatible = "buck_vcore";
				regulator-name = "vcore";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vgpu_reg: buck_vgpu {
				regulator-compatible = "buck_vgpu";
				regulator-name = "vgpu";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
			};


			mt6397_vdrm_reg: buck_vdrm {
				regulator-compatible = "buck_vdrm";
				regulator-name = "vdrm";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1400000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vio18_reg: buck_vio18 {
				regulator-compatible = "buck_vio18";
				regulator-name = "vio18";
				regulator-min-microvolt = <1620000>;
				regulator-max-microvolt = <1980000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vtcxo_reg: ldo_vtcxo {
				regulator-compatible = "ldo_vtcxo";
				regulator-name = "vtcxo";
				regulator-always-on;
			};


			mt6397_va28_reg: ldo_va28 {
				regulator-compatible = "ldo_va28";
				regulator-name = "va28";
				regulator-always-on;
			};


			mt6397_vcama_reg: ldo_vcama {
				regulator-compatible = "ldo_vcama";
				regulator-name = "vcama";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vio28_reg: ldo_vio28 {
				regulator-compatible = "ldo_vio28";
				regulator-name = "vio28";
				regulator-always-on;
			};


			mt6397_vusb_reg: ldo_vusb {
				regulator-compatible = "ldo_vusb";
				regulator-name = "vusb";
			};


			mt6397_vmc_reg: ldo_vmc {
				regulator-compatible = "ldo_vmc";
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vmch_reg: ldo_vmch {
				regulator-compatible = "ldo_vmch";
				regulator-name = "vmch";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
				regulator-compatible = "ldo_vemc3v3";
				regulator-name = "vemc_3v3";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp1_reg: ldo_vgp1 {
				regulator-compatible = "ldo_vgp1";
				regulator-name = "vcamd";
				regulator-min-microvolt = <1220000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <240>;
			};


			mt6397_vgp2_reg: ldo_vgp2 {
				regulator-compatible = "ldo_vgp2";
				regulator-name = "vcamio";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
				regulator-always-on;
			};


			mt6397_vgp3_reg: ldo_vgp3 {
				regulator-compatible = "ldo_vgp3";
				regulator-name = "vcamaf";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp4_reg: ldo_vgp4 {
				regulator-compatible = "ldo_vgp4";
				regulator-name = "vgp4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp5_reg: ldo_vgp5 {
				regulator-compatible = "ldo_vgp5";
				regulator-name = "vgp5";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp6_reg: ldo_vgp6 {
				regulator-compatible = "ldo_vgp6";
				regulator-name = "vgp6";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vibr_reg: ldo_vibr {
				regulator-compatible = "ldo_vibr";
				regulator-name = "vibr";
				regulator-min-microvolt = <1300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};
		};
	};
};


&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	status = "okay";
};


&mmc2 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_uhs>;
	status = "okay";
};


&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins_a>;
	status = "okay";
};


&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins_a>;
	status = "okay";


	max98090: audio-codec@10 {
		compatible = "maxim,max98090";
		reg = <0x10>;
		interrupt-parent = <&pio>;
		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&max98090_irq>;
	};
};

https://github.com/mtk09422/chromiumos-third_party-kernel-mediatek/blob/1d8e9e85054735332fae9fcf9b5d4eb2b35bc90a/arch/arm/boot/dts/mt8135-crosnb.dts#L150-L405

&pwrap {
	pmic: mt6397 {
		compatible = "mediatek,mt6397";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;


		rtc: rtc@8000 {
			compatible = "mediatek,mt6397-rtc";
			reg = <0x8000 0x3e>;
			interrupt-parent = <&pmic>;
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
		};


		mt6397codec: mt6397codec {
			compatible = "mediatek,mt6397-codec";
		};


		pinctrl@0x0000C000 {
			compatible = "mediatek,mt6397-pinctrl";
			reg = <0 0x0000C000 0 0x0108>;
			gpio-controller;
		};


		mt6397clock: mt6397clock {
			compatible = "mediatek,mt6397-clk";
			#clock-cells = <1>;
		};


		mt6397regulator: mt6397regulator {
			compatible = "mediatek,mt6397-regulator";


			mt6397_vpca15_reg: buck_vpca15 {
				regulator-compatible = "buck_vpca15";
				regulator-name = "vpca15";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vpca7_reg: buck_vpca7 {
				regulator-compatible = "buck_vpca7";
				regulator-name = "vpca7";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vsramca15_reg: buck_vsramca15 {
				regulator-compatible = "buck_vsramca15";
				regulator-name = "vsramca15";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vsramca7_reg: buck_vsramca7 {
				regulator-compatible = "buck_vsramca7";
				regulator-name = "vsramca7";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vcore_reg: buck_vcore {
				regulator-compatible = "buck_vcore";
				regulator-name = "vcore";
				regulator-min-microvolt = < 850000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vgpu_reg: buck_vgpu {
				regulator-compatible = "buck_vgpu";
				regulator-name = "vgpu";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
			};


			mt6397_vdrm_reg: buck_vdrm {
				regulator-compatible = "buck_vdrm";
				regulator-name = "vdrm";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1400000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vio18_reg: buck_vio18 {
				regulator-compatible = "buck_vio18";
				regulator-name = "vio18";
				regulator-min-microvolt = <1620000>;
				regulator-max-microvolt = <1980000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};


			mt6397_vtcxo_reg: ldo_vtcxo {
				regulator-compatible = "ldo_vtcxo";
				regulator-name = "vtcxo";
				regulator-always-on;
			};


			mt6397_va28_reg: ldo_va28 {
				regulator-compatible = "ldo_va28";
				regulator-name = "va28";
				regulator-always-on;
			};


			mt6397_vcama_reg: ldo_vcama {
				regulator-compatible = "ldo_vcama";
				regulator-name = "vcama";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vio28_reg: ldo_vio28 {
				regulator-compatible = "ldo_vio28";
				regulator-name = "vio28";
				regulator-always-on;
			};


			mt6397_vusb_reg: ldo_vusb {
				regulator-compatible = "ldo_vusb";
				regulator-name = "vusb";
			};


			mt6397_vmc_reg: ldo_vmc {
				regulator-compatible = "ldo_vmc";
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vmch_reg: ldo_vmch {
				regulator-compatible = "ldo_vmch";
				regulator-name = "vmch";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
				regulator-compatible = "ldo_vemc3v3";
				regulator-name = "vemc_3v3";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp1_reg: ldo_vgp1 {
				regulator-compatible = "ldo_vgp1";
				regulator-name = "vcamd";
				regulator-min-microvolt = <1220000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <240>;
			};


			mt6397_vgp2_reg: ldo_vgp2 {
				regulator-compatible = "ldo_vgp2";
				regulator-name = "vcamio";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp3_reg: ldo_vgp3 {
				regulator-compatible = "ldo_vgp3";
				regulator-name = "vcamaf";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp4_reg: ldo_vgp4 {
				regulator-compatible = "ldo_vgp4";
				regulator-name = "vgp4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
				regulator-always-on;
			};


			mt6397_vgp5_reg: ldo_vgp5 {
				regulator-compatible = "ldo_vgp5";
				regulator-name = "vgp5";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <218>;
			};


			mt6397_vgp6_reg: ldo_vgp6 {
				regulator-compatible = "ldo_vgp6";
				regulator-name = "vgp6";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
				regulator-always-on;
			};


			mt6397_vibr_reg: ldo_vibr {
				regulator-compatible = "ldo_vibr";
				regulator-name = "vibr";
				regulator-min-microvolt = <1300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};
		};
	};
};

https://github.com/mtk09422/chromiumos-third_party-kernel-mediatek/blob/1d8e9e85054735332fae9fcf9b5d4eb2b35bc90a/arch/arm/boot/dts/mt8135-evbp1.dts#L47-L268

[akku1139]

• rtc interrupts