qspipsu: possible missing target processor

[foxhoundsk]

In the following qspipsu header:

embeddedsw/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_control.h

Lines 66 to 68 in 1bb19ac

	#if defined (__MICROBLAZE__) || defined (__riscv)
	#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
	#endif

It suggests that XPS_SYS_CTRL_BASEADDR is available for non-RPU builds. But, inside xqspipsu_hw.c:752:

embeddedsw/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.c

Line 752 in 1bb19ac

XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,

it uses XPS_SYS_CTRL_BASEADDR, and the use site is within the RPU build scope:

embeddedsw/XilinxProcessorIPLib/drivers/qspipsu/src/xqspipsu_hw.c

Lines 708 to 764 in 1bb19ac

	#if defined (ARMR5) || defined (__aarch64__) || defined (__MICROBLAZE__) || defined (__riscv)
	/*****************************************************************************/
	/**
	*
	* Sets the Tapdelay values for the QSPIPSU device driver.The device
	* must be idle rather than busy transferring data before setting Tapdelay.
	*
	* @param InstancePtr Pointer to the XQspiPsu instance.
	* @param TapdelayBypss Contains the IOU_TAPDLY_BYPASS register value.
	* @param LPBKDelay Contains the GQSPI_LPBK_DLY_ADJ register value.
	* @param Datadelay Contains the QSPI_DATA_DLY_ADJ register value.
	*
	* @return
	* - XST_SUCCESS if options are successfully set.
	* - XST_DEVICE_BUSY if the device is currently transferring data.
	* The transfer must complete or be aborted before setting TapDelay.
	*
	* @note
	* This function is not thread-safe.
	*
	******************************************************************************/
	s32 XQspipsu_Set_TapDelay(const XQspiPsu *InstancePtr, u32 TapdelayBypass,
	u32 LPBKDelay, u32 Datadelay)
	{
	s32 Status;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	/*
	* Do not allow to modify the Control Register while a transfer is in
	* progress. Not thread-safe.
	*/
	if (InstancePtr->IsBusy == (u32)TRUE) {
	Status = (s32)XST_DEVICE_BUSY;
	} else {
	#if defined (__aarch64__) && (EL1_NONSECURE == 1) && !defined (versal)
	Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
	IOU_TAPDLY_BYPASS_OFFSET) | ((u64)(0x4) << 32),
	(u64)TapdelayBypass, 0, 0, 0, 0, 0);
	#elif defined (versal)
	XQspiPsu_WriteReg(XQSPIPS_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
	TapdelayBypass);
	#else
	XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR, IOU_TAPDLY_BYPASS_OFFSET,
	TapdelayBypass);
	#endif
	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
	XQSPIPSU_LPBK_DLY_ADJ_OFFSET, LPBKDelay);
	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
	XQSPIPSU_DATA_DLY_ADJ_OFFSET, Datadelay);
	Status = (s32)XST_SUCCESS;
	}
	return Status;
	}
	#endif

Considering that qspipsu does not use xparameters_ps.h, which typically provides XPS_SYS_CTRL_BASEADDR, is it correct that xqspipsu_control.h should add RPU as one of the target processors? That is:

-#if defined (__MICROBLAZE__) || defined (__riscv)
+#if defined (__MICROBLAZE__) || defined (__riscv) || defined (ARMR5)
#define XPS_SYS_CTRL_BASEADDR   0xFF180000U     /**< System controller Baseaddress */
#endif

[zeeshanmohd-amd]

Hi @foxhoundsk, Thanks for reporting this, your analysis is correct. XPS_SYS_CTRL_BASEADDR was getting used in the ARMR5 (RPU) build scope, but it was defined only for MicroBlaze and RISC-V. We have fixed this by extending the guard to also cover ARMR5 and aarch64 (non-versal) platforms and added an #ifndef so that the BSP provided definition is used when available. This change will be part of the 2026.2 release.