diff --git a/embassy-mcxa/Cargo.toml b/embassy-mcxa/Cargo.toml index e5b4088890..0a01cb11e7 100644 --- a/embassy-mcxa/Cargo.toml +++ b/embassy-mcxa/Cargo.toml @@ -59,13 +59,22 @@ grounded = { version = "0.2.1", features = ["cas", "critical-section"] } heapless = "0.9" maitake-sync = { version = "0.3.0", default-features = false, features = ["critical-section", "no-cache-pad"] } nb = "1.1.0" -nxp-pac = { git = "https://github.com/embassy-rs/nxp-pac.git", rev = "b644ff07f59805b1fb362eee45a2de7becf29172", features = ["rt"] } +nxp-pac = { git = "https://github.com/embassy-rs/nxp-pac.git", rev = "25da488cb2b9498b4127f11e94f40771f0ab7f28", features = ["rt"] } paste = "1.0.15" rand-core-06 = { package = "rand_core", version = "0.6" } rand-core-09 = { package = "rand_core", version = "0.9" } rand-core-10 = { package = "rand_core", version = "0.10" } +[build-dependencies] +nxp-pac = { git = "https://github.com/embassy-rs/nxp-pac.git", rev = "25da488cb2b9498b4127f11e94f40771f0ab7f28", default-features = false, features = ["metadata"] } +proc-macro2 = "1.0.106" +quote = "1.0.45" +regex = "1.12.3" +syn = "2.0.117" +convert_case = "0.11" +indexmap = "2.14.0" + [features] default = ["rt", "swd-swo-as-gpio", "dma-ipd-req"] diff --git a/embassy-mcxa/build.rs b/embassy-mcxa/build.rs new file mode 100644 index 0000000000..ffbc80dbd8 --- /dev/null +++ b/embassy-mcxa/build.rs @@ -0,0 +1,391 @@ +use std::collections::HashMap; +use std::io::Write; +use std::path::{Path, PathBuf}; +use std::process::Command; +use std::{env, fs}; + +use build_common::CfgSet; +use convert_case::ccase; +use indexmap::IndexMap; +use nxp_pac::metadata::METADATA; +use proc_macro2::TokenStream; +use quote::{format_ident, quote}; +use regex::Regex; + +mod build_common; + +fn main() { + let mut cfgs = CfgSet::new(); + build_common::set_target_cfgs(&mut cfgs); + + // TODO: Declare all possible driver cfgs. Needs extra info in pac metadata + + // Enable all drivers for this chip + for peripheral in METADATA.peripherals { + if peripheral.driver_name.is_empty() { + continue; + } + + let cfg_name = match peripheral.driver_name.split_once("::") { + Some((path, _block)) => path, + None => peripheral.driver_name, + } + .replace("/", "_"); + + cfgs.enable(&cfg_name); + // Temporary until todo above is removed + cfgs.declare(&cfg_name); + } + + let generated = [ + generate_peripherals_call(), + generate_interrupt_mod_call(), + generate_dma_requests_enum(), + generate_gpio_pin_impls(), + generate_adc_pin_impls(), + generate_clkout_impls(), + generate_lpi2c_pin_impls(), + generate_i3c_pin_impls(), + generate_spi_pin_impls(), + generate_ctimer_pin_impls(), + generate_lpuart_pin_impls(), + ]; + + let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + let out_file = out_dir.join("_generated.rs"); + fs::write(&out_file, generated.into_iter().collect::().to_string()).unwrap(); + rustfmt(&out_file); +} + +fn generate_peripherals_call() -> TokenStream { + let mut singletons: Vec = Vec::new(); + // Add pins + singletons.extend(METADATA.pins.iter().map(|pin| pin.name.to_owned())); + // Add peripherals + singletons.extend(METADATA.peripherals.iter().map(|peripheral| peripheral.name.to_owned())); + + // Add DMA channels + let dma_regex = Regex::new(r"(?i:^DMA)(\d+)").unwrap(); + let dma_channels_regex = Regex::new(r"(?i:DMA)(\d+)").unwrap(); + for (dma_num, dma_peripheral) in METADATA + .peripherals + .iter() + .filter_map(|p| get_regex_num(p.name, &dma_regex).map(|dma_num| (dma_num, p))) + { + let channels_num = get_regex_num(dma_peripheral.driver_name, &dma_channels_regex).unwrap(); + + for channel in 0..channels_num { + singletons.push(format!("DMA{dma_num}_CH{channel}")); + } + } + + // Add CTIMER channels + let ctimer_regex = Regex::new(r"(?i:^CTIMER)(\d+)").unwrap(); + for ctimer_num in METADATA + .peripherals + .iter() + .filter_map(|p| get_regex_num(p.name, &ctimer_regex)) + { + for num in 0..4 { + singletons.push(format!("CTIMER{ctimer_num}_CH{num}")); + } + } + + // TODO: Remove singletons for pins with dual-use based on feature flags + + // Output the singletons + let singleton_tokens: Vec<_> = singletons.iter().map(|s| format_ident!("{}", s)).collect(); + + quote! { + embassy_hal_internal::peripherals!(#(#singleton_tokens),*); + } +} + +fn generate_interrupt_mod_call() -> TokenStream { + let mut irqs = Vec::new(); + for (name, _) in METADATA.interrupts { + irqs.push(format_ident!("{}", name)); + } + + quote! { + embassy_hal_internal::interrupt_mod!( + #( + #irqs, + )* + ); + } +} + +fn generate_gpio_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let gpio_regex = Regex::new(r"(?i:^GPIO)(\d+)").unwrap(); + for (gpio_num, gpio_peripheral) in METADATA + .peripherals + .iter() + .filter_map(|p| get_regex_num(p.name, &gpio_regex).map(|gpio_num| (gpio_num, p))) + { + let peripheral = format_ident!("{}", gpio_peripheral.name); + let gpio_num = proc_macro2::Literal::u32_unsuffixed(gpio_num); + + for s in gpio_peripheral.signals { + assert_eq!(s.pins.len(), 1, "Each gpio signal should only have 1 pin: {s:?}"); + let pin = format_ident!("{}", s.pins[0].pin); + let pin_num = proc_macro2::Literal::u32_unsuffixed(s.name.parse().unwrap()); + + generated.extend(quote! { + impl_gpio_pin!(#pin, #gpio_num, #pin_num, #peripheral); + }); + } + } + + generated +} + +fn generate_adc_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let adc_regex = Regex::new(r"^ADC\d+").unwrap(); + let adc_channel_regex = Regex::new(r"(?:^A)(\d+)").unwrap(); + for adc in METADATA.peripherals.iter().filter(|p| adc_regex.is_match(p.name)) { + let adc_name = format_ident!("{}", adc.name); + for signal in adc.signals { + let channel: u8 = get_regex_num(signal.name, &adc_channel_regex) + .expect(&format!("Could not get ADC channel from: {}", signal.name)) + .try_into() + .unwrap(); + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + generated.extend(quote! { + impl_adc_pin!(#pin_name, #adc_name, #channel); + }); + } + } + } + + generated +} + +fn generate_clkout_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + for clkout in METADATA + .peripherals + .iter() + .filter(|p| p.name.to_ascii_lowercase() == "clkout") + { + for signal in clkout.signals { + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + generated.extend(quote! { + impl_clkout_pin!(#pin_name, #mux); + }); + } + } + } + + generated +} + +fn generate_lpi2c_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let lpi2c_regex = Regex::new(r"^LPI2C\d+").unwrap(); + for lpi2c in METADATA.peripherals.iter().filter(|p| lpi2c_regex.is_match(p.name)) { + let lpi2c_name = format_ident!("{}", lpi2c.name); + for signal in lpi2c.signals { + let signal_pin = format_ident!("{}Pin", ccase!(pascal, signal.name)); + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + generated.extend(quote! { + impl_lpi2c_pin!(#pin_name, #lpi2c_name, #mux, #signal_pin); + }); + } + } + } + + generated +} + +fn generate_i3c_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let i3c_regex = Regex::new(r"^I3C\d+").unwrap(); + for i3c in METADATA.peripherals.iter().filter(|p| i3c_regex.is_match(p.name)) { + let i3c_name = format_ident!("{}", i3c.name); + for signal in i3c.signals { + let signal_pin = format_ident!("{}Pin", ccase!(pascal, signal.name)); + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + generated.extend(quote! { + impl_i3c_pin!(#pin_name, #i3c_name, #mux, #signal_pin); + }); + } + } + } + + generated +} + +fn generate_spi_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let spi_regex = Regex::new(r"^LPSPI\d+").unwrap(); + for spi in METADATA.peripherals.iter().filter(|p| spi_regex.is_match(p.name)) { + let spi_name = format_ident!("{}", spi.name); + for signal in spi.signals { + let signal_pin = format_ident!("{}Pin", ccase!(pascal, signal.name)); + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + generated.extend(quote! { + impl_spi_pin!(#pin_name, #spi_name, #mux, #signal_pin); + }); + } + } + } + + generated +} + +fn generate_ctimer_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let ctimer_regex = Regex::new(r"^CTIMER\d+").unwrap(); + let match_channel_regex = Regex::new(r"(?:^MAT)(\d+)").unwrap(); + + for ctimer in METADATA.peripherals.iter().filter(|p| ctimer_regex.is_match(p.name)) { + let ctimer_name = format_ident!("{}", ctimer.name); + + let mut inp_pins = IndexMap::new(); + let mut mat_pins = IndexMap::new(); + + // There are multiple INPn and MATn signals + // And they share pins. We don't use that, so we need to filter out duplicates to prevent duplicate trait impls + for signal in ctimer.signals { + if signal.name.starts_with("INP") { + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + inp_pins.insert(pin_name, mux); + } + } else if let Some(match_index) = get_regex_num(signal.name, &match_channel_regex) { + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + mat_pins.insert(pin_name.clone(), mux); + + let ctimer_channel = format_ident!("{}_CH{}", ctimer_name, match_index); + generated.extend(quote! { + impl_ctimer_match!(#ctimer_name, #ctimer_channel, #pin_name); + }); + } + } else { + unreachable!() + } + } + + for (pin_name, mux) in inp_pins { + generated.extend(quote! { + impl_ctimer_input_pin!(#pin_name, #ctimer_name, #mux); + }); + } + for (pin_name, mux) in mat_pins { + generated.extend(quote! { + impl_ctimer_output_pin!(#pin_name, #ctimer_name, #mux); + }); + } + } + + generated +} + +fn generate_lpuart_pin_impls() -> TokenStream { + let mut generated = TokenStream::new(); + + let lpuart_regex = Regex::new(r"^LPUART\d+").unwrap(); + for lpuart in METADATA.peripherals.iter().filter(|p| lpuart_regex.is_match(p.name)) { + let lpuart_name = format_ident!("{}", lpuart.name); + for signal in lpuart.signals { + let signal_name = format_ident!("{}", signal.name); + for pin in signal.pins { + let pin_name = format_ident!("{}", pin.pin); + let mux = format_ident!("MUX{}", pin.alt); + generated.extend(quote! { + impl_lpuart_pin!(#lpuart_name, #pin_name, #mux, #signal_name); + }); + } + } + } + + generated +} + +fn generate_dma_requests_enum() -> TokenStream { + let mut dma_requests = HashMap::new(); + for dma_mux in METADATA.peripherals.iter().flat_map(|p| p.dma_muxing) { + dma_requests.insert(dma_mux.signal, dma_mux.request); + } + let mut sorted_dma_requests = dma_requests.into_iter().collect::>(); + sorted_dma_requests.sort_unstable_by_key(|(_, request)| *request); + let enum_variants = sorted_dma_requests.into_iter().map(|(name, value)| { + use convert_case::ccase; + let name = format_ident!("{}", ccase!(pascal, name)); + quote! { #name = #value } + }); + quote! { + /// DMA request sources + #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)] + #[repr(u8)] + #[allow(dead_code)] + pub enum DmaRequest { + #(#enum_variants),* + } + + impl DmaRequest { + /// Convert enumerated value into a raw integer + pub const fn number(self) -> u8 { + self as u8 + } + + /// Convert a raw integer into an enumerated value + /// + /// ## SAFETY + /// + /// The given number MUST be one of the defined variant, e.g. a number + /// derived from [`Self::number()`], otherwise it is immediate undefined behavior. + pub unsafe fn from_number_unchecked(num: u8) -> Self { + unsafe { core::mem::transmute(num) } + } + } + } +} + +/// rustfmt a given path. +/// Failures are logged to stderr and ignored. +fn rustfmt(path: impl AsRef) { + let path = path.as_ref(); + match Command::new("rustfmt").args([path]).output() { + Err(e) => { + eprintln!("failed to exec rustfmt {:?}: {:?}", path, e); + } + Ok(out) => { + if !out.status.success() { + eprintln!("rustfmt {:?} failed:", path); + eprintln!("=== STDOUT:"); + std::io::stderr().write_all(&out.stdout).unwrap(); + eprintln!("=== STDERR:"); + std::io::stderr().write_all(&out.stderr).unwrap(); + } + } + } +} + +fn get_regex_num(string: &str, regex: &Regex) -> Option { + regex + .captures(string) + .map(|cap| cap.extract::<1>().1[0].parse::().unwrap()) +} diff --git a/embassy-mcxa/build_common.rs b/embassy-mcxa/build_common.rs new file mode 100644 index 0000000000..4f24e6d37b --- /dev/null +++ b/embassy-mcxa/build_common.rs @@ -0,0 +1,94 @@ +// NOTE: this file is copy-pasted between several Embassy crates, because there is no +// straightforward way to share this code: +// - it cannot be placed into the root of the repo and linked from each build.rs using `#[path = +// "../build_common.rs"]`, because `cargo publish` requires that all files published with a crate +// reside in the crate's directory, +// - it cannot be symlinked from `embassy-xxx/build_common.rs` to `../build_common.rs`, because +// symlinks don't work on Windows. + +use std::collections::HashSet; +use std::env; + +/// Helper for emitting cargo instruction for enabling configs (`cargo:rustc-cfg=X`) and declaring +/// them (`cargo:rust-check-cfg=cfg(X)`). +#[derive(Debug)] +pub struct CfgSet { + enabled: HashSet, + declared: HashSet, +} + +impl CfgSet { + pub fn new() -> Self { + Self { + enabled: HashSet::new(), + declared: HashSet::new(), + } + } + + /// Enable a config, which can then be used in `#[cfg(...)]` for conditional compilation. + /// + /// All configs that can potentially be enabled should be unconditionally declared using + /// [`Self::declare()`]. + pub fn enable(&mut self, cfg: impl AsRef) { + if self.enabled.insert(cfg.as_ref().to_owned()) { + println!("cargo:rustc-cfg={}", cfg.as_ref()); + } + } + + pub fn enable_all(&mut self, cfgs: &[impl AsRef]) { + for cfg in cfgs.iter() { + self.enable(cfg.as_ref()); + } + } + + /// Declare a valid config for conditional compilation, without enabling it. + /// + /// This enables rustc to check that the configs in `#[cfg(...)]` attributes are valid. + pub fn declare(&mut self, cfg: impl AsRef) { + if self.declared.insert(cfg.as_ref().to_owned()) { + println!("cargo:rustc-check-cfg=cfg({})", cfg.as_ref()); + } + } + + pub fn declare_all(&mut self, cfgs: &[impl AsRef]) { + for cfg in cfgs.iter() { + self.declare(cfg.as_ref()); + } + } + + pub fn set(&mut self, cfg: impl Into, enable: bool) { + let cfg = cfg.into(); + if enable { + self.enable(cfg.clone()); + } + self.declare(cfg); + } +} + +/// Sets configs that describe the target platform. +pub fn set_target_cfgs(cfgs: &mut CfgSet) { + let target = env::var("TARGET").unwrap(); + + if target.starts_with("thumbv6m-") { + cfgs.enable_all(&["cortex_m", "armv6m"]); + } else if target.starts_with("thumbv7m-") { + cfgs.enable_all(&["cortex_m", "armv7m"]); + } else if target.starts_with("thumbv7em-") { + cfgs.enable_all(&["cortex_m", "armv7m", "armv7em"]); + } else if target.starts_with("thumbv8m.base") { + cfgs.enable_all(&["cortex_m", "armv8m", "armv8m_base"]); + } else if target.starts_with("thumbv8m.main") { + cfgs.enable_all(&["cortex_m", "armv8m", "armv8m_main"]); + } + cfgs.declare_all(&[ + "cortex_m", + "armv6m", + "armv7m", + "armv7em", + "armv8m", + "armv8m_base", + "armv8m_main", + ]); + + cfgs.set("has_fpu", target.ends_with("-eabihf")); +} diff --git a/embassy-mcxa/src/adc.rs b/embassy-mcxa/src/adc.rs index 038c4deeb2..0ecd799cf2 100644 --- a/embassy-mcxa/src/adc.rs +++ b/embassy-mcxa/src/adc.rs @@ -821,7 +821,7 @@ impl Handler for InterruptHandler { } } -mod sealed { +pub(crate) mod sealed { /// Seal a trait pub trait Sealed {} @@ -966,11 +966,13 @@ pub struct Async; impl sealed::Sealed for Async {} impl Mode for Async {} -macro_rules! impl_pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_adc_pin { ($pin:ident, $peri:ident, $channel:literal) => { - impl sealed::SealedAdcPin for crate::peripherals::$pin {} + impl crate::adc::sealed::SealedAdcPin for crate::peripherals::$pin {} - impl AdcPin for crate::peripherals::$pin { + impl crate::adc::AdcPin for crate::peripherals::$pin { #[inline] fn channel(&self) -> u8 { $channel @@ -978,120 +980,3 @@ macro_rules! impl_pin { } }; } - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx_pins { - use super::*; - - impl_pin!(P2_0, ADC0, 0); - impl_pin!(P2_4, ADC0, 1); - impl_pin!(P2_15, ADC0, 2); - impl_pin!(P2_3, ADC0, 3); - impl_pin!(P2_2, ADC0, 4); - impl_pin!(P2_12, ADC0, 5); - impl_pin!(P2_16, ADC0, 6); - impl_pin!(P2_7, ADC0, 7); - impl_pin!(P0_18, ADC0, 8); - impl_pin!(P0_19, ADC0, 9); - impl_pin!(P0_20, ADC0, 10); - impl_pin!(P0_21, ADC0, 11); - impl_pin!(P0_22, ADC0, 12); - impl_pin!(P0_23, ADC0, 13); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_3, ADC0, 14); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_6, ADC0, 15); - impl_pin!(P1_0, ADC0, 16); - impl_pin!(P1_1, ADC0, 17); - impl_pin!(P1_2, ADC0, 18); - impl_pin!(P1_3, ADC0, 19); - impl_pin!(P1_4, ADC0, 20); - impl_pin!(P1_5, ADC0, 21); - impl_pin!(P1_6, ADC0, 22); - impl_pin!(P1_7, ADC0, 23); - - // ??? - // impl_pin!(P1_10, ADC0, 255); - - impl_pin!(P2_1, ADC1, 0); - impl_pin!(P2_5, ADC1, 1); - impl_pin!(P2_19, ADC1, 2); - impl_pin!(P2_6, ADC1, 3); - impl_pin!(P2_3, ADC1, 4); - impl_pin!(P2_13, ADC1, 5); - impl_pin!(P2_17, ADC1, 6); - impl_pin!(P2_7, ADC1, 7); - impl_pin!(P1_10, ADC1, 8); - impl_pin!(P1_11, ADC1, 9); - impl_pin!(P1_12, ADC1, 10); - impl_pin!(P1_13, ADC1, 11); - impl_pin!(P1_14, ADC1, 12); - impl_pin!(P1_15, ADC1, 13); - // ??? - // impl_pin!(P1_16, ADC1, 255); - // impl_pin!(P1_17, ADC1, 255); - // impl_pin!(P1_18, ADC1, 255); - // impl_pin!(P1_19, ADC1, 255); - // ??? - impl_pin!(P3_31, ADC1, 20); - impl_pin!(P3_30, ADC1, 21); - impl_pin!(P3_29, ADC1, 22); -} - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx_pins { - use super::*; - - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_3, ADC0, 14); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_6, ADC0, 15); - impl_pin!(P0_14, ADC0, 10); - impl_pin!(P0_15, ADC0, 11); - impl_pin!(P0_18, ADC0, 8); - impl_pin!(P0_19, ADC0, 9); - impl_pin!(P0_22, ADC0, 12); - impl_pin!(P0_23, ADC0, 13); - - impl_pin!(P1_0, ADC0, 16); - impl_pin!(P1_1, ADC0, 17); - impl_pin!(P1_2, ADC0, 18); - impl_pin!(P1_3, ADC0, 19); - impl_pin!(P1_4, ADC0, 20); - impl_pin!(P1_5, ADC0, 21); - impl_pin!(P1_6, ADC0, 22); - impl_pin!(P1_7, ADC0, 23); - impl_pin!(P1_10, ADC1, 8); - impl_pin!(P1_11, ADC1, 9); - impl_pin!(P1_12, ADC1, 10); - impl_pin!(P1_13, ADC1, 11); - impl_pin!(P1_14, ADC1, 12); - impl_pin!(P1_15, ADC1, 13); - impl_pin!(P1_16, ADC1, 14); - impl_pin!(P1_17, ADC1, 15); - impl_pin!(P1_18, ADC1, 16); - impl_pin!(P1_19, ADC1, 17); - - impl_pin!(P2_0, ADC0, 0); - impl_pin!(P2_1, ADC1, 0); - impl_pin!(P2_2, ADC0, 4); - impl_pin!(P2_3, ADC0, 3); - impl_pin!(P2_3, ADC1, 4); - impl_pin!(P2_4, ADC0, 1); - impl_pin!(P2_5, ADC1, 1); - impl_pin!(P2_6, ADC1, 3); - impl_pin!(P2_7, ADC0, 7); - impl_pin!(P2_7, ADC1, 7); - impl_pin!(P2_12, ADC0, 5); - impl_pin!(P2_13, ADC1, 5); - impl_pin!(P2_15, ADC0, 2); - impl_pin!(P2_16, ADC0, 6); - impl_pin!(P2_17, ADC1, 6); - impl_pin!(P2_19, ADC1, 2); - - #[cfg(feature = "rosc-32k-as-gpio")] - impl_pin!(P5_0, ADC1, 20); - #[cfg(feature = "rosc-32k-as-gpio")] - impl_pin!(P5_1, ADC1, 21); - impl_pin!(P5_2, ADC1, 22); -} diff --git a/embassy-mcxa/src/chips/mcxa2xx.rs b/embassy-mcxa/src/chips/mcxa2xx.rs index db4a7e0490..3829511870 100644 --- a/embassy-mcxa/src/chips/mcxa2xx.rs +++ b/embassy-mcxa/src/chips/mcxa2xx.rs @@ -1,454 +1,8 @@ //! Module for MCXA2xx family -pub use inner_periph::{Peripherals, peripherals}; - +use crate::_generated::Peripherals; use crate::interrupt::InterruptExt; -// NOTE: macro generates missing safety docs and unsafe calls in unsafe blocks, -// allow for now, and put in a module so we can apply the rule to that scope. -#[allow(clippy::missing_safety_doc, unsafe_op_in_unsafe_fn)] -mod inner_periph { - #[rustfmt::skip] - embassy_hal_internal::peripherals!( - ADC0, - ADC1, - - AOI0, - AOI1, - - CAN0, - - CDOG0, - CDOG1, - - // CLKOUT is not specifically a peripheral (it's part of SYSCON), - // but we still want it to be a singleton. - CLKOUT, - - CMC, - CMP0, - CMP1, - CRC0, - - CTIMER0, - - CTIMER0_CH0, - CTIMER0_CH1, - CTIMER0_CH2, - CTIMER0_CH3, - - CTIMER1, - - CTIMER1_CH0, - CTIMER1_CH1, - CTIMER1_CH2, - CTIMER1_CH3, - - CTIMER2, - - CTIMER2_CH0, - CTIMER2_CH1, - CTIMER2_CH2, - CTIMER2_CH3, - - CTIMER3, - - CTIMER3_CH0, - CTIMER3_CH1, - CTIMER3_CH2, - CTIMER3_CH3, - - CTIMER4, - - CTIMER4_CH0, - CTIMER4_CH1, - CTIMER4_CH2, - CTIMER4_CH3, - - DBGMAILBOX, - DMA0, - DMA0_CH0, - DMA0_CH1, - DMA0_CH2, - DMA0_CH3, - DMA0_CH4, - DMA0_CH5, - DMA0_CH6, - DMA0_CH7, - EDMA0_TCD0, - EIM0, - EQDC0, - EQDC1, - ERM0, - FLEXIO0, - FLEXPWM0, - FLEXPWM1, - FMC0, - FMU0, - FREQME0, - GLIKEY0, - - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - - I3C0, - INPUTMUX0, - - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - - LPSPI0, - LPSPI1, - - LPTMR0, - - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - - MAU0, - MBC0, - MRCC0, - OPAMP0, - OSTIMER0, - - // Normally SWDIO! - #[cfg(feature = "swd-as-gpio")] - P0_0, - // Normally SWCLK! - #[cfg(feature = "swd-as-gpio")] - P0_1, - // Normally SWO! - #[cfg(feature = "swd-swo-as-gpio")] - P0_2, - // Normally JTAG TDI! - #[cfg(feature = "jtag-extras-as-gpio")] - P0_3, - P0_4, - P0_5, - // Normally JTAG ISPMODE_N! - #[cfg(feature = "jtag-extras-as-gpio")] - P0_6, - P0_7, - P0_8, - P0_9, - P0_10, - P0_11, - P0_12, - P0_13, - P0_14, - P0_15, - P0_16, - P0_17, - P0_18, - P0_19, - P0_20, - P0_21, - P0_22, - P0_23, - P0_24, - P0_25, - P0_26, - P0_27, - P0_28, - P0_29, - P0_30, - P0_31, - - P1_0, - P1_1, - P1_2, - P1_3, - P1_4, - P1_5, - P1_6, - P1_7, - P1_8, - P1_9, - P1_10, - P1_11, - P1_12, - P1_13, - P1_14, - P1_15, - P1_16, - P1_17, - P1_18, - P1_19, - P1_20, - P1_21, - P1_22, - P1_23, - P1_24, - P1_25, - P1_26, - P1_27, - P1_28, - #[cfg(feature = "dangerous-reset-as-gpio")] - P1_29, - #[cfg(feature = "sosc-as-gpio")] - P1_30, - #[cfg(feature = "sosc-as-gpio")] - P1_31, - - P2_0, - P2_1, - P2_2, - P2_3, - P2_4, - P2_5, - P2_6, - P2_7, - P2_8, - P2_9, - P2_10, - P2_11, - P2_12, - P2_13, - P2_14, - P2_15, - P2_16, - P2_17, - P2_18, - P2_19, - P2_20, - P2_21, - P2_22, - P2_23, - P2_24, - P2_25, - P2_26, - P2_27, - P2_28, - P2_29, - P2_30, - P2_31, - - P3_0, - P3_1, - P3_2, - P3_3, - P3_4, - P3_5, - P3_6, - P3_7, - P3_8, - P3_9, - P3_10, - P3_11, - P3_12, - P3_13, - P3_14, - P3_15, - P3_16, - P3_17, - P3_18, - P3_19, - P3_20, - P3_21, - P3_22, - P3_23, - P3_24, - P3_25, - P3_26, - P3_27, - P3_28, - P3_29, - P3_30, - P3_31, - - P4_0, - P4_1, - P4_2, - P4_3, - P4_4, - P4_5, - P4_6, - P4_7, - P4_8, - P4_9, - P4_10, - P4_11, - P4_12, - P4_13, - P4_14, - P4_15, - P4_16, - P4_17, - P4_18, - P4_19, - P4_20, - P4_21, - P4_22, - P4_23, - P4_24, - P4_25, - P4_26, - P4_27, - P4_28, - P4_29, - P4_30, - P4_31, - - P5_0, - P5_1, - P5_2, - P5_3, - P5_4, - P5_5, - P5_6, - P5_7, - P5_8, - P5_9, - P5_10, - P5_11, - P5_12, - P5_13, - P5_14, - P5_15, - P5_16, - P5_17, - P5_18, - P5_19, - P5_20, - P5_21, - P5_22, - P5_23, - P5_24, - P5_25, - P5_26, - P5_27, - P5_28, - P5_29, - P5_30, - P5_31, - - PKC0, - - PORT0, - PORT1, - PORT2, - PORT3, - PORT4, - - RTC0, - SAU, - SCG0, - SCN_SCB, - SGI0, - SMARTDMA0, - SPC0, - SYSCON, - TDET0, - TRNG0, - UDF0, - USB0, - UTICK0, - VBAT0, - WAKETIMER0, - WUU0, - WWDT0, - ); -} - -// NOTE: Macro has missing safety docs and makes unsafe calls in unsafe fns -pub use inner_interrupt::*; -#[allow(clippy::missing_safety_doc, unsafe_op_in_unsafe_fn)] -mod inner_interrupt { - embassy_hal_internal::interrupt_mod!( - ADC0, - ADC1, - CAN0, - CDOG0, - CDOG1, - CMC, - CMP0, - CMP1, - CTIMER0, - CTIMER1, - CTIMER2, - CTIMER3, - CTIMER4, - DAC0, - DMA0_CH0, - DMA0_CH1, - DMA0_CH2, - DMA0_CH3, - DMA0_CH4, - DMA0_CH5, - DMA0_CH6, - DMA0_CH7, - EQDC0_COMPARE, - EQDC0_HOME, - EQDC0_INDEX, - EQDC0_WATCHDOG, - EQDC1_COMPARE, - EQDC1_HOME, - EQDC1_INDEX, - EQDC1_WATCHDOG, - ERM0_MULTI_BIT, - ERM0_SINGLE_BIT, - FLEXIO, - FLEXPWM0_FAULT, - FLEXPWM0_RELOAD_ERROR, - FLEXPWM0_SUBMODULE0, - FLEXPWM0_SUBMODULE1, - FLEXPWM0_SUBMODULE2, - FLEXPWM0_SUBMODULE3, - FLEXPWM1_FAULT, - FLEXPWM1_RELOAD_ERROR, - FLEXPWM1_SUBMODULE0, - FLEXPWM1_SUBMODULE1, - FLEXPWM1_SUBMODULE2, - FLEXPWM1_SUBMODULE3, - FMU0, - FREQME0, - GLIKEY0, - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - I3C0, - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - LPSPI0, - LPSPI1, - LPTMR0, - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - MAU, - MBC0, - OS_EVENT, - PKC, - RTC, - RTC_1HZ, - SCG0, - SGI, - SMARTDMA, - SPC0, - TDET, - TRNG0, - USB0, - UTICK0, - WAKETIMER0, - WUU0, - WWDT0, - ); -} - /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). pub fn init(cfg: crate::config::Config) -> Peripherals { @@ -527,188 +81,6 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { peripherals } -// Chip specific GPIO impls -mod gpio_impls { - use crate::gpio::{AnyPin, GpioPin, Pull, SealedPin}; - use crate::impl_pin; - use crate::pac::common::{RW, Reg}; - use crate::pac::gpio::{Pdd, Pid}; - use crate::pac::port::{Dse, Ibe, Mux, Pcr, Sre}; - - #[cfg(feature = "swd-as-gpio")] - impl_pin!(P0_0, 0, 0, GPIO0); - #[cfg(feature = "swd-as-gpio")] - impl_pin!(P0_1, 0, 1, GPIO0); - #[cfg(feature = "swd-swo-as-gpio")] - impl_pin!(P0_2, 0, 2, GPIO0); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_3, 0, 3, GPIO0); - impl_pin!(P0_4, 0, 4, GPIO0); - impl_pin!(P0_5, 0, 5, GPIO0); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_6, 0, 6, GPIO0); - impl_pin!(P0_7, 0, 7, GPIO0); - impl_pin!(P0_8, 0, 8, GPIO0); - impl_pin!(P0_9, 0, 9, GPIO0); - impl_pin!(P0_10, 0, 10, GPIO0); - impl_pin!(P0_11, 0, 11, GPIO0); - impl_pin!(P0_12, 0, 12, GPIO0); - impl_pin!(P0_13, 0, 13, GPIO0); - impl_pin!(P0_14, 0, 14, GPIO0); - impl_pin!(P0_15, 0, 15, GPIO0); - impl_pin!(P0_16, 0, 16, GPIO0); - impl_pin!(P0_17, 0, 17, GPIO0); - impl_pin!(P0_18, 0, 18, GPIO0); - impl_pin!(P0_19, 0, 19, GPIO0); - impl_pin!(P0_20, 0, 20, GPIO0); - impl_pin!(P0_21, 0, 21, GPIO0); - impl_pin!(P0_22, 0, 22, GPIO0); - impl_pin!(P0_23, 0, 23, GPIO0); - impl_pin!(P0_24, 0, 24, GPIO0); - impl_pin!(P0_25, 0, 25, GPIO0); - impl_pin!(P0_26, 0, 26, GPIO0); - impl_pin!(P0_27, 0, 27, GPIO0); - impl_pin!(P0_28, 0, 28, GPIO0); - impl_pin!(P0_29, 0, 29, GPIO0); - impl_pin!(P0_30, 0, 30, GPIO0); - impl_pin!(P0_31, 0, 31, GPIO0); - - impl_pin!(P1_0, 1, 0, GPIO1); - impl_pin!(P1_1, 1, 1, GPIO1); - impl_pin!(P1_2, 1, 2, GPIO1); - impl_pin!(P1_3, 1, 3, GPIO1); - impl_pin!(P1_4, 1, 4, GPIO1); - impl_pin!(P1_5, 1, 5, GPIO1); - impl_pin!(P1_6, 1, 6, GPIO1); - impl_pin!(P1_7, 1, 7, GPIO1); - impl_pin!(P1_8, 1, 8, GPIO1); - impl_pin!(P1_9, 1, 9, GPIO1); - impl_pin!(P1_10, 1, 10, GPIO1); - impl_pin!(P1_11, 1, 11, GPIO1); - impl_pin!(P1_12, 1, 12, GPIO1); - impl_pin!(P1_13, 1, 13, GPIO1); - impl_pin!(P1_14, 1, 14, GPIO1); - impl_pin!(P1_15, 1, 15, GPIO1); - impl_pin!(P1_16, 1, 16, GPIO1); - impl_pin!(P1_17, 1, 17, GPIO1); - impl_pin!(P1_18, 1, 18, GPIO1); - impl_pin!(P1_19, 1, 19, GPIO1); - impl_pin!(P1_20, 1, 20, GPIO1); - impl_pin!(P1_21, 1, 21, GPIO1); - impl_pin!(P1_22, 1, 22, GPIO1); - impl_pin!(P1_23, 1, 23, GPIO1); - impl_pin!(P1_24, 1, 24, GPIO1); - impl_pin!(P1_25, 1, 25, GPIO1); - impl_pin!(P1_26, 1, 26, GPIO1); - impl_pin!(P1_27, 1, 27, GPIO1); - impl_pin!(P1_28, 1, 28, GPIO1); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_pin!(P1_29, 1, 29, GPIO1); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, 1, 30, GPIO1); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, 1, 31, GPIO1); - - impl_pin!(P2_0, 2, 0, GPIO2); - impl_pin!(P2_1, 2, 1, GPIO2); - impl_pin!(P2_2, 2, 2, GPIO2); - impl_pin!(P2_3, 2, 3, GPIO2); - impl_pin!(P2_4, 2, 4, GPIO2); - impl_pin!(P2_5, 2, 5, GPIO2); - impl_pin!(P2_6, 2, 6, GPIO2); - impl_pin!(P2_7, 2, 7, GPIO2); - impl_pin!(P2_8, 2, 8, GPIO2); - impl_pin!(P2_9, 2, 9, GPIO2); - impl_pin!(P2_10, 2, 10, GPIO2); - impl_pin!(P2_11, 2, 11, GPIO2); - impl_pin!(P2_12, 2, 12, GPIO2); - impl_pin!(P2_13, 2, 13, GPIO2); - impl_pin!(P2_14, 2, 14, GPIO2); - impl_pin!(P2_15, 2, 15, GPIO2); - impl_pin!(P2_16, 2, 16, GPIO2); - impl_pin!(P2_17, 2, 17, GPIO2); - impl_pin!(P2_18, 2, 18, GPIO2); - impl_pin!(P2_19, 2, 19, GPIO2); - impl_pin!(P2_20, 2, 20, GPIO2); - impl_pin!(P2_21, 2, 21, GPIO2); - impl_pin!(P2_22, 2, 22, GPIO2); - impl_pin!(P2_23, 2, 23, GPIO2); - impl_pin!(P2_24, 2, 24, GPIO2); - impl_pin!(P2_25, 2, 25, GPIO2); - impl_pin!(P2_26, 2, 26, GPIO2); - // impl_pin!(P2_27, 2, 27, GPIO2); - // impl_pin!(P2_28, 2, 28, GPIO2); - // impl_pin!(P2_29, 2, 29, GPIO2); - // impl_pin!(P2_30, 2, 30, GPIO2); - // impl_pin!(P2_31, 2, 31, GPIO2); - - impl_pin!(P3_0, 3, 0, GPIO3); - impl_pin!(P3_1, 3, 1, GPIO3); - impl_pin!(P3_2, 3, 2, GPIO3); - impl_pin!(P3_3, 3, 3, GPIO3); - impl_pin!(P3_4, 3, 4, GPIO3); - impl_pin!(P3_5, 3, 5, GPIO3); - impl_pin!(P3_6, 3, 6, GPIO3); - impl_pin!(P3_7, 3, 7, GPIO3); - impl_pin!(P3_8, 3, 8, GPIO3); - impl_pin!(P3_9, 3, 9, GPIO3); - impl_pin!(P3_10, 3, 10, GPIO3); - impl_pin!(P3_11, 3, 11, GPIO3); - impl_pin!(P3_12, 3, 12, GPIO3); - impl_pin!(P3_13, 3, 13, GPIO3); - impl_pin!(P3_14, 3, 14, GPIO3); - impl_pin!(P3_15, 3, 15, GPIO3); - impl_pin!(P3_16, 3, 16, GPIO3); - impl_pin!(P3_17, 3, 17, GPIO3); - impl_pin!(P3_18, 3, 18, GPIO3); - impl_pin!(P3_19, 3, 19, GPIO3); - impl_pin!(P3_20, 3, 20, GPIO3); - impl_pin!(P3_21, 3, 21, GPIO3); - impl_pin!(P3_22, 3, 22, GPIO3); - impl_pin!(P3_23, 3, 23, GPIO3); - impl_pin!(P3_24, 3, 24, GPIO3); - impl_pin!(P3_25, 3, 25, GPIO3); - impl_pin!(P3_26, 3, 26, GPIO3); - impl_pin!(P3_27, 3, 27, GPIO3); - impl_pin!(P3_28, 3, 28, GPIO3); - impl_pin!(P3_29, 3, 29, GPIO3); - impl_pin!(P3_30, 3, 30, GPIO3); - impl_pin!(P3_31, 3, 31, GPIO3); - - impl_pin!(P4_0, 4, 0, GPIO4); - impl_pin!(P4_1, 4, 1, GPIO4); - impl_pin!(P4_2, 4, 2, GPIO4); - impl_pin!(P4_3, 4, 3, GPIO4); - impl_pin!(P4_4, 4, 4, GPIO4); - impl_pin!(P4_5, 4, 5, GPIO4); - impl_pin!(P4_6, 4, 6, GPIO4); - impl_pin!(P4_7, 4, 7, GPIO4); - // impl_pin!(P4_8, 4, 8, GPIO4); - // impl_pin!(P4_9, 4, 9, GPIO4); - // impl_pin!(P4_10, 4, 10, GPIO4); - // impl_pin!(P4_11, 4, 11, GPIO4); - // impl_pin!(P4_12, 4, 12, GPIO4); - // impl_pin!(P4_13, 4, 13, GPIO4); - // impl_pin!(P4_14, 4, 14, GPIO4); - // impl_pin!(P4_15, 4, 15, GPIO4); - // impl_pin!(P4_16, 4, 16, GPIO4); - // impl_pin!(P4_17, 4, 17, GPIO4); - // impl_pin!(P4_18, 4, 18, GPIO4); - // impl_pin!(P4_19, 4, 19, GPIO4); - // impl_pin!(P4_20, 4, 20, GPIO4); - // impl_pin!(P4_21, 4, 21, GPIO4); - // impl_pin!(P4_22, 4, 22, GPIO4); - // impl_pin!(P4_23, 4, 23, GPIO4); - // impl_pin!(P4_24, 4, 24, GPIO4); - // impl_pin!(P4_25, 4, 25, GPIO4); - // impl_pin!(P4_26, 4, 26, GPIO4); - // impl_pin!(P4_27, 4, 27, GPIO4); - // impl_pin!(P4_28, 4, 28, GPIO4); - // impl_pin!(P4_29, 4, 29, GPIO4); - // impl_pin!(P4_30, 4, 30, GPIO4); - // impl_pin!(P4_31, 4, 31, GPIO4); -} - /// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, /// for various low level peripherals. pub(crate) mod peripheral_gating { @@ -756,6 +128,7 @@ pub(crate) mod peripheral_gating { impl_cc_gate!(LPUART2, mrcc_glb_acc0, mrcc_glb_rst0, lpuart2, LpuartConfig); impl_cc_gate!(LPUART3, mrcc_glb_acc0, mrcc_glb_rst0, lpuart3, LpuartConfig); impl_cc_gate!(LPUART4, mrcc_glb_acc0, mrcc_glb_rst0, lpuart4, LpuartConfig); + impl_cc_gate!(LPUART5, mrcc_glb_acc1, mrcc_glb_rst1, lpuart5, LpuartConfig); // DMA0 peripheral - uses NoConfig since it has no selectable clock source impl_cc_gate!(DMA0, mrcc_glb_acc0, mrcc_glb_rst0, dma0, NoConfig); diff --git a/embassy-mcxa/src/chips/mcxa5xx.rs b/embassy-mcxa/src/chips/mcxa5xx.rs index fa04473753..1e0d48702e 100644 --- a/embassy-mcxa/src/chips/mcxa5xx.rs +++ b/embassy-mcxa/src/chips/mcxa5xx.rs @@ -1,462 +1,8 @@ //! Module for MCXA5xx family -pub use inner_periph::{Peripherals, peripherals}; - +use crate::_generated::Peripherals; use crate::interrupt::InterruptExt; -// NOTE: macro generates missing safety docs and unsafe calls in unsafe blocks, -// allow for now, and put in a module so we can apply the rule to that scope. -#[allow(clippy::missing_safety_doc, unsafe_op_in_unsafe_fn)] -mod inner_periph { - #[rustfmt::skip] - embassy_hal_internal::peripherals!( - ADC0, - ADC1, - - // AOI0, - // AOI1, - - // CAN0, - // CAN1, - - CDOG0, - CDOG1, - - // CLKOUT is not specifically a peripheral (it's part of SYSCON), - // but we still want it to be a singleton. - CLKOUT, - - // CMC, - // CMP0, - // CMP1, - CRC0, - - CTIMER0, - - CTIMER0_CH0, - CTIMER0_CH1, - CTIMER0_CH2, - CTIMER0_CH3, - - CTIMER1, - - CTIMER1_CH0, - CTIMER1_CH1, - CTIMER1_CH2, - CTIMER1_CH3, - - CTIMER2, - - CTIMER2_CH0, - CTIMER2_CH1, - CTIMER2_CH2, - CTIMER2_CH3, - - CTIMER3, - - CTIMER3_CH0, - CTIMER3_CH1, - CTIMER3_CH2, - CTIMER3_CH3, - - CTIMER4, - - CTIMER4_CH0, - CTIMER4_CH1, - CTIMER4_CH2, - CTIMER4_CH3, - - // DBGMAILBOX, - - DMA0, - DMA0_CH0, - DMA0_CH1, - DMA0_CH2, - DMA0_CH3, - DMA0_CH4, - DMA0_CH5, - DMA0_CH6, - DMA0_CH7, - // Need more work on the DMA driver before we can enable these - // DMA_CH8, - // DMA_CH9, - // DMA_CH10, - // DMA_CH11, - EDMA0_TCD0, - // Need more work on the DMA driver before we can enable this - // EDMA0_TCD1, - - // EIM0, - // EQDC0, - // EQDC1, - // ERM0, - // FLEXIO0, - // FLEXPWM0, - // FLEXPWM1, - // FMC0, - // FMU0, - // FREQME0, - // GLIKEY0, - - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - GPIO5, - - I3C0, - I3C1, - I3C2, - I3C3, - INPUTMUX0, - - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - - LPSPI0, - LPSPI1, - LPSPI2, - LPSPI3, - LPSPI4, - LPSPI5, - - // LPTMR0, - - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - LPUART5, - - // MAU0, - // MBC0, - // MRCC0, - // OPAMP0, - OSTIMER0, - - // Normally SWDIO! - #[cfg(feature = "swd-as-gpio")] - P0_0, - // Normally SWCLK! - #[cfg(feature = "swd-as-gpio")] - P0_1, - // Normally SWO! - #[cfg(feature = "swd-swo-as-gpio")] - P0_2, - // Normally JTAG TDI! - #[cfg(feature = "jtag-extras-as-gpio")] - P0_3, - P0_4, - P0_5, - // Normally JTAG ISPMODE_N! - #[cfg(feature = "jtag-extras-as-gpio")] - P0_6, - P0_7, - P0_8, - P0_9, - P0_10, - P0_11, - P0_12, - P0_13, - P0_14, - P0_15, - P0_16, - P0_17, - P0_18, - P0_19, - P0_20, - P0_21, - P0_22, - P0_23, - P0_24, - P0_25, - P0_26, - P0_27, - - P1_0, - P1_1, - P1_2, - P1_3, - P1_4, - P1_5, - P1_6, - P1_7, - P1_8, - P1_9, - P1_10, - P1_11, - P1_12, - P1_13, - P1_14, - P1_15, - P1_16, - P1_17, - P1_18, - P1_19, - // Normally RESET_B! - #[cfg(feature = "dangerous-reset-as-gpio")] - P1_29, - // Normally XTAL48M! - #[cfg(feature = "sosc-as-gpio")] - P1_30, - // Normally EXTAL48M! - #[cfg(feature = "sosc-as-gpio")] - P1_31, - - P2_0, - P2_1, - P2_2, - P2_3, - P2_4, - P2_5, - P2_6, - P2_7, - P2_8, - P2_9, - P2_10, - P2_11, - P2_12, - P2_13, - P2_14, - P2_15, - P2_16, - P2_17, - P2_18, - P2_19, - P2_20, - P2_21, - P2_22, - P2_23, - P2_24, - P2_25, - P2_26, - P2_28, - P2_29, - P2_30, - P2_31, - - P3_0, - P3_1, - P3_2, - P3_3, - P3_4, - P3_5, - P3_6, - P3_7, - P3_8, - P3_9, - P3_10, - P3_11, - P3_12, - P3_13, - P3_14, - P3_15, - P3_16, - P3_17, - P3_18, - P3_19, - P3_20, - P3_21, - P3_22, - P3_23, - P3_24, - P3_25, - P3_26, - P3_27, - P3_28, - P3_29, - P3_30, - P3_31, - - P4_0, - P4_1, - P4_2, - P4_3, - P4_4, - P4_5, - P4_6, - P4_7, - P4_8, - P4_9, - P4_10, - P4_11, - P4_12, - P4_13, - - // Normally EXTAL32K! - #[cfg(feature = "rosc-32k-as-gpio")] - P5_0, - // Normally XTAL32K! - #[cfg(feature = "rosc-32k-as-gpio")] - P5_1, - P5_2, - P5_3, - P5_4, - P5_5, - P5_6, - P5_7, - P5_8, - P5_9, - - // PKC0, - - PORT0, - PORT1, - PORT2, - PORT3, - PORT4, - PORT5, - - RTC0, - // SAU, - // SCG0, - // SCN_SCB, - // SGI0, - // SMARTDMA0, - // SPC0, - // SYSCON, - // TDET0, - TRNG0, - // UDF0, - // USB0, - // UTICK0, - // VBAT0, - // WAKETIMER0, - // WUU0, - WWDT0, - WWDT1, - ); -} - -// NOTE: Macro has missing safety docs and makes unsafe calls in unsafe fns -pub use inner_interrupt::*; -#[allow(clippy::missing_safety_doc, unsafe_op_in_unsafe_fn)] -mod inner_interrupt { - #[rustfmt::skip] - embassy_hal_internal::interrupt_mod!( - ADC0, - ADC1, - - // CAN0, - // CAN1, - - CDOG0, - CDOG1, - - // CMC, - - // CMP0, - // CMP1, - // CMP2, - - CTIMER0, - CTIMER1, - CTIMER2, - CTIMER3, - CTIMER4, - - // DAC0, - - DMA0_CH0, - DMA0_CH1, - DMA0_CH2, - DMA0_CH3, - DMA0_CH4, - DMA0_CH5, - DMA0_CH6, - DMA0_CH7, - DMA0_CH8, - DMA0_CH9, - DMA0_CH10, - DMA0_CH11, - DMA1_CH0, - DMA1_CH1, - DMA1_CH2, - DMA1_CH3, - - // EQDC0_COMPARE, - // EQDC0_HOME, - // EQDC0_INDEX, - // EQDC0_WATCHDOG, - // EQDC1_COMPARE, - // EQDC1_HOME, - // EQDC1_INDEX, - // EQDC1_WATCHDOG, - // ERM0_MULTI_BIT, - // ERM0_SINGLE_BIT, - // FLEXIO, - // FLEXPWM0_FAULT, - // FLEXPWM0_RELOAD_ERROR, - // FLEXPWM0_SUBMODULE0, - // FLEXPWM0_SUBMODULE1, - // FLEXPWM0_SUBMODULE2, - // FLEXPWM0_SUBMODULE3, - // FLEXPWM1_FAULT, - // FLEXPWM1_RELOAD_ERROR, - // FLEXPWM1_SUBMODULE0, - // FLEXPWM1_SUBMODULE1, - // FLEXPWM1_SUBMODULE2, - // FLEXPWM1_SUBMODULE3, - // FMU0, - // FREQME0, - // GLIKEY0, - - GPIO0, - GPIO1, - GPIO2, - GPIO3, - GPIO4, - GPIO5, - - I3C0, - I3C1, - I3C2, - I3C3, - - LPI2C0, - LPI2C1, - LPI2C2, - LPI2C3, - - LPSPI0, - LPSPI1, - LPSPI2, - LPSPI3, - LPSPI4, - LPSPI5, - - // LPTMR0, - LPUART0, - LPUART1, - LPUART2, - LPUART3, - LPUART4, - LPUART5, - // MAU, - // MBC0, - OS_EVENT, - // PKC, - RTC0, - // SCG0, - // SGI, - // SLCD, - // SMARTDMA, - // SPC0, - // TDET, - TRNG0, - // USB0, - // UTICK0, - // WAKETIMER0, - // WUU0, - WWDT0, - WWDT1, - ); -} - /// Initialize HAL with configuration (mirrors embassy-imxrt style). Minimal: just take peripherals. /// Also applies configurable NVIC priority for the OSTIMER OS_EVENT interrupt (no enabling). pub fn init(cfg: crate::config::Config) -> Peripherals { @@ -549,169 +95,6 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { peripherals } -// Chip specific GPIO impls -mod gpio_impls { - use crate::gpio::{AnyPin, GpioPin, Pull, SealedPin}; - use crate::impl_pin; - use crate::pac::common::{RW, Reg}; - use crate::pac::gpio::{Pdd, Pid}; - use crate::pac::port::{Dse, Ibe, Mux, Pcr, Sre}; - - #[cfg(feature = "swd-as-gpio")] - impl_pin!(P0_0, 0, 0, GPIO0); - #[cfg(feature = "swd-as-gpio")] - impl_pin!(P0_1, 0, 1, GPIO0); - #[cfg(feature = "swd-swo-as-gpio")] - impl_pin!(P0_2, 0, 2, GPIO0); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_3, 0, 3, GPIO0); - impl_pin!(P0_4, 0, 4, GPIO0); - impl_pin!(P0_5, 0, 5, GPIO0); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_6, 0, 6, GPIO0); - impl_pin!(P0_7, 0, 7, GPIO0); - impl_pin!(P0_8, 0, 8, GPIO0); - impl_pin!(P0_9, 0, 9, GPIO0); - impl_pin!(P0_10, 0, 10, GPIO0); - impl_pin!(P0_11, 0, 11, GPIO0); - impl_pin!(P0_12, 0, 12, GPIO0); - impl_pin!(P0_13, 0, 13, GPIO0); - impl_pin!(P0_14, 0, 14, GPIO0); - impl_pin!(P0_15, 0, 15, GPIO0); - impl_pin!(P0_16, 0, 16, GPIO0); - impl_pin!(P0_17, 0, 17, GPIO0); - impl_pin!(P0_18, 0, 18, GPIO0); - impl_pin!(P0_19, 0, 19, GPIO0); - impl_pin!(P0_20, 0, 20, GPIO0); - impl_pin!(P0_21, 0, 21, GPIO0); - impl_pin!(P0_22, 0, 22, GPIO0); - impl_pin!(P0_23, 0, 23, GPIO0); - impl_pin!(P0_24, 0, 24, GPIO0); - impl_pin!(P0_25, 0, 25, GPIO0); - impl_pin!(P0_26, 0, 26, GPIO0); - impl_pin!(P0_27, 0, 27, GPIO0); - - impl_pin!(P1_0, 1, 0, GPIO1); - impl_pin!(P1_1, 1, 1, GPIO1); - impl_pin!(P1_2, 1, 2, GPIO1); - impl_pin!(P1_3, 1, 3, GPIO1); - impl_pin!(P1_4, 1, 4, GPIO1); - impl_pin!(P1_5, 1, 5, GPIO1); - impl_pin!(P1_6, 1, 6, GPIO1); - impl_pin!(P1_7, 1, 7, GPIO1); - impl_pin!(P1_8, 1, 8, GPIO1); - impl_pin!(P1_9, 1, 9, GPIO1); - impl_pin!(P1_10, 1, 10, GPIO1); - impl_pin!(P1_11, 1, 11, GPIO1); - impl_pin!(P1_12, 1, 12, GPIO1); - impl_pin!(P1_13, 1, 13, GPIO1); - impl_pin!(P1_14, 1, 14, GPIO1); - impl_pin!(P1_15, 1, 15, GPIO1); - impl_pin!(P1_16, 1, 16, GPIO1); - impl_pin!(P1_17, 1, 17, GPIO1); - impl_pin!(P1_18, 1, 18, GPIO1); - impl_pin!(P1_19, 1, 19, GPIO1); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_pin!(P1_29, 1, 29, GPIO1); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, 1, 30, GPIO1); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, 1, 31, GPIO1); - - impl_pin!(P2_0, 2, 0, GPIO2); - impl_pin!(P2_1, 2, 1, GPIO2); - impl_pin!(P2_2, 2, 2, GPIO2); - impl_pin!(P2_3, 2, 3, GPIO2); - impl_pin!(P2_4, 2, 4, GPIO2); - impl_pin!(P2_5, 2, 5, GPIO2); - impl_pin!(P2_6, 2, 6, GPIO2); - impl_pin!(P2_7, 2, 7, GPIO2); - impl_pin!(P2_8, 2, 8, GPIO2); - impl_pin!(P2_9, 2, 9, GPIO2); - impl_pin!(P2_10, 2, 10, GPIO2); - impl_pin!(P2_11, 2, 11, GPIO2); - impl_pin!(P2_12, 2, 12, GPIO2); - impl_pin!(P2_13, 2, 13, GPIO2); - impl_pin!(P2_14, 2, 14, GPIO2); - impl_pin!(P2_15, 2, 15, GPIO2); - impl_pin!(P2_16, 2, 16, GPIO2); - impl_pin!(P2_17, 2, 17, GPIO2); - impl_pin!(P2_18, 2, 18, GPIO2); - impl_pin!(P2_19, 2, 19, GPIO2); - impl_pin!(P2_20, 2, 20, GPIO2); - impl_pin!(P2_21, 2, 21, GPIO2); - impl_pin!(P2_22, 2, 22, GPIO2); - impl_pin!(P2_23, 2, 23, GPIO2); - impl_pin!(P2_24, 2, 24, GPIO2); - impl_pin!(P2_25, 2, 25, GPIO2); - impl_pin!(P2_26, 2, 26, GPIO2); - impl_pin!(P2_28, 2, 28, GPIO2); - impl_pin!(P2_29, 2, 29, GPIO2); - impl_pin!(P2_30, 2, 30, GPIO2); - impl_pin!(P2_31, 2, 31, GPIO2); - - impl_pin!(P3_0, 3, 0, GPIO3); - impl_pin!(P3_1, 3, 1, GPIO3); - impl_pin!(P3_2, 3, 2, GPIO3); - impl_pin!(P3_3, 3, 3, GPIO3); - impl_pin!(P3_4, 3, 4, GPIO3); - impl_pin!(P3_5, 3, 5, GPIO3); - impl_pin!(P3_6, 3, 6, GPIO3); - impl_pin!(P3_7, 3, 7, GPIO3); - impl_pin!(P3_8, 3, 8, GPIO3); - impl_pin!(P3_9, 3, 9, GPIO3); - impl_pin!(P3_10, 3, 10, GPIO3); - impl_pin!(P3_11, 3, 11, GPIO3); - impl_pin!(P3_12, 3, 12, GPIO3); - impl_pin!(P3_13, 3, 13, GPIO3); - impl_pin!(P3_14, 3, 14, GPIO3); - impl_pin!(P3_15, 3, 15, GPIO3); - impl_pin!(P3_16, 3, 16, GPIO3); - impl_pin!(P3_17, 3, 17, GPIO3); - impl_pin!(P3_18, 3, 18, GPIO3); - impl_pin!(P3_19, 3, 19, GPIO3); - impl_pin!(P3_20, 3, 20, GPIO3); - impl_pin!(P3_21, 3, 21, GPIO3); - impl_pin!(P3_22, 3, 22, GPIO3); - impl_pin!(P3_23, 3, 23, GPIO3); - impl_pin!(P3_24, 3, 24, GPIO3); - impl_pin!(P3_25, 3, 25, GPIO3); - impl_pin!(P3_26, 3, 26, GPIO3); - impl_pin!(P3_27, 3, 27, GPIO3); - impl_pin!(P3_28, 3, 28, GPIO3); - impl_pin!(P3_29, 3, 29, GPIO3); - impl_pin!(P3_30, 3, 30, GPIO3); - impl_pin!(P3_31, 3, 31, GPIO3); - - impl_pin!(P4_0, 4, 0, GPIO4); - impl_pin!(P4_1, 4, 1, GPIO4); - impl_pin!(P4_2, 4, 2, GPIO4); - impl_pin!(P4_3, 4, 3, GPIO4); - impl_pin!(P4_4, 4, 4, GPIO4); - impl_pin!(P4_5, 4, 5, GPIO4); - impl_pin!(P4_6, 4, 6, GPIO4); - impl_pin!(P4_7, 4, 7, GPIO4); - impl_pin!(P4_8, 4, 8, GPIO4); - impl_pin!(P4_9, 4, 9, GPIO4); - impl_pin!(P4_10, 4, 10, GPIO4); - impl_pin!(P4_11, 4, 11, GPIO4); - impl_pin!(P4_12, 4, 12, GPIO4); - impl_pin!(P4_13, 4, 13, GPIO4); - - #[cfg(feature = "rosc-32k-as-gpio")] - impl_pin!(P5_0, 5, 0, GPIO5); - #[cfg(feature = "rosc-32k-as-gpio")] - impl_pin!(P5_1, 5, 1, GPIO5); - impl_pin!(P5_2, 5, 2, GPIO5); - impl_pin!(P5_3, 5, 3, GPIO5); - impl_pin!(P5_4, 5, 4, GPIO5); - impl_pin!(P5_5, 5, 5, GPIO5); - impl_pin!(P5_6, 5, 6, GPIO5); - impl_pin!(P5_7, 5, 7, GPIO5); - impl_pin!(P5_8, 5, 8, GPIO5); - impl_pin!(P5_9, 5, 9, GPIO5); -} - /// This module contains implementations of MRCC APIs, specifically of the [`Gate`] trait, /// for various low level peripherals. pub(crate) mod peripheral_gating { diff --git a/embassy-mcxa/src/clkout.rs b/embassy-mcxa/src/clkout.rs index 5be8ee9648..fb139125b0 100644 --- a/embassy-mcxa/src/clkout.rs +++ b/embassy-mcxa/src/clkout.rs @@ -227,10 +227,10 @@ fn disable_clkout() { mrcc.mrcc_clkout_clksel().write(|w| w.0 = 0b111); } -mod sealed { +pub(crate) mod sealed { use embassy_hal_internal::PeripheralType; - use crate::gpio::{GpioPin, Pull, SealedPin}; + use crate::gpio::GpioPin; /// Sealed marker trait for clockout pins pub trait ClockOutPin: GpioPin + PeripheralType { @@ -238,12 +238,16 @@ mod sealed { fn mux(&self); } - macro_rules! impl_pin { + #[doc(hidden)] + #[macro_export] + macro_rules! impl_clkout_pin { ($pin:ident, $func:ident) => { - impl ClockOutPin for crate::peripherals::$pin { + impl crate::clkout::sealed::ClockOutPin for crate::peripherals::$pin { fn mux(&self) { + use crate::gpio::SealedPin; + self.set_function(crate::pac::port::Mux::$func); - self.set_pull(Pull::Disabled); + self.set_pull(crate::gpio::Pull::Disabled); // TODO: we may want to expose these as options to allow the slew rate // and drive strength for clocks if they are particularly high speed. @@ -254,15 +258,4 @@ mod sealed { } }; } - - // TODO: 5xx reference manual states that P0_6 and P3_8 are clkout pins (Table 352), but the pinmux - // table doesn't list which alt mode corresponds with clkout (Table 340) - #[cfg(feature = "mcxa2xx")] - #[cfg(feature = "jtag-extras-as-gpio")] - impl_pin!(P0_6, MUX12); - #[cfg(feature = "mcxa2xx")] - impl_pin!(P3_8, MUX12); - - impl_pin!(P3_6, MUX1); - impl_pin!(P4_2, MUX1); } diff --git a/embassy-mcxa/src/clocks/periph_helpers/mod.rs b/embassy-mcxa/src/clocks/periph_helpers.rs similarity index 99% rename from embassy-mcxa/src/clocks/periph_helpers/mod.rs rename to embassy-mcxa/src/clocks/periph_helpers.rs index 393aabe62c..f560d0be61 100644 --- a/embassy-mcxa/src/clocks/periph_helpers/mod.rs +++ b/embassy-mcxa/src/clocks/periph_helpers.rs @@ -14,20 +14,6 @@ use crate::pac::mrcc::{ LpspiClkselMux, LpuartClkselMux, OstimerClkselMux, }; -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx; - -#[allow(unused_imports)] -#[cfg(feature = "mcxa2xx")] -pub use mcxa2xx::*; - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx; - -#[allow(unused_imports)] -#[cfg(feature = "mcxa5xx")] -pub use mcxa5xx::*; - #[must_use] pub struct PreEnableParts { /// The frequency fed into the peripheral, taking into account the selected diff --git a/embassy-mcxa/src/clocks/periph_helpers/mcxa2xx.rs b/embassy-mcxa/src/clocks/periph_helpers/mcxa2xx.rs deleted file mode 100644 index e8de45faa8..0000000000 --- a/embassy-mcxa/src/clocks/periph_helpers/mcxa2xx.rs +++ /dev/null @@ -1 +0,0 @@ -//! MCXA2xx only peripheral clocks helpers. diff --git a/embassy-mcxa/src/clocks/periph_helpers/mcxa5xx.rs b/embassy-mcxa/src/clocks/periph_helpers/mcxa5xx.rs deleted file mode 100644 index 6d75109ba2..0000000000 --- a/embassy-mcxa/src/clocks/periph_helpers/mcxa5xx.rs +++ /dev/null @@ -1 +0,0 @@ -//! MCXA5xx only peripheral clocks helpers. diff --git a/embassy-mcxa/src/ctimer/capture.rs b/embassy-mcxa/src/ctimer/capture.rs index 067f9ce40a..a317a8d318 100644 --- a/embassy-mcxa/src/ctimer/capture.rs +++ b/embassy-mcxa/src/ctimer/capture.rs @@ -168,7 +168,7 @@ impl<'d> Capture<'d> { /// /// Upon `Drop`, the external `pin` will be placed into `Disabled` /// state. - pub fn new_with_input_pin, PIN: InputPin>( + pub fn new_with_input_pin, PIN: InputPin>( ctimer: CTimer<'d>, ch: Peri<'d, CH>, pin: Peri<'d, PIN>, diff --git a/embassy-mcxa/src/ctimer/mod.rs b/embassy-mcxa/src/ctimer/mod.rs index 3d0996f37b..b66b29c1f5 100644 --- a/embassy-mcxa/src/ctimer/mod.rs +++ b/embassy-mcxa/src/ctimer/mod.rs @@ -9,7 +9,7 @@ use paste::paste; use crate::clocks::periph_helpers::{CTimerClockSel, CTimerConfig, Div4}; use crate::clocks::{ClockError, Gate, PoweredClock, WakeGuard, enable_and_reset}; -use crate::gpio::{GpioPin, SealedPin}; +use crate::gpio::GpioPin; use crate::{interrupt, pac}; pub mod capture; @@ -249,14 +249,14 @@ impl AnyChannel { embassy_hal_internal::impl_peripheral!(AnyChannel); /// Seal a trait -trait SealedInputPin {} +pub(crate) trait SealedInputPin {} /// Seal a trait -trait SealedOutputPin {} +pub(crate) trait SealedOutputPin {} /// CTimer input pin. #[allow(private_bounds)] -pub trait InputPin: GpioPin + SealedInputPin + PeripheralType { +pub trait InputPin: GpioPin + SealedInputPin + PeripheralType { fn mux(&self); } @@ -266,13 +266,16 @@ pub trait OutputPin: GpioPin + SealedOutputPin + PeripheralType fn mux(&self); } -macro_rules! impl_input_pin { - ($pin:ident, $fn:ident) => { - impl SealedInputPin for crate::peripherals::$pin {} +#[doc(hidden)] +#[macro_export] +macro_rules! impl_ctimer_input_pin { + ($pin:ident, $peri:ident, $fn:ident) => { + impl crate::ctimer::SealedInputPin for crate::peripherals::$pin {} - impl InputPin for crate::peripherals::$pin { + impl crate::ctimer::InputPin for crate::peripherals::$pin { #[inline(always)] fn mux(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); @@ -283,13 +286,16 @@ macro_rules! impl_input_pin { }; } -macro_rules! impl_output_pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_ctimer_output_pin { ($pin:ident, $peri:ident, $fn:ident) => { - impl SealedOutputPin for crate::peripherals::$pin {} + impl crate::ctimer::SealedOutputPin for crate::peripherals::$pin {} - impl OutputPin for crate::peripherals::$pin { + impl crate::ctimer::OutputPin for crate::peripherals::$pin { #[inline(always)] fn mux(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Normal.into()); @@ -299,305 +305,3 @@ macro_rules! impl_output_pin { } }; } - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx { - use super::*; - - // Input pins - #[cfg(feature = "swd-as-gpio")] - impl_input_pin!(P0_0, MUX4); - #[cfg(feature = "swd-as-gpio")] - impl_input_pin!(P0_1, MUX4); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_input_pin!(P0_6, MUX4); - - impl_input_pin!(P0_20, MUX4); - impl_input_pin!(P0_21, MUX4); - impl_input_pin!(P0_22, MUX4); - impl_input_pin!(P0_23, MUX4); - - impl_input_pin!(P1_0, MUX4); - impl_input_pin!(P1_1, MUX4); - impl_input_pin!(P1_2, MUX5); - impl_input_pin!(P1_3, MUX5); - impl_input_pin!(P1_6, MUX4); - impl_input_pin!(P1_7, MUX4); - impl_input_pin!(P1_8, MUX4); - impl_input_pin!(P1_9, MUX4); - impl_input_pin!(P1_14, MUX4); - impl_input_pin!(P1_15, MUX4); - - #[cfg(feature = "sosc-as-gpio")] - impl_input_pin!(P1_30, MUX4); - #[cfg(feature = "sosc-as-gpio")] - impl_input_pin!(P1_31, MUX4); - - impl_input_pin!(P2_0, MUX4); - impl_input_pin!(P2_1, MUX4); - impl_input_pin!(P2_2, MUX4); - impl_input_pin!(P2_3, MUX4); - impl_input_pin!(P2_4, MUX4); - impl_input_pin!(P2_5, MUX4); - impl_input_pin!(P2_6, MUX4); - impl_input_pin!(P2_7, MUX4); - - impl_input_pin!(P3_0, MUX4); - impl_input_pin!(P3_1, MUX4); - impl_input_pin!(P3_8, MUX4); - impl_input_pin!(P3_9, MUX4); - impl_input_pin!(P3_14, MUX4); - impl_input_pin!(P3_15, MUX4); - impl_input_pin!(P3_16, MUX4); - impl_input_pin!(P3_17, MUX4); - impl_input_pin!(P3_22, MUX4); - impl_input_pin!(P3_27, MUX4); - impl_input_pin!(P3_28, MUX4); - impl_input_pin!(P3_29, MUX4); - - impl_input_pin!(P4_6, MUX4); - impl_input_pin!(P4_7, MUX4); - - // Output pins - #[cfg(feature = "swd-swo-as-gpio")] - impl_output_pin!(P0_2, CTIMER0, MUX4); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_output_pin!(P0_3, CTIMER0, MUX4); - impl_output_pin!(P0_16, CTIMER0, MUX4); - impl_output_pin!(P0_17, CTIMER0, MUX4); - impl_output_pin!(P0_18, CTIMER0, MUX4); - impl_output_pin!(P0_19, CTIMER0, MUX4); - impl_output_pin!(P0_22, CTIMER0, MUX5); - impl_output_pin!(P0_23, CTIMER0, MUX5); - - impl_output_pin!(P1_0, CTIMER0, MUX5); - impl_output_pin!(P1_1, CTIMER0, MUX5); - impl_output_pin!(P1_2, CTIMER1, MUX4); - impl_output_pin!(P1_3, CTIMER1, MUX4); - impl_output_pin!(P1_4, CTIMER1, MUX4); - impl_output_pin!(P1_5, CTIMER1, MUX4); - impl_output_pin!(P1_6, CTIMER4, MUX5); - impl_output_pin!(P1_7, CTIMER4, MUX5); - impl_output_pin!(P1_8, CTIMER0, MUX5); - impl_output_pin!(P1_9, CTIMER0, MUX5); - impl_output_pin!(P1_10, CTIMER2, MUX4); - impl_output_pin!(P1_11, CTIMER2, MUX4); - impl_output_pin!(P1_12, CTIMER2, MUX4); - impl_output_pin!(P1_13, CTIMER2, MUX4); - impl_output_pin!(P1_14, CTIMER3, MUX5); - impl_output_pin!(P1_15, CTIMER3, MUX5); - - impl_output_pin!(P2_0, CTIMER2, MUX5); - impl_output_pin!(P2_1, CTIMER2, MUX5); - impl_output_pin!(P2_2, CTIMER2, MUX5); - impl_output_pin!(P2_3, CTIMER2, MUX5); - impl_output_pin!(P2_4, CTIMER1, MUX5); - impl_output_pin!(P2_5, CTIMER1, MUX5); - impl_output_pin!(P2_6, CTIMER1, MUX5); - impl_output_pin!(P2_7, CTIMER1, MUX5); - impl_output_pin!(P2_10, CTIMER3, MUX4); - impl_output_pin!(P2_11, CTIMER3, MUX4); - impl_output_pin!(P2_12, CTIMER4, MUX4); - impl_output_pin!(P2_12, CTIMER0, MUX5); - impl_output_pin!(P2_13, CTIMER4, MUX4); - impl_output_pin!(P2_13, CTIMER0, MUX5); - impl_output_pin!(P2_15, CTIMER4, MUX5); - impl_output_pin!(P2_15, CTIMER0, MUX5); - impl_output_pin!(P2_16, CTIMER3, MUX5); - impl_output_pin!(P2_16, CTIMER0, MUX5); - impl_output_pin!(P2_17, CTIMER3, MUX5); - impl_output_pin!(P2_17, CTIMER0, MUX5); - impl_output_pin!(P2_19, CTIMER3, MUX4); - impl_output_pin!(P2_20, CTIMER2, MUX4); - impl_output_pin!(P2_21, CTIMER2, MUX4); - impl_output_pin!(P2_23, CTIMER2, MUX4); - - impl_output_pin!(P3_2, CTIMER4, MUX4); - impl_output_pin!(P3_6, CTIMER4, MUX4); - impl_output_pin!(P3_7, CTIMER4, MUX4); - impl_output_pin!(P3_10, CTIMER1, MUX4); - impl_output_pin!(P3_11, CTIMER1, MUX4); - impl_output_pin!(P3_12, CTIMER1, MUX4); - impl_output_pin!(P3_13, CTIMER1, MUX4); - impl_output_pin!(P3_18, CTIMER2, MUX4); - impl_output_pin!(P3_19, CTIMER2, MUX4); - impl_output_pin!(P3_20, CTIMER2, MUX4); - impl_output_pin!(P3_21, CTIMER2, MUX4); - impl_output_pin!(P3_27, CTIMER3, MUX5); - impl_output_pin!(P3_28, CTIMER3, MUX5); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_output_pin!(P3_29, CTIMER3, MUX5); - #[cfg(feature = "sosc-as-gpio")] - impl_output_pin!(P3_30, CTIMER0, MUX4); - #[cfg(feature = "sosc-as-gpio")] - impl_output_pin!(P3_31, CTIMER0, MUX4); - - impl_output_pin!(P4_2, CTIMER4, MUX4); - impl_output_pin!(P4_3, CTIMER4, MUX4); - impl_output_pin!(P4_4, CTIMER4, MUX4); - impl_output_pin!(P4_5, CTIMER4, MUX4); -} - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx { - use super::*; - - // Input pins - #[cfg(feature = "swd-as-gpio")] - impl_input_pin!(P0_0, MUX4); - #[cfg(feature = "swd-as-gpio")] - impl_input_pin!(P0_1, MUX4); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_input_pin!(P0_6, MUX4); - impl_input_pin!(P0_7, MUX4); - impl_input_pin!(P0_14, MUX4); - impl_input_pin!(P0_15, MUX4); - impl_input_pin!(P0_20, MUX4); - impl_input_pin!(P0_21, MUX4); - impl_input_pin!(P0_22, MUX4); - impl_input_pin!(P0_23, MUX4); - - impl_input_pin!(P1_0, MUX4); - impl_input_pin!(P1_1, MUX4); - impl_input_pin!(P1_2, MUX5); - impl_input_pin!(P1_3, MUX5); - impl_input_pin!(P1_6, MUX4); - impl_input_pin!(P1_7, MUX4); - impl_input_pin!(P1_8, MUX4); - impl_input_pin!(P1_9, MUX4); - impl_input_pin!(P1_16, MUX4); - impl_input_pin!(P1_17, MUX4); - #[cfg(feature = "sosc-as-gpio")] - impl_input_pin!(P1_30, MUX4); - #[cfg(feature = "sosc-as-gpio")] - impl_input_pin!(P1_31, MUX4); - - impl_input_pin!(P2_0, MUX4); - impl_input_pin!(P2_1, MUX4); - impl_input_pin!(P2_2, MUX4); - impl_input_pin!(P2_3, MUX4); - impl_input_pin!(P2_4, MUX4); - impl_input_pin!(P2_5, MUX4); - impl_input_pin!(P2_6, MUX4); - impl_input_pin!(P2_7, MUX4); - impl_input_pin!(P2_24, MUX4); - impl_input_pin!(P2_25, MUX4); - impl_input_pin!(P2_26, MUX4); - - impl_input_pin!(P3_0, MUX4); - impl_input_pin!(P3_1, MUX4); - impl_input_pin!(P3_4, MUX4); - impl_input_pin!(P3_5, MUX4); - impl_input_pin!(P3_8, MUX4); - impl_input_pin!(P3_9, MUX4); - impl_input_pin!(P3_14, MUX4); - impl_input_pin!(P3_15, MUX4); - impl_input_pin!(P3_16, MUX4); - impl_input_pin!(P3_17, MUX4); - impl_input_pin!(P3_22, MUX4); - impl_input_pin!(P3_23, MUX4); - impl_input_pin!(P3_24, MUX4); - impl_input_pin!(P3_25, MUX4); - impl_input_pin!(P3_26, MUX4); - impl_input_pin!(P3_27, MUX4); - impl_input_pin!(P3_28, MUX4); - impl_input_pin!(P3_29, MUX4); - - impl_input_pin!(P4_6, MUX4); - impl_input_pin!(P4_7, MUX4); - - // Output pins - #[cfg(feature = "swd-swo-as-gpio")] - impl_output_pin!(P0_2, CTIMER0, MUX4); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_output_pin!(P0_3, CTIMER0, MUX4); - impl_output_pin!(P0_4, CTIMER0, MUX4); - impl_output_pin!(P0_5, CTIMER0, MUX4); - impl_output_pin!(P0_12, CTIMER0, MUX4); - impl_output_pin!(P0_13, CTIMER0, MUX4); - impl_output_pin!(P0_16, CTIMER0, MUX4); - impl_output_pin!(P0_17, CTIMER0, MUX4); - impl_output_pin!(P0_18, CTIMER0, MUX4); - impl_output_pin!(P0_19, CTIMER0, MUX4); - impl_output_pin!(P0_22, CTIMER0, MUX5); - impl_output_pin!(P0_23, CTIMER0, MUX5); - impl_output_pin!(P0_24, CTIMER0, MUX4); - impl_output_pin!(P0_25, CTIMER0, MUX4); - impl_output_pin!(P0_26, CTIMER0, MUX4); - impl_output_pin!(P0_27, CTIMER0, MUX4); - - impl_output_pin!(P1_0, CTIMER0, MUX5); - impl_output_pin!(P1_1, CTIMER0, MUX5); - impl_output_pin!(P1_2, CTIMER1, MUX4); - impl_output_pin!(P1_3, CTIMER1, MUX4); - impl_output_pin!(P1_4, CTIMER1, MUX4); - impl_output_pin!(P1_5, CTIMER1, MUX4); - impl_output_pin!(P1_6, CTIMER4, MUX5); - impl_output_pin!(P1_7, CTIMER4, MUX5); - impl_output_pin!(P1_8, CTIMER0, MUX5); - impl_output_pin!(P1_9, CTIMER0, MUX5); - impl_output_pin!(P1_10, CTIMER2, MUX4); - impl_output_pin!(P1_11, CTIMER2, MUX4); - impl_output_pin!(P1_12, CTIMER2, MUX4); - impl_output_pin!(P1_13, CTIMER2, MUX4); - impl_output_pin!(P1_14, CTIMER3, MUX5); - impl_output_pin!(P1_15, CTIMER3, MUX5); - impl_output_pin!(P1_18, CTIMER3, MUX4); - impl_output_pin!(P1_19, CTIMER3, MUX4); - - impl_output_pin!(P2_0, CTIMER2, MUX5); - impl_output_pin!(P2_1, CTIMER2, MUX5); - impl_output_pin!(P2_2, CTIMER2, MUX5); - impl_output_pin!(P2_3, CTIMER2, MUX5); - impl_output_pin!(P2_4, CTIMER1, MUX5); - impl_output_pin!(P2_5, CTIMER1, MUX5); - impl_output_pin!(P2_6, CTIMER1, MUX5); - impl_output_pin!(P2_7, CTIMER1, MUX5); - impl_output_pin!(P2_8, CTIMER3, MUX4); - impl_output_pin!(P2_9, CTIMER3, MUX4); - impl_output_pin!(P2_10, CTIMER3, MUX4); - impl_output_pin!(P2_11, CTIMER3, MUX4); - impl_output_pin!(P2_12, CTIMER0, MUX5); - impl_output_pin!(P2_12, CTIMER4, MUX4); - impl_output_pin!(P2_13, CTIMER0, MUX5); - impl_output_pin!(P2_13, CTIMER4, MUX4); - impl_output_pin!(P2_14, CTIMER4, MUX4); - impl_output_pin!(P2_15, CTIMER0, MUX5); - impl_output_pin!(P2_15, CTIMER4, MUX4); - impl_output_pin!(P2_16, CTIMER0, MUX5); - impl_output_pin!(P2_16, CTIMER3, MUX4); - impl_output_pin!(P2_17, CTIMER0, MUX5); - impl_output_pin!(P2_17, CTIMER3, MUX4); - impl_output_pin!(P2_18, CTIMER3, MUX4); - impl_output_pin!(P2_19, CTIMER3, MUX4); - impl_output_pin!(P2_20, CTIMER2, MUX4); - impl_output_pin!(P2_21, CTIMER2, MUX4); - impl_output_pin!(P2_22, CTIMER2, MUX4); - impl_output_pin!(P2_23, CTIMER2, MUX4); - - impl_output_pin!(P3_2, CTIMER4, MUX4); - impl_output_pin!(P3_3, CTIMER4, MUX4); - impl_output_pin!(P3_6, CTIMER4, MUX4); - impl_output_pin!(P3_7, CTIMER4, MUX4); - impl_output_pin!(P3_10, CTIMER1, MUX4); - impl_output_pin!(P3_11, CTIMER1, MUX4); - impl_output_pin!(P3_12, CTIMER1, MUX4); - impl_output_pin!(P3_13, CTIMER1, MUX4); - impl_output_pin!(P3_18, CTIMER2, MUX4); - impl_output_pin!(P3_19, CTIMER2, MUX4); - impl_output_pin!(P3_20, CTIMER2, MUX4); - impl_output_pin!(P3_21, CTIMER2, MUX4); - impl_output_pin!(P3_27, CTIMER3, MUX5); - impl_output_pin!(P3_28, CTIMER3, MUX5); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_output_pin!(P3_29, CTIMER3, MUX5); - #[cfg(feature = "sosc-as-gpio")] - impl_output_pin!(P3_30, CTIMER0, MUX4); - #[cfg(feature = "sosc-as-gpio")] - impl_output_pin!(P3_31, CTIMER0, MUX4); - - impl_output_pin!(P4_2, CTIMER4, MUX4); - impl_output_pin!(P4_3, CTIMER4, MUX4); - impl_output_pin!(P4_4, CTIMER4, MUX4); - impl_output_pin!(P4_5, CTIMER4, MUX4); -} diff --git a/embassy-mcxa/src/ctimer/pwm.rs b/embassy-mcxa/src/ctimer/pwm.rs index d09b4e16a2..0c44ec7160 100644 --- a/embassy-mcxa/src/ctimer/pwm.rs +++ b/embassy-mcxa/src/ctimer/pwm.rs @@ -532,15 +532,17 @@ impl<'d> SetDutyCycle for Pwm<'d> { } } -trait SealedValidMatchConfig {} +pub(crate) trait SealedValidMatchConfig {} /// Valid match channel + pin configuration marker trait #[allow(private_bounds)] pub trait ValidMatchConfig: SealedValidMatchConfig {} -macro_rules! impl_valid_match { - ($peri:ident, $ch:ident, $pin:ident, $n:literal) => { - impl SealedValidMatchConfig +#[doc(hidden)] +#[macro_export] +macro_rules! impl_ctimer_match { + ($peri:ident, $ch:ident, $pin:ident) => { + impl crate::ctimer::pwm::SealedValidMatchConfig for ( crate::peripherals::$peri, crate::peripherals::$ch, @@ -549,7 +551,7 @@ macro_rules! impl_valid_match { { } - impl ValidMatchConfig + impl crate::ctimer::pwm::ValidMatchConfig for ( crate::peripherals::$peri, crate::peripherals::$ch, @@ -559,201 +561,3 @@ macro_rules! impl_valid_match { } }; } - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx { - use super::*; - - // CTIMER0 match channels - #[cfg(feature = "swd-swo-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_2, 0); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_3, 1); - - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_16, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_17, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P0_18, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P0_19, 3); - - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_22, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_23, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P1_0, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P1_1, 3); - - #[cfg(feature = "sosc-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH2, P3_30, 2); - #[cfg(feature = "sosc-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH3, P3_31, 3); - - // CTIMER1 match channels - impl_valid_match!(CTIMER1, CTIMER1_CH0, P1_2, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P1_3, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P1_4, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P1_5, 3); - - impl_valid_match!(CTIMER1, CTIMER1_CH0, P2_4, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P2_5, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P2_6, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P2_7, 3); - - impl_valid_match!(CTIMER1, CTIMER1_CH0, P3_10, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P3_11, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P3_12, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P3_13, 3); - - // CTIMER2 match channels - impl_valid_match!(CTIMER2, CTIMER2_CH0, P1_10, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P1_11, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P1_12, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P1_13, 3); - - impl_valid_match!(CTIMER2, CTIMER2_CH0, P2_0, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P2_1, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P2_2, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P2_3, 3); - - impl_valid_match!(CTIMER2, CTIMER2_CH0, P2_20, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P2_21, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P2_23, 3); - - impl_valid_match!(CTIMER2, CTIMER2_CH0, P3_18, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P3_19, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P3_20, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P3_21, 3); - - // CTIMER3 match channels - impl_valid_match!(CTIMER3, CTIMER3_CH0, P1_14, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P1_15, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P2_10, 2); - impl_valid_match!(CTIMER3, CTIMER3_CH3, P2_11, 3); - - impl_valid_match!(CTIMER3, CTIMER3_CH0, P2_16, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P2_17, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P2_19, 3); - - impl_valid_match!(CTIMER3, CTIMER3_CH0, P3_27, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P3_28, 2); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_valid_match!(CTIMER3, CTIMER3_CH3, P3_29, 3); - - // CTIMER4 match channels - impl_valid_match!(CTIMER4, CTIMER4_CH0, P1_6, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P1_7, 1); - - impl_valid_match!(CTIMER4, CTIMER4_CH0, P2_12, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P2_13, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P2_15, 3); - - impl_valid_match!(CTIMER4, CTIMER4_CH0, P3_2, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH2, P3_6, 2); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P3_7, 3); - - impl_valid_match!(CTIMER4, CTIMER4_CH0, P4_2, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P4_3, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH2, P4_4, 2); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P4_5, 3); -} - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx { - use super::*; - - // CTIMER0 match channels - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_16, 0); - #[cfg(feature = "swd-swo-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_2, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_22, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH0, P0_24, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH0, P2_12, 0); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_17, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_23, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_25, 1); - #[cfg(feature = "jtag-extras-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH1, P0_3, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH1, P2_13, 1); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P0_12, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P0_18, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P0_26, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P0_4, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P1_0, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P1_8, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P2_15, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH2, P2_16, 2); - #[cfg(feature = "sosc-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH2, P3_30, 2); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P0_13, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P0_19, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P0_27, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P0_5, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P1_1, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P1_9, 3); - impl_valid_match!(CTIMER0, CTIMER0_CH3, P2_17, 3); - #[cfg(feature = "sosc-as-gpio")] - impl_valid_match!(CTIMER0, CTIMER0_CH3, P3_31, 3); - - // CTIMER1 match channels - impl_valid_match!(CTIMER1, CTIMER1_CH0, P1_2, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P1_3, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P1_4, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P1_5, 3); - impl_valid_match!(CTIMER1, CTIMER1_CH0, P2_4, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P2_5, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P2_6, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH0, P3_10, 0); - impl_valid_match!(CTIMER1, CTIMER1_CH1, P3_11, 1); - impl_valid_match!(CTIMER1, CTIMER1_CH2, P3_12, 2); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P2_7, 3); - impl_valid_match!(CTIMER1, CTIMER1_CH3, P3_13, 3); - - // CTIMER2 match channels - impl_valid_match!(CTIMER2, CTIMER2_CH0, P1_10, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH0, P2_0, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH0, P2_20, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH0, P3_18, 0); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P1_11, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P2_1, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P2_21, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH1, P3_19, 1); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P1_12, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P2_2, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P2_22, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH2, P3_20, 2); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P1_13, 3); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P2_23, 3); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P2_3, 3); - impl_valid_match!(CTIMER2, CTIMER2_CH3, P3_21, 3); - - // CTIMER3 match channels - impl_valid_match!(CTIMER3, CTIMER3_CH0, P1_14, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH0, P1_18, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH0, P2_16, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH0, P2_8, 0); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P1_15, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P1_19, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P2_17, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P2_9, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH1, P3_27, 1); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P2_10, 2); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P2_18, 2); - impl_valid_match!(CTIMER3, CTIMER3_CH2, P3_28, 2); - impl_valid_match!(CTIMER3, CTIMER3_CH3, P2_11, 3); - impl_valid_match!(CTIMER3, CTIMER3_CH3, P2_19, 3); - #[cfg(feature = "dangerous-reset-as-gpio")] - impl_valid_match!(CTIMER3, CTIMER3_CH3, P3_29, 3); - - // CTIMER4 match channels - impl_valid_match!(CTIMER4, CTIMER4_CH0, P1_6, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH0, P2_12, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH0, P3_2, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH0, P4_2, 0); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P1_7, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P2_13, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P3_3, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH1, P4_3, 1); - impl_valid_match!(CTIMER4, CTIMER4_CH2, P2_14, 2); - impl_valid_match!(CTIMER4, CTIMER4_CH2, P3_6, 2); - impl_valid_match!(CTIMER4, CTIMER4_CH2, P4_4, 2); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P2_15, 3); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P3_7, 3); - impl_valid_match!(CTIMER4, CTIMER4_CH3, P4_5, 3); -} diff --git a/embassy-mcxa/src/dma.rs b/embassy-mcxa/src/dma.rs index 115cbeede7..016d37e0b4 100644 --- a/embassy-mcxa/src/dma.rs +++ b/embassy-mcxa/src/dma.rs @@ -114,6 +114,7 @@ use core::task::{Context, Poll}; use embassy_hal_internal::{Peri, PeripheralType}; use maitake_sync::WaitCell; +pub(crate) use crate::_generated::DmaRequest; use crate::clocks::enable_and_reset; use crate::clocks::periph_helpers::NoConfig; use crate::dma::sealed::SealedChannel; @@ -298,207 +299,6 @@ pub struct InvalidParameters; /// than this must be split into multiple DMA operations. pub const DMA_MAX_TRANSFER_SIZE: usize = 0x7FFF; -/// DMA request sources -/// -/// (from MCXA266 reference manual PDF attachment "DMA_Configuration.xml") -#[derive(Clone, Copy, Debug)] -#[repr(u8)] -#[allow(dead_code)] -#[cfg(feature = "mcxa2xx")] -pub(crate) enum DmaRequest { - WUU0WakeUpEvent = 1, - CAN0 = 2, - LPI2C2Rx = 3, - LPI2C2Tx = 4, - LPI2C3Rx = 5, - LPI2C3Tx = 6, - I3C0Rx = 7, - I3C0Tx = 8, - LPI2C0Rx = 11, - LPI2C0Tx = 12, - LPI2C1Rx = 13, - LPI2C1Tx = 14, - LPSPI0Rx = 15, - LPSPI0Tx = 16, - LPSPI1Rx = 17, - LPSPI1Tx = 18, - LPUART0Rx = 21, - LPUART0Tx = 22, - LPUART1Rx = 23, - LPUART1Tx = 24, - LPUART2Rx = 25, - LPUART2Tx = 26, - LPUART3Rx = 27, - LPUART3Tx = 28, - LPUART4Rx = 29, - LPUART4Tx = 30, - Ctimer0M0 = 31, - Ctimer0M1 = 32, - Ctimer1M0 = 33, - Ctimer1M1 = 34, - Ctimer2M0 = 35, - Ctimer2M1 = 36, - Ctimer3M0 = 37, - Ctimer3M1 = 38, - Ctimer4M0 = 39, - Ctimer4M1 = 40, - FlexPWM0Capt0 = 41, - FlexPWM0Capt1 = 42, - FlexPWM0Capt2 = 43, - FlexPWM0Capt3 = 44, - FlexPWM0Val0 = 45, - FlexPWM0Val1 = 46, - FlexPWM0Val2 = 47, - FlexPWM0Val3 = 48, - LPTMR0CounterMatchEvent = 49, - ADC0FifoRequest = 51, - ADC1FifoRequest = 52, - CMP0 = 53, - CMP1 = 54, - CMP2 = 55, - DAC0FifoRequest = 56, - GPIO0PinEvent0 = 60, - GPIO1PinEvent0 = 61, - GPIO2PinEvent0 = 62, - GPIO3PinEvent0 = 63, - GPIO4PinEvent0 = 64, - QDC0 = 65, - QDC1 = 66, - FlexIO0SR0 = 71, - FlexIO0SR1 = 72, - FlexIO0SR2 = 73, - FlexIO0SR3 = 74, - FlexPWM1ReqCapt0 = 79, - FlexPWM1ReqCapt1 = 80, - FlexPWM1ReqCapt2 = 81, - FlexPWM1ReqCapt3 = 82, - FlexPWM1ReqVal0 = 83, - FlexPWM1ReqVal1 = 84, - FlexPWM1ReqVal2 = 85, - FlexPWM1ReqVal3 = 86, - CAN1 = 87, - LPUART5Rx = 102, - LPUART5Tx = 103, - MAU0MAU = 115, - SGI0ReqIdat = 119, - SGI0ReqOdat = 120, - ADC2FifoRequest = 123, - ADC3FifoRequest = 124, -} - -/// DMA request sources -/// -/// (from MCXA577 reference manual PDF attachment "DMA_Configuration.xml") -#[derive(Clone, Copy, Debug)] -#[repr(u8)] -#[allow(dead_code)] -#[cfg(feature = "mcxa5xx")] -pub(crate) enum DmaRequest { - WUU0WakeUpEvent = 1, - CAN0 = 2, - LPI2C2Rx = 3, - LPI2C2Tx = 4, - LPI2C3Rx = 5, - LPI2C3Tx = 6, - I3C0Rx = 7, - I3C0Tx = 8, - I3C1Rx = 9, - I3C1Tx = 10, - LPI2C0Rx = 11, - LPI2C0Tx = 12, - LPI2C1Rx = 13, - LPI2C1Tx = 14, - LPSPI0Rx = 15, - LPSPI0Tx = 16, - LPSPI1Rx = 17, - LPSPI1Tx = 18, - LPSPI2Rx = 19, - LPSPI2Tx = 20, - LPUART0Rx = 21, - LPUART0Tx = 22, - LPUART1Rx = 23, - LPUART1Tx = 24, - LPUART2Rx = 25, - LPUART2Tx = 26, - LPUART3Rx = 27, - LPUART3Tx = 28, - LPUART4Rx = 29, - LPUART4Tx = 30, - Ctimer0M0 = 31, - Ctimer0M1 = 32, - Ctimer1M0 = 33, - Ctimer1M1 = 34, - Ctimer2M0 = 35, - Ctimer2M1 = 36, - Ctimer3M0 = 37, - Ctimer3M1 = 38, - Ctimer4M0 = 39, - Ctimer4M1 = 40, - LPTMR0CounterMatchEvent = 49, - ADC0FifoRequest = 51, - ADC1FifoRequest = 52, - CMP0 = 53, - DAC0FifoRequest = 56, - DAC1FifoRequest = 57, - GPIO5PinEvent0 = 59, - GPIO0PinEvent0 = 60, - GPIO1PinEvent0 = 61, - GPIO2PinEvent0 = 62, - GPIO3PinEvent0 = 63, - GPIO4PinEvent0 = 64, - TsiEndOfScan = 69, - TsiOutOfRange = 70, - FlexIO0SR0 = 71, - FlexIO0SR1 = 72, - FlexIO0SR2 = 73, - FlexIO0SR3 = 74, - CAN1 = 87, - EspiCh0 = 92, - EspiCh1 = 93, - LPI2C4Rx = 94, - LPI2C4Tx = 95, - LPSPI3Rx = 96, - LPSPI3Tx = 97, - LPSPI4Rx = 98, - LPSPI4Tx = 99, - LPSPI5Rx = 100, - LPSPI5Tx = 101, - LPUART5Rx = 102, - LPUART5Tx = 103, - I3C2Rx = 106, - I3C2Tx = 107, - I3C3Rx = 108, - I3C3Tx = 109, - FlexSPI0Rx = 110, - FlexSPI0Tx = 111, - ITRCTmprOut0 = 117, - SGI0ReqIdat = 119, - SGI0ReqOdat = 120, - Gpio0PinEvent1 = 132, - Gpio1PinEvent1 = 133, - Gpio2PinEvent1 = 134, - Gpio3PinEvent1 = 135, - Gpio4PinEvent1 = 136, - Gpio5PinEvent1 = 137, -} - -impl DmaRequest { - /// Convert enumerated value into a raw integer - pub const fn number(self) -> u8 { - self as u8 - } - - /// Convert a raw integer into an enumerated value - /// - /// ## SAFETY - /// - /// The given number MUST be one of the defined variant, e.g. a number - /// derived from [`Self::number()`], otherwise it is immediate undefined behavior. - pub unsafe fn from_number_unchecked(num: u8) -> Self { - unsafe { core::mem::transmute(num) } - } -} - mod sealed { /// Sealed trait for DMA channels. pub trait SealedChannel { diff --git a/embassy-mcxa/src/gpio.rs b/embassy-mcxa/src/gpio.rs index f898d5d977..a68d21291c 100644 --- a/embassy-mcxa/src/gpio.rs +++ b/embassy-mcxa/src/gpio.rs @@ -423,10 +423,10 @@ impl GpioPin for AnyPin {} #[doc(hidden)] #[macro_export] -macro_rules! impl_pin { +macro_rules! impl_gpio_pin { ($peri:ident, $port:expr, $pin:expr, $block:ident) => { ::paste::paste! { - impl SealedPin for $crate::peripherals::$peri { + impl crate::gpio::SealedPin for $crate::peripherals::$peri { #[inline(always)] fn port(&self) -> u8 { $port @@ -448,17 +448,17 @@ macro_rules! impl_pin { } #[inline(always)] - fn pcr_reg(&self) -> Reg { + fn pcr_reg(&self) -> crate::pac::common::Reg { self.port_reg().pcr($pin) } #[inline(always)] - fn set_function(&self, function: Mux) { + fn set_function(&self, function: crate::pac::port::Mux) { self.pcr_reg().modify(|w| w.set_mux(function)); } #[inline(always)] - fn set_pull(&self, pull: Pull) { + fn set_pull(&self, pull: crate::gpio::Pull) { let (pull_enable, pull_select) = pull.into(); self.pcr_reg().modify(|w| { w.set_pe(pull_enable); @@ -467,36 +467,37 @@ macro_rules! impl_pin { } #[inline(always)] - fn set_drive_strength(&self, strength: Dse) { + fn set_drive_strength(&self, strength: crate::pac::port::Dse) { self.pcr_reg().modify(|w| w.set_dse(strength)); } #[inline(always)] - fn set_slew_rate(&self, slew_rate: Sre) { + fn set_slew_rate(&self, slew_rate: crate::pac::port::Sre) { self.pcr_reg().modify(|w| w.set_sre(slew_rate)); } #[inline(always)] fn set_enable_input_buffer(&self, buffer_enabled: bool) { + use crate::pac::port::Ibe; self.pcr_reg().modify(|w| w.set_ibe(if buffer_enabled { Ibe::IBE1 } else { Ibe::IBE0 })); } #[inline(always)] fn set_as_disabled(&self) { // Set GPIO direction as input - self.gpio().pddr().modify(|w| w.set_pdd(self.pin() as usize, Pdd::PDD0)); + self.gpio().pddr().modify(|w| w.set_pdd(self.pin() as usize, crate::pac::gpio::Pdd::PDD0)); // Set input buffer as disabled self.set_enable_input_buffer(false); // Set mode as GPIO (vs other potential functions) - self.set_function(Mux::MUX0); + self.set_function(crate::pac::port::Mux::MUX0); // Set pin as disabled - self.gpio().pidr().modify(|w| w.set_pid(self.pin() as usize, Pid::PID1)); + self.gpio().pidr().modify(|w| w.set_pid(self.pin() as usize, crate::pac::gpio::Pid::PID1)); } } - impl GpioPin for crate::peripherals::$peri {} + impl crate::gpio::GpioPin for crate::peripherals::$peri {} - impl From for AnyPin { + impl From for crate::gpio::AnyPin { fn from(value: crate::peripherals::$peri) -> Self { value.degrade() } @@ -504,8 +505,10 @@ macro_rules! impl_pin { impl crate::peripherals::$peri { /// Convenience helper to obtain a type-erased handle to this pin. - pub fn degrade(&self) -> AnyPin { - AnyPin::new( + pub fn degrade(&self) -> crate::gpio::AnyPin { + use crate::gpio::SealedPin; + + crate::gpio::AnyPin::new( self.port(), self.pin(), self.gpio(), @@ -524,13 +527,14 @@ macro_rules! impl_pin { ::Interrupt, crate::gpio::InterruptHandler, >, - ) -> embassy_hal_internal::Peri<'p, AnyPin> { + ) -> embassy_hal_internal::Peri<'p, crate::gpio::AnyPin> { use crate::interrupt::typelevel::Interrupt; + use crate::gpio::SealedPin; unsafe { <::Instance as crate::gpio::Instance>::Interrupt::enable(); } unsafe { - embassy_hal_internal::Peri::new_unchecked(AnyPin::new( + embassy_hal_internal::Peri::new_unchecked(crate::gpio::AnyPin::new( this.port(), this.pin(), this.gpio(), diff --git a/embassy-mcxa/src/i2c/mod.rs b/embassy-mcxa/src/i2c/mod.rs index 232edafc22..a0e14369ea 100644 --- a/embassy-mcxa/src/i2c/mod.rs +++ b/embassy-mcxa/src/i2c/mod.rs @@ -7,15 +7,16 @@ use paste::paste; use crate::clocks::Gate; use crate::clocks::periph_helpers::Lpi2cConfig; use crate::dma::{DmaChannel, DmaRequest}; -use crate::gpio::{GpioPin, SealedPin}; +use crate::gpio::GpioPin; use crate::{interrupt, pac}; pub mod controller; pub mod target; -mod sealed { +pub(crate) mod sealed { /// Seal a trait pub trait Sealed {} + pub trait SealedPin {} } trait SealedInstance: Gate { @@ -72,8 +73,8 @@ macro_rules! impl_instance { = crate::clocks::periph_helpers::Lpi2cInstance::[]; const PERF_INT_INCR: fn() = crate::perf_counters::[]; const PERF_INT_WAKE_INCR: fn() = crate::perf_counters::[]; - const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; - const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; } impl Instance for crate::peripherals::[] { @@ -87,12 +88,27 @@ macro_rules! impl_instance { impl_instance!(0, 1, 2, 3); /// SCL pin trait. -pub trait SclPin: GpioPin + sealed::Sealed + PeripheralType { +pub trait SclPin: GpioPin + sealed::SealedPin + PeripheralType { fn mux(&self); } /// SDA pin trait. -pub trait SdaPin: GpioPin + sealed::Sealed + PeripheralType { +pub trait SdaPin: GpioPin + sealed::SealedPin + PeripheralType { + fn mux(&self); +} + +/// SCLS pin trait. (SCL secondary) +pub trait SclsPin: GpioPin + sealed::SealedPin + PeripheralType { + fn mux(&self); +} + +/// SDAS pin trait. (SDA secondary) +pub trait SdasPin: GpioPin + sealed::SealedPin + PeripheralType { + fn mux(&self); +} + +/// HREQ pin trait. (Host request) +pub trait HreqPin: GpioPin + sealed::SealedPin + PeripheralType { fn mux(&self); } @@ -126,12 +142,15 @@ impl sealed::Sealed for Dma<'_> {} impl Mode for Dma<'_> {} impl AsyncMode for Dma<'_> {} -macro_rules! impl_pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_lpi2c_pin { ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { - impl sealed::Sealed for crate::peripherals::$pin {} + impl crate::i2c::sealed::SealedPin for crate::peripherals::$pin {} - impl $trait for crate::peripherals::$pin { + impl crate::i2c::$trait for crate::peripherals::$pin { fn mux(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); @@ -141,76 +160,3 @@ macro_rules! impl_pin { } }; } - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx { - use super::*; - - impl_pin!(P0_16, LPI2C0, MUX2, SdaPin); - impl_pin!(P0_17, LPI2C0, MUX2, SclPin); - impl_pin!(P0_18, LPI2C0, MUX2, SclPin); - impl_pin!(P0_19, LPI2C0, MUX2, SdaPin); - impl_pin!(P1_0, LPI2C1, MUX3, SdaPin); - impl_pin!(P1_1, LPI2C1, MUX3, SclPin); - impl_pin!(P1_2, LPI2C1, MUX3, SdaPin); - impl_pin!(P1_3, LPI2C1, MUX3, SclPin); - impl_pin!(P1_8, LPI2C2, MUX3, SdaPin); - impl_pin!(P1_9, LPI2C2, MUX3, SclPin); - impl_pin!(P1_10, LPI2C2, MUX3, SdaPin); - impl_pin!(P1_11, LPI2C2, MUX3, SclPin); - impl_pin!(P1_12, LPI2C1, MUX2, SdaPin); - impl_pin!(P1_13, LPI2C1, MUX2, SclPin); - impl_pin!(P1_14, LPI2C1, MUX2, SclPin); - impl_pin!(P1_15, LPI2C1, MUX2, SdaPin); - - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, LPI2C0, MUX3, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, LPI2C0, MUX3, SclPin); - - impl_pin!(P3_27, LPI2C3, MUX2, SclPin); - impl_pin!(P3_28, LPI2C3, MUX2, SdaPin); - // impl_pin!(P3_29, LPI2C3, MUX2, HreqPin); What is this HREQ pin? - impl_pin!(P3_30, LPI2C3, MUX2, SclPin); - impl_pin!(P3_31, LPI2C3, MUX2, SdaPin); - impl_pin!(P4_2, LPI2C2, MUX2, SdaPin); - impl_pin!(P4_3, LPI2C0, MUX2, SclPin); - impl_pin!(P4_4, LPI2C2, MUX2, SdaPin); - impl_pin!(P4_5, LPI2C0, MUX2, SclPin); - // impl_pin!(P4_6, LPI2C0, MUX2, HreqPin); What is this HREQ pin? -} - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx { - use super::*; - - impl_pin!(P0_16, LPI2C0, MUX2, SdaPin); - impl_pin!(P0_17, LPI2C0, MUX2, SclPin); - impl_pin!(P0_18, LPI2C0, MUX2, SclPin); - impl_pin!(P0_19, LPI2C0, MUX2, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, LPI2C0, MUX3, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, LPI2C0, MUX3, SclPin); - - impl_pin!(P1_0, LPI2C1, MUX3, SdaPin); - impl_pin!(P1_1, LPI2C1, MUX3, SclPin); - impl_pin!(P1_12, LPI2C1, MUX2, SdaPin); - impl_pin!(P1_13, LPI2C1, MUX2, SclPin); - impl_pin!(P1_14, LPI2C1, MUX2, SclPin); - impl_pin!(P1_15, LPI2C1, MUX2, SdaPin); - - impl_pin!(P1_8, LPI2C2, MUX3, SdaPin); - impl_pin!(P1_9, LPI2C2, MUX3, SclPin); - impl_pin!(P4_2, LPI2C2, MUX2, SdaPin); - impl_pin!(P4_3, LPI2C2, MUX2, SclPin); - impl_pin!(P4_4, LPI2C2, MUX2, SdaPin); - impl_pin!(P4_5, LPI2C2, MUX2, SclPin); - - impl_pin!(P3_20, LPI2C3, MUX2, SdaPin); - impl_pin!(P3_21, LPI2C3, MUX2, SclPin); - impl_pin!(P3_27, LPI2C3, MUX2, SclPin); - impl_pin!(P3_28, LPI2C3, MUX2, SdaPin); - impl_pin!(P3_30, LPI2C3, MUX2, SclPin); - impl_pin!(P3_31, LPI2C3, MUX2, SdaPin); -} diff --git a/embassy-mcxa/src/i3c/mod.rs b/embassy-mcxa/src/i3c/mod.rs index 99b4d350d4..2b1449cfd9 100644 --- a/embassy-mcxa/src/i3c/mod.rs +++ b/embassy-mcxa/src/i3c/mod.rs @@ -9,7 +9,7 @@ use paste::paste; use crate::clocks::Gate; use crate::clocks::periph_helpers::I3cConfig; use crate::dma::{DmaChannel, DmaRequest}; -use crate::gpio::{GpioPin, SealedPin}; +use crate::gpio::GpioPin; use crate::{interrupt, pac}; pub mod controller; @@ -48,7 +48,7 @@ impl interrupt::typelevel::Handler for InterruptHandl } } -mod sealed { +pub(crate) mod sealed { /// Seal a trait pub trait Sealed {} } @@ -130,6 +130,11 @@ pub trait SdaPin: GpioPin + sealed::Sealed + PeripheralType { fn mux(&self); } +/// PUR pin trait. (Pull up resistance) +pub trait PurPin: GpioPin + sealed::Sealed + PeripheralType { + fn mux(&self); +} + /// Driver mode. #[allow(private_bounds)] pub trait Mode: sealed::Sealed {} @@ -161,13 +166,16 @@ impl sealed::Sealed for Dma<'_> {} impl Mode for Dma<'_> {} impl AsyncMode for Dma<'_> {} -macro_rules! impl_pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_i3c_pin { ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { - paste! { - impl sealed::Sealed for crate::peripherals::$pin {} + paste::paste! { + impl crate::i3c::sealed::Sealed for crate::peripherals::$pin {} - impl $trait for crate::peripherals::$pin { + impl crate::i3c::$trait for crate::peripherals::$pin { fn mux(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); @@ -178,57 +186,3 @@ macro_rules! impl_pin { } }; } - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx_pins { - use super::*; - // impl_pin!(P0_2, I3C0, MUX10, PurPin); REVISIT: what is this for? - impl_pin!(P0_17, I3C0, MUX10, SclPin); - impl_pin!(P0_18, I3C0, MUX10, SdaPin); - impl_pin!(P1_8, I3C0, MUX10, SdaPin); - impl_pin!(P1_9, I3C0, MUX10, SclPin); - // impl_pin!(P1_11, I3C0, MUX10, PurPin); REVISIT: what is this for? - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, I3C0, MUX10, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, I3C0, MUX10, SclPin); -} - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx_pins { - use super::*; - - // impl_pin!(P0_2, I3C0, MUX10, PurPin); REVISIT: what is this for? - impl_pin!(P0_16, I3C0, MUX10, SdaPin); - impl_pin!(P0_17, I3C0, MUX10, SclPin); - impl_pin!(P0_20, I3C0, MUX10, SdaPin); - impl_pin!(P0_21, I3C0, MUX10, SclPin); - // impl_pin!(P0_22, I3C0, MUX10, PurPin); REVISIT: what is this for? - - impl_pin!(P1_5, I3C1, MUX10, SdaPin); - impl_pin!(P1_6, I3C1, MUX10, SdaPin); - impl_pin!(P1_7, I3C1, MUX10, SdaPin); - impl_pin!(P1_8, I3C1, MUX10, SdaPin); - impl_pin!(P1_9, I3C1, MUX10, SclPin); - impl_pin!(P1_14, I3C1, MUX10, SdaPin); - // impl_pin!(P1_15, I3C1, MUX10, PurPin); REVISIT: what is this for? - impl_pin!(P1_16, I3C1, MUX10, SdaPin); - impl_pin!(P1_17, I3C1, MUX10, SclPin); - impl_pin!(P1_18, I3C1, MUX10, SdaPin); - impl_pin!(P1_19, I3C1, MUX10, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_30, I3C2, MUX10, SdaPin); - #[cfg(feature = "sosc-as-gpio")] - impl_pin!(P1_31, I3C2, MUX10, SclPin); - - // impl_pin!(P4_0, I3C2, MUX10, PurPin); REVISIT: what is this for? - // impl_pin!(P4_1, I3C3, MUX10, PurPin); REVISIT: what is this for? - // impl_pin!(P4_12, I3C2, MUX10, PurPin); REVISIT: what is this for? - // impl_pin!(P4_13, I3C3, MUX10, PurPin); REVISIT: what is this for? - impl_pin!(P4_2, I3C3, MUX10, SdaPin); - impl_pin!(P4_3, I3C2, MUX10, SclPin); - impl_pin!(P4_4, I3C2, MUX10, SdaPin); - impl_pin!(P4_5, I3C3, MUX10, SclPin); - impl_pin!(P4_6, I3C3, MUX10, SclPin); - impl_pin!(P4_7, I3C3, MUX10, SdaPin); -} diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs index 3c37ecc089..448a2dd046 100644 --- a/embassy-mcxa/src/lib.rs +++ b/embassy-mcxa/src/lib.rs @@ -13,47 +13,63 @@ #[cfg(feature = "mcxa2xx")] #[path = "."] mod mcxa2xx_exclusive { - pub mod flash; + pub mod flash; // TODO: Add dummy driver to metadata - pub use crate::chips::mcxa2xx::{Peripherals, init, interrupt, peripherals}; + pub use crate::chips::mcxa2xx::init; } /// Module for MCXA5xx-specific HAL drivers #[cfg(feature = "mcxa5xx")] #[path = "."] mod mcxa5xx_exclusive { - pub use crate::chips::mcxa5xx::{Peripherals, init, interrupt, peripherals}; + pub use crate::chips::mcxa5xx::init; } -/// Module for HAL drivers supported by all chips -#[path = "."] -mod all_chips { - pub mod adc; - pub mod cdog; - pub mod clkout; - pub mod clocks; - pub mod config; - pub mod crc; - pub mod ctimer; - pub mod dma; - #[cfg(feature = "executor-platform")] - pub mod executor; - pub mod gpio; - pub mod i2c; - pub mod i3c; - pub mod inputmux; - pub mod lpuart; - pub mod ostimer; - pub mod perf_counters; - pub mod reset_reason; - pub mod rtc; - pub mod spi; - pub mod trng; - pub mod wwdt; -} +#[cfg(mcxa_ADC)] +pub mod adc; +#[cfg(mcxa_CDOG)] +pub mod cdog; +#[cfg(any(mcxa_MRCC5xx, mcxa_MRCC2xx))] +pub mod clkout; // TODO: Add dummy driver to metadata +#[cfg(any(mcxa_MRCC5xx, mcxa_MRCC2xx))] +pub mod clocks; +pub mod config; +#[cfg(mcxa_CRC)] +pub mod crc; +#[cfg(mcxa_CTIMER)] +pub mod ctimer; +#[cfg(mcxa_DMA)] +pub mod dma; +#[cfg(feature = "executor-platform")] +pub mod executor; +#[cfg(mcxa_GPIO)] +pub mod gpio; +#[cfg(mcxa_LPI2C)] +pub mod i2c; +#[cfg(mcxa_I3C)] +pub mod i3c; +#[cfg(mcxa_INPUTMUX)] +pub mod inputmux; +#[cfg(mcxa_LPUART)] +pub mod lpuart; +#[cfg(mcxa_OSTIMER)] +pub mod ostimer; +pub mod perf_counters; +#[cfg(mcxa_CMC)] +pub mod reset_reason; +#[cfg(mcxa_RTC5xx)] +#[path = "rtc/mcxa5xx.rs"] +pub mod rtc; +#[cfg(mcxa_RTC2xx)] +#[path = "rtc/mcxa2xx.rs"] +pub mod rtc; +#[cfg(mcxa_LPSPI)] +pub mod spi; +#[cfg(mcxa_TRNG)] +pub mod trng; +#[cfg(mcxa_WWDT)] +pub mod wwdt; -#[allow(unused_imports)] -pub use all_chips::*; #[cfg(feature = "mcxa2xx")] pub use mcxa2xx_exclusive::*; #[cfg(feature = "mcxa5xx")] @@ -61,6 +77,19 @@ pub use mcxa5xx_exclusive::*; pub(crate) mod chips; +pub(crate) mod _generated { + #![allow(dead_code)] + #![allow(unused_imports)] + #![allow(non_snake_case)] + #![allow(missing_docs)] + + use crate::{ + impl_adc_pin, impl_clkout_pin, impl_ctimer_input_pin, impl_ctimer_match, impl_ctimer_output_pin, impl_gpio_pin, + impl_i3c_pin, impl_lpi2c_pin, impl_lpuart_pin, impl_spi_pin, + }; + include!(concat!(env!("OUT_DIR"), "/_generated.rs")); +} + // Re-export interrupt traits and types // Re-export Peri and PeripheralType to allow applications to express Peri types and requirements. pub use embassy_hal_internal::{Peri, PeripheralType}; @@ -69,6 +98,8 @@ pub use nxp_pac as pac; #[cfg(not(feature = "unstable-pac"))] pub(crate) use nxp_pac as pac; +pub use crate::_generated::{Peripherals, interrupt, peripherals}; + const HALS_SELECTED: usize = const { cfg!(feature = "mcxa2xx") as usize + cfg!(feature = "mcxa5xx") as usize }; /// Ensure exactly one chip feature is set. diff --git a/embassy-mcxa/src/lpuart/mod.rs b/embassy-mcxa/src/lpuart/mod.rs index b879234203..a996d716f1 100644 --- a/embassy-mcxa/src/lpuart/mod.rs +++ b/embassy-mcxa/src/lpuart/mod.rs @@ -155,8 +155,8 @@ macro_rules! impl_instance { const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance = crate::clocks::periph_helpers::LpuartInstance::[]; - const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; - const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; const PERF_INT_INCR: fn() = crate::perf_counters::[]; const PERF_INT_WAKE_INCR: fn() = crate::perf_counters::[]; } @@ -178,9 +178,7 @@ macro_rules! impl_instance { // LPUART3: RX=27, TX=28 -> Lpuart3RxRequest, Lpuart3TxRequest // LPUART4: RX=29, TX=30 -> Lpuart4RxRequest, Lpuart4TxRequest // LPUART5: RX=31, TX=32 -> Lpuart5RxRequest, Lpuart5TxRequest -impl_instance!(0; 1; 2; 3; 4); -#[cfg(feature = "mcxa5xx")] -impl_instance!(5); +impl_instance!(0; 1; 2; 3; 4; 5); /// Perform software reset on the LPUART peripheral fn perform_software_reset(info: &'static Info) { @@ -441,213 +439,59 @@ pub trait RtsPin: Into + sealed::Sealed + PeripheralType { fn as_rts(&self); } -macro_rules! impl_tx_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl TxPin for crate::peripherals::$pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_lpuart_pin { + ($inst:ident, $pin:ident, $alt:ident, TXD) => { + impl crate::lpuart::TxPin for crate::peripherals::$pin { const MUX: crate::pac::port::Mux = crate::pac::port::Mux::$alt; fn as_tx(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Normal.into()); - self.set_function(>::MUX); + self.set_function(>::MUX); self.set_enable_input_buffer(false); } } }; -} - -macro_rules! impl_rx_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl RxPin for crate::peripherals::$pin { + ($inst:ident, $pin:ident, $alt:ident, RXD) => { + impl crate::lpuart::RxPin for crate::peripherals::$pin { const MUX: crate::pac::port::Mux = crate::pac::port::Mux::$alt; fn as_rx(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); - self.set_function(>::MUX); + self.set_function(>::MUX); self.set_enable_input_buffer(true); } } }; -} - -macro_rules! impl_cts_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl CtsPin for crate::peripherals::$pin { + ($inst:ident, $pin:ident, $alt:ident, CTS_B) => { + impl crate::lpuart::CtsPin for crate::peripherals::$pin { const MUX: crate::pac::port::Mux = crate::pac::port::Mux::$alt; fn as_cts(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); - self.set_function(>::MUX); + self.set_function(>::MUX); self.set_enable_input_buffer(true); } } }; -} - -macro_rules! impl_rts_pin { - ($inst:ident, $pin:ident, $alt:ident) => { - impl RtsPin for crate::peripherals::$pin { + ($inst:ident, $pin:ident, $alt:ident, RTS_B) => { + impl crate::lpuart::RtsPin for crate::peripherals::$pin { const MUX: crate::pac::port::Mux = crate::pac::port::Mux::$alt; fn as_rts(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Normal.into()); - self.set_function(>::MUX); + self.set_function(>::MUX); self.set_enable_input_buffer(false); } } }; } -// LPUART 0 -#[cfg(feature = "jtag-extras-as-gpio")] -impl_tx_pin!(LPUART0, P0_3, MUX2); -impl_tx_pin!(LPUART0, P0_21, MUX3); -impl_tx_pin!(LPUART0, P2_1, MUX2); -#[cfg(feature = "mcxa5xx")] -impl_tx_pin!(LPUART0, P4_9, MUX2); - -#[cfg(feature = "swd-swo-as-gpio")] -impl_rx_pin!(LPUART0, P0_2, MUX2); -impl_rx_pin!(LPUART0, P0_20, MUX3); -impl_rx_pin!(LPUART0, P2_0, MUX2); -#[cfg(feature = "mcxa5xx")] -impl_rx_pin!(LPUART0, P4_8, MUX2); - -#[cfg(feature = "swd-as-gpio")] -impl_cts_pin!(LPUART0, P0_1, MUX2); -impl_cts_pin!(LPUART0, P0_23, MUX3); -impl_cts_pin!(LPUART0, P2_3, MUX2); -#[cfg(feature = "mcxa5xx")] -impl_cts_pin!(LPUART0, P4_11, MUX2); - -#[cfg(feature = "swd-as-gpio")] -impl_rts_pin!(LPUART0, P0_0, MUX2); -impl_rts_pin!(LPUART0, P0_22, MUX3); -impl_rts_pin!(LPUART0, P2_2, MUX2); -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART0, P4_10, MUX2); - -// LPUART 1 -impl_tx_pin!(LPUART1, P1_9, MUX2); -impl_tx_pin!(LPUART1, P2_13, MUX3); -impl_tx_pin!(LPUART1, P3_9, MUX3); -impl_tx_pin!(LPUART1, P3_21, MUX3); - -impl_rx_pin!(LPUART1, P1_8, MUX2); -impl_rx_pin!(LPUART1, P2_12, MUX3); -impl_rx_pin!(LPUART1, P3_8, MUX3); -impl_rx_pin!(LPUART1, P3_20, MUX3); - -impl_cts_pin!(LPUART1, P1_11, MUX2); -impl_cts_pin!(LPUART1, P2_17, MUX3); -impl_cts_pin!(LPUART1, P3_11, MUX3); -impl_cts_pin!(LPUART1, P3_23, MUX3); - -impl_rts_pin!(LPUART1, P1_10, MUX2); -impl_rts_pin!(LPUART1, P2_15, MUX3); -impl_rts_pin!(LPUART1, P2_16, MUX3); -impl_rts_pin!(LPUART1, P3_10, MUX3); -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART1, P3_22, MUX3); - -// LPUART 2 -impl_tx_pin!(LPUART2, P1_5, MUX3); -impl_tx_pin!(LPUART2, P1_13, MUX3); -impl_tx_pin!(LPUART2, P2_2, MUX3); -impl_tx_pin!(LPUART2, P2_10, MUX3); -impl_tx_pin!(LPUART2, P3_15, MUX2); - -impl_rx_pin!(LPUART2, P1_4, MUX3); -impl_rx_pin!(LPUART2, P1_12, MUX3); -impl_rx_pin!(LPUART2, P2_3, MUX3); -impl_rx_pin!(LPUART2, P2_11, MUX3); -impl_rx_pin!(LPUART2, P3_14, MUX2); - -impl_cts_pin!(LPUART2, P1_7, MUX3); -impl_cts_pin!(LPUART2, P1_15, MUX3); -impl_cts_pin!(LPUART2, P2_4, MUX3); -impl_cts_pin!(LPUART2, P3_13, MUX2); - -impl_rts_pin!(LPUART2, P1_6, MUX3); -impl_rts_pin!(LPUART2, P1_14, MUX3); -impl_rts_pin!(LPUART2, P2_5, MUX3); -impl_rts_pin!(LPUART2, P3_12, MUX2); - -// LPUART 3 -impl_tx_pin!(LPUART3, P3_1, MUX3); -impl_tx_pin!(LPUART3, P3_12, MUX3); -impl_tx_pin!(LPUART3, P4_5, MUX3); - -impl_rx_pin!(LPUART3, P3_0, MUX3); -impl_rx_pin!(LPUART3, P3_13, MUX3); -impl_rx_pin!(LPUART3, P4_2, MUX3); - -impl_cts_pin!(LPUART3, P3_7, MUX3); -impl_cts_pin!(LPUART3, P3_14, MUX3); -impl_cts_pin!(LPUART3, P4_6, MUX3); - -impl_rts_pin!(LPUART3, P3_6, MUX3); -impl_rts_pin!(LPUART3, P3_15, MUX3); -impl_rts_pin!(LPUART3, P4_7, MUX3); - -// LPUART 4 -impl_tx_pin!(LPUART4, P2_7, MUX3); -impl_tx_pin!(LPUART4, P3_19, MUX2); -impl_tx_pin!(LPUART4, P3_27, MUX3); -impl_tx_pin!(LPUART4, P4_3, MUX3); - -impl_rx_pin!(LPUART4, P2_6, MUX3); -impl_rx_pin!(LPUART4, P3_18, MUX2); -#[cfg(feature = "mcxa2xx")] -impl_rx_pin!(LPUART4, P3_28, MUX3); -impl_rx_pin!(LPUART4, P4_4, MUX3); - -impl_cts_pin!(LPUART4, P2_0, MUX3); -impl_cts_pin!(LPUART4, P3_17, MUX2); -#[cfg(feature = "mcxa2xx")] -impl_cts_pin!(LPUART4, P3_31, MUX3); - -impl_rts_pin!(LPUART4, P2_1, MUX3); -impl_rts_pin!(LPUART4, P3_16, MUX2); -#[cfg(feature = "mcxa2xx")] -impl_rts_pin!(LPUART4, P3_30, MUX3); - -// LPUART 5 -#[cfg(feature = "mcxa5xx")] -impl_tx_pin!(LPUART5, P0_25, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_tx_pin!(LPUART5, P1_10, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_tx_pin!(LPUART5, P1_17, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_tx_pin!(LPUART5, P3_10, MUX8); - -#[cfg(feature = "mcxa5xx")] -impl_rx_pin!(LPUART5, P0_24, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rx_pin!(LPUART5, P1_11, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rx_pin!(LPUART5, P1_16, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rx_pin!(LPUART5, P3_11, MUX8); - -#[cfg(feature = "mcxa5xx")] -impl_cts_pin!(LPUART5, P0_27, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_cts_pin!(LPUART5, P1_12, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_cts_pin!(LPUART5, P1_19, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_cts_pin!(LPUART5, P3_8, MUX8); - -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART5, P0_26, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART5, P1_13, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART5, P1_18, MUX8); -#[cfg(feature = "mcxa5xx")] -impl_rts_pin!(LPUART5, P3_9, MUX8); - /// LPUART error types #[derive(Debug, Copy, Clone, Eq, PartialEq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/embassy-mcxa/src/rtc/mod.rs b/embassy-mcxa/src/rtc/mod.rs deleted file mode 100644 index 43f4ad23a1..0000000000 --- a/embassy-mcxa/src/rtc/mod.rs +++ /dev/null @@ -1,13 +0,0 @@ -//! RTC DateTime driver. - -#[cfg(feature = "mcxa2xx")] -mod mcxa2xx; - -#[cfg(feature = "mcxa2xx")] -pub use mcxa2xx::{Config, DateTime, InterruptHandler, Rtc}; - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx; - -#[cfg(feature = "mcxa5xx")] -pub use mcxa5xx::{Compensation, Config, DateTime, InterruptHandler, Month, Rtc, Weekday}; diff --git a/embassy-mcxa/src/spi/controller.rs b/embassy-mcxa/src/spi/controller.rs index b7697d984c..632fd1987b 100644 --- a/embassy-mcxa/src/spi/controller.rs +++ b/embassy-mcxa/src/spi/controller.rs @@ -10,7 +10,7 @@ use embassy_hal_internal::drop::OnDrop; pub use embedded_hal_1::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity}; use nxp_pac::lpspi::{Cpha, Cpol, Lsbf, Master, Mbf, Outcfg, Pcspol, Pincfg, Prescale, Rrf, Rtf, Rxmsk, Txmsk}; -use super::{Async, AsyncMode, Blocking, Dma, Info, Instance, MisoPin, Mode as IoMode, MosiPin, SckPin}; +use super::{Async, AsyncMode, Blocking, Dma, Info, Instance, Mode as IoMode, SckPin, SdiPin, SdoPin}; use crate::clocks::periph_helpers::{Div4, LpspiClockSel, LpspiConfig}; use crate::clocks::{ClockError, PoweredClock, WakeGuard, enable_and_reset}; use crate::dma::{Channel, DMA_MAX_TRANSFER_SIZE, DmaChannel, TransferOptions}; @@ -364,8 +364,8 @@ impl<'d> Spi<'d, Blocking> { pub fn new_blocking( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - mosi: Peri<'d, impl MosiPin + 'd>, - miso: Peri<'d, impl MisoPin + 'd>, + mosi: Peri<'d, impl SdiPin + 'd>, + miso: Peri<'d, impl SdoPin + 'd>, config: Config, ) -> Result { sck.mux(); @@ -383,7 +383,7 @@ impl<'d> Spi<'d, Blocking> { pub fn new_blocking_txonly( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - mosi: Peri<'d, impl MosiPin + 'd>, + mosi: Peri<'d, impl SdiPin + 'd>, config: Config, ) -> Result { sck.mux(); @@ -399,7 +399,7 @@ impl<'d> Spi<'d, Blocking> { pub fn new_blocking_rxonly( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - miso: Peri<'d, impl MisoPin + 'd>, + miso: Peri<'d, impl SdoPin + 'd>, config: Config, ) -> Result { sck.mux(); @@ -417,8 +417,8 @@ impl<'d> Spi<'d, Async> { pub fn new_async( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - mosi: Peri<'d, impl MosiPin + 'd>, - miso: Peri<'d, impl MisoPin + 'd>, + mosi: Peri<'d, impl SdiPin + 'd>, + miso: Peri<'d, impl SdoPin + 'd>, _irq: impl interrupt::typelevel::Binding> + 'd, config: Config, ) -> Result { @@ -440,7 +440,7 @@ impl<'d> Spi<'d, Async> { pub fn new_async_txonly( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - mosi: Peri<'d, impl MosiPin + 'd>, + mosi: Peri<'d, impl SdiPin + 'd>, _irq: impl interrupt::typelevel::Binding> + 'd, config: Config, ) -> Result { @@ -460,7 +460,7 @@ impl<'d> Spi<'d, Async> { pub fn new_async_rxonly( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - miso: Peri<'d, impl MisoPin + 'd>, + miso: Peri<'d, impl SdoPin + 'd>, _irq: impl interrupt::typelevel::Binding> + 'd, config: Config, ) -> Result { @@ -482,8 +482,8 @@ impl<'d> Spi<'d, Dma<'d>> { pub fn new_async_with_dma( _peri: Peri<'d, T>, sck: Peri<'d, impl SckPin + 'd>, - mosi: Peri<'d, impl MosiPin + 'd>, - miso: Peri<'d, impl MisoPin + 'd>, + mosi: Peri<'d, impl SdiPin + 'd>, + miso: Peri<'d, impl SdoPin + 'd>, tx_dma: Peri<'d, impl Channel>, rx_dma: Peri<'d, impl Channel>, _irq: impl interrupt::typelevel::Binding> + 'd, diff --git a/embassy-mcxa/src/spi/mod.rs b/embassy-mcxa/src/spi/mod.rs index 98b1cc720e..7b32a6c458 100644 --- a/embassy-mcxa/src/spi/mod.rs +++ b/embassy-mcxa/src/spi/mod.rs @@ -6,13 +6,15 @@ use paste::paste; use crate::clocks::Gate; use crate::clocks::periph_helpers::LpspiConfig; use crate::dma::{DmaChannel, DmaRequest}; -use crate::gpio::{GpioPin, SealedPin}; +use crate::gpio::GpioPin; use crate::{interrupt, pac}; pub mod controller; -mod sealed { +pub(crate) mod sealed { /// Seal a trait pub trait Sealed {} + + pub trait SealedSpiPin {} } trait SealedInstance: Gate { @@ -69,8 +71,8 @@ macro_rules! impl_instance { = crate::clocks::periph_helpers::LpspiInstance::[]; const PERF_INT_INCR: fn() = crate::perf_counters::[]; const PERF_INT_WAKE_INCR: fn() = crate::perf_counters::[]; - const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; - const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const TX_DMA_REQUEST: DmaRequest = DmaRequest::[]; + const RX_DMA_REQUEST: DmaRequest = DmaRequest::[]; } impl Instance for crate::peripherals::[] { @@ -86,23 +88,45 @@ impl_instance!(0, 1); #[cfg(feature = "mcxa5xx")] impl_instance!(2, 3, 4, 5); -trait SealedSpiPin {} - -/// MOSI pin trait. +/// MOSI or data pin 0 during parallel data transfers pin trait. #[allow(private_bounds)] -pub trait MosiPin: GpioPin + SealedSpiPin + PeripheralType { +pub trait SdiPin: GpioPin + sealed::SealedSpiPin + PeripheralType { fn mux(&self); } -/// MISO pin trait. +/// MISO or data pin 1 during parallel data transfers pin trait. #[allow(private_bounds)] -pub trait MisoPin: GpioPin + SealedSpiPin + PeripheralType { +pub trait SdoPin: GpioPin + sealed::SealedSpiPin + PeripheralType { fn mux(&self); } /// SCK pin trait. #[allow(private_bounds)] -pub trait SckPin: GpioPin + SealedSpiPin + PeripheralType { +pub trait SckPin: GpioPin + sealed::SealedSpiPin + PeripheralType { + fn mux(&self); +} + +/// Peripheral chip select pin trait. +#[allow(private_bounds)] +pub trait Pcs0Pin: GpioPin + sealed::SealedSpiPin + PeripheralType { + fn mux(&self); +} + +/// Peripheral chip select or host request pin trait. +#[allow(private_bounds)] +pub trait Pcs1Pin: GpioPin + sealed::SealedSpiPin + PeripheralType { + fn mux(&self); +} + +/// Peripheral chip select or data pin 2 during parallel data transfers pin trait. +#[allow(private_bounds)] +pub trait Pcs2Pin: GpioPin + sealed::SealedSpiPin + PeripheralType { + fn mux(&self); +} + +/// Peripheral chip select or data pin 3 during parallel data transfers pin trait. +#[allow(private_bounds)] +pub trait Pcs3Pin: GpioPin + sealed::SealedSpiPin + PeripheralType { fn mux(&self); } @@ -136,12 +160,15 @@ impl sealed::Sealed for Dma<'_> {} impl Mode for Dma<'_> {} impl AsyncMode for Dma<'_> {} -macro_rules! impl_pin { +#[doc(hidden)] +#[macro_export] +macro_rules! impl_spi_pin { ($pin:ident, $peri:ident, $fn:ident, $trait:ident) => { - impl SealedSpiPin for crate::peripherals::$pin {} + impl crate::spi::sealed::SealedSpiPin for crate::peripherals::$pin {} - impl $trait for crate::peripherals::$pin { + impl crate::spi::$trait for crate::peripherals::$pin { fn mux(&self) { + use crate::gpio::SealedPin; self.set_pull(crate::gpio::Pull::Disabled); self.set_slew_rate(crate::gpio::SlewRate::Fast.into()); self.set_drive_strength(crate::gpio::DriveStrength::Double.into()); @@ -151,60 +178,3 @@ macro_rules! impl_pin { } }; } - -#[cfg(feature = "swd-as-gpio")] -impl_pin!(P0_1, LPSPI0, MUX3, MisoPin); -#[cfg(feature = "swd-swo-as-gpio")] -impl_pin!(P0_2, LPSPI0, MUX3, SckPin); -#[cfg(feature = "jtag-extras-as-gpio")] -impl_pin!(P0_3, LPSPI0, MUX3, MosiPin); - -impl_pin!(P1_0, LPSPI0, MUX2, MosiPin); -impl_pin!(P1_1, LPSPI0, MUX2, SckPin); -impl_pin!(P1_2, LPSPI0, MUX2, MisoPin); - -impl_pin!(P2_12, LPSPI1, MUX2, SckPin); -impl_pin!(P2_13, LPSPI1, MUX2, MosiPin); -impl_pin!(P2_15, LPSPI1, MUX2, MisoPin); -impl_pin!(P2_16, LPSPI1, MUX2, MisoPin); - -impl_pin!(P3_8, LPSPI1, MUX2, MosiPin); -impl_pin!(P3_9, LPSPI1, MUX2, MisoPin); -impl_pin!(P3_10, LPSPI1, MUX2, SckPin); - -#[cfg(feature = "mcxa5xx")] -mod mcxa5xx { - use super::*; - - impl_pin!(P0_20, LPSPI4, MUX8, MisoPin); - impl_pin!(P0_21, LPSPI4, MUX8, SckPin); - impl_pin!(P0_22, LPSPI4, MUX8, MosiPin); - - impl_pin!(P1_12, LPSPI5, MUX5, MisoPin); - impl_pin!(P1_13, LPSPI5, MUX5, SckPin); - impl_pin!(P1_14, LPSPI5, MUX8, MosiPin); - - impl_pin!(P2_0, LPSPI2, MUX8, MisoPin); - impl_pin!(P2_1, LPSPI2, MUX8, SckPin); - impl_pin!(P2_2, LPSPI2, MUX8, MosiPin); - - impl_pin!(P3_4, LPSPI4, MUX3, MosiPin); - impl_pin!(P3_3, LPSPI4, MUX3, SckPin); - impl_pin!(P3_2, LPSPI4, MUX3, MisoPin); - impl_pin!(P3_7, LPSPI3, MUX7, SckPin); - impl_pin!(P3_8, LPSPI3, MUX7, MosiPin); - impl_pin!(P3_9, LPSPI3, MUX7, MisoPin); - impl_pin!(P3_14, LPSPI3, MUX7, MisoPin); - impl_pin!(P3_15, LPSPI3, MUX7, MosiPin); - impl_pin!(P3_16, LPSPI3, MUX7, SckPin); - impl_pin!(P3_20, LPSPI3, MUX7, MosiPin); - impl_pin!(P3_21, LPSPI3, MUX7, SckPin); - impl_pin!(P3_22, LPSPI3, MUX7, MisoPin); - - impl_pin!(P4_3, LPSPI2, MUX8, SckPin); - impl_pin!(P4_4, LPSPI2, MUX8, MisoPin); - impl_pin!(P4_5, LPSPI2, MUX8, MosiPin); - impl_pin!(P4_8, LPSPI5, MUX8, MosiPin); - impl_pin!(P4_9, LPSPI5, MUX8, MisoPin); - impl_pin!(P4_10, LPSPI5, MUX8, SckPin); -} diff --git a/examples/mcxa2xx/src/bin/spi-async.rs b/examples/mcxa2xx/src/bin/spi-async.rs index 4bd9529dff..f6bdb68604 100644 --- a/examples/mcxa2xx/src/bin/spi-async.rs +++ b/examples/mcxa2xx/src/bin/spi-async.rs @@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) { let mut config = controller::Config::default(); config.frequency = 1_000_000; - let mut spi = Spi::new_async(p.LPSPI1, p.P3_10, p.P3_8, p.P3_9, Irqs, config).unwrap(); + let mut spi = Spi::new_async(p.LPSPI1, p.P3_10, p.P3_9, p.P3_8, Irqs, config).unwrap(); let mut rx_buf = [0u8; 32]; let tx_buf = [0x55u8; 32]; diff --git a/examples/mcxa2xx/src/bin/spi-blocking.rs b/examples/mcxa2xx/src/bin/spi-blocking.rs index d2d0e6bc86..d88d1ace55 100644 --- a/examples/mcxa2xx/src/bin/spi-blocking.rs +++ b/examples/mcxa2xx/src/bin/spi-blocking.rs @@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) { let mut config = controller::Config::default(); config.frequency = 1_000_000; - let mut spi = Spi::new_blocking(p.LPSPI1, p.P3_10, p.P3_8, p.P3_9, config).unwrap(); + let mut spi = Spi::new_blocking(p.LPSPI1, p.P3_10, p.P3_9, p.P3_8, config).unwrap(); let mut rx_buf = [0u8; 32]; let tx_buf = [0x55u8; 32]; diff --git a/examples/mcxa2xx/src/bin/spi-dma.rs b/examples/mcxa2xx/src/bin/spi-dma.rs index e0dd6bd115..88aace0255 100644 --- a/examples/mcxa2xx/src/bin/spi-dma.rs +++ b/examples/mcxa2xx/src/bin/spi-dma.rs @@ -29,7 +29,7 @@ async fn main(_spawner: Spawner) { let mut config = controller::Config::default(); config.frequency = 1_000_000; let mut spi = - Spi::new_async_with_dma(p.LPSPI1, p.P3_10, p.P3_8, p.P3_9, p.DMA0_CH0, p.DMA0_CH1, Irqs, config).unwrap(); + Spi::new_async_with_dma(p.LPSPI1, p.P3_10, p.P3_9, p.P3_8, p.DMA0_CH0, p.DMA0_CH1, Irqs, config).unwrap(); let mut rx_buf = [0u8; 32]; let tx_buf = [0xa5u8; 32]; diff --git a/examples/mcxa5xx/src/bin/i2c-target-dma.rs b/examples/mcxa5xx/src/bin/i2c-target-dma.rs index 55cc83bba0..36f546003f 100644 --- a/examples/mcxa5xx/src/bin/i2c-target-dma.rs +++ b/examples/mcxa5xx/src/bin/i2c-target-dma.rs @@ -33,7 +33,7 @@ async fn main(_spawner: Spawner) { // config.address = target::Address::Range(0x20..0x30); let mut target = - target::I2c::new_async_with_dma(p.LPI2C3, p.P3_27, p.P3_28, p.DMA0_CH0, p.DMA0_CH1, Irqs, config).unwrap(); + target::I2c::new_async_with_dma(p.LPI2C3, p.P3_27, p.P3_20, p.DMA0_CH0, p.DMA0_CH1, Irqs, config).unwrap(); let mut buf = [0u8; 256]; loop {