diff --git a/Cargo.lock b/Cargo.lock index 1b56338..642658c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -103,7 +103,7 @@ checksum = "613afe47fcd5fac7ccf1db93babcb082c5994d996f20b8b159f2ad1658eb5724" [[package]] name = "chiptool" version = "0.1.0" -source = "git+https://github.com/embassy-rs/chiptool.git?rev=be1bff3e9e1b27b090e69bd9ac753c66fdcce678#be1bff3e9e1b27b090e69bd9ac753c66fdcce678" +source = "git+https://github.com/embassy-rs/chiptool.git?rev=859f02b7c3408f52c37065de6f1ad1b1bcb0c94a#859f02b7c3408f52c37065de6f1ad1b1bcb0c94a" dependencies = [ "anyhow", "clap", diff --git a/data/metadata/peripherals/README.md b/data/metadata/peripherals/README.md index 6f658da..5c45a47 100644 --- a/data/metadata/peripherals/README.md +++ b/data/metadata/peripherals/README.md @@ -10,8 +10,6 @@ Even though they are assembled by hand, they are derived from the SVD files prov This derivation ideally happens through chiptool transforms, but manual changes to these files are also allowed. When adding manual changes, please note them with appropriate comments in the YAML files. - - ## Updating The generator when using the `extract` command will put transformed SVD data into the `raw` folder. Anything in this folder is not used directly, but can be used by you as a start to define metapac peripherals and chips. @@ -30,4 +28,6 @@ Thus the workflow to add or change a peripheral is as follows: (change MCXA577 t * Copy the file over, and check the changes compared to what was already committed when relevant. * It is also allowed to change the file by hand at this point, but please use comments to denote what and why you changed (and why you didn't use a transform). * Generate the new nxp-pac code by running `cargo run -p generator -- generate MCXA577` -* Check the code changes and commit both the nxp-pac code and the metadata definitions. \ No newline at end of file +* Check the code changes and commit both the nxp-pac code and the metadata definitions. + +This process has been partially captured in the `update.sh` script in this directory. diff --git a/data/metadata/peripherals/mcxa/ADC.yaml b/data/metadata/peripherals/mcxa/ADC.yaml index 58da4b0..e738c79 100644 --- a/data/metadata/peripherals/mcxa/ADC.yaml +++ b/data/metadata/peripherals/mcxa/ADC.yaml @@ -100,7 +100,7 @@ block/Adc: - name: cal_gar description: Calibration General A-Side Registers. array: - len: 34 + len: 33 stride: 4 byte_offset: 1024 fieldset: CalGar @@ -108,6 +108,10 @@ block/Adc: description: Configuration 2 Register. byte_offset: 4088 fieldset: Cfg2 + - name: tst + description: ADC Test Register. + byte_offset: 4092 + fieldset: Tst fieldset/CalGar: description: Calibration General A-Side Registers. fields: @@ -157,6 +161,21 @@ fieldset/Cfg: fieldset/Cfg2: description: Configuration 2 Register. fields: + - name: as_settle + description: Async SAR settling delay. + bit_offset: 0 + bit_size: 2 + enum: AsSettle + - name: as_lto + description: Async SAR latch time out delay. + bit_offset: 2 + bit_size: 2 + enum: AsLto + - name: noise_cancel + description: Noise cancellation delay selection. + bit_offset: 4 + bit_size: 2 + enum: NoiseCancel - name: jleft description: Justified Left Enable register. bit_offset: 8 @@ -227,6 +246,15 @@ fieldset/Cmdl: bit_offset: 7 bit_size: 1 enum: Mode + - name: altb_adch + description: Alternate Channel B Input Channel Select. + bit_offset: 16 + bit_size: 5 + enum: AltbAdch + - name: altben + description: Alternate Channel B Select Enable. + bit_offset: 21 + bit_size: 1 fieldset/Ctrl: description: Control Register. fields: @@ -494,6 +522,30 @@ fieldset/Tctrl: bit_offset: 24 bit_size: 3 enum: Tcmd +fieldset/Tst: + description: ADC Test Register. + fields: + - name: cst_long + description: Calibration Sample Time Long. + bit_offset: 0 + bit_size: 1 + enum: CstLong + - name: foffp + description: Force P-side positive offset. + bit_offset: 9 + bit_size: 1 + - name: foffp2 + description: Force P-side negative offset. + bit_offset: 11 + bit_size: 1 + - name: ipp_do_en + description: Enable FIFO Data out to Pin. + bit_offset: 22 + bit_size: 1 + - name: testen + description: Enable test configuration. + bit_offset: 23 + bit_size: 1 fieldset/Tstat: description: Trigger Status Register. fields: @@ -566,741 +618,834 @@ fieldset/Verid: enum/AdcActive: bit_size: 1 variants: - - name: NOT_ACTIVE + - name: NotActive description: The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. value: 0 - - name: BUSY + - name: Busy description: The ADC is processing a conversion, running through the power up delay, or servicing a trigger. value: 1 +enum/AltbAdch: + bit_size: 5 + variants: + - name: SelectCh0b + description: Select CH0B. + value: 0 + - name: SelectCh1b + description: Select CH1B. + value: 1 + - name: SelectCh2b + description: Select CH2B. + value: 2 + - name: SelectCh3b + description: Select CH3B. + value: 3 + - name: SelectCorrespondingCHnB4 + description: Select corresponding channel CHnB. + value: 4 + - name: SelectCorrespondingCHnB5 + description: Select corresponding channel CHnB. + value: 5 + - name: SelectCorrespondingCHnB6 + description: Select corresponding channel CHnB. + value: 6 + - name: SelectCorrespondingCHnB7 + description: Select corresponding channel CHnB. + value: 7 + - name: SelectCorrespondingCHnB8 + description: Select corresponding channel CHnB. + value: 8 + - name: SelectCorrespondingCHnB9 + description: Select corresponding channel CHnB. + value: 9 + - name: SelectCh30b + description: Select CH30B. + value: 30 + - name: SelectCh31b + description: Select CH31B. + value: 31 +enum/AsLto: + bit_size: 2 + variants: + - name: ShortestDelay + description: Shortest delay. + value: 0 + - name: Mid1Delay + description: Mid 1 delay. + value: 1 + - name: Mid2Delay + description: Mid 2 delay. + value: 2 + - name: LongestDelay + description: Longest delay. + value: 3 +enum/AsSettle: + bit_size: 2 + variants: + - name: ShortestDelay + description: Shortest delay. + value: 0 + - name: Mid1Delay + description: Mid 1 delay. + value: 1 + - name: Mid2Delay + description: Mid 2 delay. + value: 2 + - name: LongestDelay + description: Longest delay. + value: 3 enum/Avgs: bit_size: 4 variants: - - name: NO_AVERAGE + - name: NoAverage description: Single conversion. value: 0 - - name: AVERAGE_2 + - name: Average2 description: 2 conversions averaged. value: 1 - - name: AVERAGE_4 + - name: Average4 description: 4 conversions averaged. value: 2 - - name: AVERAGE_8 + - name: Average8 description: 8 conversions averaged. value: 3 - - name: AVERAGE_16 + - name: Average16 description: 16 conversions averaged. value: 4 - - name: AVERAGE_32 + - name: Average32 description: 32 conversions averaged. value: 5 - - name: AVERAGE_64 + - name: Average64 description: 64 conversions averaged. value: 6 - - name: AVERAGE_128 + - name: Average128 description: 128 conversions averaged. value: 7 - - name: AVERAGE_256 + - name: Average256 description: 256 conversions averaged. value: 8 - - name: AVERAGE_512 + - name: Average512 description: 512 conversions averaged. value: 9 - - name: AVERAGE_1024 + - name: Average1024 description: 1024 conversions averaged. value: 10 enum/CalAvgs: bit_size: 4 variants: - - name: NO_AVERAGE + - name: NoAverage description: Single conversion. value: 0 - - name: AVERAGE_2 + - name: Average2 description: 2 conversions averaged. value: 1 - - name: AVERAGE_4 + - name: Average4 description: 4 conversions averaged. value: 2 - - name: AVERAGE_8 + - name: Average8 description: 8 conversions averaged. value: 3 - - name: AVERAGE_16 + - name: Average16 description: 16 conversions averaged. value: 4 - - name: AVERAGE_32 + - name: Average32 description: 32 conversions averaged. value: 5 - - name: AVERAGE_64 + - name: Average64 description: 64 conversions averaged. value: 6 - - name: AVERAGE_128 + - name: Average128 description: 128 conversions averaged. value: 7 - - name: AVERAGE_256 + - name: Average256 description: 256 conversions averaged. value: 8 - - name: AVERAGE_512 + - name: Average512 description: 512 conversions averaged. value: 9 - - name: AVERAGE_1024 + - name: Average1024 description: 1024 conversions averaged. value: 10 enum/CalRdy: bit_size: 1 variants: - - name: NOT_SET + - name: NotSet description: Calibration is incomplete or hasn't been ran. value: 0 - - name: HARDWARE_CAL_STEP_COMPLETED + - name: HardwareCalStepCompleted description: The ADC is calibrated. value: 1 enum/CalReq: bit_size: 1 variants: - - name: NO_CALIBRATION_REQUEST + - name: NoCalibrationRequest description: No request for hardware calibration has been made. value: 0 - - name: CALIBRATION_REQUEST_PENDING + - name: CalibrationRequestPending description: A request for hardware calibration has been made. value: 1 enum/Calhs: bit_size: 1 variants: - - name: NO_ACTIVE_HS_TRIM_REQUEST + - name: NoActiveHsTrimRequest description: No request for high speed mode trim has been made. value: 0 - - name: HS_TRIM_REQUEST_PENDING + - name: HsTrimRequestPending description: Request for high speed mode trim has been made. value: 1 enum/Calofs: bit_size: 1 variants: - - name: NO_ACTIVE_OFFSET_CALIBRATION_REQUEST + - name: NoActiveOffsetCalibrationRequest description: No request for offset calibration has been made. value: 0 - - name: OFFSET_CALIBRATION_REQUEST_PENDING + - name: OffsetCalibrationRequestPending description: Request for offset calibration function. value: 1 enum/Calofsi: bit_size: 1 variants: - - name: CAL_FUNCTION_NOT_AVAILABLE + - name: CalFunctionNotAvailable description: Calibration Not Implemented. value: 0 - - name: CAL_FUNCTION_AVAILABLE + - name: CalFunctionAvailable description: Calibration Implemented. value: 1 enum/Cmdact: bit_size: 3 variants: - - name: NO_COMMAND_ACTIVE + - name: NoCommandActive description: No command is currently in progress. value: 0 - - name: COMMAND_1 + - name: Command1 description: Command 1 currently being executed. value: 1 - - name: COMMAND_2 + - name: Command2 description: Command 2 currently being executed. value: 2 - - name: COMMAND_X_3 + - name: CommandX3 description: Associated command number is currently being executed. value: 3 - - name: COMMAND_X_4 + - name: CommandX4 description: Associated command number is currently being executed. value: 4 - - name: COMMAND_X_5 + - name: CommandX5 description: Associated command number is currently being executed. value: 5 - - name: COMMAND_X_6 + - name: CommandX6 description: Associated command number is currently being executed. value: 6 - - name: COMMAND_X_7 + - name: CommandX7 description: Associated command number is currently being executed. value: 7 enum/Cmdsrc: bit_size: 3 variants: - - name: NOT_VALID + - name: NotValid description: Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. value: 0 - - name: CMD1 + - name: Cmd1 description: CMD1 buffer used as control settings for this conversion. value: 1 - - name: CORRESPONDING_CMD_2 + - name: CorrespondingCmd2 description: Corresponding command buffer used as control settings for this conversion. value: 2 - - name: CORRESPONDING_CMD_3 + - name: CorrespondingCmd3 description: Corresponding command buffer used as control settings for this conversion. value: 3 - - name: CORRESPONDING_CMD_4 + - name: CorrespondingCmd4 description: Corresponding command buffer used as control settings for this conversion. value: 4 - - name: CORRESPONDING_CMD_5 + - name: CorrespondingCmd5 description: Corresponding command buffer used as control settings for this conversion. value: 5 - - name: CORRESPONDING_CMD_6 + - name: CorrespondingCmd6 description: Corresponding command buffer used as control settings for this conversion. value: 6 - - name: CMD7 + - name: Cmd7 description: CMD7 buffer used as control settings for this conversion. value: 7 enum/Cmpen: bit_size: 2 variants: - - name: DISABLED_ALWAYS_STORE_RESULT + - name: DisabledAlwaysStoreResult description: Compare disabled. value: 0 - - name: COMPARE_RESULT_STORE_IF_TRUE + - name: CompareResultStoreIfTrue description: Compare enabled. Store on true. value: 2 - - name: COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE + - name: CompareResultKeepConvertingUntilTrueStoreIfTrue description: Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. value: 3 +enum/CstLong: + bit_size: 1 + variants: + - name: Sample3p5 + description: Normal sample time. Minimum sample time of 3.5 ADCK cycles. + value: 0 + - name: Sample67p5 + description: Increased sample time. 67.5 ADCK cycles total sample time. + value: 1 enum/Csw: bit_size: 3 variants: - - name: CSCALE_NOT_SUPPORTED + - name: CscaleNotSupported description: Channel scaling not supported. value: 0 - - name: BIT_WIDTH_1 + - name: BitWidth1 description: Channel scaling supported. 1-bit CSCALE control field. value: 1 - - name: BIT_WIDTH_6 + - name: BitWidth6 description: Channel scaling supported. 6-bit CSCALE control field. value: 6 enum/Ctype: bit_size: 2 variants: - - name: SINGLE_ENDED_A_SIDE_CHANNEL + - name: SingleEndedASideChannel description: Single-Ended Mode. Only A side channel is converted. value: 0 enum/Diffen: bit_size: 1 variants: - - name: DIFFERENTIAL_NOT_SUPPORTED + - name: DifferentialNotSupported description: Differential operation not supported. value: 0 - - name: DIFFERENTIAL_SUPPORTED + - name: DifferentialSupported description: Differential operation supported. value: 1 enum/Dozen: bit_size: 1 variants: - - name: ENABLED + - name: Enabled description: ADC is enabled in low power mode. value: 0 - - name: DISABLED + - name: Disabled description: ADC is disabled in low power mode. value: 1 enum/Fifosize: bit_size: 8 variants: - - name: ENTRIES_2 + - name: Entries2 description: Result FIFO depth = 2 dataword. value: 1 - - name: ENTRIES_4 + - name: Entries4 description: Result FIFO depth = 4 datawords. value: 4 - - name: ENTRIES_8 + - name: Entries8 description: Result FIFO depth = 8 datawords. value: 8 - - name: ENTRIES_16 + - name: Entries16 description: Result FIFO depth = 16 datawords. value: 16 - - name: ENTRIES_32 + - name: Entries32 description: Result FIFO depth = 32 datawords. value: 32 - - name: ENTRIES_64 + - name: Entries64 description: Result FIFO depth = 64 datawords. value: 64 enum/Fof0: bit_size: 1 variants: - - name: NO_OVERFLOW + - name: NoOverflow description: No result FIFO 0 overflow has occurred since the last time the flag was cleared. value: 0 - - name: OVERFLOW_DETECTED + - name: OverflowDetected description: At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. value: 1 enum/Gcc0Rdy: bit_size: 1 variants: - - name: GAIN_CAL_NOT_VALID + - name: GainCalNotValid description: The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. value: 0 - - name: HARDWARE_CAL_ROUTINE_COMPLETED + - name: HardwareCalRoutineCompleted description: The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR]. value: 1 enum/HptExdi: bit_size: 1 variants: - - name: ENABLED + - name: Enabled description: High priority trigger exceptions are enabled. value: 0 - - name: DISABLED + - name: Disabled description: High priority trigger exceptions are disabled. value: 1 enum/Hsextra: bit_size: 1 variants: - - name: HSEXTRA_0 - description: No extra cycle added. + - name: Hsextra0 + description: No extra cycle added. Allow 2 ADCK cycles for async SAR operation. value: 0 - - name: HSEXTRA_1 - description: Extra cycle added. + - name: Hsextra1 + description: Extra cycle added. Allow 3 ADCK cycles for async SAR operation. value: 1 enum/Iadcki: bit_size: 1 variants: - - name: INTERNAL_CLK_NOT_AVAILABLE + - name: InternalClkNotAvailable description: Internal clock source not implemented. value: 0 - - name: INTERNAL_CLK_AVAILABLE + - name: InternalClkAvailable description: Internal clock source (and CFG[ADCKEN]) implemented. value: 1 enum/Loop: bit_size: 4 variants: - - name: CMD_EXEC_1X + - name: CmdExec1x description: Looping not enabled. Command executes 1 time. value: 0 - - name: CMD_EXEC_2X + - name: CmdExec2x description: Loop 1 time. Command executes 2 times. value: 1 - - name: CMD_EXEC_3X + - name: CmdExec3x description: Loop 2 times. Command executes 3 times. value: 2 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_3 + - name: CmdExecutesCorrespondingTimes3 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 3 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_4 + - name: CmdExecutesCorrespondingTimes4 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 4 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_5 + - name: CmdExecutesCorrespondingTimes5 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 5 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_6 + - name: CmdExecutesCorrespondingTimes6 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 6 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_7 + - name: CmdExecutesCorrespondingTimes7 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 7 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_8 + - name: CmdExecutesCorrespondingTimes8 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 8 - - name: CMD_EXECUTES_CORRESPONDING_TIMES_9 + - name: CmdExecutesCorrespondingTimes9 description: Loop corresponding number of times. Command executes LOOP+1 times. value: 9 - - name: CMD_EXEC_15X + - name: CmdExec15x description: Loop 15 times. Command executes 16 times. value: 15 enum/Loopcnt: bit_size: 4 variants: - - name: RESULT_1 + - name: Result1 description: Result is from initial conversion in command. value: 0 - - name: RESULT_2 + - name: Result2 description: Result is from second conversion in command. value: 1 - - name: CORRESPONDING_RESULT_2 + - name: CorrespondingResult2 description: Result is from LOOPCNT+1 conversion in command. value: 2 - - name: CORRESPONDING_RESULT_3 + - name: CorrespondingResult3 description: Result is from LOOPCNT+1 conversion in command. value: 3 - - name: CORRESPONDING_RESULT_4 + - name: CorrespondingResult4 description: Result is from LOOPCNT+1 conversion in command. value: 4 - - name: CORRESPONDING_RESULT_5 + - name: CorrespondingResult5 description: Result is from LOOPCNT+1 conversion in command. value: 5 - - name: CORRESPONDING_RESULT_6 + - name: CorrespondingResult6 description: Result is from LOOPCNT+1 conversion in command. value: 6 - - name: CORRESPONDING_RESULT_7 + - name: CorrespondingResult7 description: Result is from LOOPCNT+1 conversion in command. value: 7 - - name: CORRESPONDING_RESULT_8 + - name: CorrespondingResult8 description: Result is from LOOPCNT+1 conversion in command. value: 8 - - name: CORRESPONDING_RESULT_9 + - name: CorrespondingResult9 description: Result is from LOOPCNT+1 conversion in command. value: 9 - - name: RESULT_16 + - name: Result16 description: Result is from 16th conversion in command. value: 15 enum/Mode: bit_size: 1 variants: - - name: DATA_12_BITS + - name: Data12Bits description: Standard resolution. Single-ended 12-bit conversion. value: 0 - - name: DATA_16_BITS + - name: Data16Bits description: High resolution. Single-ended 16-bit conversion. value: 1 enum/Mvi: bit_size: 1 variants: - - name: MULTIPLE_REF_NOT_SUPPORTED + - name: MultipleRefNotSupported description: Single voltage reference high (VREFH) input supported. value: 0 - - name: MULTIPLE_REF_SUPPORTED + - name: MultipleRefSupported description: Multiple voltage reference high (VREFH) inputs supported. value: 1 enum/Next: bit_size: 3 variants: - - name: NO_NEXT_CMD_TERMINATE_ON_FINISH + - name: NoNextCmdTerminateOnFinish description: No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. value: 0 - - name: DO_CMD1_NEXT + - name: DoCmd1Next description: Select CMD1 command buffer register as next command. value: 1 - - name: DO_CORRESPONDING_CMD_NEXT_2 + - name: DoCorrespondingCmdNext2 description: Select corresponding CMD command buffer register as next command. value: 2 - - name: DO_CORRESPONDING_CMD_NEXT_3 + - name: DoCorrespondingCmdNext3 description: Select corresponding CMD command buffer register as next command. value: 3 - - name: DO_CORRESPONDING_CMD_NEXT_4 + - name: DoCorrespondingCmdNext4 description: Select corresponding CMD command buffer register as next command. value: 4 - - name: DO_CORRESPONDING_CMD_NEXT_5 + - name: DoCorrespondingCmdNext5 description: Select corresponding CMD command buffer register as next command. value: 5 - - name: DO_CORRESPONDING_CMD_NEXT_6 + - name: DoCorrespondingCmdNext6 description: Select corresponding CMD command buffer register as next command. value: 6 - - name: DO_CMD7_NEXT + - name: DoCmd7Next description: Select CMD7 command buffer register as next command. value: 7 +enum/NoiseCancel: + bit_size: 2 + variants: + - name: Disabled + description: Noise cancelling disabled. + value: 0 + - name: ShortDelay + description: Shortest delay. + value: 1 + - name: MidDelay + description: Mid delay. + value: 2 + - name: LongestDelay + description: Longest delay. + value: 3 enum/NumFifo: bit_size: 3 variants: - - name: NO_FIFO_IMPLEMENTED + - name: NoFifoImplemented description: N/A. value: 0 - - name: CNT_1 + - name: Cnt1 description: This design supports one result FIFO. value: 1 - - name: CNT_2 + - name: Cnt2 description: This design supports two result FIFOs. value: 2 - - name: CNT_3 + - name: Cnt3 description: This design supports three result FIFOs. value: 3 - - name: CNT_4 + - name: Cnt4 description: This design supports four result FIFOs. value: 4 enum/NumSec: bit_size: 1 variants: - - name: SINGLE_CONVERTOR + - name: SingleConvertor description: This design supports one single ended conversion at a time. value: 0 - - name: DUAL_CONVERTOR + - name: DualConvertor description: This design supports two simultaneous single ended conversions. value: 1 enum/Pwrsel: bit_size: 1 variants: - - name: LOWEST + - name: Lowest description: Low power. value: 0 - - name: HIGHEST + - name: Highest description: High power. value: 1 enum/Rdy0: bit_size: 1 variants: - - name: BELOW_THRESHOLD + - name: BelowThreshold description: Result FIFO 0 data level not above watermark level. value: 0 - - name: ABOVE_THRESHOLD + - name: AboveThreshold description: Result FIFO 0 holding data above watermark level. value: 1 enum/Refsel: bit_size: 2 variants: - - name: OPTION_1 + - name: Option1 description: (Default) Option 1 setting. value: 0 - - name: OPTION_2 + - name: Option2 description: Option 2 setting. value: 1 - - name: OPTION_3 + - name: Option3 description: Option 3 setting. value: 2 enum/Res: bit_size: 1 variants: - - name: MAX_13_BIT + - name: Max13Bit description: Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). value: 0 - - name: MAX_16_BIT + - name: Max16Bit description: Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b). value: 1 enum/Rst: bit_size: 1 variants: - - name: RELEASED_FROM_RESET + - name: ReleasedFromReset description: ADC logic is not reset. value: 0 - - name: HELD_IN_RESET + - name: HeldInReset description: ADC logic is reset. value: 1 enum/Rstfifo0: bit_size: 1 variants: - - name: NO_ACTION + - name: NoAction description: No effect. value: 0 - - name: TRIGGER_RESET + - name: TriggerReset description: FIFO 0 is reset. value: 1 enum/Sts: bit_size: 3 variants: - - name: SAMPLE_3P5 + - name: Sample3p5 description: Minimum sample time of 3.5 ADCK cycles. value: 0 - - name: SAMPLE_5P5 + - name: Sample5p5 description: 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. value: 1 - - name: SAMPLE_7P5 + - name: Sample7p5 description: 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. value: 2 - - name: SAMPLE_11P5 + - name: Sample11p5 description: 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. value: 3 - - name: SAMPLE_19P5 + - name: Sample19p5 description: 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. value: 4 - - name: SAMPLE_35P5 + - name: Sample35p5 description: 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. value: 5 - - name: SAMPLE_67P5 + - name: Sample67p5 description: 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. value: 6 - - name: SAMPLE_131P5 + - name: Sample131p5 description: 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. value: 7 enum/Tcmd: bit_size: 3 variants: - - name: NOT_VALID + - name: NotValid description: Not a valid selection from the command buffer. Trigger event is ignored. value: 0 - - name: EXECUTE_CMD1 + - name: ExecuteCmd1 description: CMD1 is executed. value: 1 - - name: EXECUTE_CORRESPONDING_CMD_2 + - name: ExecuteCorrespondingCmd2 description: Corresponding CMD is executed. value: 2 - - name: EXECUTE_CORRESPONDING_CMD_3 + - name: ExecuteCorrespondingCmd3 description: Corresponding CMD is executed. value: 3 - - name: EXECUTE_CORRESPONDING_CMD_4 + - name: ExecuteCorrespondingCmd4 description: Corresponding CMD is executed. value: 4 - - name: EXECUTE_CORRESPONDING_CMD_5 + - name: ExecuteCorrespondingCmd5 description: Corresponding CMD is executed. value: 5 - - name: EXECUTE_CORRESPONDING_CMD_6 + - name: ExecuteCorrespondingCmd6 description: Corresponding CMD is executed. value: 6 - - name: EXECUTE_CMD7 + - name: ExecuteCmd7 description: CMD7 is executed. value: 7 enum/TcompFlag: bit_size: 4 variants: - - name: NO_TRIGGER + - name: NoTrigger description: No triggers have been completed. Trigger completion interrupts are disabled. value: 0 - - name: BIT0_MEANS_TRIGGER_0_COMPLETED + - name: Bit0MeansTrigger0Completed description: Trigger 0 has been completed and trigger 0 has enabled completion interrupts. value: 1 - - name: BIT1_MEANS_TRIGGER_1_COMPLETED + - name: Bit1MeansTrigger1Completed description: Trigger 1 has been completed and trigger 1 has enabled completion interrupts. value: 2 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_3 + - name: SetBitsIndicateTriggerXCompleted3 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 3 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_4 + - name: SetBitsIndicateTriggerXCompleted4 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 4 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_5 + - name: SetBitsIndicateTriggerXCompleted5 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 5 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_6 + - name: SetBitsIndicateTriggerXCompleted6 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 6 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_7 + - name: SetBitsIndicateTriggerXCompleted7 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 7 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_8 + - name: SetBitsIndicateTriggerXCompleted8 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 8 - - name: SET_BITS_INDICATE_TRIGGER_X_COMPLETED_9 + - name: SetBitsIndicateTriggerXCompleted9 description: Associated trigger sequence has completed and has enabled completion interrupts. value: 9 - - name: ALL_BITS_SET_INDICATE_ALL_TRIGGERS_COMPLETED + - name: AllBitsSetIndicateAllTriggersCompleted description: Every trigger sequence has been completed and every trigger has enabled completion interrupts. value: 15 enum/TcompIe: bit_size: 4 variants: - - name: DISABLED + - name: Disabled description: Trigger completion interrupts are disabled. value: 0 - - name: TRIGGER_0_COMPLETE_ENABLED + - name: Trigger0CompleteEnabled description: Trigger completion interrupts are enabled for trigger source 0 only. value: 1 - - name: TRIGGER_1_COMPLETE_ENABLED + - name: Trigger1CompleteEnabled description: Trigger completion interrupts are enabled for trigger source 1 only. value: 2 - - name: TRIGGER_X_COMPLETE_ENABLED_3 + - name: TriggerXCompleteEnabled3 description: Associated trigger completion interrupts are enabled. value: 3 - - name: TRIGGER_X_COMPLETE_ENABLED_4 + - name: TriggerXCompleteEnabled4 description: Associated trigger completion interrupts are enabled. value: 4 - - name: TRIGGER_X_COMPLETE_ENABLED_5 + - name: TriggerXCompleteEnabled5 description: Associated trigger completion interrupts are enabled. value: 5 - - name: TRIGGER_X_COMPLETE_ENABLED_6 + - name: TriggerXCompleteEnabled6 description: Associated trigger completion interrupts are enabled. value: 6 - - name: TRIGGER_X_COMPLETE_ENABLED_7 + - name: TriggerXCompleteEnabled7 description: Associated trigger completion interrupts are enabled. value: 7 - - name: TRIGGER_X_COMPLETE_ENABLED_8 + - name: TriggerXCompleteEnabled8 description: Associated trigger completion interrupts are enabled. value: 8 - - name: TRIGGER_X_COMPLETE_ENABLED_9 + - name: TriggerXCompleteEnabled9 description: Associated trigger completion interrupts are enabled. value: 9 - - name: ALL_TRIGGER_COMPLETES_ENABLED + - name: AllTriggerCompletesEnabled description: Trigger completion interrupts are enabled for every trigger source. value: 15 enum/TcompInt: bit_size: 1 variants: - - name: FLAG_CLEAR + - name: FlagClear description: Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. value: 0 - - name: COMPLETION_DETECTED + - name: CompletionDetected description: Trigger sequence has been completed and all data is stored in the associated FIFO. value: 1 enum/TexcInt: bit_size: 1 variants: - - name: NO_EXCEPTION + - name: NoException description: No trigger exceptions have occurred. value: 0 - - name: EXCEPTION_DETECTED + - name: ExceptionDetected description: A trigger exception has occurred and is pending acknowledgement. value: 1 enum/TexcNum: bit_size: 4 variants: - - name: NO_EXCEPTIONS + - name: NoExceptions description: No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. value: 0 - - name: BIT0_MEANS_TRIGGER_0_INTERRUPTED + - name: Bit0MeansTrigger0Interrupted description: Trigger 0 has been interrupted by a high priority exception. value: 1 - - name: BIT1_MEANS_TRIGGER_1_INTERRUPTED + - name: Bit1MeansTrigger1Interrupted description: Trigger 1 has been interrupted by a high priority exception. value: 2 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_3 + - name: SetBitsIndicateTriggerXInterrupted3 description: Associated trigger sequence has interrupted by a high priority exception. value: 3 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_4 + - name: SetBitsIndicateTriggerXInterrupted4 description: Associated trigger sequence has interrupted by a high priority exception. value: 4 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_5 + - name: SetBitsIndicateTriggerXInterrupted5 description: Associated trigger sequence has interrupted by a high priority exception. value: 5 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_6 + - name: SetBitsIndicateTriggerXInterrupted6 description: Associated trigger sequence has interrupted by a high priority exception. value: 6 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_7 + - name: SetBitsIndicateTriggerXInterrupted7 description: Associated trigger sequence has interrupted by a high priority exception. value: 7 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_8 + - name: SetBitsIndicateTriggerXInterrupted8 description: Associated trigger sequence has interrupted by a high priority exception. value: 8 - - name: SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_9 + - name: SetBitsIndicateTriggerXInterrupted9 description: Associated trigger sequence has interrupted by a high priority exception. value: 9 - - name: ALL_BITS_SET_INDICATE_ALL_TRIGGERS_INTERRUPTED + - name: AllBitsSetIndicateAllTriggersInterrupted description: Every trigger sequence has been interrupted by a high priority exception. value: 15 enum/Tpri: bit_size: 2 variants: - - name: HIGHEST_PRIORITY + - name: HighestPriority description: Set to highest priority, Level 1. value: 0 - - name: CORRESPONDING_LOWER_PRIORITY_1 + - name: CorrespondingLowerPriority1 description: Set to corresponding priority level. value: 1 - - name: CORRESPONDING_LOWER_PRIORITY_2 + - name: CorrespondingLowerPriority2 description: Set to corresponding priority level. value: 2 - - name: LOWEST_PRIORITY + - name: LowestPriority description: Set to lowest priority, Level 4. value: 3 enum/Tprictrl: bit_size: 2 variants: - - name: ABORT_CURRENT_ON_PRIORITY + - name: AbortCurrentOnPriority description: If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. value: 0 - - name: FINISH_CURRENT_ON_PRIORITY + - name: FinishCurrentOnPriority description: If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. value: 1 - - name: FINISH_SEQUENCE_ON_PRIORITY + - name: FinishSequenceOnPriority description: If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. value: 2 enum/Trgact: bit_size: 2 variants: - - name: TRIG_0 + - name: Trig0 description: Command (sequence) associated with Trigger 0 currently being executed. value: 0 - - name: TRIG_1 + - name: Trig1 description: Command (sequence) associated with Trigger 1 currently being executed. value: 1 - - name: TRIG_2 + - name: Trig2 description: Command (sequence) associated with Trigger 2 currently being executed. value: 2 - - name: TRIG_3 + - name: Trig3 description: Command (sequence) associated with Trigger 3 currently being executed. value: 3 enum/Tsrc: bit_size: 2 variants: - - name: TRIGGER_0 + - name: Trigger0 description: Trigger source 0 initiated this conversion. value: 0 - - name: TRIGGER_1 + - name: Trigger1 description: Trigger source 1 initiated this conversion. value: 1 - - name: TRIGGER_2 + - name: Trigger2 description: Trigger source 2 initiated this conversion. value: 2 - - name: TRIGGER_3 + - name: Trigger3 description: Trigger source 3 initiated this conversion. value: 3 enum/Vr1rngi: bit_size: 1 variants: - - name: REF1_FIXED_VOLTAGE_RANGE + - name: Ref1FixedVoltageRange description: Range control not required. CFG[VREF1RNG] is not implemented. value: 0 - - name: REF1_SELECTABLE_VOLTAGE_RANGE + - name: Ref1SelectableVoltageRange description: Range control required. CFG[VREF1RNG] is implemented. value: 1 diff --git a/data/metadata/peripherals/mcxa/AHBSC.yaml b/data/metadata/peripherals/mcxa/AHBSC.yaml index 12555a9..2555be4 100644 --- a/data/metadata/peripherals/mcxa/AHBSC.yaml +++ b/data/metadata/peripherals/mcxa/AHBSC.yaml @@ -1,6 +1,13 @@ block/Ahbsc: description: AHBSC. items: + - name: ahb_slave_port_p0_slave_rule + description: AHB Slave Port 0 Rule. + array: + len: 4 + stride: 4 + byte_offset: 0 + fieldset: AhbSlavePortP0SlaveRule - name: flash00_mem_rule description: Flash Memory Rule. array: @@ -8,171 +15,177 @@ block/Ahbsc: stride: 4 byte_offset: 16 fieldset: Flash00MemRule - - name: flash01_mem_rule + - name: flash01_mem_rule0 description: Flash Memory Rule. + byte_offset: 32 + fieldset: Flash01MemRule0 + - name: flash02_mem_rule0 + description: Flash Memory Rule. + byte_offset: 48 + fieldset: Flash02MemRule0 + - name: ahb_slave_port_p1_slave_rule + description: AHB Slave Port 1 Rule. array: len: 4 stride: 4 - byte_offset: 32 - fieldset: Flash01MemRule - - name: flash02_mem_rule - description: Flash IFR0 Rule register. - byte_offset: 48 - fieldset: Flash02MemRule - - name: flash03_mem_rule - description: Flash Memory Rule. byte_offset: 64 - fieldset: Flash03MemRule + fieldset: AhbSlavePortP1SlaveRule - name: rom_mem_rule description: ROM Memory Rule. array: len: 4 stride: 4 - byte_offset: 96 + byte_offset: 80 fieldset: RomMemRule - - name: ramx_mem_rule + - name: ahb_slave_port_p2_slave_rule + description: AHB Slave Port 2 Rule. + array: + len: 4 + stride: 4 + byte_offset: 96 + fieldset: AhbSlavePortP2SlaveRule + - name: ramx_mem_rule0 description: RAMX Memory Rule. + byte_offset: 112 + fieldset: RamxMemRule0 + - name: ahb_slave_port_p3_slave_rule + description: AHB Slave Port 3 Rule. array: len: 4 stride: 4 byte_offset: 128 - fieldset: RamMemRule + fieldset: AhbSlavePortP3SlaveRule - name: rama_mem_rule - description: RAMA Memory Rule 0. + description: RAMA Memory Rule. array: - len: 8 + len: 4 stride: 4 - byte_offset: 160 + byte_offset: 144 fieldset: RamMemRule + - name: ahb_slave_port_p4_slave_rule + description: AHB Slave Port 4 Rule. + array: + len: 4 + stride: 4 + byte_offset: 160 + fieldset: AhbSlavePortP4SlaveRule - name: ramb_mem_rule - description: RAMB Memory Rule 0. + description: RAMB Memory Rule. array: - len: 8 + len: 4 stride: 4 - byte_offset: 208 + byte_offset: 176 fieldset: RamMemRule - - name: ahb_slave_port_p5_slave_rule0 - description: AHB Slave Port 5 Rule Register. - byte_offset: 240 - fieldset: AhbSlavePortP5SlaveRule0 + - name: ahb_peripheral_slave_port_p5_slave_rule0 + description: AHB Peripheral Slave Port 5 Slave Rule 0. + byte_offset: 192 + fieldset: AhbPeripheralSlavePortP5SlaveRule0 + - name: ahb_peripheral_slave_port_p5_slave_rule1 + description: AHB Peripheral Slave Port 5 Slave Rule 1. + byte_offset: 196 + fieldset: AhbPeripheralSlavePortP5SlaveRule1 - name: apb_peripheral_group0_mem_rule0 - description: APB Bridge Group 0 Memory Rule Register 0. - byte_offset: 256 + description: APB Bridge Group 0 Memory Rule 0. + byte_offset: 208 fieldset: ApbPeripheralGroup0MemRule0 - name: apb_peripheral_group0_mem_rule1 - description: APB Bridge Group 0 Memory Rule Register 1. - byte_offset: 260 + description: APB Bridge Group 0 Memory Rule 1. + byte_offset: 212 fieldset: ApbPeripheralGroup0MemRule1 + - name: apb_peripheral_group0_mem_rule2 + description: APB Bridge Group 0 Rule 2. + byte_offset: 216 + access: Read + - name: apb_peripheral_group0_mem_rule3 + description: APB Bridge Group 0 Memory Rule 3. + byte_offset: 220 + access: Read - name: aips_bridge_group0_mem_rule0 description: AIPS Bridge Group 0 Memory Rule 0. - byte_offset: 272 + byte_offset: 224 fieldset: AipsBridgeGroup0MemRule0 - name: aips_bridge_group0_mem_rule1 description: AIPS Bridge Group 0 Memory Rule 1. - byte_offset: 276 + byte_offset: 228 fieldset: AipsBridgeGroup0MemRule1 - - name: aips_bridge_group1_mem_rule0 - description: AIPS Bridge Group 1 Memory Rule 0. - byte_offset: 288 - fieldset: AipsBridgeGroup1MemRule0 - - name: aips_bridge_group1_mem_rule1 - description: AIPS Bridge Group 1 Memory Rule 1. - byte_offset: 292 - fieldset: AipsBridgeGroup1MemRule1 - - name: ahb_secure_ctrl_mem_rule0 - description: AHB Secure Control Peripheral Rule. - byte_offset: 304 - fieldset: AhbSecureCtrlMemRule0 - - name: ahb_peripheral0_mem_rule1 - description: AHB Peripheral 0 Memory Rule 1. - byte_offset: 320 - fieldset: AhbPeripheral0MemRule1 - - name: ahb_peripheral0_mem_rule2 - description: AHB Peripheral 0 Memory Rule 2. - byte_offset: 336 - fieldset: AhbPeripheral0MemRule2 - - name: ahb_peripheral0_mem_rule3 - description: AHB Peripheral 0 Memory Rule 3. - byte_offset: 352 - fieldset: AhbPeripheral0MemRule3 - - name: ahb_peripheral0_mem_rule4 - description: AHB Peripheral 0 Memory Rule 4. - byte_offset: 368 - fieldset: AhbPeripheral0MemRule4 - - name: ahb_peripheral0_mem_rule5 - description: AHB Peripheral 0 Memory Rule 5. - byte_offset: 384 - fieldset: AhbPeripheral0MemRule5 + - name: aips_bridge_group0_mem_rule2 + description: AIPS Bridge Group 0 Memory Rule 2. + byte_offset: 232 + fieldset: AipsBridgeGroup0MemRule2 + - name: aips_bridge_group0_mem_rule3 + description: AIPS Bridge Group 0 Memory Rule 3. + byte_offset: 236 + fieldset: AipsBridgeGroup0MemRule3 - name: aips_bridge_group2_mem_rule0 - description: AIPS Bridge Group 2 Rule 0. - byte_offset: 416 + description: AIPS Bridge Group 2 Memory Rule 0. + byte_offset: 240 fieldset: AipsBridgeGroup2MemRule0 - name: aips_bridge_group2_mem_rule1 - description: AIPS Bridge Group 2 Rule 1. - byte_offset: 420 + description: AIPS Bridge Group 2 Memory Rule 1. + byte_offset: 244 fieldset: AipsBridgeGroup2MemRule1 - name: aips_bridge_group2_mem_rule2 - description: AIPS Bridge Group 2 Rule 2. - byte_offset: 424 + description: AIPS Bridge Group 2 Memory Rule 2. + byte_offset: 248 fieldset: AipsBridgeGroup2MemRule2 - name: aips_bridge_group2_mem_rule3 - description: AIPS Bridge Group 2 Rule 3. - byte_offset: 428 + description: AIPS Bridge Group 2 Memory Rule 3. + byte_offset: 252 fieldset: AipsBridgeGroup2MemRule3 - - name: aips_bridge_group2_mem_rule4 - description: AIPS Bridge Group 2 Rule 4. - byte_offset: 432 - fieldset: AipsBridgeGroup2MemRule4 - - name: aips_bridge_group2_mem_rule5 - description: AIPS Bridge Group 2 Rule 5. - byte_offset: 436 - fieldset: AipsBridgeGroup2MemRule5 - - name: aips_bridge_group2_mem_rule6 - description: AIPS Bridge Group 2 Rule 6. - byte_offset: 440 - fieldset: AipsBridgeGroup2MemRule6 - - name: aips_bridge_group2_mem_rule7 - description: AIPS Bridge Group 2 Rule 7. - byte_offset: 444 - fieldset: AipsBridgeGroup2MemRule7 - - name: aips_bridge_group2_mem_rule8 - description: AIPS Bridge Group 2 Rule 8. - byte_offset: 448 - fieldset: AipsBridgeGroup2MemRule8 - - name: aips_bridge_group2_mem_rule9 - description: AIPS Bridge Group 2 Rule 9. - byte_offset: 452 - fieldset: AipsBridgeGroup2MemRule9 - - name: aips_bridge_group2_mem_rule10 - description: AIPS Bridge Group 2 Rule 10. - byte_offset: 456 - fieldset: AipsBridgeGroup2MemRule10 - - name: aips_bridge_group2_mem_rule11 - description: AIPS Bridge Group 2 Rule 11. - byte_offset: 460 - fieldset: AipsBridgeGroup2MemRule11 - - name: aips_bridge_group2_mem_rule12 - description: AIPS Bridge Group 2 Rule 12. - byte_offset: 464 - fieldset: AipsBridgeGroup2MemRule12 - - name: aips_bridge_group2_mem_rule13 - description: AIPS Bridge Group 2 Rule 13. - byte_offset: 468 - fieldset: AipsBridgeGroup2MemRule13 - - name: flexspi0_region0_mem_rule - description: FLEXSPI0 Region 0 Memory Rule. + - name: aips_bridge_group3_mem_rule0 + description: AIPS Bridge Group 3 Rule 0. + byte_offset: 256 + fieldset: AipsBridgeGroup3MemRule0 + - name: aips_bridge_group3_mem_rule1 + description: AIPS Bridge Group 3 Memory Rule 1. + byte_offset: 260 + access: Read + - name: aips_bridge_group3_mem_rule2 + description: AIPS Bridge Group 3 Rule 2. + byte_offset: 264 + fieldset: AipsBridgeGroup3MemRule2 + - name: aips_bridge_group3_mem_rule3 + description: AIPS Bridge Group 3 Rule 3. + byte_offset: 268 + fieldset: AipsBridgeGroup3MemRule3 + - name: ahb_secure_ctrl_peripheral_rule0 + description: AHB Secure Control Peripheral Rule 0. + byte_offset: 272 + fieldset: AhbSecureCtrlPeripheralRule0 + - name: ahb_slave_port_p6_slave_rule + description: AHB Slave Port 6 Rule. array: len: 4 stride: 4 - byte_offset: 496 - fieldset: Flexspi0Region0MemRule - - name: flexspi0_region1_6_mem_rule - description: 'Array of registers: FLEXSPI0_REGION_MEM_RULE.' + byte_offset: 288 + fieldset: AhbSlavePortP6SlaveRule + - name: aon_domain_peripheral_mem_rule0 + description: AON Domain Peripheral Rule 0. + byte_offset: 304 + fieldset: AonDomainPeripheralMemRule0 + - name: aon_domain_peripheral_mem_rule1 + description: AON Domain Peripheral Rule 1. + byte_offset: 308 + fieldset: AonDomainPeripheralMemRule1 + - name: aon_domain_peripheral_mem_rule2 + description: AON Domain Peripheral Rule 2. + byte_offset: 312 + fieldset: AonDomainPeripheralMemRule2 + - name: aon_domain_peripheral_mem_rule3 + description: AON Domain Peripheral Rule 3. + byte_offset: 316 + fieldset: AonDomainPeripheralMemRule3 + - name: ahb_slave_port_p7_slave_rule + description: AHB Slave Port 6 Rule. array: - len: 6 - stride: 16 - byte_offset: 512 - block: Flexspi0Region16MemRule + len: 4 + stride: 4 + byte_offset: 320 + fieldset: AhbSlavePortP7SlaveRule + - name: aon_domain_sram_mem_rule0 + description: AON Domain SRAM Memory Rule. + byte_offset: 336 + fieldset: AonDomainSramMemRule0 - name: sec_vio_addr description: Security Violation Address. array: @@ -220,669 +233,689 @@ block/Ahbsc: description: Secure Control. byte_offset: 4092 fieldset: MiscCtrlReg -block/Flexspi0Region16MemRule: - description: 'Array of registers: FLEXSPI0_REGION_MEM_RULE.' - items: - - name: flexspi0_region_mem_rule - description: FLEXSPI0 Region index Memory Rule. - byte_offset: 0 - fieldset: Flexspi0RegionMemRule -fieldset/AhbPeripheral0MemRule1: - description: AHB Peripheral 0 Memory Rule 1. +fieldset/AhbPeripheralSlavePortP5SlaveRule0: + description: AHB Peripheral Slave Port 5 Slave Rule 0. fields: - - name: gpio0 - description: GPIO0. - bit_offset: 0 + - name: aips4_slaves + description: AIPS4 slaves. + bit_offset: 16 bit_size: 2 enum: Rule - - name: gpio0_alias - description: GPIO0 ALIAS. - bit_offset: 4 + - name: cdog0 + description: CDOG0. + bit_offset: 20 bit_size: 2 enum: Rule -fieldset/AhbPeripheral0MemRule2: - description: AHB Peripheral 0 Memory Rule 2. - fields: - - name: gpio1 - description: GPIO1. - bit_offset: 0 + - name: debug_mailbox + description: DEBUG_MAILBOX. + bit_offset: 24 bit_size: 2 enum: Rule - - name: gpio1_alias - description: GPIO1 ALIAS. - bit_offset: 4 + - name: gpio1 + description: GPIO1. + bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AhbPeripheral0MemRule3: - description: AHB Peripheral 0 Memory Rule 3. +fieldset/AhbPeripheralSlavePortP5SlaveRule1: + description: AHB Peripheral Slave Port 5 Slave Rule 1. fields: - name: gpio2 description: GPIO2. bit_offset: 0 bit_size: 2 enum: Rule - - name: gpio2_alias - description: GPIO2 ALIAS. + - name: gpio3 + description: GPIO3. bit_offset: 4 bit_size: 2 enum: Rule -fieldset/AhbPeripheral0MemRule4: - description: AHB Peripheral 0 Memory Rule 4. - fields: - - name: gpio3 - description: GPIO3. - bit_offset: 0 + - name: cdog1 + description: CDOG1. + bit_offset: 8 bit_size: 2 enum: Rule - - name: gpio3_alias - description: GPIO3 ALIAS. - bit_offset: 4 +fieldset/AhbSecureCtrlPeripheralRule0: + description: AHB Secure Control Peripheral Rule 0. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 4 + stride: 4 enum: Rule -fieldset/AhbPeripheral0MemRule5: - description: AHB Peripheral 0 Memory Rule 5. +fieldset/AhbSlavePortP0SlaveRule: + description: AHB Slave Port 0 Rule. fields: - - name: gpio4 - description: GPIO4. + - name: rule + description: Rule 0. bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule - - name: gpio4_alias - description: GPIO4 ALIAS. - bit_offset: 4 +fieldset/AhbSlavePortP1SlaveRule: + description: AHB Slave Port 1 Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule -fieldset/AhbSecureCtrlMemRule0: - description: AHB Secure Control Peripheral Rule. +fieldset/AhbSlavePortP2SlaveRule: + description: AHB Slave Port 2 Rule. fields: - name: rule - description: AHBSC. + description: Rule 0. bit_offset: 0 bit_size: 2 array: - len: 4 + len: 8 stride: 4 enum: Rule -fieldset/AhbSlavePortP5SlaveRule0: - description: AHB Slave Port 5 Rule Register. +fieldset/AhbSlavePortP3SlaveRule: + description: AHB Slave Port 3 Rule. fields: - - name: cdog0 - description: CDOG0. - bit_offset: 12 + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule - - name: cdog1 - description: CDOG1. - bit_offset: 16 +fieldset/AhbSlavePortP4SlaveRule: + description: AHB Slave Port 4 Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule - - name: debug_mailbox - description: DEBUG_MAILBOX. - bit_offset: 20 +fieldset/AhbSlavePortP6SlaveRule: + description: AHB Slave Port 6 Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule - - name: mau0 - description: Rule 6. - bit_offset: 24 +fieldset/AhbSlavePortP7SlaveRule: + description: AHB Slave Port 6 Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule fieldset/AipsBridgeGroup0MemRule0: description: AIPS Bridge Group 0 Memory Rule 0. fields: - - name: ewm0 - description: EWM0. + - name: e_dma_0_mp + description: eDMA_0_MP. bit_offset: 0 bit_size: 2 enum: Rule - - name: romcp - description: ROMCP. + - name: e_dma_0_tcd0 + description: eDMA_0_TCD0. bit_offset: 4 bit_size: 2 enum: Rule - - name: pkc0 - description: PKC0. + - name: e_dma_0_tcd1 + description: eDMA_0_TCD1. bit_offset: 8 bit_size: 2 enum: Rule - - name: dma_1_mp - description: DMA_1_MP. + - name: e_dma_0_tcd2 + description: eDMA_0_TCD2. bit_offset: 12 bit_size: 2 enum: Rule - - name: dma_1_ch0 - description: DMA_1_CH0. + - name: e_dma_0_tcd3 + description: FLEXSPI0 Registers. bit_offset: 16 bit_size: 2 enum: Rule - - name: dma_1_ch1 - description: DMA_1_CH1. + - name: e_dma_0_tcd4 + description: eDMA_0_TCD4 (Reserved). bit_offset: 20 bit_size: 2 enum: Rule - - name: dma_1_ch2 - description: DMA_1_CH2. + - name: e_dma_0_tcd5 + description: eDMA_0_TCD5 (Reserved). bit_offset: 24 bit_size: 2 enum: Rule - - name: dma_1_ch3 - description: DMA_1_CH3. + - name: e_dma_0_tcd6 + description: eDMA_0_TCD6 (Reserved). bit_offset: 28 bit_size: 2 enum: Rule fieldset/AipsBridgeGroup0MemRule1: description: AIPS Bridge Group 0 Memory Rule 1. fields: - - name: enet0_0 - description: ENET0_0. - bit_offset: 16 + - name: e_dma_0_tcd7 + description: eDMA_0_TCD7 (Reserved). + bit_offset: 0 bit_size: 2 enum: Rule - - name: enet0_1 - description: ENET0_1. - bit_offset: 20 + - name: aoi0 + description: AOI0. + bit_offset: 4 bit_size: 2 enum: Rule - - name: e_spi - description: eSPI. - bit_offset: 28 + - name: crc0 + description: CRC0. + bit_offset: 8 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup1MemRule0: - description: AIPS Bridge Group 1 Memory Rule 0. - fields: - - name: flexspi0 - description: FLEXSPI0. - bit_offset: 0 + - name: cmc0 + description: CMC0. + bit_offset: 12 bit_size: 2 enum: Rule - - name: lpspi2 - description: LPSPI2. - bit_offset: 4 + - name: erm0 + description: ERM0. + bit_offset: 20 bit_size: 2 enum: Rule - - name: lpspi3 - description: LPSPI3. - bit_offset: 8 + - name: mbc0 + description: MBC0. + bit_offset: 24 bit_size: 2 enum: Rule - - name: lpspi4 - description: LPSPI4. - bit_offset: 12 + - name: scg0 + description: SCG0. + bit_offset: 28 bit_size: 2 enum: Rule - - name: lpspi5 - description: LPSPI5. - bit_offset: 16 +fieldset/AipsBridgeGroup0MemRule2: + description: AIPS Bridge Group 0 Memory Rule 2. + fields: + - name: syscon + description: SYSCON. + bit_offset: 4 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup1MemRule1: - description: AIPS Bridge Group 1 Memory Rule 1. - fields: - - name: spi_fileter0 - description: SPI_FILETER0. + - name: wuu0 + description: WUU0. + bit_offset: 8 + bit_size: 2 + enum: Rule + - name: fmc0 + description: FMC0. bit_offset: 16 bit_size: 2 enum: Rule - - name: t1s0 - description: 10BASE_T1S0. + - name: fmu0 + description: FMU0. bit_offset: 20 bit_size: 2 enum: Rule - - name: usb1 - description: USB1. + - name: fmu0_tst + description: FMU0_TST. bit_offset: 24 bit_size: 2 enum: Rule - - name: usb1_phy - description: USB1_PHY. + - name: bcanxl + description: BCANXL (Reserved). bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule0: - description: AIPS Bridge Group 2 Rule 0. +fieldset/AipsBridgeGroup0MemRule3: + description: AIPS Bridge Group 0 Memory Rule 3. fields: - - name: dma_0_mp - description: DMA_0_MP. + - name: candma + description: CANDMA (Reserved). bit_offset: 0 bit_size: 2 enum: Rule - - name: dma_0_ch0 - description: DMA_0_CH0. + - name: flexio + description: FLEXIO (Reserved). bit_offset: 4 bit_size: 2 enum: Rule - - name: dma_0_ch1 - description: DMA_0_CH1. + - name: lpi2c0 + description: LPI2C0. bit_offset: 8 bit_size: 2 enum: Rule - - name: dma_0_ch2 - description: DMA_0_CH2. + - name: lpi2c1 + description: LPI2C1. bit_offset: 12 bit_size: 2 enum: Rule - - name: dma_0_ch3 - description: DMA_0_CH3. + - name: lpspi0 + description: LPSPI0. bit_offset: 16 bit_size: 2 enum: Rule - - name: dma_0_ch4 - description: DMA_0_CH4. + - name: lpspi1 + description: LPSPI1. bit_offset: 20 bit_size: 2 enum: Rule - - name: dma_0_ch5 - description: DMA_0_CH5. + - name: lpspi2 + description: LPSPI2 (Reserved). bit_offset: 24 bit_size: 2 enum: Rule - - name: dma_0_ch6 - description: DMA_0_CH6. + - name: lpuart0 + description: LPUART0. bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule1: - description: AIPS Bridge Group 2 Rule 1. +fieldset/AipsBridgeGroup2MemRule0: + description: AIPS Bridge Group 2 Memory Rule 0. fields: - - name: dma_0_ch7 - description: DMA_0_CH7. + - name: lpuart1 + description: LPUART1. bit_offset: 0 bit_size: 2 enum: Rule - - name: dma_0_ch8 - description: DMA_0_CH8. + - name: lpuart2 + description: LPUART2 (Reserved). bit_offset: 4 bit_size: 2 enum: Rule - - name: dma_0_ch9 - description: DMA_0_CH9. + - name: lpuart3 + description: LPUART3 (Reserved). bit_offset: 8 bit_size: 2 enum: Rule - - name: dma_0_ch10 - description: DMA_0_CH10. + - name: lpuart4 + description: LPUART4 (Reserved). bit_offset: 12 bit_size: 2 enum: Rule - - name: dma_0_ch11 - description: DMA_0_CH11. + - name: usb_fs_otg + description: USB_FS_OTG (Reserved). bit_offset: 16 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule10: - description: AIPS Bridge Group 2 Rule 10. + - name: usb_fs_dcd + description: USB_FS_DCD (Reserved). + bit_offset: 20 + bit_size: 2 + enum: Rule + - name: usb_typec_pd + description: USB_TYPEC_PD (Reserved). + bit_offset: 24 + bit_size: 2 + enum: Rule + - name: quad_decoder0 + description: QUAD_DECODER0 (Reserved). + bit_offset: 28 + bit_size: 2 + enum: Rule +fieldset/AipsBridgeGroup2MemRule1: + description: AIPS Bridge Group 2 Memory Rule 1. fields: - - name: can1_region0 - description: CAN1 Region 0. + - name: quad_decoder1 + description: QUAD_DECODER1 (Reserved). bit_offset: 0 bit_size: 2 enum: Rule - - name: can1_region1 - description: CAN1 Region 1. + - name: flexpwm0 + description: FLEXPWM0. bit_offset: 4 bit_size: 2 enum: Rule - - name: can1_region2 - description: CAN1 Region 2. + - name: flexpwm1 + description: FLEXPWM1 (Reserved). bit_offset: 8 bit_size: 2 enum: Rule - - name: can1_region3 - description: CAN1 Region 3. + - name: lptmr0 + description: LPTMR0 (Reserved). bit_offset: 12 bit_size: 2 enum: Rule - - name: lpi2c2 - description: LPI2C2. + - name: lptmr1 + description: LPTMR1 (Reserved). bit_offset: 16 bit_size: 2 enum: Rule - - name: lpi2c3 - description: LPI2C3. + - name: ostimer0 + description: OSTIMER0. bit_offset: 20 bit_size: 2 enum: Rule - - name: lpi2c4 - description: LPI2C4. + - name: wake_timer + description: WAKE_TIMER (Reserved). bit_offset: 24 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule11: - description: AIPS Bridge Group 2 Rule 11. - fields: - - name: lpuart5 - description: LPUART5. - bit_offset: 8 + - name: hsadc0 + description: HSADC0. + bit_offset: 28 bit_size: 2 enum: Rule - - name: i3c3 - description: I3C3. - bit_offset: 24 +fieldset/AipsBridgeGroup2MemRule2: + description: AIPS Bridge Group 2 Memory Rule 2. + fields: + - name: adc1 + description: ADC1 (Reserved). + bit_offset: 0 bit_size: 2 enum: Rule - - name: gpio5 - description: GPIO5. - bit_offset: 28 + - name: cmp0 + description: CMP0. + bit_offset: 4 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule12: - description: AIPS Bridge Group 2 Rule 12. - fields: - - name: gpio5_alias - description: GPIO5_ALIAS. - bit_offset: 0 + - name: cmp1 + description: CMP1 (Reserved). + bit_offset: 8 bit_size: 2 enum: Rule - - name: port5 - description: PORT5. + - name: cmp2 + description: CMP2 (Reserved). bit_offset: 12 bit_size: 2 enum: Rule - - name: dgdet0 - description: DGDET0. + - name: dac0 + description: DAC0 (Reserved). + bit_offset: 16 + bit_size: 2 + enum: Rule + - name: dac1 + description: DAC1 (Reserved). bit_offset: 20 bit_size: 2 enum: Rule - - name: itrc0 - description: ITRC0. + - name: dac2 + description: DAC2 (Reserved). + bit_offset: 24 + bit_size: 2 + enum: Rule + - name: opamp0 + description: OPAMP0 (Reserved). bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule13: - description: AIPS Bridge Group 2 Rule 13. +fieldset/AipsBridgeGroup2MemRule3: + description: AIPS Bridge Group 2 Memory Rule 3. fields: - - name: glikey0 - description: GLIKEY0. + - name: opamp1 + description: OPAMP1 (Reserved). bit_offset: 0 bit_size: 2 enum: Rule - - name: tdet0 - description: TDET0. + - name: opamp2 + description: OPAMP2 (Reserved). bit_offset: 4 bit_size: 2 enum: Rule - - name: seccon - description: SECCON. + - name: sd_adc0 + description: SD_ADC0 (Reserved). bit_offset: 8 bit_size: 2 enum: Rule - - name: sgi0 - description: SGI0. + - name: dgo_gpio1_3 + description: DGO_GPIO1_3 (Reserved). bit_offset: 12 bit_size: 2 enum: Rule - - name: trng0 - description: TRNG0. + - name: port1 + description: PORT1. bit_offset: 16 bit_size: 2 enum: Rule - - name: udf0 - description: UDF0. + - name: port2 + description: PORT2. bit_offset: 20 bit_size: 2 enum: Rule - - name: rtc0 - description: RTC0. + - name: port3 + description: PORT3. bit_offset: 24 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule2: - description: AIPS Bridge Group 2 Rule 2. + - name: port4 + description: PORT4 (Reserved). + bit_offset: 28 + bit_size: 2 + enum: Rule +fieldset/AipsBridgeGroup3MemRule0: + description: AIPS Bridge Group 3 Rule 0. fields: - - name: syscon - description: SYSCON. + - name: port5 + description: PORT5 (Reserved). + bit_offset: 0 + bit_size: 2 + enum: Rule + - name: sai + description: SAI (Reserved). bit_offset: 4 bit_size: 2 enum: Rule - - name: wuu - description: WUU. + - name: segment_lcd + description: SEGMENT_LCD (Reserved). bit_offset: 8 bit_size: 2 enum: Rule - - name: vbat - description: VBAT. + - name: tsi + description: TSI (Reserved). bit_offset: 12 bit_size: 2 enum: Rule - - name: fmc - description: FMC. + - name: mu0 + description: MU0. bit_offset: 16 bit_size: 2 enum: Rule - - name: fmu - description: FMU. + - name: mu1 + description: MU1 (Reserved). bit_offset: 20 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule3: - description: AIPS Bridge Group 2 Rule 3. +fieldset/AipsBridgeGroup3MemRule2: + description: AIPS Bridge Group 3 Rule 2. fields: - - name: flexio - description: FLEXIO. + - name: pkc0 + description: PKC0. + bit_offset: 0 + bit_size: 2 + enum: Rule + - name: sgi0 + description: SGI0. bit_offset: 4 bit_size: 2 enum: Rule - - name: lpi2c0 - description: LPI2C0. + - name: trng0 + description: TRNG0. bit_offset: 8 bit_size: 2 enum: Rule - - name: lpi2c1 - description: LPI2C1. + - name: udf0 + description: CAN0 RULE0. bit_offset: 12 bit_size: 2 enum: Rule - - name: lpspi0 - description: LPSPI0. - bit_offset: 16 - bit_size: 2 - enum: Rule - - name: lpspi1 - description: LPSPI1. - bit_offset: 20 - bit_size: 2 - enum: Rule - - name: i3c2 - description: I3C2. - bit_offset: 24 - bit_size: 2 - enum: Rule - - name: lpuart0 - description: LPUART0. + - name: e_mda_1_mp + description: eDMA_1_MP. bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule4: - description: AIPS Bridge Group 2 Rule 4. +fieldset/AipsBridgeGroup3MemRule3: + description: AIPS Bridge Group 3 Rule 3. fields: - - name: lpuart1 - description: LPUART1. + - name: e_dma_1_tcd0 + description: eDMA_1_TCD0. bit_offset: 0 bit_size: 2 enum: Rule - - name: lpuart2 - description: LPUART2. + - name: e_dma_1_tcd1 + description: eDMA_1_TCD1. bit_offset: 4 bit_size: 2 enum: Rule - - name: lpuart3 - description: LPUART3. + - name: e_dma_1_tcd2 + description: eDMA_1_TCD2. bit_offset: 8 bit_size: 2 enum: Rule - - name: lpuart4 - description: LPUART4. + - name: e_dma_1_tcd3 + description: eDMA_1_TCD3. bit_offset: 12 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule5: - description: AIPS Bridge Group 2 Rule 5. +fieldset/AonDomainPeripheralMemRule0: + description: AON Domain Peripheral Rule 0. fields: - - name: lptmr - description: LPTMR. - bit_offset: 12 - bit_size: 2 - enum: Rule - - name: ostimer - description: OSTIMER. - bit_offset: 20 - bit_size: 2 - enum: Rule - - name: wake_timer - description: WAKE_TIMER. - bit_offset: 24 + - name: lpi2c + description: LPI2C. + bit_offset: 0 bit_size: 2 enum: Rule - - name: adc0 - description: ADC0. - bit_offset: 28 + - name: rule1 + description: LPI2C (Reserved). + bit_offset: 4 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule6: - description: AIPS Bridge Group 2 Rule 6. - fields: - - name: adc1 - description: ADC1. - bit_offset: 0 + - name: lpuart + description: LPUART. + bit_offset: 8 bit_size: 2 enum: Rule - - name: cmp0 - description: CMP0. - bit_offset: 4 + - name: rule3 + description: LPUART (Reserved). + bit_offset: 12 bit_size: 2 enum: Rule - - name: dac0 - description: DAC0. + - name: mub + description: MUB. bit_offset: 16 bit_size: 2 enum: Rule - - name: dac1 - description: DAC1. + - name: port0 + description: PORT0. bit_offset: 20 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule7: - description: AIPS Bridge Group 2 Rule 7. - fields: - - name: vref0 - description: VREF0. - bit_offset: 12 + - name: acmp + description: ACMP. + bit_offset: 24 bit_size: 2 enum: Rule - - name: port0 - description: PORT0. - bit_offset: 16 + - name: rule7 + description: ACMP (Reserved). + bit_offset: 28 bit_size: 2 enum: Rule - - name: port1 - description: PORT1. - bit_offset: 20 +fieldset/AonDomainPeripheralMemRule1: + description: AON Domain Peripheral Rule 1. + fields: + - name: lptimer + description: LPTIMER. + bit_offset: 0 bit_size: 2 enum: Rule - - name: port2 - description: PORT2. + - name: qtmr32_0 + description: QTMR32_0. bit_offset: 24 bit_size: 2 enum: Rule - - name: port3 - description: PORT3. + - name: qtmr32_1 + description: QTMR32_1. bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule8: - description: AIPS Bridge Group 2 Rule 8. +fieldset/AonDomainPeripheralMemRule2: + description: AON Domain Peripheral Rule 2. fields: - - name: port4 - description: PORT4. + - name: gp_gpr + description: GP_GPR. bit_offset: 0 bit_size: 2 enum: Rule - - name: tsi0 - description: TSI0. - bit_offset: 12 + - name: inputmux + description: INPUTMUX. + bit_offset: 4 bit_size: 2 enum: Rule - - name: aoi0 - description: AOI0. - bit_offset: 16 + - name: lpadc + description: LPADC. + bit_offset: 8 bit_size: 2 enum: Rule - - name: crc0 - description: CRC0. - bit_offset: 20 + - name: sglcd + description: SGLCD0. + bit_offset: 16 bit_size: 2 enum: Rule - - name: cmc - description: CMC. - bit_offset: 24 + - name: kpp + description: KPP. + bit_offset: 20 bit_size: 2 enum: Rule - - name: eim - description: EIM. + - name: advc2 + description: KPP. bit_offset: 28 bit_size: 2 enum: Rule -fieldset/AipsBridgeGroup2MemRule9: - description: AIPS Bridge Group 2 Rule 9. +fieldset/AonDomainPeripheralMemRule3: + description: AON Domain Peripheral Rule 3. fields: - - name: erm - description: ERM. + - name: pmic_ctrl + description: PMIC_CTRL. bit_offset: 0 bit_size: 2 enum: Rule - - name: mbc - description: MBC. + - name: cgu + description: CGU. bit_offset: 4 bit_size: 2 enum: Rule - - name: scg - description: SCG. + - name: smm + description: SMM. bit_offset: 8 bit_size: 2 enum: Rule - - name: spc - description: SPC. + - name: lpcmp + description: LPCMP. bit_offset: 12 bit_size: 2 enum: Rule - - name: can0_region0 - description: CAN0 Region 0. - bit_offset: 16 - bit_size: 2 - enum: Rule - - name: can0_region1 - description: CAN0 Region 1. - bit_offset: 20 - bit_size: 2 - enum: Rule - - name: can0_region2 - description: CAN0 Region 2. - bit_offset: 24 + - name: aon_gpio + description: AON_GPIO. + bit_offset: 28 bit_size: 2 enum: Rule - - name: can0_region3 - description: CAN0 Region 3. - bit_offset: 28 +fieldset/AonDomainSramMemRule0: + description: AON Domain SRAM Memory Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 bit_size: 2 + array: + len: 8 + stride: 4 enum: Rule fieldset/ApbPeripheralGroup0MemRule0: - description: APB Bridge Group 0 Memory Rule Register 0. + description: APB Bridge Group 0 Memory Rule 0. fields: - - name: inputmux - description: INPUTMUX. + - name: inputmux0 + description: INPUTMUX0. bit_offset: 4 bit_size: 2 enum: Rule - - name: i3c0 - description: I3C0. - bit_offset: 8 - bit_size: 2 - enum: Rule - - name: i3c1 - description: I3C1. - bit_offset: 12 - bit_size: 2 - enum: Rule - name: ctimer0 description: CTIMER0. bit_offset: 16 @@ -898,26 +931,16 @@ fieldset/ApbPeripheralGroup0MemRule0: bit_offset: 24 bit_size: 2 enum: Rule - - name: ctimer3 - description: CTIMER3. - bit_offset: 28 - bit_size: 2 - enum: Rule fieldset/ApbPeripheralGroup0MemRule1: - description: APB Bridge Group 0 Memory Rule Register 1. + description: APB Bridge Group 0 Memory Rule 1. fields: - - name: ctimer4 - description: CTIMER4. - bit_offset: 0 - bit_size: 2 - enum: Rule - - name: freqme - description: FREQME. + - name: freqme00 + description: FREQME00. bit_offset: 4 bit_size: 2 enum: Rule - - name: utick - description: UTCIK0. + - name: utick0 + description: UTICK0. bit_offset: 12 bit_size: 2 enum: Rule @@ -926,16 +949,6 @@ fieldset/ApbPeripheralGroup0MemRule1: bit_offset: 16 bit_size: 2 enum: Rule - - name: wwdt1 - description: WWDT1. - bit_offset: 20 - bit_size: 2 - enum: Rule - - name: smartdma - description: SmartDMA. - bit_offset: 24 - bit_size: 2 - enum: Rule fieldset/Cpu0LockReg: description: Miscellaneous CPU0 Control Signals. fields: @@ -975,20 +988,9 @@ fieldset/Flash00MemRule: len: 8 stride: 4 enum: Rule -fieldset/Flash01MemRule: +fieldset/Flash01MemRule0: description: Flash Memory Rule. fields: - - name: rule - description: Rule 0. - bit_offset: 0 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: Rule -fieldset/Flash02MemRule: - description: Flash IFR0 Rule register. - fields: - name: rule description: Rule 0. bit_offset: 0 @@ -997,7 +999,7 @@ fieldset/Flash02MemRule: len: 4 stride: 4 enum: Rule -fieldset/Flash03MemRule: +fieldset/Flash02MemRule0: description: Flash Memory Rule. fields: - name: rule @@ -1008,92 +1010,40 @@ fieldset/Flash03MemRule: len: 4 stride: 4 enum: Rule -fieldset/Flexspi0Region0MemRule: - description: FLEXSPI0 Region 0 Memory Rule. - fields: - - name: rule - description: Rule 0. - bit_offset: 0 - bit_size: 2 - array: - len: 8 - stride: 4 - enum: Rule -fieldset/Flexspi0RegionMemRule: - description: FLEXSPI0 Region index Memory Rule. - fields: - - name: rule - description: Rule 0. - bit_offset: 0 - bit_size: 2 - array: - len: 4 - stride: 4 - enum: Rule fieldset/MasterSecAntiPolReg: description: Master Secure Level. fields: - - name: smartdma - description: SMARTDMA Data. - bit_offset: 4 - bit_size: 2 - enum: MasterSec - name: dma0 - description: eDMA0. - bit_offset: 6 - bit_size: 2 - enum: MasterSec - - name: dma1 - description: eDMA1. - bit_offset: 8 + description: DMA0. + bit_offset: 2 bit_size: 2 enum: MasterSec - name: pkc description: PKC. - bit_offset: 10 - bit_size: 2 - enum: MasterSec - - name: enet0 - description: ENET0. - bit_offset: 24 + bit_offset: 4 bit_size: 2 enum: MasterSec - - name: usb1 - description: USB1. - bit_offset: 26 + - name: dma1 + description: DMA1. + bit_offset: 6 bit_size: 2 enum: MasterSec fieldset/MasterSecLevel: description: Master Secure Level. fields: - - name: smartdma - description: SMARTDMA Data. - bit_offset: 4 - bit_size: 2 - enum: MasterSec - name: dma0 - description: eDMA0. - bit_offset: 6 - bit_size: 2 - enum: MasterSec - - name: dma1 - description: eDMA1. - bit_offset: 8 + description: DMA0. + bit_offset: 2 bit_size: 2 enum: MasterSec - name: pkc description: PKC. - bit_offset: 10 - bit_size: 2 - enum: MasterSec - - name: enet0 - description: ENET0. - bit_offset: 24 + bit_offset: 4 bit_size: 2 enum: MasterSec - - name: usb1 - description: USB1. - bit_offset: 26 + - name: dma1 + description: DMA1. + bit_offset: 6 bit_size: 2 enum: MasterSec fieldset/MiscCtrlDpReg: @@ -1173,7 +1123,18 @@ fieldset/MiscCtrlReg: bit_size: 2 enum: MiscCtrlRegIdauAllNs fieldset/RamMemRule: - description: RAMA Memory Rule 0. + description: RAMA Memory Rule. + fields: + - name: rule + description: Rule 0. + bit_offset: 0 + bit_size: 2 + array: + len: 8 + stride: 4 + enum: Rule +fieldset/RamxMemRule0: + description: RAMX Memory Rule. fields: - name: rule description: Rule 0. @@ -1214,38 +1175,13 @@ fieldset/SecVioAddr: fieldset/SecVioInfoValid: description: Security Violation Info Validity for Address. fields: - - name: vio_info_valid0 + - name: vio_info_valid description: Violation information valid flag for AHB port 0. bit_offset: 0 bit_size: 1 - - name: vio_info_valid1 - description: Violation information valid flag for AHB port 1. - bit_offset: 1 - bit_size: 1 - - name: vio_info_valid2 - description: Violation information valid flag for AHB port 2. - bit_offset: 2 - bit_size: 1 - - name: vio_info_valid3 - description: Violation information valid flag for AHB port 3. - bit_offset: 3 - bit_size: 1 - - name: vio_info_valid4 - description: Violation information valid flag for AHB port 4. - bit_offset: 4 - bit_size: 1 - - name: vio_info_valid5 - description: Violation information valid flag for AHB port 5. - bit_offset: 5 - bit_size: 1 - - name: vio_info_valid6 - description: Violation information valid flag for AHB port 6. - bit_offset: 6 - bit_size: 1 - - name: vio_info_valid7 - description: Violation information valid flag for AHB port 7. - bit_offset: 7 - bit_size: 1 + array: + len: 8 + stride: 1 fieldset/SecVioMiscInfo: description: Security Violation Miscellaneous Information at Address. fields: @@ -1271,171 +1207,156 @@ fieldset/SecVioMiscInfo: enum/LockNsMpu: bit_size: 2 variants: - - name: LOCK_NS_MPU_EQ_1 + - name: LockNsMpuEq1 description: CM33 (CPU0) LOCK_NS_MPU is 1. value: 1 - - name: LOCK_NS_MPU_EQ_0 + - name: LockNsMpuEq0 description: CM33 (CPU0) LOCK_NS_MPU is 0. value: 2 enum/LockNsVtor: bit_size: 2 variants: - - name: LOCK_NS_VTOR_EQ_1 + - name: LockNsVtorEq1 description: CM33 (CPU0) LOCKNSVTOR is 1. value: 1 - - name: LOCK_NS_VTOR_EQ_0 + - name: LockNsVtorEq0 description: CM33 (CPU0) LOCKNSVTOR is 0. value: 2 enum/LockSMpu: bit_size: 2 variants: - - name: LOCK_S_MPU_EQ_1 + - name: LockSMpuEq1 description: CM33 (CPU0) LOCK_S_MPU is 1. value: 1 - - name: LOCK_S_MPU_EQ_0 + - name: LockSMpuEq0 description: CM33 (CPU0) LOCK_S_MPU is 0. value: 2 enum/LockSVtaircr: bit_size: 2 variants: - - name: LOCK_S_VTAIRCR_EQ_1 + - name: LockSVtaircrEq1 description: CM33 (CPU0) LOCK_S_VTAIRCR is 1. value: 1 - - name: LOCK_S_VTAIRCR_EQ_0 + - name: LockSVtaircrEq0 description: CM33 (CPU0) LOCK_S_VTAIRCR is 0. value: 2 enum/LockSau: bit_size: 2 variants: - - name: LOCK_SAU_EQ_1 + - name: LockSauEq1 description: CM33 (CPU0) LOCK_SAU is 1. value: 1 - - name: LOCK_SAU_EQ_0 + - name: LockSauEq0 description: CM33 (CPU0) LOCK_SAU is 0. value: 2 enum/MasterSec: bit_size: 2 variants: - - name: NONSECURE_NONPRIV_MASTER - description: Non-secure and non-privileged Master. + - name: NonsecureNonprivMaster + description: Secure and privileged Master. value: 0 - - name: NONSECURE_PRIV_MASTER - description: Non-secure and privileged Master. - value: 1 - - name: SECURE_NONPRIV_MASTER + - name: NonsecurePrivMaster description: Secure and non-privileged Master. + value: 1 + - name: SecureNonprivMaster + description: Non-secure and privileged Master. value: 2 - - name: SECURE_PRIV_MASTER - description: Secure and privileged Master. + - name: SecurePrivMaster + description: Non-secure and non-privileged Master. value: 3 enum/MiscCtrlEnable: bit_size: 2 variants: - - name: ENABLED + - name: Enabled description: Enables the privilege checking of non-secure mode access. value: 1 - - name: DISABLED + - name: Disabled description: Disables the privilege checking of non-secure mode access. value: 2 enum/MiscCtrlRegDisableStrictMode: bit_size: 2 variants: - - name: AHBTM - description: Master can access memories and peripherals at the same level or below that level. + - name: Ahbtm + description: Master strict mode is disabled and can access memories and peripherals at the same level or below that level. value: 1 - - name: AHBSM1 - description: Master can access memories and peripherals at same level only. + - name: Ahbsm1 + description: Master strict mode is enabled and can access memories and peripherals at same level only. value: 2 enum/MiscCtrlRegDisableViolationAbort: bit_size: 2 variants: - - name: NO_ABORT + - name: NoAbort description: The violation detected by the secure checker will not cause an abort, but a secure_violation_irq (interrupt request) will still be asserted and serviced by ISR. value: 1 - - name: ABORT + - name: Abort description: The violation detected by the secure checker will cause an abort. value: 2 enum/MiscCtrlRegIdauAllNs: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: IDAU is disabled, which means that all memories are attributed as non-secure memory. value: 1 - - name: ENABLED + - name: Enabled description: IDAU is enabled (restrictive mode). value: 2 enum/MiscCtrlRegWriteLock: bit_size: 2 variants: - - name: LOCKED + - name: Locked description: Writes to this register and to the Memory and Peripheral RULE registers are not allowed. value: 1 - - name: NOT_LOCKED + - name: NotLocked description: Writes to this register and to the Memory and Peripheral RULE registers are allowed. value: 2 enum/Rule: bit_size: 2 variants: - - name: NONSECURE_NONPRIV_USER_ALLOWED + - name: NonsecureNonprivUserAllowed description: Non-secure and non-privilege user access allowed. value: 0 - - name: NONSECURE_PRIV_USER_ALLOWED + - name: NonsecurePrivUserAllowed description: Non-secure and privilege access allowed. value: 1 - - name: SECURE_NONPRIV_USER_ALLOWED + - name: SecureNonprivUserAllowed description: Secure and non-privilege user access allowed. value: 2 - - name: SECURE_PRIV_USER_ALLOWED + - name: SecurePrivUserAllowed description: Secure and privilege user access allowed. value: 3 enum/SecVioInfoDataAccess: bit_size: 1 variants: - - name: CODE + - name: Code description: Code. value: 0 - - name: DATA + - name: Data description: Data. value: 1 enum/SecVioInfoMaster: bit_size: 5 variants: - - name: CPU0_CODE - description: CM33 Code. + - name: Cpu0Code + description: M33 Code. value: 0 - - name: CPU0_SYS - description: CM33 System. + - name: Cpu0Sys + description: M33 System. value: 1 - - name: SDMA_INSTR - description: SMARTDMA Instruction. - value: 2 - - name: SDMA_DATA - description: SMARTDMA Data. - value: 3 - - name: E_DMA1 - description: eDMA1. - value: 4 - - name: E_DMA0 - description: eDMA0. + - name: Dma0 + description: DMA0. value: 5 - - name: USB_HS - description: USB HS. - value: 6 - - name: ESPI - description: eSPI. - value: 10 - - name: PKC + - name: Dma1 + description: DMA1. + value: 7 + - name: Pkc description: PKC. value: 12 - - name: ENET - description: Ethernet. - value: 13 enum/SecVioInfoWrite: bit_size: 1 variants: - - name: READ + - name: Read description: Read access. value: 0 - - name: WRITE + - name: Write description: Write access. value: 1 diff --git a/data/metadata/peripherals/mcxa/CDOG.yaml b/data/metadata/peripherals/mcxa/CDOG.yaml index 0dbb464..cc95d29 100644 --- a/data/metadata/peripherals/mcxa/CDOG.yaml +++ b/data/metadata/peripherals/mcxa/CDOG.yaml @@ -1,5 +1,5 @@ block/Cdog: - description: CDOG. + description: Code Watchdog Timer. items: - name: control description: Control Register. @@ -14,6 +14,11 @@ block/Cdog: byte_offset: 8 access: Read fieldset: InstructionTimer + - name: secure_counter + description: Secure Counter Register. + byte_offset: 12 + access: Read + fieldset: SecureCounter - name: status description: Status 1 Register. byte_offset: 16 @@ -87,11 +92,6 @@ block/Cdog: byte_offset: 72 access: Write fieldset: Sub256 - - name: assert16 - description: ASSERT16 Command Register. - byte_offset: 76 - access: Write - fieldset: Assert16 fieldset/Add: description: ADD Command Register. fields: @@ -120,13 +120,6 @@ fieldset/Add256: description: ADD 256. bit_offset: 0 bit_size: 32 -fieldset/Assert16: - description: ASSERT16 Command Register. - fields: - - name: ast16 - description: ASSERT16 Command. - bit_offset: 0 - bit_size: 32 fieldset/Control: description: Control Register. fields: @@ -229,6 +222,13 @@ fieldset/Restart: description: Restart command. bit_offset: 0 bit_size: 32 +fieldset/SecureCounter: + description: Secure Counter Register. + fields: + - name: seccnt + description: Secure Counter. + bit_offset: 0 + bit_size: 32 fieldset/Start: description: START Command Register. fields: @@ -308,39 +308,39 @@ fieldset/Sub256: enum/Ctrl: bit_size: 3 variants: - - name: ENABLE_RESET + - name: EnableReset description: Enable reset. value: 1 - - name: ENABLE_INTERRUPT + - name: EnableInterrupt description: Enable interrupt. value: 2 - - name: DISABLE_BOTH + - name: DisableBoth description: Disable both reset and interrupt. value: 4 enum/DebugHaltCtrl: bit_size: 2 variants: - - name: RUN_TIMER + - name: RunTimer description: Keep the timer running. value: 1 - - name: PAUSE_TIMER + - name: PauseTimer description: Stop the timer. value: 2 enum/IrqPause: bit_size: 2 variants: - - name: RUN_TIMER + - name: RunTimer description: Keep the timer running. value: 1 - - name: PAUSE_TIMER + - name: PauseTimer description: Stop the timer. value: 2 enum/LockCtrl: bit_size: 2 variants: - - name: LOCKED + - name: Locked description: Locked. value: 1 - - name: UNLOCKED + - name: Unlocked description: Unlocked. value: 2 diff --git a/data/metadata/peripherals/mcxa/CMC.yaml b/data/metadata/peripherals/mcxa/CMC.yaml index 6c20f44..c08da63 100644 --- a/data/metadata/peripherals/mcxa/CMC.yaml +++ b/data/metadata/peripherals/mcxa/CMC.yaml @@ -1,503 +1,629 @@ -block/CMC: - description: CMC. +block/Cmc: + description: Core Mode Controller. items: - - name: VERID + - name: verid description: Version ID. byte_offset: 0 access: Read - fieldset: VERID - - name: CKCTRL + fieldset: Verid + - name: param + description: Parameter. + byte_offset: 4 + access: Read + - name: ckctrl description: Clock Control. byte_offset: 16 - fieldset: CKCTRL - - name: CKSTAT + fieldset: Ckctrl + - name: ckstat description: Clock Status. byte_offset: 20 - fieldset: CKSTAT - - name: PMPROT + fieldset: Ckstat + - name: pmprot description: Power Mode Protection. byte_offset: 24 - fieldset: PMPROT - - name: GPMCTRL + fieldset: Pmprot + - name: gpmctrl description: Global Power Mode Control. byte_offset: 28 - fieldset: GPMCTRL - - name: PMCTRLMAIN + fieldset: Gpmctrl + - name: pmctrlmain description: Power Mode Control. byte_offset: 32 - fieldset: PMCTRLMAIN - - name: SRS + fieldset: Pmctrlmain + - name: srs description: System Reset Status. byte_offset: 128 access: Read - fieldset: SRS - - name: RPC + fieldset: Srs + - name: rpc description: Reset Pin Control. byte_offset: 132 - fieldset: RPC - - name: SSRS + fieldset: Rpc + - name: ssrs description: Sticky System Reset Status. byte_offset: 136 - fieldset: SSRS - - name: SRIE + fieldset: Ssrs + - name: srie description: System Reset Interrupt Enable. byte_offset: 140 - fieldset: SRIE - - name: SRIF + fieldset: Srie + - name: srif description: System Reset Interrupt Flag. byte_offset: 144 - fieldset: SRIF - - name: MR0 + fieldset: Srif + - name: mr0 description: Mode. byte_offset: 160 - fieldset: MR0 - - name: FM0 + fieldset: Mr0 + - name: fm0 description: Force Mode. byte_offset: 176 - fieldset: FM0 - - name: FLASHCR + fieldset: Fm0 + - name: sramdis0 + description: SRAM Shut Down Register. + byte_offset: 192 + fieldset: Sramdis0 + - name: sramret0 + description: SRAM Deep Sleep Register. + byte_offset: 208 + fieldset: Sramret0 + - name: flashcr description: Flash Control. byte_offset: 224 - fieldset: FLASHCR - - name: CORECTL + fieldset: Flashcr + - name: bsr + description: BootROM Status Register. + byte_offset: 256 + fieldset: Bsr + - name: corectl description: Core Control. byte_offset: 272 - fieldset: CORECTL - - name: DBGCTL + fieldset: Corectl + - name: dbgctl description: Debug Control. byte_offset: 288 - fieldset: DBGCTL -fieldset/CKCTRL: + fieldset: Dbgctl + - name: unlock + description: Unlock Register. + byte_offset: 512 + fieldset: Unlock + - name: test + description: Test Register. + byte_offset: 516 + fieldset: Test +fieldset/Bsr: + description: BootROM Status Register. + fields: + - name: stat + description: Provides status information written by the BootROM. + bit_offset: 0 + bit_size: 32 +fieldset/Ckctrl: description: Clock Control. fields: - - name: CKMODE + - name: ckmode description: Clocking Mode. bit_offset: 0 bit_size: 4 - enum: CKCTRL_CKMODE - - name: LOCK + enum: Ckmode + - name: lock description: Lock. bit_offset: 31 bit_size: 1 -fieldset/CKSTAT: +fieldset/Ckstat: description: Clock Status. fields: - - name: CKMODE + - name: ckmode description: Low Power Status. bit_offset: 0 bit_size: 4 - enum: CKSTAT_CKMODE - - name: WAKEUP + enum: Ckmode + - name: wakeup description: Wake-up Source. bit_offset: 8 bit_size: 8 - - name: VALID + - name: valid description: Clock Status Valid. bit_offset: 31 bit_size: 1 -fieldset/CORECTL: +fieldset/Corectl: description: Core Control. fields: - - name: NPIE + - name: npie description: Non-maskable Pin Interrupt Enable. bit_offset: 0 bit_size: 1 -fieldset/DBGCTL: +fieldset/Dbgctl: description: Debug Control. fields: - - name: SOD + - name: sod description: Sleep Or Debug. bit_offset: 0 bit_size: 1 -fieldset/FLASHCR: +fieldset/Flashcr: description: Flash Control. fields: - - name: FLASHDIS + - name: flashdis description: Flash Disable. bit_offset: 0 bit_size: 1 - - name: FLASHDOZE + - name: flashdoze description: Flash Doze. bit_offset: 1 bit_size: 1 - - name: FLASHWAKE + - name: flashwake description: Flash Wake. bit_offset: 2 bit_size: 1 -fieldset/FM0: +fieldset/Fm0: description: Force Mode. fields: - - name: FORCECFG + - name: forcecfg description: Boot Configuration. bit_offset: 0 bit_size: 1 -fieldset/GPMCTRL: +fieldset/Gpmctrl: description: Global Power Mode Control. fields: - - name: LPMODE + - name: lpmode description: Low-Power Mode. bit_offset: 0 bit_size: 4 -fieldset/MR0: +fieldset/Mr0: description: Mode. fields: - - name: ISPMODE_n - description: In System Programming Mode. + - name: ispmode_n + description: Boot Configuration. bit_offset: 0 bit_size: 1 -fieldset/PMCTRLMAIN: +fieldset/Pmctrlmain: description: Power Mode Control. fields: - - name: LPMODE + - name: lpmode description: Low-Power Mode. bit_offset: 0 bit_size: 4 - enum: PMCTRLMAIN_LPMODE -fieldset/PMPROT: + enum: PmctrlmainLpmode +fieldset/Pmprot: description: Power Mode Protection. fields: - - name: LPMODE + - name: lpmode description: Low-Power Mode. bit_offset: 0 bit_size: 4 - enum: PMPROT_LPMODE - - name: LOCK + enum: PmprotLpmode + - name: lock description: Lock Register. bit_offset: 31 bit_size: 1 -fieldset/RPC: +fieldset/Rpc: description: Reset Pin Control. fields: - - name: FILTCFG + - name: filtcfg description: Reset Filter Configuration. bit_offset: 0 bit_size: 5 - - name: FILTEN + - name: filten description: Filter Enable. bit_offset: 8 bit_size: 1 - - name: LPFEN + - name: lpfen description: Low-Power Filter Enable. bit_offset: 9 bit_size: 1 -fieldset/SRIE: +fieldset/Sramdis0: + description: SRAM Shut Down Register. + fields: + - name: dis + description: Shut Down Enable. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/Sramret0: + description: SRAM Deep Sleep Register. + fields: + - name: ret + description: Deep Sleep Enable. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/Srie: description: System Reset Interrupt Enable. fields: - - name: PIN + - name: pin description: Pin Reset. bit_offset: 8 bit_size: 1 - - name: DAP + - name: dap description: DAP Reset. bit_offset: 9 bit_size: 1 - - name: LPACK + - name: lpack description: Low Power Acknowledge Timeout Reset. bit_offset: 11 bit_size: 1 - - name: SCG + - name: scg description: System Clock Generation Reset. bit_offset: 12 bit_size: 1 - - name: WWDT0 - description: Windowed Watchdog 0 Reset. + - name: wdog0 + description: Watchdog 0 Reset. bit_offset: 13 bit_size: 1 - - name: SW + - name: sw description: Software Reset. bit_offset: 14 bit_size: 1 - - name: LOCKUP + - name: lockup description: Lockup Reset. bit_offset: 15 bit_size: 1 - - name: CDOG0 + - name: wdog1 + description: Watchdog 1 Reset. + bit_offset: 25 + bit_size: 1 + - name: cdog0 description: Code Watchdog 0 Reset. bit_offset: 26 bit_size: 1 - - name: CDOG1 + - name: cdog1 description: Code Watchdog 1 Reset. bit_offset: 27 bit_size: 1 -fieldset/SRIF: +fieldset/Srif: description: System Reset Interrupt Flag. fields: - - name: PIN + - name: pin description: Pin Reset. bit_offset: 8 bit_size: 1 - - name: DAP + - name: dap description: DAP Reset. bit_offset: 9 bit_size: 1 - - name: LPACK + - name: lpack description: Low Power Acknowledge Timeout Reset. bit_offset: 11 bit_size: 1 - - name: WWDT0 - description: Windowed Watchdog 0 Reset. + - name: wdog0 + description: Watchdog 0 Reset. bit_offset: 13 bit_size: 1 - - name: SW + - name: sw description: Software Reset. bit_offset: 14 bit_size: 1 - - name: LOCKUP + - name: lockup description: Lockup Reset. bit_offset: 15 bit_size: 1 - - name: CDOG0 + - name: wdog1 + description: Watchdog 1 Reset. + bit_offset: 25 + bit_size: 1 + - name: cdog0 description: Code Watchdog 0 Reset. bit_offset: 26 bit_size: 1 - - name: CDOG1 + - name: cdog1 description: Code Watchdog 1 Reset. bit_offset: 27 bit_size: 1 -fieldset/SRS: +fieldset/Srs: description: System Reset Status. fields: - - name: WAKEUP + - name: wakeup description: Wake-up Reset. bit_offset: 0 bit_size: 1 - - name: POR + - name: por description: Power-on Reset. bit_offset: 1 bit_size: 1 - - name: VD - description: Voltage Detect Reset. + - name: lvd + description: Low Voltage Detect Reset. bit_offset: 2 bit_size: 1 - - name: WARM + - name: hvd + description: High Voltage Detect Reset. + bit_offset: 3 + bit_size: 1 + - name: warm description: Warm Reset. bit_offset: 4 bit_size: 1 - - name: FATAL + - name: fatal description: Fatal Reset. bit_offset: 5 bit_size: 1 - - name: PIN + - name: pin description: Pin Reset. bit_offset: 8 bit_size: 1 - - name: DAP + - name: dap description: Debug Access Port Reset. bit_offset: 9 bit_size: 1 - - name: RSTACK + - name: rstack description: Reset Timeout. bit_offset: 10 bit_size: 1 - - name: LPACK + - name: lpack description: Low Power Acknowledge Timeout Reset. bit_offset: 11 bit_size: 1 - - name: SCG + - name: scg description: System Clock Generation Reset. bit_offset: 12 bit_size: 1 - - name: WWDT0 - description: Windowed Watchdog 0 Reset. + - name: wdog0 + description: Watchdog 0 Reset. bit_offset: 13 bit_size: 1 - - name: SW + - name: sw description: Software Reset. bit_offset: 14 bit_size: 1 - - name: LOCKUP + - name: lockup description: Lockup Reset. bit_offset: 15 bit_size: 1 - - name: CDOG0 + - name: wdog1 + description: Watchdog 1 Reset. + bit_offset: 25 + bit_size: 1 + - name: cdog0 description: Code Watchdog 0 Reset. bit_offset: 26 bit_size: 1 - - name: CDOG1 + - name: cdog1 description: Code Watchdog 1 Reset. bit_offset: 27 bit_size: 1 - - name: JTAG + - name: jtag description: JTAG System Reset. bit_offset: 28 bit_size: 1 - - name: TAMPER + - name: secvio + description: Security Violation Reset. + bit_offset: 30 + bit_size: 1 + - name: tamper description: Tamper Reset. bit_offset: 31 bit_size: 1 -fieldset/SSRS: +fieldset/Ssrs: description: Sticky System Reset Status. fields: - - name: WAKEUP + - name: wakeup description: Wake-up Reset. bit_offset: 0 bit_size: 1 - - name: POR + - name: por description: Power-on Reset. bit_offset: 1 bit_size: 1 - - name: VD - description: Voltage Detect Reset. + - name: lvd + description: Low Voltage Detect Reset. bit_offset: 2 bit_size: 1 - - name: WARM + - name: hvd + description: High Voltage Detect Reset. + bit_offset: 3 + bit_size: 1 + - name: warm description: Warm Reset. bit_offset: 4 bit_size: 1 - - name: FATAL + - name: fatal description: Fatal Reset. bit_offset: 5 bit_size: 1 - - name: PIN + - name: pin description: Pin Reset. bit_offset: 8 bit_size: 1 - - name: DAP + - name: dap description: DAP Reset. bit_offset: 9 bit_size: 1 - - name: RSTACK + - name: rstack description: Reset Timeout. bit_offset: 10 bit_size: 1 - - name: LPACK + - name: lpack description: Low Power Acknowledge Timeout Reset. bit_offset: 11 bit_size: 1 - - name: SCG + - name: scg description: System Clock Generation Reset. bit_offset: 12 bit_size: 1 - - name: WWDT0 - description: Windowed Watchdog 0 Reset. + - name: wdog0 + description: Watchdog 0 Reset. bit_offset: 13 bit_size: 1 - - name: SW + - name: sw description: Software Reset. bit_offset: 14 bit_size: 1 - - name: LOCKUP + - name: lockup description: Lockup Reset. bit_offset: 15 bit_size: 1 - - name: CDOG0 + - name: wdog1 + description: Watchdog 1 Reset. + bit_offset: 25 + bit_size: 1 + - name: cdog0 description: Code Watchdog 0 Reset. bit_offset: 26 bit_size: 1 - - name: CDOG1 + - name: cdog1 description: Code Watchdog 1 Reset. bit_offset: 27 bit_size: 1 - - name: JTAG + - name: jtag description: JTAG System Reset. bit_offset: 28 bit_size: 1 - - name: TAMPER + - name: secvio + description: Security Violation Reset. + bit_offset: 30 + bit_size: 1 + - name: tamper description: Tamper Reset. bit_offset: 31 bit_size: 1 -fieldset/VERID: +fieldset/Test: + description: Test Register. + fields: + - name: observe + description: Observe. + bit_offset: 0 + bit_size: 4 + enum: Observe +fieldset/Unlock: + description: Unlock Register. + fields: + - name: alwr + description: Allow Writes. + bit_offset: 0 + bit_size: 1 + - name: value + description: Value. + bit_offset: 16 + bit_size: 16 +fieldset/Verid: description: Version ID. fields: - - name: FEATURE + - name: feature description: Feature Specification Number. bit_offset: 0 bit_size: 16 - - name: MINOR + - name: minor description: Minor Version Number. bit_offset: 16 bit_size: 8 - - name: MAJOR + - name: major description: Major Version Number. bit_offset: 24 bit_size: 8 -enum/CKCTRL_CKMODE: +enum/Ckmode: bit_size: 4 variants: - - name: CKMODE0000 + - name: Ckmode0000 description: Core clock is on. value: 0 - - name: CKMODE0001 + - name: Ckmode0001 description: Core clock is off. value: 1 - - name: CKMODE1111 + - name: Ckmode0011 + description: Core and platform clocks are off. + value: 3 + - name: Ckmode0111 + description: Core, platform, and peripheral clocks are off, but no change in Low-Power mode. + value: 7 + - name: Ckmode1111 description: Core, platform, and peripheral clocks are off, and core enters Low-Power mode. value: 15 -enum/CKSTAT_CKMODE: +enum/Observe: bit_size: 4 variants: - - name: CKMODE0000 - description: Core clock is on. + - name: Test0 + description: Core Active (not sleeping, halted or in reset). value: 0 - - name: CKMODE0001 - description: Core clock is off. + - name: Test1 + description: Core clock gated. value: 1 - - name: CKMODE1111 - description: Core, platform, and peripheral clocks are off, and core enters Low-Power mode. - value: 15 -enum/PMCTRLMAIN_LPMODE: + - name: Test10 + description: Bus master clock gated. + value: 2 + - name: Test11 + description: Bus slave clock gated. + value: 3 + - name: Test100 + description: Peripherals clock gated. + value: 4 + - name: Test101 + description: Flash clock gated. + value: 5 + - name: Test110 + description: All clocks gated. + value: 6 + - name: Test111 + description: CMC clock gated. + value: 7 +enum/PmctrlmainLpmode: bit_size: 4 variants: - - name: LPMODE0000 - description: Active/Sleep. + - name: Lpmode0000 + description: Active. value: 0 - - name: LPMODE0001 - description: Deep Sleep. + - name: Lpmode0001 + description: Sleep. value: 1 - - name: LPMODE0011 - description: Power Down. + - name: Lpmode0011 + description: Deep Sleep. value: 3 - - name: LPMODE1111 + - name: Lpmode0111 + description: Power Down. + value: 7 + - name: Lpmode1111 description: Deep-Power Down. value: 15 -enum/PMPROT_LPMODE: +enum/PmprotLpmode: bit_size: 4 variants: - - name: DISABLED + - name: Disabled description: Not allowed. value: 0 - - name: EN + - name: En description: Allowed. value: 1 - - name: EN1 + - name: En1 description: Allowed. value: 2 - - name: EN2 + - name: En2 description: Allowed. value: 3 - - name: EN3 + - name: En3 description: Allowed. value: 4 - - name: EN4 + - name: En4 description: Allowed. value: 5 - - name: EN5 + - name: En5 description: Allowed. value: 6 - - name: EN6 + - name: En6 description: Allowed. value: 7 - - name: EN7 + - name: En7 description: Allowed. value: 8 - - name: EN8 + - name: En8 description: Allowed. value: 9 - - name: EN9 + - name: En9 description: Allowed. value: 10 - - name: EN10 + - name: En10 description: Allowed. value: 11 - - name: EN11 + - name: En11 description: Allowed. value: 12 - - name: EN12 + - name: En12 description: Allowed. value: 13 - - name: EN13 + - name: En13 description: Allowed. value: 14 - - name: EN14 + - name: En14 description: Allowed. value: 15 diff --git a/data/metadata/peripherals/mcxa/CRC.yaml b/data/metadata/peripherals/mcxa/CRC.yaml index cdb870e..3b5316b 100644 --- a/data/metadata/peripherals/mcxa/CRC.yaml +++ b/data/metadata/peripherals/mcxa/CRC.yaml @@ -49,43 +49,13 @@ fieldset/Ctrl: bit_offset: 30 bit_size: 2 enum: Tot -fieldset/Data: - description: Data. - fields: - - name: ll - description: Lower Part of Low Byte. - bit_offset: 0 - bit_size: 8 - - name: lu - description: Upper Part of Low Byte. - bit_offset: 8 - bit_size: 8 - - name: hl - description: Lower Part of High Byte. - bit_offset: 16 - bit_size: 8 - - name: hu - description: Upper Part of High Byte. - bit_offset: 24 - bit_size: 8 -fieldset/Gpoly: - description: Polynomial. - fields: - - name: low - description: Low Half-Word. - bit_offset: 0 - bit_size: 16 - - name: high - description: High Half-Word. - bit_offset: 16 - bit_size: 16 enum/Fxor: bit_size: 1 variants: - - name: NOXOR + - name: Noxor description: Disables XOR on reading data. value: 0 - - name: INVERT + - name: Invert description: Inverts or complements the read value of the CRC Data. value: 1 enum/Tcrc: @@ -100,39 +70,39 @@ enum/Tcrc: enum/Tot: bit_size: 2 variants: - - name: NOTRNPS + - name: Notrnps description: No transposition. value: 0 - - name: BTS_TRNPS + - name: BtsTrnps description: Bits in bytes are transposed, but bytes are not transposed. value: 1 - - name: BYTS_BTS_TRNPS + - name: BytsBtsTrnps description: Both bits in bytes and bytes are transposed. value: 2 - - name: BYTS_TRNPS + - name: BytsTrnps description: Only bytes are transposed, no bits in a byte are transposed. value: 3 enum/Totr: bit_size: 2 variants: - - name: NOTRNPS + - name: Notrnps description: No transposition. value: 0 - - name: BTS_TRNPS + - name: BtsTrnps description: Bits in bytes are transposed, but bytes are not transposed. value: 1 - - name: BYTS_BTS_TRNPS + - name: BytsBtsTrnps description: Both bits in bytes and bytes are transposed. value: 2 - - name: BYTS_TRNPS + - name: BytsTrnps description: Only bytes are transposed, no bits in a byte are transposed. value: 3 enum/Was: bit_size: 1 variants: - - name: DATA + - name: Data description: Data values. value: 0 - - name: SEED + - name: Seed description: Seed values. value: 1 diff --git a/data/metadata/peripherals/mcxa/CTIMER.yaml b/data/metadata/peripherals/mcxa/CTIMER.yaml index 51638ce..a05c844 100644 --- a/data/metadata/peripherals/mcxa/CTIMER.yaml +++ b/data/metadata/peripherals/mcxa/CTIMER.yaml @@ -70,62 +70,50 @@ fieldset/Ccr: description: Rising Edge of Capture Channel 0. bit_offset: 0 bit_size: 1 - enum: Capre - name: cap0fe description: Falling Edge of Capture Channel 0. bit_offset: 1 bit_size: 1 - enum: Capfe - name: cap0i description: Generate Interrupt on Channel 0 Capture Event. bit_offset: 2 bit_size: 1 - enum: Capi - name: cap1re description: Rising Edge of Capture Channel 1. bit_offset: 3 bit_size: 1 - enum: Capre - name: cap1fe description: Falling Edge of Capture Channel 1. bit_offset: 4 bit_size: 1 - enum: Capfe - name: cap1i description: Generate Interrupt on Channel 1 Capture Event. bit_offset: 5 bit_size: 1 - enum: Capi - name: cap2re description: Rising Edge of Capture Channel 2. bit_offset: 6 bit_size: 1 - enum: Capre - name: cap2fe description: Falling Edge of Capture Channel 2. bit_offset: 7 bit_size: 1 - enum: Capfe - name: cap2i description: Generate Interrupt on Channel 2 Capture Event. bit_offset: 8 bit_size: 1 - enum: Capi - name: cap3re description: Rising Edge of Capture Channel 3. bit_offset: 9 bit_size: 1 - enum: Capre - name: cap3fe description: Falling Edge of Capture Channel 3. bit_offset: 10 bit_size: 1 - enum: Capfe - name: cap3i description: Generate Interrupt on Channel 3 Capture Event. bit_offset: 11 bit_size: 1 - enum: Capi fieldset/Cr: description: Capture. fields: @@ -162,22 +150,18 @@ fieldset/Emr: description: External Match 0. bit_offset: 0 bit_size: 1 - enum: Em - name: em1 description: External Match 1. bit_offset: 1 bit_size: 1 - enum: Em - name: em2 description: External Match 2. bit_offset: 2 bit_size: 1 - enum: Em - name: em3 description: External Match 3. bit_offset: 3 bit_size: 1 - enum: Em - name: emc0 description: External Match Control 0. bit_offset: 4 @@ -240,82 +224,66 @@ fieldset/Mcr: description: Interrupt on MR0. bit_offset: 0 bit_size: 1 - enum: Mri - name: mr0r description: Reset on MR0. bit_offset: 1 bit_size: 1 - enum: Mrr - name: mr0s description: Stop on MR0. bit_offset: 2 bit_size: 1 - enum: Mrs - name: mr1i description: Interrupt on MR1. bit_offset: 3 bit_size: 1 - enum: Mri - name: mr1r description: Reset on MR1. bit_offset: 4 bit_size: 1 - enum: Mrr - name: mr1s description: Stop on MR1. bit_offset: 5 bit_size: 1 - enum: Mrs - name: mr2i description: Interrupt on MR2. bit_offset: 6 bit_size: 1 - enum: Mri - name: mr2r description: Reset on MR2. bit_offset: 7 bit_size: 1 - enum: Mrr - name: mr2s description: Stop on MR2. bit_offset: 8 bit_size: 1 - enum: Mrs - name: mr3i description: Interrupt on MR3. bit_offset: 9 bit_size: 1 - enum: Mri - name: mr3r description: Reset on MR3. bit_offset: 10 bit_size: 1 - enum: Mrr - name: mr3s description: Stop on MR3. bit_offset: 11 bit_size: 1 - enum: Mrs - name: mr0rl description: Reload MR. bit_offset: 24 bit_size: 1 - enum: Mrrl - name: mr1rl description: Reload MR. bit_offset: 25 bit_size: 1 - enum: Mrrl - name: mr2rl description: Reload MR. bit_offset: 26 bit_size: 1 - enum: Mrrl - name: mr3rl description: Reload MR. bit_offset: 27 bit_size: 1 - enum: Mrrl fieldset/Mr: description: Match. fields: @@ -393,156 +361,84 @@ fieldset/Tcr: description: Allow Trigger Count Enable. bit_offset: 5 bit_size: 1 -enum/Capfe: - bit_size: 1 - variants: - - name: CAPFE0 - description: Does not load. - value: 0 - - name: CAPFE1 - description: Loads. - value: 1 -enum/Capi: - bit_size: 1 - variants: - - name: CAPI0 - description: Does not generate. - value: 0 - - name: CAPI1 - description: Generates. - value: 1 -enum/Capre: - bit_size: 1 - variants: - - name: CAPRE0 - description: Does not load. - value: 0 - - name: CAPRE1 - description: Loads. - value: 1 enum/Cinsel: bit_size: 2 variants: - - name: CHANNEL_0 + - name: Channel0 description: Channel 0, CAPn[0] for CTIMERn. value: 0 - - name: CHANNEL_1 + - name: Channel1 description: Channel 1, CAPn[1] for CTIMERn. value: 1 - - name: CHANNEL_2 + - name: Channel2 description: Channel 2, CAPn[2] for CTIMERn. value: 2 - - name: CHANNEL_3 + - name: Channel3 description: Channel 3, CAPn[3] for CTIMERn. value: 3 enum/Ctmode: bit_size: 2 variants: - - name: TIMER + - name: Timer description: Timer mode. value: 0 - - name: COUNTER_RISING_EDGE + - name: CounterRisingEdge description: Counter mode rising edge. value: 1 - - name: COUNTER_FALLING_EDGE + - name: CounterFallingEdge description: Counter mode falling edge. value: 2 - - name: COUNTER_DUAL_EDGE + - name: CounterDualEdge description: Counter mode dual edge. value: 3 -enum/Em: - bit_size: 1 - variants: - - name: CLEAR - description: Low. - value: 0 - - name: SET - description: High. - value: 1 enum/Emc: bit_size: 2 variants: - - name: DO_NOTHING + - name: DoNothing description: Does nothing. value: 0 - - name: CLEAR + - name: Clear description: Goes low. value: 1 - - name: SET + - name: Set description: Goes high. value: 2 - - name: TOGGLE + - name: Toggle description: Toggles. value: 3 -enum/Mri: - bit_size: 1 - variants: - - name: MRI0 - description: Does not generate. - value: 0 - - name: MRI1 - description: Generates. - value: 1 -enum/Mrr: - bit_size: 1 - variants: - - name: MRR0 - description: Does not reset. - value: 0 - - name: MRR1 - description: Resets. - value: 1 -enum/Mrrl: - bit_size: 1 - variants: - - name: MRRL0 - description: Does not reload. - value: 0 - - name: MRRL1 - description: Reloads. - value: 1 -enum/Mrs: - bit_size: 1 - variants: - - name: MRS0 - description: Does not stop. - value: 0 - - name: MRS1 - description: Stops. - value: 1 enum/Pwmen: bit_size: 1 variants: - - name: MATCH + - name: Match description: Disable. value: 0 - - name: PWM + - name: Pwm description: Enable. value: 1 enum/Selcc: bit_size: 3 variants: - - name: CHANNEL_0_RISING + - name: Channel0Rising description: Capture channel 0 rising edge. value: 0 - - name: CHANNEL_0_FALLING + - name: Channel0Falling description: Capture channel 0 falling edge. value: 1 - - name: CHANNEL_1_RISING + - name: Channel1Rising description: Capture channel 1 rising edge. value: 2 - - name: CHANNEL_1_FALLING + - name: Channel1Falling description: Capture channel 1 falling edge. value: 3 - - name: CHANNEL_2_RISING + - name: Channel2Rising description: Capture channel 2 rising edge. value: 4 - - name: CHANNEL_2_FALLING + - name: Channel2Falling description: Capture channel 2 falling edge. value: 5 - - name: CHANNEL_3_RISING + - name: Channel3Rising description: Capture channel 3 rising edge. value: 6 - - name: CHANNEL_3_FALLING + - name: Channel3Falling description: Capture channel 3 falling edge. value: 7 diff --git a/data/metadata/peripherals/mcxa/DMA.yaml b/data/metadata/peripherals/mcxa/DMA.yaml index 139da51..690b371 100644 --- a/data/metadata/peripherals/mcxa/DMA.yaml +++ b/data/metadata/peripherals/mcxa/DMA.yaml @@ -1,3 +1,5 @@ +# File not directly generated from transforms! + block/Dma4: description: DMA MP. items: @@ -424,64 +426,64 @@ fieldset/MpInt: enum/Active: bit_size: 1 variants: - - name: IDLE + - name: Idle description: eDMA is idle. value: 0 - - name: EXECUTION + - name: Execution description: eDMA is executing a channel. value: 1 enum/Cx: bit_size: 1 variants: - - name: NORMAL_OPERATION + - name: NormalOperation description: Normal operation. value: 0 - - name: DATA_TRANSFER_CANCEL + - name: DataTransferCancel description: Cancel the remaining data transfer. value: 1 enum/Dae: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No destination address configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: Last recorded error was a configuration error detected in the TCDn_DADDR field. value: 1 enum/Dbe: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No destination bus error. value: 0 - - name: BUS_ERROR + - name: BusError description: Last recorded error was a bus error on a destination write. value: 1 enum/Doe: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No destination offset configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: Last recorded error was a configuration error detected in the TCDn_DOFF field. value: 1 enum/Hae: bit_size: 1 variants: - - name: NORMAL_OPERATION + - name: NormalOperation description: Normal operation. value: 0 - - name: HALT + - name: Halt description: Any error causes the HALT field to be set to 1. value: 1 enum/Halt: bit_size: 1 variants: - - name: NORMAL_OPERATION + - name: NormalOperation description: Normal operation. value: 0 - - name: STALL + - name: Stall description: Stall the start of any new channels. value: 1 enum/MpCsrEcx: @@ -505,54 +507,54 @@ enum/MpEsEcx: enum/Nce: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No NBYTES/CITER configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error. value: 1 enum/Sae: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No source address configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: Last recorded error was a configuration error detected in the TCDn_SADDR field. value: 1 enum/Sbe: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No source bus error. value: 0 - - name: BUS_ERROR + - name: BusError description: Last recorded error was a bus error on a source read. value: 1 enum/Sge: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No scatter/gather configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field. value: 1 enum/Soe: bit_size: 1 variants: - - name: NO_ERROR + - name: NoError description: No source offset configuration error. value: 0 - - name: CONFIGURATION_ERROR + - name: ConfigurationError description: Last recorded error was a configuration error detected in the TCDn_SOFF field. value: 1 enum/Vld: bit_size: 1 variants: - - name: NO_FIELD_SET_ONE + - name: NoFieldSetOne description: No CHn_ES[ERR] fields are set to 1. value: 0 - - name: ATLEAST_ONE_FIELD + - name: AtleastOneField description: At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared. value: 1 diff --git a/data/metadata/peripherals/mcxa/EDMA_TCD.yaml b/data/metadata/peripherals/mcxa/EDMA_TCD.yaml index 9ea28da..2036493 100644 --- a/data/metadata/peripherals/mcxa/EDMA_TCD.yaml +++ b/data/metadata/peripherals/mcxa/EDMA_TCD.yaml @@ -1,562 +1,575 @@ -block/TCD8: +# File not directly generated from transforms! + +block/Tcd8: description: DMA TCD. items: - - name: TCD - description: 'Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF.' - array: - len: 8 - stride: 4096 - byte_offset: 0 - block: TCD -block/TCD4: + - name: tcd + description: "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF." + array: + len: 8 + stride: 4096 + byte_offset: 0 + block: Tcd +block/Tcd4: description: DMA TCD. items: - - name: TCD - description: 'Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF.' - array: - len: 4 - stride: 4096 - byte_offset: 0 - block: TCD -block/TCD: - description: 'Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF.' + - name: tcd + description: "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF." + array: + len: 4 + stride: 4096 + byte_offset: 0 + block: Tcd +block/Tcd: + description: "Array of registers: CH_CSR, CH_ES, CH_INT, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF." items: - - name: CH_CSR - description: Channel Control and Status. - byte_offset: 0 - fieldset: CH_CSR - - name: CH_ES - description: Channel Error Status. - byte_offset: 4 - fieldset: CH_ES - - name: CH_INT - description: Channel Interrupt Status. - byte_offset: 8 - fieldset: CH_INT - - name: CH_SBR - description: Channel System Bus. - byte_offset: 12 - fieldset: CH_SBR - - name: CH_PRI - description: Channel Priority. - byte_offset: 16 - fieldset: CH_PRI - - name: CH_MUX - description: Channel Multiplexor Configuration. - byte_offset: 20 - fieldset: CH_MUX - - name: TCD_SADDR - description: TCD Source Address. - byte_offset: 32 - fieldset: TCD_SADDR - - name: TCD_SOFF - description: TCD Signed Source Address Offset. - byte_offset: 36 - bit_size: 16 - fieldset: TCD_SOFF - - name: TCD_ATTR - description: TCD Transfer Attributes. - byte_offset: 38 - bit_size: 16 - fieldset: TCD_ATTR - - name: TCD_NBYTES_MLOFFNO - description: TCD Transfer Size Without Minor Loop Offsets. - byte_offset: 40 - fieldset: TCD_NBYTES_MLOFFNO - - name: TCD_NBYTES_MLOFFYES - description: TCD Transfer Size with Minor Loop Offsets. - byte_offset: 40 - fieldset: TCD_NBYTES_MLOFFYES - - name: TCD_SLAST_SDA - description: TCD Last Source Address Adjustment / Store DADDR Address. - byte_offset: 44 - fieldset: TCD_SLAST_SDA - - name: TCD_DADDR - description: TCD Destination Address. - byte_offset: 48 - fieldset: TCD_DADDR - - name: TCD_DOFF - description: TCD Signed Destination Address Offset. - byte_offset: 52 - bit_size: 16 - fieldset: TCD_DOFF - - name: TCD_CITER_ELINKNO - description: TCD Current Major Loop Count (Minor Loop Channel Linking Disabled). - byte_offset: 54 - bit_size: 16 - fieldset: TCD_CITER_ELINKNO - - name: TCD_CITER_ELINKYES - description: TCD Current Major Loop Count (Minor Loop Channel Linking Enabled). - byte_offset: 54 - bit_size: 16 - fieldset: TCD_CITER_ELINKYES - - name: TCD_DLAST_SGA - description: TCD Last Destination Address Adjustment / Scatter Gather Address. - byte_offset: 56 - fieldset: TCD_DLAST_SGA - - name: TCD_CSR - description: TCD Control and Status. - byte_offset: 60 - bit_size: 16 - fieldset: TCD_CSR - - name: TCD_BITER_ELINKNO - description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled). - byte_offset: 62 - bit_size: 16 - fieldset: TCD_BITER_ELINKNO - - name: TCD_BITER_ELINKYES - description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled). - byte_offset: 62 - bit_size: 16 - fieldset: TCD_BITER_ELINKYES -fieldset/CH_CSR: + - name: ch_csr + description: Channel Control and Status. + byte_offset: 0 + fieldset: ChCsr + - name: ch_es + description: Channel Error Status. + byte_offset: 4 + fieldset: ChEs + - name: ch_int + description: Channel Interrupt Status. + byte_offset: 8 + fieldset: ChInt + - name: ch_sbr + description: Channel System Bus. + byte_offset: 12 + fieldset: ChSbr + - name: ch_pri + description: Channel Priority. + byte_offset: 16 + fieldset: ChPri + - name: ch_mux + description: Channel Multiplexor Configuration. + byte_offset: 20 + fieldset: ChMux + - name: tcd_saddr + description: TCD Source Address. + byte_offset: 32 + fieldset: TcdSaddr + - name: tcd_soff + description: TCD Signed Source Address Offset. + byte_offset: 36 + bit_size: 16 + fieldset: TcdSoff + - name: tcd_attr + description: TCD Transfer Attributes. + byte_offset: 38 + bit_size: 16 + fieldset: TcdAttr + - name: tcd_nbytes_mloffno + description: TCD Transfer Size Without Minor Loop Offsets. + byte_offset: 40 + fieldset: TcdNbytesMloffno + - name: tcd_nbytes_mloffyes + description: TCD Transfer Size with Minor Loop Offsets. + byte_offset: 40 + fieldset: TcdNbytesMloffyes + - name: tcd_slast_sda + description: TCD Last Source Address Adjustment / Store DADDR Address. + byte_offset: 44 + fieldset: TcdSlastSda + - name: tcd_daddr + description: TCD Destination Address. + byte_offset: 48 + fieldset: TcdDaddr + - name: tcd_doff + description: TCD Signed Destination Address Offset. + byte_offset: 52 + bit_size: 16 + fieldset: TcdDoff + - name: tcd_citer_elinkno + description: TCD Current Major Loop Count (Minor Loop Channel Linking Disabled). + byte_offset: 54 + bit_size: 16 + fieldset: TcdCiterElinkno + - name: tcd_citer_elinkyes + description: TCD Current Major Loop Count (Minor Loop Channel Linking Enabled). + byte_offset: 54 + bit_size: 16 + fieldset: TcdCiterElinkyes + - name: tcd_dlast_sga + description: TCD Last Destination Address Adjustment / Scatter Gather Address. + byte_offset: 56 + fieldset: TcdDlastSga + - name: tcd_csr + description: TCD Control and Status. + byte_offset: 60 + bit_size: 16 + fieldset: TcdCsr + - name: tcd_biter_elinkno + description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled). + byte_offset: 62 + bit_size: 16 + fieldset: TcdBiterElinkno + - name: tcd_biter_elinkyes + description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled). + byte_offset: 62 + bit_size: 16 + fieldset: TcdBiterElinkyes +fieldset/ChCsr: description: Channel Control and Status. fields: - - name: ERQ - description: Enable DMA Request. - bit_offset: 0 - bit_size: 1 - - name: EARQ - description: Enable Asynchronous DMA Request. - bit_offset: 1 - bit_size: 1 - - name: EEI - description: Enable Error Interrupt. - bit_offset: 2 - bit_size: 1 - - name: EBW - description: Enable Buffered Writes. - bit_offset: 3 - bit_size: 1 - - name: DONE - description: Channel Done. - bit_offset: 30 - bit_size: 1 - - name: ACTIVE - description: Channel Active. - bit_offset: 31 - bit_size: 1 -fieldset/CH_ES: + - name: erq + description: Enable DMA Request. + bit_offset: 0 + bit_size: 1 + - name: earq + description: Enable Asynchronous DMA Request. + bit_offset: 1 + bit_size: 1 + - name: eei + description: Enable Error Interrupt. + bit_offset: 2 + bit_size: 1 + - name: ebw + description: Enable Buffered Writes. + bit_offset: 3 + bit_size: 1 + - name: done + description: Channel Done. + bit_offset: 30 + bit_size: 1 + - name: active + description: Channel Active. + bit_offset: 31 + bit_size: 1 +fieldset/ChEs: description: Channel Error Status. fields: - - name: DBE - description: Destination Bus Error. - bit_offset: 0 - bit_size: 1 - - name: SBE - description: Source Bus Error. - bit_offset: 1 - bit_size: 1 - - name: SGE - description: Scatter/Gather Configuration Error. - bit_offset: 2 - bit_size: 1 - - name: NCE - description: NBYTES/CITER Configuration Error. - bit_offset: 3 - bit_size: 1 - - name: DOE - description: Destination Offset Error. - bit_offset: 4 - bit_size: 1 - - name: DAE - description: Destination Address Error. - bit_offset: 5 - bit_size: 1 - - name: SOE - description: Source Offset Error. - bit_offset: 6 - bit_size: 1 - - name: SAE - description: Source Address Error. - bit_offset: 7 - bit_size: 1 - - name: ERR - description: Error In Channel. - bit_offset: 31 - bit_size: 1 -fieldset/CH_INT: + - name: dbe + description: Destination Bus Error. + bit_offset: 0 + bit_size: 1 + - name: sbe + description: Source Bus Error. + bit_offset: 1 + bit_size: 1 + - name: sge + description: Scatter/Gather Configuration Error. + bit_offset: 2 + bit_size: 1 + - name: nce + description: NBYTES/CITER Configuration Error. + bit_offset: 3 + bit_size: 1 + - name: doe + description: Destination Offset Error. + bit_offset: 4 + bit_size: 1 + - name: dae + description: Destination Address Error. + bit_offset: 5 + bit_size: 1 + - name: soe + description: Source Offset Error. + bit_offset: 6 + bit_size: 1 + - name: sae + description: Source Address Error. + bit_offset: 7 + bit_size: 1 + - name: err + description: Error In Channel. + bit_offset: 31 + bit_size: 1 +fieldset/ChInt: description: Channel Interrupt Status. fields: - - name: INT - description: Interrupt Request. - bit_offset: 0 - bit_size: 1 -fieldset/CH_MUX: + - name: int + description: Interrupt Request. + bit_offset: 0 + bit_size: 1 +fieldset/ChMux: description: Channel Multiplexor Configuration. fields: - - name: SRC - description: Service Request Source. - bit_offset: 0 - bit_size: 7 -fieldset/CH_PRI: + - name: src + description: Service Request Source. + bit_offset: 0 + bit_size: 7 +fieldset/ChPri: description: Channel Priority. fields: - - name: APL - description: Arbitration Priority Level. - bit_offset: 0 - bit_size: 3 - - name: DPA - description: Disable Preempt Ability. - bit_offset: 30 - bit_size: 1 - enum: DPA - - name: ECP - description: Enable Channel Preemption. - bit_offset: 31 - bit_size: 1 - enum: ECP -fieldset/CH_SBR: + - name: apl + description: Arbitration Priority Level. + bit_offset: 0 + bit_size: 3 + - name: dpa + description: Disable Preempt Ability. + bit_offset: 30 + bit_size: 1 + enum: Dpa + - name: ecp + description: Enable Channel Preemption. + bit_offset: 31 + bit_size: 1 + enum: Ecp +fieldset/ChSbr: description: Channel System Bus. fields: - - name: MID - description: Master ID. - bit_offset: 0 - bit_size: 4 - - name: PAL - description: Privileged Access Level. - bit_offset: 15 - bit_size: 1 - enum: PAL - - name: EMI - description: Enable Master ID Replication. - bit_offset: 16 - bit_size: 1 -fieldset/TCD_ATTR: + - name: mid + description: Master ID. + bit_offset: 0 + bit_size: 4 + - name: sec + description: Security Level. + bit_offset: 14 + bit_size: 1 + enum: Sec + - name: pal + description: Privileged Access Level. + bit_offset: 15 + bit_size: 1 + enum: Pal + - name: emi + description: Enable Master ID Replication. + bit_offset: 16 + bit_size: 1 + - name: attr + description: Attribute Output. + bit_offset: 17 + bit_size: 4 +fieldset/TcdAttr: description: TCD Transfer Attributes. bit_size: 16 fields: - - name: DSIZE - description: Destination Data Transfer Size. - bit_offset: 0 - bit_size: 3 - enum: SIZE - - name: DMOD - description: Destination Address Modulo. - bit_offset: 3 - bit_size: 5 - - name: SSIZE - description: Source Data Transfer Size. - bit_offset: 8 - bit_size: 3 - enum: SIZE - - name: SMOD - description: Source Address Modulo. - bit_offset: 11 - bit_size: 5 - enum: SMOD -fieldset/TCD_BITER_ELINKNO: + - name: dsize + description: Destination Data Transfer Size. + bit_offset: 0 + bit_size: 3 + enum: Size + - name: dmod + description: Destination Address Modulo. + bit_offset: 3 + bit_size: 5 + - name: ssize + description: Source Data Transfer Size. + bit_offset: 8 + bit_size: 3 + enum: Size + - name: smod + description: Source Address Modulo. + bit_offset: 11 + bit_size: 5 +fieldset/TcdBiterElinkno: description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled). bit_size: 16 fields: - - name: BITER - description: Starting Major Iteration Count. - bit_offset: 0 - bit_size: 15 - - name: ELINK - description: Enables Link. - bit_offset: 15 - bit_size: 1 -fieldset/TCD_BITER_ELINKYES: + - name: biter + description: Starting Major Iteration Count. + bit_offset: 0 + bit_size: 15 + - name: elink + description: Enables Link. + bit_offset: 15 + bit_size: 1 +fieldset/TcdBiterElinkyes: description: TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled). bit_size: 16 fields: - - name: BITER - description: Starting Major Iteration Count. - bit_offset: 0 - bit_size: 9 - - name: LINKCH - description: Link Channel Number. - bit_offset: 9 - bit_size: 3 - - name: ELINK - description: Enable Link. - bit_offset: 15 - bit_size: 1 -fieldset/TCD_CITER_ELINKNO: + - name: biter + description: Starting Major Iteration Count. + bit_offset: 0 + bit_size: 9 + - name: linkch + description: Link Channel Number. + bit_offset: 9 + bit_size: 4 + - name: elink + description: Enable Link. + bit_offset: 15 + bit_size: 1 +fieldset/TcdCiterElinkno: description: TCD Current Major Loop Count (Minor Loop Channel Linking Disabled). bit_size: 16 fields: - - name: CITER - description: Current Major Iteration Count. - bit_offset: 0 - bit_size: 15 - - name: ELINK - description: Enable Link. - bit_offset: 15 - bit_size: 1 -fieldset/TCD_CITER_ELINKYES: + - name: citer + description: Current Major Iteration Count. + bit_offset: 0 + bit_size: 15 + - name: elink + description: Enable Link. + bit_offset: 15 + bit_size: 1 +fieldset/TcdCiterElinkyes: description: TCD Current Major Loop Count (Minor Loop Channel Linking Enabled). bit_size: 16 fields: - - name: CITER - description: Current Major Iteration Count. - bit_offset: 0 - bit_size: 9 - - name: LINKCH - description: Minor Loop Link Channel Number. - bit_offset: 9 - bit_size: 3 - - name: ELINK - description: Enable Link. - bit_offset: 15 - bit_size: 1 -fieldset/TCD_CSR: + - name: citer + description: Current Major Iteration Count. + bit_offset: 0 + bit_size: 9 + - name: linkch + description: Minor Loop Link Channel Number. + bit_offset: 9 + bit_size: 4 + - name: elink + description: Enable Link. + bit_offset: 15 + bit_size: 1 +fieldset/TcdCsr: description: TCD Control and Status. bit_size: 16 fields: - - name: START - description: Channel Start. - bit_offset: 0 - bit_size: 1 - enum: START - - name: INTMAJOR - description: Enable Interrupt If Major count complete. - bit_offset: 1 - bit_size: 1 - - name: INTHALF - description: Enable Interrupt If Major Counter Half-complete. - bit_offset: 2 - bit_size: 1 - - name: DREQ - description: Disable Request. - bit_offset: 3 - bit_size: 1 - enum: DREQ - - name: ESG - description: Enable Scatter/Gather Processing. - bit_offset: 4 - bit_size: 1 - enum: ESG - - name: MAJORELINK - description: Enable Link When Major Loop Complete. - bit_offset: 5 - bit_size: 1 - - name: EEOP - description: Enable End-Of-Packet Processing. - bit_offset: 6 - bit_size: 1 - - name: ESDA - description: Enable Store Destination Address. - bit_offset: 7 - bit_size: 1 - - name: MAJORLINKCH - description: Major Loop Link Channel Number. - bit_offset: 8 - bit_size: 3 - - name: BWC - description: Bandwidth Control. - bit_offset: 14 - bit_size: 2 - enum: BWC -fieldset/TCD_DADDR: + - name: start + description: Channel Start. + bit_offset: 0 + bit_size: 1 + enum: Start + - name: intmajor + description: Enable Interrupt If Major count complete. + bit_offset: 1 + bit_size: 1 + - name: inthalf + description: Enable Interrupt If Major Counter Half-complete. + bit_offset: 2 + bit_size: 1 + - name: dreq + description: Disable Request. + bit_offset: 3 + bit_size: 1 + enum: Dreq + - name: esg + description: Enable Scatter/Gather Processing. + bit_offset: 4 + bit_size: 1 + enum: Esg + - name: majorelink + description: Enable Link When Major Loop Complete. + bit_offset: 5 + bit_size: 1 + - name: eeop + description: Enable End-Of-Packet Processing. + bit_offset: 6 + bit_size: 1 + - name: esda + description: Enable Store Destination Address. + bit_offset: 7 + bit_size: 1 + - name: majorlinkch + description: Major Loop Link Channel Number. + bit_offset: 8 + bit_size: 4 + - name: bwc + description: Bandwidth Control. + bit_offset: 14 + bit_size: 2 + enum: Bwc +fieldset/TcdDaddr: description: TCD Destination Address. fields: - - name: DADDR - description: Destination Address. - bit_offset: 0 - bit_size: 32 -fieldset/TCD_DLAST_SGA: + - name: daddr + description: Destination Address. + bit_offset: 0 + bit_size: 32 +fieldset/TcdDlastSga: description: TCD Last Destination Address Adjustment / Scatter Gather Address. fields: - - name: DLAST_SGA - description: Last Destination Address Adjustment / Scatter Gather Address. - bit_offset: 0 - bit_size: 32 -fieldset/TCD_DOFF: + - name: dlast_sga + description: Last Destination Address Adjustment / Scatter Gather Address. + bit_offset: 0 + bit_size: 32 +fieldset/TcdDoff: description: TCD Signed Destination Address Offset. bit_size: 16 fields: - - name: DOFF - description: Destination Address Signed Offset. - bit_offset: 0 - bit_size: 16 -fieldset/TCD_NBYTES_MLOFFNO: + - name: doff + description: Destination Address Signed Offset. + bit_offset: 0 + bit_size: 16 +fieldset/TcdNbytesMloffno: description: TCD Transfer Size Without Minor Loop Offsets. fields: - - name: NBYTES - description: Number of Bytes To Transfer Per Service Request. - bit_offset: 0 - bit_size: 30 - - name: DMLOE - description: Destination Minor Loop Offset Enable. - bit_offset: 30 - bit_size: 1 - enum: TCD_NBYTES_MLOFFNO_DMLOE - - name: SMLOE - description: Source Minor Loop Offset Enable. - bit_offset: 31 - bit_size: 1 - enum: TCD_NBYTES_MLOFFNO_SMLOE -fieldset/TCD_NBYTES_MLOFFYES: + - name: nbytes + description: Number of Bytes To Transfer Per Service Request. + bit_offset: 0 + bit_size: 30 + - name: dmloe + description: Destination Minor Loop Offset Enable. + bit_offset: 30 + bit_size: 1 + enum: TcdNbytesMloffnoDmloe + - name: smloe + description: Source Minor Loop Offset Enable. + bit_offset: 31 + bit_size: 1 + enum: TcdNbytesMloffnoSmloe +fieldset/TcdNbytesMloffyes: description: TCD Transfer Size with Minor Loop Offsets. fields: - - name: NBYTES - description: Number of Bytes To Transfer Per Service Request. - bit_offset: 0 - bit_size: 10 - - name: MLOFF - description: Minor Loop Offset. - bit_offset: 10 - bit_size: 20 - - name: DMLOE - description: Destination Minor Loop Offset Enable. - bit_offset: 30 - bit_size: 1 - enum: TCD_NBYTES_MLOFFYES_DMLOE - - name: SMLOE - description: Source Minor Loop Offset Enable. - bit_offset: 31 - bit_size: 1 - enum: TCD_NBYTES_MLOFFYES_SMLOE -fieldset/TCD_SADDR: + - name: nbytes + description: Number of Bytes To Transfer Per Service Request. + bit_offset: 0 + bit_size: 10 + - name: mloff + description: Minor Loop Offset. + bit_offset: 10 + bit_size: 20 + - name: dmloe + description: Destination Minor Loop Offset Enable. + bit_offset: 30 + bit_size: 1 + enum: TcdNbytesMloffyesDmloe + - name: smloe + description: Source Minor Loop Offset Enable. + bit_offset: 31 + bit_size: 1 + enum: TcdNbytesMloffyesSmloe +fieldset/TcdSaddr: description: TCD Source Address. fields: - - name: SADDR - description: Source Address. - bit_offset: 0 - bit_size: 32 -fieldset/TCD_SLAST_SDA: + - name: saddr + description: Source Address. + bit_offset: 0 + bit_size: 32 +fieldset/TcdSlastSda: description: TCD Last Source Address Adjustment / Store DADDR Address. fields: - - name: SLAST_SDA - description: Last Source Address Adjustment / Store DADDR Address. - bit_offset: 0 - bit_size: 32 -fieldset/TCD_SOFF: + - name: slast_sda + description: Last Source Address Adjustment / Store DADDR Address. + bit_offset: 0 + bit_size: 32 +fieldset/TcdSoff: description: TCD Signed Source Address Offset. bit_size: 16 fields: - - name: SOFF - description: Source Address Signed Offset. - bit_offset: 0 - bit_size: 16 -enum/BWC: + - name: soff + description: Source Address Signed Offset. + bit_offset: 0 + bit_size: 16 +enum/Bwc: bit_size: 2 variants: - - name: NO_STALL - description: No eDMA engine stalls. - value: 0 - - name: ENGINE_STALLS_FOUR - description: eDMA engine stalls for 4 cycles after each R/W. - value: 2 - - name: ENGINE_STALLS_EIGHT - description: eDMA engine stalls for 8 cycles after each R/W. - value: 3 -enum/DPA: + - name: NoStall + description: No eDMA engine stalls. + value: 0 + - name: EngineStallsFour + description: eDMA engine stalls for 4 cycles after each R/W. + value: 2 + - name: EngineStallsEight + description: eDMA engine stalls for 8 cycles after each R/W. + value: 3 +enum/Dpa: bit_size: 1 variants: - - name: SUSPEND - description: Channel can suspend a lower-priority channel. - value: 0 - - name: CANNOT_SUSPEND - description: Channel cannot suspend any other channel, regardless of channel priority. - value: 1 -enum/DREQ: + - name: Suspend + description: Channel can suspend a lower-priority channel. + value: 0 + - name: CannotSuspend + description: Channel cannot suspend any other channel, regardless of channel priority. + value: 1 +enum/Dreq: bit_size: 1 variants: - - name: CHANNEL_NOT_AFFECTED - description: No operation. - value: 0 - - name: ERQ_FIELD_CLEAR - description: Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests. - value: 1 -enum/ECP: + - name: ChannelNotAffected + description: No operation. + value: 0 + - name: ErqFieldClear + description: Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests. + value: 1 +enum/Ecp: bit_size: 1 variants: - - name: CANNOT_SUSPEND - description: Channel cannot be suspended by a higher-priority channel's service request. - value: 0 - - name: SUSPEND - description: Channel can be temporarily suspended by a higher-priority channel's service request. - value: 1 -enum/ESG: + - name: CannotSuspend + description: Channel cannot be suspended by a higher-priority channel's service request. + value: 0 + - name: Suspend + description: Channel can be temporarily suspended by a higher-priority channel's service request. + value: 1 +enum/Esg: bit_size: 1 variants: - - name: NORMAL_FORMAT - description: Current channel's TCD is normal format. - value: 0 - - name: SCATTER_GATHER_FORMAT - description: Current channel's TCD specifies scatter/gather format. - value: 1 -enum/PAL: + - name: NormalFormat + description: Current channel's TCD is normal format. + value: 0 + - name: ScatterGatherFormat + description: Current channel's TCD specifies scatter/gather format. + value: 1 +enum/Pal: bit_size: 1 variants: - - name: USER_PROTECTION - description: User protection level for DMA transfers. - value: 0 - - name: PRIVILEGED_PROTECTION - description: Privileged protection level for DMA transfers. - value: 1 -enum/SMOD: - bit_size: 5 + - name: UserProtection + description: User protection level for DMA transfers. + value: 0 + - name: PrivilegedProtection + description: Privileged protection level for DMA transfers. + value: 1 +enum/Sec: + bit_size: 1 variants: - - name: DISABLE - description: Source address modulo feature disabled. - value: 0 -enum/SIZE: + - name: NonsecureProtection + description: Nonsecure protection level for DMA transfers. + value: 0 + - name: SecureProtection + description: Secure protection level for DMA transfers. + value: 1 +enum/Size: bit_size: 3 variants: - - name: EIGHT_BIT - description: 8-bit. - value: 0 - - name: SIXTEEN_BIT - description: 16-bit. - value: 1 - - name: THIRTYTWO_BIT - description: 32-bit. - value: 2 - - name: SIXTYFOUR_BIT - description: 64-bit. - value: 3 - - name: SIXTEEN_BYTE - description: 16-byte. - value: 4 - - name: THIRTYTWO_BYTE - description: 32-byte. - value: 5 -enum/START: + - name: EightBit + description: 8-bit. + value: 0 + - name: SixteenBit + description: 16-bit. + value: 1 + - name: ThirtytwoBit + description: 32-bit. + value: 2 + - name: SixtyfourBit + description: 64-bit. + value: 3 + - name: SixteenByte + description: 16-byte. + value: 4 + - name: ThirtytwoByte + description: 32-byte. + value: 5 +enum/Start: bit_size: 1 variants: - - name: CHANNEL_NOT_STARTED - description: Channel not explicitly started. - value: 0 - - name: CHANNEL_STARTED - description: Channel explicitly started via a software-initiated service request. - value: 1 -enum/TCD_NBYTES_MLOFFNO_DMLOE: + - name: ChannelNotStarted + description: Channel not explicitly started. + value: 0 + - name: ChannelStarted + description: Channel explicitly started via a software-initiated service request. + value: 1 +enum/TcdNbytesMloffnoDmloe: bit_size: 1 variants: - - name: OFFSET_NOT_APPLIED - description: Minor loop offset not applied to DADDR. - value: 0 - - name: OFFSET_APPLIED - description: Minor loop offset applied to DADDR. - value: 1 -enum/TCD_NBYTES_MLOFFNO_SMLOE: + - name: OffsetNotApplied + description: Minor loop offset not applied to DADDR. + value: 0 + - name: OffsetApplied + description: Minor loop offset applied to DADDR. + value: 1 +enum/TcdNbytesMloffnoSmloe: bit_size: 1 variants: - - name: OFFSET_NOT_APPLIED - description: Minor loop offset not applied to SADDR. - value: 0 - - name: OFFSET_APPLIED - description: Minor loop offset applied to SADDR. - value: 1 -enum/TCD_NBYTES_MLOFFYES_DMLOE: + - name: OffsetNotApplied + description: Minor loop offset not applied to SADDR. + value: 0 + - name: OffsetApplied + description: Minor loop offset applied to SADDR. + value: 1 +enum/TcdNbytesMloffyesDmloe: bit_size: 1 variants: - - name: OFFSET_NOT_APPLIED - description: Minor loop offset not applied to DADDR. - value: 0 - - name: OFFSET_APPLIED - description: Minor loop offset applied to DADDR. - value: 1 -enum/TCD_NBYTES_MLOFFYES_SMLOE: + - name: OffsetNotApplied + description: Minor loop offset not applied to DADDR. + value: 0 + - name: OffsetApplied + description: Minor loop offset applied to DADDR. + value: 1 +enum/TcdNbytesMloffyesSmloe: bit_size: 1 variants: - - name: OFFSET_NOT_APPLIED - description: Minor loop offset not applied to SADDR. - value: 0 - - name: OFFSET_APPLIED - description: Minor loop offset applied to SADDR. - value: 1 + - name: OffsetNotApplied + description: Minor loop offset not applied to SADDR. + value: 0 + - name: OffsetApplied + description: Minor loop offset applied to SADDR. + value: 1 diff --git a/data/metadata/peripherals/mcxa/FLEXPWM.yaml b/data/metadata/peripherals/mcxa/FLEXPWM.yaml index c4b3187..5935f33 100644 --- a/data/metadata/peripherals/mcxa/FLEXPWM.yaml +++ b/data/metadata/peripherals/mcxa/FLEXPWM.yaml @@ -1159,486 +1159,486 @@ fieldset/Swcout: enum/Fauto: bit_size: 4 variants: - - name: MANUAL + - name: Manual description: Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL[FSAFE]. value: 0 - - name: AUTOMATIC + - name: Automatic description: Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. value: 1 enum/Fflag: bit_size: 4 variants: - - name: NO_FLAG + - name: NoFlag description: No fault on the FAULTx pin. value: 0 - - name: FLAG + - name: Flag description: Fault on the FAULTx pin. value: 1 enum/Ffull: bit_size: 4 variants: - - name: PWM_OUTPUTS_NOT_REENABLED + - name: PwmOutputsNotReenabled description: PWM outputs are not re-enabled at the start of a full cycle. value: 0 - - name: PWM_OUTPUTS_REENABLED + - name: PwmOutputsReenabled description: PWM outputs are re-enabled at the start of a full cycle. value: 1 enum/Fhalf: bit_size: 4 variants: - - name: PWM_OUTPUTS_NOT_REENABLED + - name: PwmOutputsNotReenabled description: PWM outputs are not re-enabled at the start of a half cycle. value: 0 - - name: PWM_OUTPUTS_REENABLED + - name: PwmOutputsReenabled description: PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). value: 1 enum/Fie: bit_size: 4 variants: - - name: DISABLED + - name: Disabled description: FAULTx CPU interrupt requests disabled. value: 0 - - name: ENABLED + - name: Enabled description: FAULTx CPU interrupt requests enabled. value: 1 enum/Flvl: bit_size: 4 variants: - - name: LOGIC_0 + - name: Logic0 description: A logic 0 on the fault input indicates a fault condition. value: 0 - - name: LOGIC_1 + - name: Logic1 description: A logic 1 on the fault input indicates a fault condition. value: 1 enum/Fsafe: bit_size: 4 variants: - - name: NORMAL + - name: Normal description: Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). value: 0 - - name: SAFE + - name: Safe description: Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. value: 1 enum/Ipol: bit_size: 4 variants: - - name: PWM23 + - name: Pwm23 description: PWM23 is used to generate complementary PWM pair in the corresponding submodule. value: 0 - - name: PWM45 + - name: Pwm45 description: PWM45 is used to generate complementary PWM pair in the corresponding submodule. value: 1 enum/Ldok: bit_size: 4 variants: - - name: DISABLED + - name: Disabled description: Do not load new values. value: 0 - - name: ENABLED + - name: Enabled description: Load prescaler, modulus, and PWM values of the corresponding submodule. value: 1 enum/Nocomb: bit_size: 4 variants: - - name: ENABLED + - name: Enabled description: There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. value: 0 - - name: DISABLED + - name: Disabled description: The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. value: 1 enum/Run: bit_size: 4 variants: - - name: DISABLED + - name: Disabled description: PWM counter is stopped, but PWM outputs hold the current state. value: 0 - - name: ENABLED + - name: Enabled description: PWM counter is started in the corresponding submodule. value: 1 enum/SmcaptctrlxEdgx: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: Disabled. value: 0 - - name: FALLING_EDGE + - name: FallingEdge description: Capture falling edges. value: 1 - - name: RISING_EDGE + - name: RisingEdge description: Capture rising edges. value: 2 - - name: ANY_EDGE + - name: AnyEdge description: Capture any edge. value: 3 enum/SmcaptctrlxInpSelx: bit_size: 1 variants: - - name: PWM_X + - name: PwmX description: Raw PWM_X input signal selected as source. value: 0 - - name: EDGE_COUNTER + - name: EdgeCounter description: Edge Counter. value: 1 enum/SmcaptctrlxOneshotx: bit_size: 1 variants: - - name: FREE_RUNNING + - name: FreeRunning description: Free Running. value: 0 - - name: ONE_SHOT + - name: OneShot description: One Shot. value: 1 enum/SmctrlClkSel: bit_size: 2 variants: - - name: IPBUS + - name: Ipbus description: The IPBus clock is used as the clock for the local prescaler and counter. value: 0 - - name: EXT_CLK + - name: ExtClk description: EXT_CLK is used as the clock for the local prescaler and counter. value: 1 - - name: AUX_CLK + - name: AuxClk description: Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0. value: 2 enum/SmctrlCompmode: bit_size: 1 variants: - - name: EQUAL_TO + - name: EqualTo description: The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period. value: 0 - - name: EQUAL_TO_OR_GREATER_THAN + - name: EqualToOrGreaterThan description: The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. value: 1 enum/SmctrlForceSel: bit_size: 3 variants: - - name: LOCAL + - name: Local description: The local force signal, CTRL2[FORCE], from this submodule is used to force updates. value: 0 - - name: MASTER + - name: Master description: The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0. value: 1 - - name: LOCAL_RELOAD + - name: LocalReload description: The local reload signal from this submodule is used to force updates without regard to the state of LDOK. value: 2 - - name: MASTER_RELOAD + - name: MasterReload description: The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. value: 3 - - name: LOCAL_SYNC + - name: LocalSync description: The local sync signal from this submodule is used to force updates. value: 4 - - name: MASTER_SYNC + - name: MasterSync description: The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. value: 5 - - name: EXT_FORCE + - name: ExtForce description: The external force signal, EXT_FORCE, from outside the PWM module causes updates. value: 6 - - name: EXT_SYNC + - name: ExtSync description: The external sync signal, EXT_SYNC, from outside the PWM module causes updates. value: 7 enum/SmctrlIndep: bit_size: 1 variants: - - name: COMPLEMENTARY + - name: Complementary description: PWM_A and PWM_B form a complementary PWM pair. value: 0 - - name: INDEPENDENT + - name: Independent description: PWM_A and PWM_B outputs are independent PWMs. value: 1 enum/SmctrlInitSel: bit_size: 2 variants: - - name: PWM_X + - name: PwmX description: Local sync (PWM_X) causes initialization. value: 0 - - name: MASTER_RELOAD + - name: MasterReload description: Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs. value: 1 - - name: MASTER_SYNC + - name: MasterSync description: Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. value: 2 - - name: EXT_SYNC + - name: ExtSync description: EXT_SYNC causes initialization. value: 3 enum/SmctrlLdfq: bit_size: 4 variants: - - name: EVERYPWM + - name: Everypwm description: Every PWM opportunity. value: 0 - - name: EVERY2PWM + - name: Every2pwm description: Every 2 PWM opportunities. value: 1 - - name: EVERY3PWM + - name: Every3pwm description: Every 3 PWM opportunities. value: 2 - - name: EVERY4PWM + - name: Every4pwm description: Every 4 PWM opportunities. value: 3 - - name: EVERY5PWM + - name: Every5pwm description: Every 5 PWM opportunities. value: 4 - - name: EVERY6PWM + - name: Every6pwm description: Every 6 PWM opportunities. value: 5 - - name: EVERY7PWM + - name: Every7pwm description: Every 7 PWM opportunities. value: 6 - - name: EVERY8PWM + - name: Every8pwm description: Every 8 PWM opportunities. value: 7 - - name: EVERY9PWM + - name: Every9pwm description: Every 9 PWM opportunities. value: 8 - - name: EVERY10PWM + - name: Every10pwm description: Every 10 PWM opportunities. value: 9 - - name: EVERY11PWM + - name: Every11pwm description: Every 11 PWM opportunities. value: 10 - - name: EVERY12PWM + - name: Every12pwm description: Every 12 PWM opportunities. value: 11 - - name: EVERY13PWM + - name: Every13pwm description: Every 13 PWM opportunities. value: 12 - - name: EVERY14PWM + - name: Every14pwm description: Every 14 PWM opportunities. value: 13 - - name: EVERY15PWM + - name: Every15pwm description: Every 15 PWM opportunities. value: 14 - - name: EVERY16PWM + - name: Every16pwm description: Every 16 PWM opportunities. value: 15 enum/SmctrlLdmod: bit_size: 1 variants: - - name: NEXT_PWM_RELOAD + - name: NextPwmReload description: Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. value: 0 - - name: MTCTRL_LDOK_SET + - name: MtctrlLdokSet description: Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. value: 1 enum/SmctrlPrsc: bit_size: 3 variants: - - name: ONE + - name: One description: Prescaler 1. value: 0 - - name: TWO + - name: Two description: Prescaler 2. value: 1 - - name: FOUR + - name: Four description: Prescaler 4. value: 2 - - name: EIGHT + - name: Eight description: Prescaler 8. value: 3 - - name: SIXTEEN + - name: Sixteen description: Prescaler 16. value: 4 - - name: THIRTYTWO + - name: Thirtytwo description: Prescaler 32. value: 5 - - name: SIXTYFOUR + - name: Sixtyfour description: Prescaler 64. value: 6 - - name: HUNDREDTWENTYEIGHT + - name: Hundredtwentyeight description: Prescaler 128. value: 7 enum/SmctrlReloadSel: bit_size: 1 variants: - - name: LOCAL + - name: Local description: The local RELOAD signal is used to reload registers. value: 0 - - name: MASTER + - name: Master description: The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0. value: 1 enum/SmdmaenCaptde: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: Read DMA requests disabled. value: 0 - - name: EXCEEDFIFO + - name: Exceedfifo description: Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which watermark(s) the DMA request is sensitive. value: 1 - - name: LOCAL_SYNC + - name: LocalSync description: A local synchronization (VAL1 matches counter) sets the read DMA request. value: 2 - - name: LOCAL_RELOAD + - name: LocalReload description: A local reload (STS[RF] being set) sets the read DMA request. value: 3 enum/SmdmaenFand: bit_size: 1 variants: - - name: OR + - name: Or description: Selected FIFO watermarks are OR'ed together. value: 0 - - name: AND + - name: And description: Selected FIFO watermarks are AND'ed together. value: 1 enum/SmintenCmpie: bit_size: 6 variants: - - name: DISABLED + - name: Disabled description: The corresponding STS[CMPF] bit will not cause an interrupt request. value: 0 - - name: ENABLED + - name: Enabled description: The corresponding STS[CMPF] bit will cause an interrupt request. value: 1 enum/SmoctrlPwmafs: bit_size: 2 variants: - - name: LOGIC_0 + - name: Logic0 description: Output is forced to logic 0 state prior to consideration of output polarity control. value: 0 - - name: LOGIC_1 + - name: Logic1 description: Output is forced to logic 1 state prior to consideration of output polarity control. value: 1 - - name: TRISTATED_2 + - name: Tristated2 description: Output is put in a high-impedance state. value: 2 - - name: TRISTATED_3 + - name: Tristated3 description: Output is put in a high-impedance state. value: 3 enum/SmoctrlPwmbfs: bit_size: 2 variants: - - name: LOGIC_0 + - name: Logic0 description: Output is forced to logic 0 state prior to consideration of output polarity control. value: 0 - - name: LOGIC_1 + - name: Logic1 description: Output is forced to logic 1 state prior to consideration of output polarity control. value: 1 - - name: TRISTATED_2 + - name: Tristated2 description: Output is put in a high-impedance state. value: 2 - - name: TRISTATED_3 + - name: Tristated3 description: Output is put in a high-impedance state. value: 3 enum/SmoctrlPwmxfs: bit_size: 2 variants: - - name: LOGIC_0 + - name: Logic0 description: Output is forced to logic 0 state prior to consideration of output polarity control. value: 0 - - name: LOGIC_1 + - name: Logic1 description: Output is forced to logic 1 state prior to consideration of output polarity control. value: 1 - - name: TRISTATED_2 + - name: Tristated2 description: Output is put in a high-impedance state. value: 2 - - name: TRISTATED_3 + - name: Tristated3 description: Output is put in a high-impedance state. value: 3 enum/Smout: bit_size: 1 variants: - - name: LOGIC_0 + - name: Logic0 description: A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. value: 0 - - name: LOGIC_1 + - name: Logic1 description: A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. value: 1 enum/Smsel23: bit_size: 2 variants: - - name: PWM + - name: pwm description: Generated SM0PWM23 signal used by the deadtime logic. value: 0 - - name: INVERTED_PWM + - name: Invertedpwm description: Inverted generated SM0PWM23 signal used by the deadtime logic. value: 1 - - name: OUT + - name: out description: SWCOUT[SM0OUT23] used by the deadtime logic. value: 2 - - name: PWM_EXTA + - name: PwmExta description: PWM0_EXTA signal used by the deadtime logic. value: 3 enum/Smsel45: bit_size: 2 variants: - - name: PWM + - name: pwm description: Generated SM0PWM45 signal used by the deadtime logic. value: 0 - - name: INVERTED_PWM + - name: Invertedpwm description: Inverted generated SM0PWM45 signal used by the deadtime logic. value: 1 - - name: OUT + - name: out description: SWCOUT[SM0OUT45] used by the deadtime logic. value: 2 enum/SmstsCmpf: bit_size: 6 variants: - - name: NO_EVENT + - name: NoEvent description: No compare event has occurred for a particular VALx value. value: 0 - - name: EVENT + - name: Event description: A compare event has occurred for a particular VALx value. value: 1 enum/SmtctrlOutTrigEn: bit_size: 6 variants: - - name: VAL0 + - name: Val0 description: PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. value: 1 enum/SmtctrlPwaot: bit_size: 1 variants: - - name: PWM_OUT_TRIG0_SIGNAL + - name: PwmOutTrig0Signal description: Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. value: 0 - - name: PWMA_OUTPUT + - name: PwmaOutput description: Route the PWM_A output to the PWM_MUX_TRIG0 port. value: 1 enum/SmtctrlPwbot: bit_size: 1 variants: - - name: PWM_OUT_TRIG1_SIGNAL + - name: PwmOutTrig1Signal description: Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. value: 0 - - name: PWMB_OUTPUT + - name: PwmbOutput description: Route the PWM_B output to the PWM_MUX_TRIG1 port. value: 1 enum/SmtctrlTrgfrq: bit_size: 1 variants: - - name: EVERYPWM + - name: Everypwm description: Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. value: 0 - - name: FINALPWM + - name: Finalpwm description: Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. value: 1 enum/StretchCntPrsc: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: Stretch count is zero, no stretch. value: 0 - - name: ENABLED + - name: Enabled description: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. value: 1 - - name: DISABLED_LOCKED + - name: DisabledLocked description: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. value: 2 - - name: ENABLED_LOCKED + - name: EnabledLocked description: Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. value: 3 enum/Wrprot: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: Write protection off (default). value: 0 - - name: ENABLED + - name: Enabled description: Write protection on. value: 1 - - name: DISABLED_LOCKED + - name: DisabledLocked description: Write protection off and locked until chip reset. value: 2 - - name: ENABLED_LOCKED + - name: EnabledLocked description: Write protection on and locked until chip reset. value: 3 diff --git a/data/metadata/peripherals/mcxa/FMU.yaml b/data/metadata/peripherals/mcxa/FMU.yaml index a5c6b9c..bcf78b3 100644 --- a/data/metadata/peripherals/mcxa/FMU.yaml +++ b/data/metadata/peripherals/mcxa/FMU.yaml @@ -1,335 +1,413 @@ -block/FMU: +block/Fmu: description: Flash. items: - - name: FSTAT + - name: fstat description: Flash Status Register. byte_offset: 0 - fieldset: FSTAT - - name: FCNFG + fieldset: Fstat + - name: fcnfg description: Flash Configuration Register. byte_offset: 4 - fieldset: FCNFG - - name: FCTRL + fieldset: Fcnfg + - name: fctrl description: Flash Control Register. byte_offset: 8 - fieldset: FCTRL - - name: FCCOB + fieldset: Fctrl + - name: ftest + description: Flash Test Register. + byte_offset: 12 + access: Read + fieldset: Ftest + - name: fccob description: Flash Common Command Object Registers. array: len: 8 stride: 4 byte_offset: 16 - fieldset: FCCOB -fieldset/FCCOB: + fieldset: Fccob +fieldset/Fccob: description: Flash Common Command Object Registers. fields: - - name: CCOBn + - name: cco_bn description: CCOBn. bit_offset: 0 bit_size: 32 -fieldset/FCNFG: +fieldset/Fcnfg: description: Flash Configuration Register. fields: - - name: CCIE + - name: ccie description: Command Complete Interrupt Enable. bit_offset: 7 bit_size: 1 - enum: CCIE - - name: ERSREQ + enum: Ccie + - name: ersreq description: Mass Erase Request. bit_offset: 8 bit_size: 1 - enum: ERSREQ - - name: DFDIE + enum: Ersreq + - name: dfdie description: Double Bit Fault Detect Interrupt Enable. bit_offset: 16 bit_size: 1 - enum: DFDIE - - name: ERSIEN0 + enum: Dfdie + - name: ersien0 description: Erase IFR Sector Enable - Block 0. bit_offset: 24 bit_size: 4 - enum: ERSIEN0 - - name: ERSIEN1 + enum: Ersien0 + - name: ersien1 description: Erase IFR Sector Enable - Block 1 (for dual block configs). bit_offset: 28 bit_size: 4 - enum: ERSIEN1 -fieldset/FCTRL: + enum: Ersien1 +fieldset/Fctrl: description: Flash Control Register. fields: - - name: RWSC + - name: rwsc description: Read Wait-State Control. bit_offset: 0 bit_size: 4 - - name: LSACTIVE + - name: lsactive description: Low speed active mode. bit_offset: 8 bit_size: 1 - enum: LSACTIVE - - name: FDFD + enum: Lsactive + - name: fdfd description: Force Double Bit Fault Detect. bit_offset: 16 bit_size: 1 - enum: FDFD - - name: ABTREQ + enum: Fdfd + - name: abtreq description: Abort Request. bit_offset: 24 bit_size: 1 - enum: ABTREQ -fieldset/FSTAT: + enum: Abtreq +fieldset/Fstat: description: Flash Status Register. fields: - - name: FAIL + - name: fail description: Command Fail Flag. bit_offset: 0 bit_size: 1 - enum: FAIL - - name: CMDABT + enum: Fail + - name: cmdabt description: Command Abort Flag. bit_offset: 2 bit_size: 1 - enum: CMDABT - - name: PVIOL + enum: Cmdabt + - name: pviol description: Command Protection Violation Flag. bit_offset: 4 bit_size: 1 - enum: PVIOL - - name: ACCERR + enum: Pviol + - name: accerr description: Command Access Error Flag. bit_offset: 5 bit_size: 1 - enum: ACCERR - - name: CWSABT + enum: Accerr + - name: cwsabt description: Command Write Sequence Abort Flag. bit_offset: 6 bit_size: 1 - enum: CWSABT - - name: CCIF + enum: Cwsabt + - name: ccif description: Command Complete Interrupt Flag. bit_offset: 7 bit_size: 1 - enum: CCIF - - name: CMDPRT + enum: Ccif + - name: cmdprt description: Command protection level. bit_offset: 8 bit_size: 2 - enum: CMDPRT - - name: CMDP + enum: Cmdprt + - name: cmdp description: Command protection status flag. bit_offset: 11 bit_size: 1 - enum: CMDP - - name: CMDDID + enum: Cmdp + - name: cmddid description: Command domain ID. bit_offset: 12 bit_size: 4 - - name: DFDIF + - name: dfdif description: Double Bit Fault Detect Interrupt Flag. bit_offset: 16 bit_size: 1 - enum: DFDIF - - name: SALV_USED + enum: Dfdif + - name: salv_used description: Salvage Used for Erase operation. bit_offset: 17 bit_size: 1 - enum: SALV_USED - - name: PEWEN + enum: SalvUsed + - name: pewen description: Program-Erase Write Enable Control. bit_offset: 24 bit_size: 2 - enum: PEWEN - - name: PERDY + enum: Pewen + - name: perdy description: Program-Erase Ready Control/Status Flag. bit_offset: 31 bit_size: 1 - enum: PERDY -enum/ABTREQ: + enum: Perdy +fieldset/Ftest: + description: Flash Test Register. + fields: + - name: tmectl + description: Test Mode Entry Control. + bit_offset: 0 + bit_size: 1 + enum: Tmectl + - name: tmewr + description: Test Mode Entry Writable. + bit_offset: 1 + bit_size: 1 + enum: Tmewr + - name: tme + description: Test Mode Entry. + bit_offset: 2 + bit_size: 1 + enum: Tme + - name: tmode + description: Test Mode Status. + bit_offset: 3 + bit_size: 1 + enum: Tmode + - name: tmelock + description: Test Mode Entry Lock. + bit_offset: 4 + bit_size: 1 + enum: Tmelock +enum/Abtreq: bit_size: 1 variants: - - name: abtreq0 + - name: Abtreq0 description: No request to abort a command write sequence. value: 0 - - name: abtreq1 + - name: Abtreq1 description: Request to abort a command write sequence. value: 1 -enum/ACCERR: +enum/Accerr: bit_size: 1 variants: - - name: accerr0 + - name: Accerr0 description: No access error detected. value: 0 - - name: accerr1 + - name: Accerr1 description: Access error detected. value: 1 -enum/CCIE: +enum/Ccie: bit_size: 1 variants: - - name: ccie0 + - name: Ccie0 description: Command complete interrupt disabled. value: 0 - - name: ccie1 + - name: Ccie1 description: Command complete interrupt enabled. value: 1 -enum/CCIF: +enum/Ccif: bit_size: 1 variants: - - name: ccif0 + - name: Ccif0 description: Flash command, initialization, or power mode recovery in progress. value: 0 - - name: ccif1 + - name: Ccif1 description: Flash command, initialization, or power mode recovery has completed. value: 1 -enum/CMDABT: +enum/Cmdabt: bit_size: 1 variants: - - name: cmdabt0 + - name: Cmdabt0 description: No command abort detected. value: 0 - - name: cmdabt1 + - name: Cmdabt1 description: Command abort detected. value: 1 -enum/CMDP: +enum/Cmdp: bit_size: 1 variants: - - name: cmdp0 + - name: Cmdp0 description: Command protection level and domain ID are stale. value: 0 - - name: cmdp1 + - name: Cmdp1 description: Command protection level (CMDPRT) and domain ID (CMDDID) are set. value: 1 -enum/CMDPRT: +enum/Cmdprt: bit_size: 2 variants: - - name: cmdprt00 + - name: Cmdprt00 description: Secure, normal access. value: 0 - - name: cmdprt01 + - name: Cmdprt01 description: Secure, privileged access. value: 1 - - name: cmdprt10 + - name: Cmdprt10 description: Nonsecure, normal access. value: 2 - - name: cmdprt11 + - name: Cmdprt11 description: Nonsecure, privileged access. value: 3 -enum/CWSABT: +enum/Cwsabt: bit_size: 1 variants: - - name: cwsabt0 + - name: Cwsabt0 description: Command write sequence not aborted. value: 0 - - name: cwsabt1 + - name: Cwsabt1 description: Command write sequence aborted. value: 1 -enum/DFDIE: +enum/Dfdie: bit_size: 1 variants: - - name: dfdie0 + - name: Dfdie0 description: Double bit fault detect interrupt disabled. value: 0 - - name: dfdie1 + - name: Dfdie1 description: Double bit fault detect interrupt enabled. value: 1 -enum/DFDIF: +enum/Dfdif: bit_size: 1 variants: - - name: dfdif0 + - name: Dfdif0 description: Double bit fault not detected during a valid flash read access. value: 0 - - name: dfdif1 + - name: Dfdif1 description: Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access. value: 1 -enum/ERSIEN0: +enum/Ersien0: bit_size: 4 variants: - - name: ersien00 + - name: Ersien00 description: Block 0 IFR Sector X is protected from erase by ERSSCR command. value: 0 - - name: ersien01 + - name: Ersien01 description: Block 0 IFR Sector X is not protected from erase by ERSSCR command. value: 1 -enum/ERSIEN1: +enum/Ersien1: bit_size: 4 variants: - - name: ersien10 + - name: Ersien10 description: Block 1 IFR Sector X is protected from erase by ERSSCR command. value: 0 - - name: ersien11 + - name: Ersien11 description: Block 1 IFR Sector X is not protected from erase by ERSSCR command. value: 1 -enum/ERSREQ: +enum/Ersreq: bit_size: 1 variants: - - name: ersreq0 + - name: Ersreq0 description: No request or request complete. value: 0 - - name: ersreq1 + - name: Ersreq1 description: Request to run the Mass Erase operation. value: 1 -enum/FAIL: +enum/Fail: bit_size: 1 variants: - - name: fail0 + - name: Fail0 description: Error not detected. value: 0 - - name: fail1 + - name: Fail1 description: Error detected. value: 1 -enum/FDFD: +enum/Fdfd: bit_size: 1 variants: - - name: fdfd0 + - name: Fdfd0 description: FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller. value: 0 - - name: fdfd1 + - name: Fdfd1 description: FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set. value: 1 -enum/LSACTIVE: +enum/Lsactive: bit_size: 1 variants: - - name: lsactive0 + - name: Lsactive0 description: Full speed active mode requested. value: 0 - - name: lsactive1 + - name: Lsactive1 description: Low speed active mode requested. value: 1 -enum/PERDY: +enum/Perdy: bit_size: 1 variants: - - name: perdy0 + - name: Perdy0 description: Program or sector erase command operation not stalled. value: 0 - - name: perdy1 + - name: Perdy1 description: Program or sector erase command operation ready to execute. value: 1 -enum/PEWEN: +enum/Pewen: bit_size: 2 variants: - - name: pewen00 + - name: Pewen00 description: Writes are not enabled. value: 0 - - name: pewen01 + - name: Pewen01 description: Writes are enabled for one flash or IFR phrase (phrase programming, sector erase). value: 1 - - name: pewen10 + - name: Pewen10 description: Writes are enabled for one flash or IFR page (page programming). value: 2 -enum/PVIOL: +enum/Pviol: bit_size: 1 variants: - - name: pviol0 + - name: Pviol0 description: No protection violation detected. value: 0 - - name: pviol1 + - name: Pviol1 description: Protection violation detected. value: 1 -enum/SALV_USED: +enum/SalvUsed: bit_size: 1 variants: - - name: salv_used0 + - name: SalvUsed0 description: Salvage not used during last operation. value: 0 - - name: salv_used1 + - name: SalvUsed1 description: Salvage used during the last erase operation. value: 1 +enum/Tme: + bit_size: 1 + variants: + - name: Tme0 + description: Test mode entry not requested. + value: 0 + - name: Tme1 + description: Test mode entry requested. + value: 1 +enum/Tmectl: + bit_size: 1 + variants: + - name: Tmectl0 + description: FTEST register always reads 0 and writes to FTEST are ignored. + value: 0 + - name: Tmectl1 + description: FTEST register is readable and can be written to enable writability of TME. + value: 1 +enum/Tmelock: + bit_size: 1 + variants: + - name: Tmelock0 + description: FTEST register not locked from accepting writes. + value: 0 + - name: Tmelock1 + description: FTEST register locked from accepting writes. + value: 1 +enum/Tmewr: + bit_size: 1 + variants: + - name: Tmewr0 + description: TME bit is not writable. + value: 0 + - name: Tmewr1 + description: TME bit is writable. + value: 1 +enum/Tmode: + bit_size: 1 + variants: + - name: Tmode0 + description: Test mode not active. + value: 0 + - name: Tmode1 + description: Test mode active. + value: 1 diff --git a/data/metadata/peripherals/mcxa/GPIO.yaml b/data/metadata/peripherals/mcxa/GPIO.yaml index ccd7dc5..aaa6e44 100644 --- a/data/metadata/peripherals/mcxa/GPIO.yaml +++ b/data/metadata/peripherals/mcxa/GPIO.yaml @@ -11,6 +11,26 @@ block/Gpio: byte_offset: 4 access: Read fieldset: Param + - name: lock + description: Lock. + byte_offset: 12 + fieldset: Lock + - name: pcns + description: Pin Control Nonsecure. + byte_offset: 16 + fieldset: Pcns + - name: icns + description: Interrupt Control Nonsecure. + byte_offset: 20 + fieldset: Icns + - name: pcnp + description: Pin Control Nonprivilege. + byte_offset: 24 + fieldset: Pcnp + - name: icnp + description: Interrupt Control Nonprivilege. + byte_offset: 28 + fieldset: Icnp - name: pdor description: Port Data Output. byte_offset: 64 @@ -66,93 +86,20 @@ block/Gpio: - name: isfr description: Interrupt Status Flag. array: - len: 1 - stride: 0 + len: 2 + stride: 4 byte_offset: 288 fieldset: Isfr fieldset/Gichr: description: Global Interrupt Control High. fields: - - name: giwe16 + - name: giwe description: Global Interrupt Write Enable. bit_offset: 0 bit_size: 1 - enum: Giwe16 - - name: giwe17 - description: Global Interrupt Write Enable. - bit_offset: 1 - bit_size: 1 - enum: Giwe17 - - name: giwe18 - description: Global Interrupt Write Enable. - bit_offset: 2 - bit_size: 1 - enum: Giwe18 - - name: giwe19 - description: Global Interrupt Write Enable. - bit_offset: 3 - bit_size: 1 - enum: Giwe19 - - name: giwe20 - description: Global Interrupt Write Enable. - bit_offset: 4 - bit_size: 1 - enum: Giwe20 - - name: giwe21 - description: Global Interrupt Write Enable. - bit_offset: 5 - bit_size: 1 - enum: Giwe21 - - name: giwe22 - description: Global Interrupt Write Enable. - bit_offset: 6 - bit_size: 1 - enum: Giwe22 - - name: giwe23 - description: Global Interrupt Write Enable. - bit_offset: 7 - bit_size: 1 - enum: Giwe23 - - name: giwe24 - description: Global Interrupt Write Enable. - bit_offset: 8 - bit_size: 1 - enum: Giwe24 - - name: giwe25 - description: Global Interrupt Write Enable. - bit_offset: 9 - bit_size: 1 - enum: Giwe25 - - name: giwe26 - description: Global Interrupt Write Enable. - bit_offset: 10 - bit_size: 1 - enum: Giwe26 - - name: giwe27 - description: Global Interrupt Write Enable. - bit_offset: 11 - bit_size: 1 - enum: Giwe27 - - name: giwe28 - description: Global Interrupt Write Enable. - bit_offset: 12 - bit_size: 1 - enum: Giwe28 - - name: giwe29 - description: Global Interrupt Write Enable. - bit_offset: 13 - bit_size: 1 - enum: Giwe29 - - name: giwe30 - description: Global Interrupt Write Enable. - bit_offset: 14 - bit_size: 1 - enum: Giwe30 - - name: giwe31 - description: Global Interrupt Write Enable. - bit_offset: 15 - bit_size: 1 - enum: Giwe31 + array: + len: 16 + stride: 1 - name: giwd description: Global Interrupt Write Data. bit_offset: 16 @@ -160,90 +107,43 @@ fieldset/Gichr: fieldset/Giclr: description: Global Interrupt Control Low. fields: - - name: giwe0 + - name: giwe description: Global Interrupt Write Enable. bit_offset: 0 bit_size: 1 - enum: Giwe0 - - name: giwe1 - description: Global Interrupt Write Enable. - bit_offset: 1 - bit_size: 1 - enum: Giwe1 - - name: giwe2 - description: Global Interrupt Write Enable. - bit_offset: 2 - bit_size: 1 - enum: Giwe2 - - name: giwe3 - description: Global Interrupt Write Enable. - bit_offset: 3 - bit_size: 1 - enum: Giwe3 - - name: giwe4 - description: Global Interrupt Write Enable. - bit_offset: 4 - bit_size: 1 - enum: Giwe4 - - name: giwe5 - description: Global Interrupt Write Enable. - bit_offset: 5 - bit_size: 1 - enum: Giwe5 - - name: giwe6 - description: Global Interrupt Write Enable. - bit_offset: 6 - bit_size: 1 - enum: Giwe6 - - name: giwe7 - description: Global Interrupt Write Enable. - bit_offset: 7 - bit_size: 1 - enum: Giwe7 - - name: giwe8 - description: Global Interrupt Write Enable. - bit_offset: 8 - bit_size: 1 - enum: Giwe8 - - name: giwe9 - description: Global Interrupt Write Enable. - bit_offset: 9 - bit_size: 1 - enum: Giwe9 - - name: giwe10 - description: Global Interrupt Write Enable. - bit_offset: 10 - bit_size: 1 - enum: Giwe10 - - name: giwe11 - description: Global Interrupt Write Enable. - bit_offset: 11 - bit_size: 1 - enum: Giwe11 - - name: giwe12 - description: Global Interrupt Write Enable. - bit_offset: 12 - bit_size: 1 - enum: Giwe12 - - name: giwe13 - description: Global Interrupt Write Enable. - bit_offset: 13 - bit_size: 1 - enum: Giwe13 - - name: giwe14 - description: Global Interrupt Write Enable. - bit_offset: 14 - bit_size: 1 - enum: Giwe14 - - name: giwe15 - description: Global Interrupt Write Enable. - bit_offset: 15 - bit_size: 1 - enum: Giwe15 + array: + len: 16 + stride: 1 - name: giwd description: Global Interrupt Write Data. bit_offset: 16 bit_size: 16 +fieldset/Icnp: + description: Interrupt Control Nonprivilege. + fields: + - name: npe0 + description: Nonprivilege Enable. + bit_offset: 0 + bit_size: 1 + enum: IcnpNpe0 + - name: npe1 + description: Nonprivilege Enable. + bit_offset: 1 + bit_size: 1 + enum: IcnpNpe1 +fieldset/Icns: + description: Interrupt Control Nonsecure. + fields: + - name: nse0 + description: Nonsecure Enable. + bit_offset: 0 + bit_size: 1 + enum: IcnsNse0 + - name: nse1 + description: Nonsecure Enable. + bit_offset: 1 + bit_size: 1 + enum: IcnsNse1 fieldset/Icr: description: Interrupt Control index. fields: @@ -252,6 +152,16 @@ fieldset/Icr: bit_offset: 16 bit_size: 4 enum: Irqc + - name: irqs + description: Interrupt Select. + bit_offset: 20 + bit_size: 1 + enum: Irqs + - name: lk + description: Lock. + bit_offset: 23 + bit_size: 1 + enum: Lk - name: isf description: Interrupt Status Flag. bit_offset: 24 @@ -264,162 +174,149 @@ fieldset/Isfr: description: Interrupt Status Flag. bit_offset: 0 bit_size: 1 - enum: Isf0 - name: isf1 description: Interrupt Status Flag. bit_offset: 1 bit_size: 1 - enum: Isf1 - name: isf2 description: Interrupt Status Flag. bit_offset: 2 bit_size: 1 - enum: Isf2 - name: isf3 description: Interrupt Status Flag. bit_offset: 3 bit_size: 1 - enum: Isf3 - name: isf4 description: Interrupt Status Flag. bit_offset: 4 bit_size: 1 - enum: Isf4 - name: isf5 description: Interrupt Status Flag. bit_offset: 5 bit_size: 1 - enum: Isf5 - name: isf6 description: Interrupt Status Flag. bit_offset: 6 bit_size: 1 - enum: Isf6 - name: isf7 description: Interrupt Status Flag. bit_offset: 7 bit_size: 1 - enum: Isf7 - name: isf8 description: Interrupt Status Flag. bit_offset: 8 bit_size: 1 - enum: Isf8 - name: isf9 description: Interrupt Status Flag. bit_offset: 9 bit_size: 1 - enum: Isf9 - name: isf10 description: Interrupt Status Flag. bit_offset: 10 bit_size: 1 - enum: Isf10 - name: isf11 description: Interrupt Status Flag. bit_offset: 11 bit_size: 1 - enum: Isf11 - name: isf12 description: Interrupt Status Flag. bit_offset: 12 bit_size: 1 - enum: Isf12 - name: isf13 description: Interrupt Status Flag. bit_offset: 13 bit_size: 1 - enum: Isf13 - name: isf14 description: Interrupt Status Flag. bit_offset: 14 bit_size: 1 - enum: Isf14 - name: isf15 description: Interrupt Status Flag. bit_offset: 15 bit_size: 1 - enum: Isf15 - name: isf16 description: Interrupt Status Flag. bit_offset: 16 bit_size: 1 - enum: Isf16 - name: isf17 description: Interrupt Status Flag. bit_offset: 17 bit_size: 1 - enum: Isf17 - name: isf18 description: Interrupt Status Flag. bit_offset: 18 bit_size: 1 - enum: Isf18 - name: isf19 description: Interrupt Status Flag. bit_offset: 19 bit_size: 1 - enum: Isf19 - name: isf20 description: Interrupt Status Flag. bit_offset: 20 bit_size: 1 - enum: Isf20 - name: isf21 description: Interrupt Status Flag. bit_offset: 21 bit_size: 1 - enum: Isf21 - name: isf22 description: Interrupt Status Flag. bit_offset: 22 bit_size: 1 - enum: Isf22 - name: isf23 description: Interrupt Status Flag. bit_offset: 23 bit_size: 1 - enum: Isf23 - name: isf24 description: Interrupt Status Flag. bit_offset: 24 bit_size: 1 - enum: Isf24 - name: isf25 description: Interrupt Status Flag. bit_offset: 25 bit_size: 1 - enum: Isf25 - name: isf26 description: Interrupt Status Flag. bit_offset: 26 bit_size: 1 - enum: Isf26 - name: isf27 description: Interrupt Status Flag. bit_offset: 27 bit_size: 1 - enum: Isf27 - name: isf28 description: Interrupt Status Flag. bit_offset: 28 bit_size: 1 - enum: Isf28 - name: isf29 description: Interrupt Status Flag. bit_offset: 29 bit_size: 1 - enum: Isf29 - name: isf30 description: Interrupt Status Flag. bit_offset: 30 bit_size: 1 - enum: Isf30 - name: isf31 description: Interrupt Status Flag. bit_offset: 31 bit_size: 1 - enum: Isf31 +fieldset/Lock: + description: Lock. + fields: + - name: pcns + description: Lock PCNS. + bit_offset: 0 + bit_size: 1 + - name: icns + description: Lock ICNS. + bit_offset: 1 + bit_size: 1 + - name: pcnp + description: Lock PCNP. + bit_offset: 2 + bit_size: 1 + - name: icnp + description: Lock ICNP. + bit_offset: 3 + bit_size: 1 fieldset/Param: description: Parameter. fields: @@ -427,6 +324,28 @@ fieldset/Param: description: Interrupt Number. bit_offset: 0 bit_size: 4 +fieldset/Pcnp: + description: Pin Control Nonprivilege. + fields: + - name: npe + description: Nonprivilege Enable. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: PcnpNpe0 +fieldset/Pcns: + description: Pin Control Nonsecure. + fields: + - name: nse + description: Nonsecure Enable. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 + enum: PcnsNse0 fieldset/Pcor: description: Port Clear Output. fields: @@ -517,7 +436,6 @@ fieldset/Verid: description: Feature Specification Number. bit_offset: 0 bit_size: 16 - enum: Feature - name: minor description: Minor Version Number. bit_offset: 16 @@ -526,687 +444,174 @@ fieldset/Verid: description: Major Version Number. bit_offset: 24 bit_size: 8 -enum/Feature: - bit_size: 16 - variants: - - name: FEATURE0 - description: Basic implementation. - value: 0 - - name: FEATURE1 - description: Protection registers implemented. - value: 1 -enum/Giwe0: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe1: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe10: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe11: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe12: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe13: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe14: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe15: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe16: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe17: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe18: +enum/IcnpNpe0: bit_size: 1 variants: - - name: GIWE0 - description: Not updated. + - name: Npe0 + description: Privilege access. value: 0 - - name: GIWE1 - description: Updated. + - name: Npe1 + description: Nonprivilege access. value: 1 -enum/Giwe19: +enum/IcnpNpe1: bit_size: 1 variants: - - name: GIWE0 - description: Not updated. + - name: Npe0 + description: Privilege access. value: 0 - - name: GIWE1 - description: Updated. + - name: Npe1 + description: Nonprivilege access. value: 1 -enum/Giwe2: +enum/IcnsNse0: bit_size: 1 variants: - - name: GIWE0 - description: Not updated. + - name: Nse0 + description: Secure access. value: 0 - - name: GIWE1 - description: Updated. + - name: Nse1 + description: Nonsecure access. value: 1 -enum/Giwe20: +enum/IcnsNse1: bit_size: 1 variants: - - name: GIWE0 - description: Not updated. + - name: Nse0 + description: Secure access. value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe21: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe22: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe23: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe24: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe25: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe26: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe27: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe28: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe29: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe3: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe30: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe31: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe4: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe5: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe6: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe7: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe8: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. - value: 1 -enum/Giwe9: - bit_size: 1 - variants: - - name: GIWE0 - description: Not updated. - value: 0 - - name: GIWE1 - description: Updated. + - name: Nse1 + description: Nonsecure access. value: 1 enum/Irqc: bit_size: 4 variants: - - name: IRQC0 + - name: Irqc0 description: ISF is disabled. value: 0 - - name: IRQC1 + - name: Irqc1 description: ISF and DMA request on rising edge. value: 1 - - name: IRQC2 + - name: Irqc2 description: ISF and DMA request on falling edge. value: 2 - - name: IRQC3 + - name: Irqc3 description: ISF and DMA request on either edge. value: 3 - - name: IRQC5 + - name: Irqc5 description: ISF sets on rising edge. value: 5 - - name: IRQC6 + - name: Irqc6 description: ISF sets on falling edge. value: 6 - - name: IRQC7 + - name: Irqc7 description: ISF sets on either edge. value: 7 - - name: IRQC8 + - name: Irqc8 description: ISF and interrupt when logic 0. value: 8 - - name: IRQC9 + - name: Irqc9 description: ISF and interrupt on rising edge. value: 9 - - name: IRQC10 + - name: Irqc10 description: ISF and interrupt on falling edge. value: 10 - - name: IRQC11 + - name: Irqc11 description: ISF and Interrupt on either edge. value: 11 - - name: IRQC12 + - name: Irqc12 description: ISF and interrupt when logic 1. value: 12 - - name: IRQC13 + - name: Irqc13 description: Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals). value: 13 - - name: IRQC14 + - name: Irqc14 description: Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals). value: 14 -enum/Isf: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf0: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf1: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf10: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf11: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf12: +enum/Irqs: bit_size: 1 variants: - - name: ISF0 - description: Not detected. + - name: Irqs0 + description: Interrupt, trigger output, or DMA request 0. value: 0 - - name: ISF1 - description: Detected. + - name: Irqs1 + description: Interrupt, trigger output, or DMA request 1. value: 1 -enum/Isf13: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf14: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf15: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf16: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf17: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf18: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf19: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf2: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf20: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf21: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf22: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf23: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf24: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf25: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf26: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf27: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf28: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf29: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf3: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf30: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf31: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf4: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf5: +enum/Isf: bit_size: 1 variants: - - name: ISF0 + - name: Isf0 description: Not detected. value: 0 - - name: ISF1 + - name: Isf1 description: Detected. value: 1 -enum/Isf6: +enum/Lk: bit_size: 1 variants: - - name: ISF0 - description: Not detected. + - name: Lk0 + description: Not locked. value: 0 - - name: ISF1 - description: Detected. + - name: Lk1 + description: Locked. value: 1 -enum/Isf7: +enum/PcnpNpe0: bit_size: 1 variants: - - name: ISF0 - description: Not detected. + - name: Npe0 + description: Privilege access. value: 0 - - name: ISF1 - description: Detected. + - name: Npe1 + description: Nonprivilege access. value: 1 -enum/Isf8: +enum/PcnsNse0: bit_size: 1 variants: - - name: ISF0 - description: Not detected. + - name: Nse0 + description: Secure access. value: 0 - - name: ISF1 - description: Detected. - value: 1 -enum/Isf9: - bit_size: 1 - variants: - - name: ISF0 - description: Not detected. - value: 0 - - name: ISF1 - description: Detected. + - name: Nse1 + description: Nonsecure access. value: 1 enum/Pd: bit_size: 1 variants: - - name: PD0 + - name: Pd0 description: Logic zero. value: 0 - - name: PD1 + - name: Pd1 description: Logic one. value: 1 enum/Pdd: bit_size: 1 variants: - - name: PDD0 + - name: Pdd0 description: Input. value: 0 - - name: PDD1 + - name: Pdd1 description: Output. value: 1 enum/Pid: bit_size: 1 variants: - - name: PID0 + - name: Pid0 description: Configured for general-purpose input. value: 0 - - name: PID1 + - name: Pid1 description: Disabled for general-purpose input. value: 1 enum/Ptco: bit_size: 1 variants: - - name: PTCO0 + - name: Ptco0 description: No change. value: 0 - - name: PTCO1 + - name: Ptco1 description: Corresponding field in PDOR becomes 0. value: 1 enum/Ptso: bit_size: 1 variants: - - name: PTSO0 + - name: Ptso0 description: No change. value: 0 - - name: PTSO1 + - name: Ptso1 description: Corresponding field in PDOR becomes 1. value: 1 diff --git a/data/metadata/peripherals/mcxa/I3C.yaml b/data/metadata/peripherals/mcxa/I3C.yaml index 6962a62..aa71b69 100644 --- a/data/metadata/peripherals/mcxa/I3C.yaml +++ b/data/metadata/peripherals/mcxa/I3C.yaml @@ -38,6 +38,15 @@ block/I3c: description: Target DMA Control. byte_offset: 32 fieldset: Sdmactrl + - name: shdrbtcfg + description: Target HDR-BT Configuration. + byte_offset: 36 + fieldset: Shdrbtcfg + - name: shdrbtlast + description: Target HDR-Last. + byte_offset: 40 + access: Read + fieldset: Shdrbtlast - name: sdatactrl description: Target Data Control. byte_offset: 44 @@ -77,11 +86,6 @@ block/I3c: byte_offset: 84 access: Write fieldset: Swdatab1 - - name: swdatah1 - description: Target Write Data Halfword. - byte_offset: 84 - access: Write - fieldset: Swdatah1 - name: scapabilities2 description: Target Capabilities 2. byte_offset: 92 @@ -92,10 +96,6 @@ block/I3c: byte_offset: 96 access: Read fieldset: Scapabilities - - name: sdynaddr - description: Target Dynamic Address. - byte_offset: 100 - fieldset: Sdynaddr - name: smaxlimits description: Target Maximum Limits. byte_offset: 104 @@ -158,6 +158,15 @@ block/I3c: description: Controller DMA Control. byte_offset: 160 fieldset: Mdmactrl + - name: mhdrbtcfg + description: Controller HDR-BT Configuration. + byte_offset: 164 + fieldset: Mhdrbtcfg + - name: mhdrbtlast + description: Controller HDR-Last. + byte_offset: 168 + access: Read + fieldset: Mhdrbtlast - name: mdatactrl description: Controller Data Control. byte_offset: 172 @@ -197,11 +206,6 @@ block/I3c: byte_offset: 204 access: Write fieldset: Mwdatab1 - - name: mwdatah1 - description: Controller Write Halfword Data (to Bus). - byte_offset: 204 - access: Write - fieldset: Mwdatah1 - name: mwmsg_sdr_control description: Controller Write Message Control in SDR mode. byte_offset: 208 @@ -241,11 +245,25 @@ block/I3c: description: Controller Dynamic Address. byte_offset: 228 fieldset: Mdynaddr + - name: mwdataw + description: Write Word Data (to Bus). + byte_offset: 240 + access: Write + fieldset: Mwdataw + - name: mrdataw + description: Read Word Data (from Bus). + byte_offset: 248 + access: Read + fieldset: Mrdataw - name: smapctrl0 description: Map Feature Control 0. byte_offset: 284 access: Read fieldset: Smapctrl0 + - name: smapctrl1 + description: Map Feature Control 1. + byte_offset: 288 + fieldset: Smapctrl1 - name: ibiext1 description: Extended IBI Data 1. byte_offset: 320 @@ -254,6 +272,16 @@ block/I3c: description: Extended IBI Data 2. byte_offset: 324 fieldset: Ibiext2 + - name: swdataw + description: Target Write Word Data (to Bus). + byte_offset: 336 + access: Write + fieldset: Swdataw + - name: srdataw + description: Target Read Word Data (from Bus). + byte_offset: 344 + access: Read + fieldset: Srdataw - name: sid description: Target Module ID. byte_offset: 4092 @@ -508,6 +536,34 @@ fieldset/Merrwarn: description: Timeout Error Flag. bit_offset: 20 bit_size: 1 +fieldset/Mhdrbtcfg: + description: Controller HDR-BT Configuration. + fields: + - name: mlhdr + description: Multi-Lane HDR. + bit_offset: 0 + bit_size: 2 + enum: Mlhdr + - name: mldat + description: Multi-Lane Data. + bit_offset: 2 + bit_size: 2 + enum: Mldat + - name: crc32 + description: CRC32. + bit_offset: 4 + bit_size: 1 + - name: datalen + description: Data Length. + bit_offset: 16 + bit_size: 16 +fieldset/Mhdrbtlast: + description: Controller HDR-Last. + fields: + - name: datalen + description: Data Length. + bit_offset: 16 + bit_size: 16 fieldset/Mibirules: description: Controller In-band Interrupt Registry and Rules. fields: @@ -663,6 +719,13 @@ fieldset/Mrdatah: description: High Byte. bit_offset: 8 bit_size: 8 +fieldset/Mrdataw: + description: Read Word Data (from Bus). + fields: + - name: value + description: Value. + bit_offset: 0 + bit_size: 32 fieldset/MrmsgDdr: description: Controller Read Message in DDR mode. fields: @@ -778,13 +841,6 @@ fieldset/Mwdatah: description: End of Message. bit_offset: 16 bit_size: 1 -fieldset/Mwdatah1: - description: Controller Write Halfword Data (to Bus). - fields: - - name: value - description: Value. - bit_offset: 0 - bit_size: 16 fieldset/Mwdatahe: description: Controller Write Data Halfword End. fields: @@ -796,6 +852,13 @@ fieldset/Mwdatahe: description: Data Byte 1. bit_offset: 8 bit_size: 8 +fieldset/Mwdataw: + description: Write Word Data (to Bus). + fields: + - name: data + description: Data. + bit_offset: 0 + bit_size: 32 fieldset/MwmsgDdrControl: description: 'Controller Write Message in DDR mode: First Control Word.' fields: @@ -984,8 +1047,8 @@ fieldset/Sconfig: description: Ignore TE0 or TE1 Errors. bit_offset: 3 bit_size: 1 - - name: hdrok - description: HDR OK. + - name: ddrok + description: Double Data Rate OK. bit_offset: 4 bit_size: 1 - name: offline @@ -1012,6 +1075,10 @@ fieldset/Sctrl: description: Extended Data. bit_offset: 3 bit_size: 1 + - name: mapidx + description: Map Index. + bit_offset: 4 + bit_size: 1 - name: ibidata description: In-Band Interrupt Data. bit_offset: 8 @@ -1089,30 +1156,6 @@ fieldset/Sdmactrl: bit_offset: 4 bit_size: 2 enum: SdmactrlDmawidth -fieldset/Sdynaddr: - description: Target Dynamic Address. - fields: - - name: davalid - description: Dynamic Address Valid. - bit_offset: 0 - bit_size: 1 - enum: SdynaddrDavalid - - name: daddr - description: Dynamic Address. - bit_offset: 1 - bit_size: 7 - - name: mapsa - description: Map a Static Address. - bit_offset: 12 - bit_size: 1 - - name: sa10b - description: 10-Bit Static Address. - bit_offset: 13 - bit_size: 3 - - name: key - description: Key. - bit_offset: 16 - bit_size: 16 fieldset/Serrwarn: description: Target Errors and Warnings. fields: @@ -1152,6 +1195,10 @@ fieldset/Serrwarn: description: TE0 or TE1 Error Flag. bit_offset: 11 bit_size: 1 + - name: hinvreq + description: HDR-BT Invalid Request Flag. + bit_offset: 13 + bit_size: 1 - name: oread description: Over-Read Error Flag. bit_offset: 16 @@ -1160,6 +1207,29 @@ fieldset/Serrwarn: description: Over-Write Error Flag. bit_offset: 17 bit_size: 1 +fieldset/Shdrbtcfg: + description: Target HDR-BT Configuration. + fields: + - name: crc32 + description: CRC32 Select. + bit_offset: 2 + bit_size: 1 + enum: ShdrbtcfgCrc32 + - name: wdatamax + description: Maximum Data. + bit_offset: 4 + bit_size: 12 + - name: datalen + description: Read Data Length. + bit_offset: 16 + bit_size: 16 +fieldset/Shdrbtlast: + description: Target HDR-Last. + fields: + - name: datalen + description: Data Length. + bit_offset: 16 + bit_size: 16 fieldset/Sid: description: Target Module ID. fields: @@ -1342,6 +1412,29 @@ fieldset/Smapctrl0: bit_offset: 8 bit_size: 3 enum: Cause +fieldset/Smapctrl1: + description: Map Feature Control 1. + fields: + - name: ena + description: Enable. + bit_offset: 0 + bit_size: 1 + - name: addr + description: Address. + bit_offset: 1 + bit_size: 7 + - name: mapsa + description: MAP Static Address. + bit_offset: 8 + bit_size: 1 + - name: sa10b + description: Static Address 10-Bit Extension. + bit_offset: 9 + bit_size: 3 + - name: nack + description: Not Acknowledged. + bit_offset: 12 + bit_size: 1 fieldset/Smaxlimits: description: Target Maximum Limits. fields: @@ -1391,6 +1484,13 @@ fieldset/Srdatah: description: High Byte. bit_offset: 8 bit_size: 8 +fieldset/Srdataw: + description: Target Read Word Data (from Bus). + fields: + - name: value + description: Value. + bit_offset: 0 + bit_size: 32 fieldset/Sstatus: description: Target Status. fields: @@ -1565,13 +1665,6 @@ fieldset/Swdatah: description: End of Message. bit_offset: 16 bit_size: 1 -fieldset/Swdatah1: - description: Target Write Data Halfword. - fields: - - name: data - description: Data. - bit_offset: 0 - bit_size: 16 fieldset/Swdatahe: description: Target Write Data Halfword End. fields: @@ -1583,696 +1676,727 @@ fieldset/Swdatahe: description: Data 1. bit_offset: 8 bit_size: 8 +fieldset/Swdataw: + description: Target Write Word Data (to Bus). + fields: + - name: data + description: Data. + bit_offset: 0 + bit_size: 32 enum/Actstate: bit_size: 2 variants: - - name: NO_LATENCY + - name: NoLatency description: NO_LATENCY (normal bus operations). value: 0 - - name: LATENCY_1MS + - name: Latency1ms description: LATENCY_1MS (1 ms of latency). value: 1 - - name: LATENCY_100MS + - name: Latency100ms description: LATENCY_100MS (100 ms of latency). value: 2 - - name: LATENCY_10S + - name: Latency10s description: LATENCY_10S (10 seconds of latency). value: 3 enum/Cause: bit_size: 3 variants: - - name: NONE + - name: None description: No information (this value occurs when not configured to write DA). value: 0 - - name: ENTDAA + - name: Entdaa description: Set using ENTDAA. value: 1 - - name: SETDASA + - name: Setdasa description: Set using SETDASA, SETAASA, or SETNEWDA. value: 2 - - name: RSTDAA + - name: Rstdaa description: Cleared using RSTDAA. value: 3 - - name: AUTOMAP + - name: Automap description: Auto MAP change happened last. value: 4 enum/Ccchandle: bit_size: 4 variants: - - name: ALL_DISABLED + - name: AllDisabled description: All handling features disabled. value: 0 - - name: BLOCK_HANDLE + - name: BlockHandle description: The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items. value: 1 enum/Disto: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enabled. value: 0 - - name: DISABLE - description: Disabled, if configured. + - name: Disable + description: Disabled. value: 1 enum/Dma: bit_size: 1 variants: - - name: DMANO + - name: Dmano description: Not supported. value: 0 - - name: DMAYES + - name: Dmayes description: Supported. value: 1 enum/Evdet: bit_size: 2 variants: - - name: NONE + - name: None description: NONE (no event or no pending event). value: 0 - - name: NO_REQUEST + - name: NoRequest description: NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)). value: 1 - - name: NACKED + - name: Nacked description: NACKed (not acknowledged, request sent and rejected); I3C tries again. value: 2 - - name: ACKED + - name: Acked description: ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent). value: 3 enum/Extfifo: bit_size: 3 variants: - - name: NO_EXT_FIFO + - name: NoExtFifo description: No external FIFO available. value: 0 - - name: STD_EXT_FIFO + - name: StdExtFifo description: Standard available or free external FIFO. value: 1 - - name: REQUEST_EXT_FIFO + - name: RequestExtFifo description: Request track external FIFO. value: 2 enum/Fiforx: bit_size: 2 variants: - - name: FIFO_2BYTE + - name: Fifo2byte description: Two or three. value: 0 - - name: FIFO_4BYTE + - name: Fifo4byte description: Four. value: 1 - - name: FIFO_8BYTE + - name: Fifo8byte description: Eight. value: 2 - - name: FIFO_16BYTE + - name: Fifo16byte description: 16 or larger. value: 3 enum/Fifotx: bit_size: 2 variants: - - name: FIFO_2BYTE + - name: Fifo2byte description: Two. value: 0 - - name: FIFO_4BYTE + - name: Fifo4byte description: Four. value: 1 - - name: FIFO_8BYTE + - name: Fifo8byte description: Eight. value: 2 - - name: FIFO_16BYTE + - name: Fifo16byte description: 16 or larger. value: 3 enum/Group: bit_size: 2 variants: - - name: NOTSUPPORTED + - name: Notsupported description: v1.1 group addressing not supported. value: 0 - - name: ONE + - name: One description: One group supported. value: 1 - - name: TWO + - name: Two description: Two groups supported. value: 2 - - name: THREE + - name: Three description: Three groups supported. value: 3 enum/Hdrsupp: bit_size: 2 variants: - - name: NO_HDR + - name: NoHdr description: No HDR modes supported. value: 0 - - name: DDR + - name: Ddr description: DDR mode supported. value: 1 enum/Hjdis: bit_size: 1 variants: - - name: MR_ENABLED + - name: MrEnabled description: Enabled. value: 0 - - name: MR_DISABLED + - name: MrDisabled description: Disabled. value: 1 enum/Hkeep: bit_size: 2 variants: - - name: NONE + - name: None description: None. value: 0 - - name: WIRED_IN + - name: WiredIn description: WIRED_IN. value: 1 - - name: PASSIVE_SDA + - name: PassiveSda description: PASSIVE_SDA (I2C mode, no clock stretches mode). value: 2 - - name: PASSIVE_ON_SDA_SCL + - name: PassiveOnSdaScl description: PASSIVE_ON_SDA_SCL. value: 3 enum/I2c: bit_size: 1 variants: - - name: I3CMESSAGE + - name: I3cmessage description: I3C message. value: 0 - - name: I2CMESSAGE + - name: I2cmessage description: I2C message. value: 1 enum/I3cCasDel: bit_size: 2 variants: - - name: NO_DELAY + - name: NoDelay description: No delay. value: 0 - - name: ONE_HALF_CLK + - name: OneHalfClk description: Increases SCL clock period by 1/2. value: 1 - - name: ONE_CLK + - name: OneClk description: Increases SCL clock period by 1. value: 2 - - name: ONE_AND_ONE_HALF_CLK + - name: OneAndOneHalfClk description: Increases SCL clock period by 3/2. value: 3 enum/I3cCasrDel: bit_size: 2 variants: - - name: NO_DELAY + - name: NoDelay description: No delay. value: 0 - - name: ONE_HALF_CLK + - name: OneHalfClk description: Increases SCL clock period by 1/2. value: 1 - - name: ONE_CLK + - name: OneClk description: Increases SCL clock period by 1. value: 2 - - name: ONE_AND_ONE_HALF_CLK + - name: OneAndOneHalfClk description: Increases SCL clock period by 1 1/2. value: 3 enum/IbiMrHj: bit_size: 5 variants: - - name: ALL_DISABLED + - name: AllDisabled description: Application cannot generate IBI, CR, or HJ. value: 0 - - name: IBI + - name: Ibi description: Application can generate an IBI. value: 1 enum/Ibidis: bit_size: 1 variants: - - name: INTERRUPTS_ENABLED + - name: InterruptsEnabled description: Enabled. value: 0 - - name: INTERRUPTS_DISABLED + - name: InterruptsDisabled description: Disabled. value: 1 enum/Ibiresp: bit_size: 2 variants: - - name: ACK + - name: Ack description: ACK (acknowledge). value: 0 - - name: NACK + - name: Nack description: NACK (reject). value: 1 - - name: ACK_WITH_MANDATORY + - name: AckWithMandatory description: Acknowledge with mandatory byte. value: 2 - - name: MANUAL + - name: Manual description: Manual. value: 3 enum/Ibitype: bit_size: 2 variants: - - name: NONE + - name: None description: 'NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0).' value: 0 - - name: IBI + - name: Ibi description: IBI. value: 1 - - name: MR + - name: Mr description: CR. value: 2 - - name: HJ + - name: Hj description: HJ. value: 3 enum/Idena: bit_size: 2 variants: - - name: APPLICATION + - name: Application description: Application. value: 0 - - name: HW + - name: Hw description: Hardware. value: 1 - - name: HW_BUT + - name: HwBut description: Hardware, but the I3C module instance handles ID 48b. value: 2 - - name: PARTNO + - name: Partno description: A part number register (PARTNO). value: 3 enum/Idreg: bit_size: 4 variants: - - name: ALL_DISABLED + - name: AllDisabled description: All ID register features disabled. value: 0 - - name: ID_INSTANCE + - name: IdInstance description: ID Instance is a register; used if there is no PARTNO register. value: 1 enum/Int: bit_size: 1 variants: - - name: INTERRUPTSNO + - name: Interruptsno description: Not supported. value: 0 - - name: INTERRUPTSYES + - name: Interruptsyes description: Supported. value: 1 enum/Laststatic: bit_size: 1 variants: - - name: I3C + - name: I3c description: I3C dynamic address. value: 0 - - name: I2C + - name: I2c description: I2C static address. value: 1 enum/Master: bit_size: 1 variants: - - name: MASTERNOTSUPPORTED + - name: Masternotsupported description: Not supported. value: 0 - - name: MASTERSUPPORTED + - name: Mastersupported description: Supported. value: 1 enum/MctrlDir: bit_size: 1 variants: - - name: DIRWRITE + - name: Dirwrite description: Write. value: 0 - - name: DIRREAD + - name: Dirread description: Read. value: 1 enum/MdatactrlRxtrig: bit_size: 2 variants: - - name: NOT_EMPTY + - name: NotEmpty description: Trigger when not empty (default). value: 0 - - name: QUARTER_OR_MORE + - name: QuarterOrMore description: Trigger when 1/4 full or more. value: 1 - - name: HALF_OR_MORE + - name: HalfOrMore description: Trigger when 1/2 full or more. value: 2 - - name: THREE_QUARTER_OR_MORE + - name: ThreeQuarterOrMore description: Trigger when 3/4 full or more. value: 3 enum/MdatactrlTxtrig: bit_size: 2 variants: - - name: EMPTY + - name: Empty description: Trigger when empty. value: 0 - - name: QUARTER_OR_LESS + - name: QuarterOrLess description: Trigger when 1/4 full or less. value: 1 - - name: HALF_OR_LESS + - name: HalfOrLess description: Trigger when 1/2 full or less. value: 2 - - name: FULL_OR_LESS + - name: FullOrLess description: Trigger when 1 less than full or less (default). value: 3 enum/MdmactrlDmafb: bit_size: 2 variants: - - name: NOT_USED + - name: NotUsed description: DMA not used. value: 0 - - name: ENABLE_ONE_FRAME + - name: EnableOneFrame description: Enable DMA for one frame. value: 1 - - name: ENABLE + - name: Enable description: Enable DMA until DMA is turned off. value: 2 enum/MdmactrlDmatb: bit_size: 2 variants: - - name: NOT_USED + - name: NotUsed description: DMA not used. value: 0 - - name: ENABLE_ONE_FRAME + - name: EnableOneFrame description: Enable DMA for one frame (ended by DMA or terminated). value: 1 - - name: ENABLE + - name: Enable description: Enable DMA until DMA is turned off. value: 2 enum/MdmactrlDmawidth: bit_size: 2 variants: - - name: BYTE_0 + - name: Byte0 description: Byte. value: 0 - - name: BYTE_1 + - name: Byte1 description: Byte. value: 1 - - name: HALF_WORD + - name: HalfWord description: Halfword (16 bits). value: 2 +enum/Mldat: + bit_size: 2 + variants: + - name: Single + description: Single lane for data. + value: 0 + - name: Dual + description: Dual lane for data. + value: 1 + - name: Quad + description: Quad-lane data. + value: 3 +enum/Mlhdr: + bit_size: 2 + variants: + - name: Single + description: Single lane for header. + value: 0 + - name: Dual + description: Dual lane for header. + value: 1 + - name: Quad + description: Quad-lane header. + value: 3 enum/Mrdis: bit_size: 1 variants: - - name: MR_ENABLED + - name: MrEnabled description: Enabled. value: 0 - - name: MR_DISABLED + - name: MrDisabled description: Disabled. value: 1 enum/Mstena: bit_size: 2 variants: - - name: MASTER_OFF + - name: MasterOff description: CONTROLLER_OFF. value: 0 - - name: MASTER_ON + - name: MasterOn description: CONTROLLER_ON. value: 1 - - name: MASTER_CAPABLE + - name: MasterCapable description: CONTROLLER_CAPABLE. value: 2 - - name: I2C_MASTER_MODE + - name: I2cMasterMode description: I2C_CONTROLLER_MODE. value: 3 enum/MwmsgSdrControlDir: bit_size: 1 variants: - - name: WRITE + - name: Write description: Write. value: 0 - - name: READ + - name: Read description: Read. value: 1 enum/Nobyte: bit_size: 1 variants: - - name: IBIBYTE + - name: Ibibyte description: With mandatory IBI byte. value: 0 - - name: NO_IBIBYTE + - name: NoIbibyte description: Without mandatory IBI byte. value: 1 enum/Request: bit_size: 3 variants: - - name: NONE + - name: None description: NONE. value: 0 - - name: EMITSTARTADDR + - name: Emitstartaddr description: EMITSTARTADDR. value: 1 - - name: EMITSTOP + - name: Emitstop description: EMITSTOP. value: 2 - - name: IBIACKNACK + - name: Ibiacknack description: IBIACKNACK. value: 3 - - name: PROCESSDAA + - name: Processdaa description: PROCESSDAA. value: 4 - - name: FORCEEXIT + - name: Forceexit description: Force Exit and Target Reset. value: 6 - - name: AUTOIBI + - name: Autoibi description: AUTOIBI. value: 7 enum/Saddr: bit_size: 2 variants: - - name: NO_STATIC + - name: NoStatic description: No static address. value: 0 - - name: STATIC + - name: Static description: Static address is fixed in hardware. value: 1 - - name: HW_CONTROL + - name: HwControl description: Hardware controls the static address dynamically (for example, from the pin strap). value: 2 - - name: CONFIG + - name: Config description: SCONFIG register supplies the static address. value: 3 enum/ScapabilitiesTimectrl: bit_size: 1 variants: - - name: NO_TIME_CONTROL_TYPE + - name: NoTimeControlType description: No time control supported. value: 0 - - name: ATLEAST1_TIME_CONTROL + - name: Atleast1TimeControl description: At least one time-control type supported. value: 1 enum/SctrlEvent: bit_size: 2 variants: - - name: NORMAL_MODE + - name: NormalMode description: NORMAL_MODE. value: 0 - - name: IBI + - name: Ibi description: IBI. value: 1 - - name: MASTER_REQUEST + - name: MasterRequest description: CONTROLLER_REQUEST. value: 2 - - name: HOT_JOIN_REQUEST + - name: HotJoinRequest description: HOT_JOIN_REQUEST. value: 3 enum/SdatactrlRxempty: bit_size: 1 variants: - - name: RXISNOTEMPTY + - name: Rxisnotempty description: Not empty. value: 0 - - name: RXISEMPTY + - name: Rxisempty description: Empty. value: 1 enum/SdatactrlRxtrig: bit_size: 2 variants: - - name: TRIGGRNOTEMPTY + - name: Triggrnotempty description: Trigger when not empty (default). value: 0 - - name: TRIGGRONEFOURTH + - name: Triggronefourth description: Trigger when 1/4 or more full. value: 1 - - name: TRIGGRONEHALF + - name: Triggronehalf description: Trigger when 1/2 or more full. value: 2 - - name: TRIGGRTHREEFOURTHS + - name: Triggrthreefourths description: Trigger when 3/4 or more full. value: 3 enum/SdatactrlTxfull: bit_size: 1 variants: - - name: TXISNOTFULL + - name: Txisnotfull description: Not full. value: 0 - - name: TXISFULL + - name: Txisfull description: Full. value: 1 enum/SdatactrlTxtrig: bit_size: 2 variants: - - name: TRIGGREMPTY + - name: Triggrempty description: Trigger when empty. value: 0 - - name: TRIGGRONEFOURTH + - name: Triggronefourth description: Trigger when 1/4 full or less. value: 1 - - name: TRIGGRONEHALF + - name: Triggronehalf description: Trigger when 1/2 full or less. value: 2 - - name: TRIGGRONELESS + - name: Triggroneless description: Default (trigger when 1 less than full or less). value: 3 enum/SdmactrlDmafb: bit_size: 2 variants: - - name: NOT_USED + - name: NotUsed description: DMA not used. value: 0 - - name: ENABLE_ONE_FRAME + - name: EnableOneFrame description: DMA enabled for one frame. value: 1 - - name: ENABLE + - name: Enable description: DMA enabled until turned off. value: 2 enum/SdmactrlDmatb: bit_size: 2 variants: - - name: NOT_USED + - name: NotUsed description: DMA not used. value: 0 - - name: ENABLE_ONE_FRAME + - name: EnableOneFrame description: DMA enabled for one frame. value: 1 - - name: ENABLE + - name: Enable description: DMA enabled until turned off. value: 2 enum/SdmactrlDmawidth: bit_size: 2 variants: - - name: BYTE_0 + - name: Byte0 description: Byte. value: 0 - - name: BYTE_1 + - name: Byte1 description: Byte. value: 1 - - name: HALF_WORD + - name: HalfWord description: Halfword (16 bits) (this value ensures that two bytes are available in the FIFO). value: 2 -enum/SdynaddrDavalid: +enum/ShdrbtcfgCrc32: bit_size: 1 variants: - - name: DANOTASSIGNED - description: 'DANOTASSIGNED: a dynamic address is not assigned.' + - name: UseCrc16 + description: CRC16. value: 0 - - name: DAASSIGNED - description: 'DAASSIGNED: a dynamic address is assigned.' + - name: UseCrc32 + description: CRC32. value: 1 enum/SstatusStart: bit_size: 1 variants: - - name: START_NOT_DETECTED + - name: StartNotDetected description: Not detected. value: 0 - - name: START_DETECTED + - name: StartDetected description: Detected. value: 1 enum/SstatusTimectrl: bit_size: 2 variants: - - name: NO_TIME_CONTROL + - name: NoTimeControl description: NO_TIME_CONTROL (no time control is enabled). value: 0 - - name: SYNC + - name: Sync description: SYNC_MODE (Synchronous mode is enabled). value: 1 - - name: ASYNC_MODE + - name: AsyncMode description: ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled). value: 2 - - name: BOTHSYNCASYNC + - name: Bothsyncasync description: BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled). value: 3 enum/SstatusTxnotfull: bit_size: 1 variants: - - name: FULL + - name: Full description: Transmit buffer full. value: 0 - - name: NOT_FULL + - name: NotFull description: Transmit buffer not full. value: 1 enum/State: bit_size: 3 variants: - - name: IDLE + - name: Idle description: IDLE (bus has stopped). value: 0 - - name: SLVREQ + - name: Slvreq description: SLVREQ (target request). value: 1 - - name: MSGSDR + - name: Msgsdr description: MSGSDR. value: 2 - - name: NORMACT + - name: Normact description: NORMACT. value: 3 - - name: DDR + - name: Ddr description: MSGDDR. value: 4 - - name: DAA + - name: Daa description: DAA. value: 5 - - name: IBIACK + - name: Ibiack description: IBIACK. value: 6 - - name: IBIRCV + - name: Ibircv description: IBIRCV. value: 7 enum/Stccch: bit_size: 1 variants: - - name: IDLE + - name: Idle description: No CCC message handled. value: 0 - - name: BUSY + - name: Busy description: Handled automatically. value: 1 enum/Stmsg: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/Stnotstop: bit_size: 1 variants: - - name: STOPPED + - name: Stopped description: In STOP condition. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/Streqrd: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Not an SDR read. value: 0 - - name: BUSY + - name: Busy description: SDR read from this target or an IBI is being pushed out. value: 1 enum/Streqwr: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Not an SDR write. value: 0 - - name: BUSY + - name: Busy description: SDR write data from the controller, but not in ENTDAA mode. value: 1 enum/Type: bit_size: 2 variants: - - name: I3C + - name: I3c description: I3C. value: 0 - - name: I2C + - name: I2c description: I2C. value: 1 - - name: DDR + - name: Ddr description: DDR. value: 2 diff --git a/data/metadata/peripherals/mcxa/INPUTMUX.yaml b/data/metadata/peripherals/mcxa/INPUTMUX.yaml index 4976ff7..e5fc0b0 100644 --- a/data/metadata/peripherals/mcxa/INPUTMUX.yaml +++ b/data/metadata/peripherals/mcxa/INPUTMUX.yaml @@ -41,6 +41,22 @@ block/Inputmux: stride: 4 byte_offset: 160 fieldset: SmartDmaTrig + - name: lpspi2_trig + description: LPSPI2 trigger input connections. + byte_offset: 192 + fieldset: LpspiTrig + - name: lpspi3_trig + description: LPSPI3 trigger input connections. + byte_offset: 224 + fieldset: LpspiTrig + - name: lpspi4_trig + description: LPSPI4 trigger input connections. + byte_offset: 256 + fieldset: LpspiTrig + - name: lpspi5_trig + description: LPSPI5 trigger input connections. + byte_offset: 288 + fieldset: LpspiTrig - name: freqmeas_ref description: Selection for frequency measurement reference clock. byte_offset: 384 @@ -71,13 +87,6 @@ block/Inputmux: description: Trigger register for TIMER4. byte_offset: 464 fieldset: Timer4trig - - name: aoi1_input - description: AOI1 trigger input connections 0. - array: - len: 16 - stride: 4 - byte_offset: 512 - fieldset: AoiInput - name: cmp0_trig description: CMP0 input connections. byte_offset: 608 @@ -89,13 +98,6 @@ block/Inputmux: stride: 4 byte_offset: 640 fieldset: AdcTrig - - name: adc2_trig - description: ADC Trigger input connections. - array: - len: 4 - stride: 4 - byte_offset: 672 - fieldset: AdcTrig - name: adc1_trig description: ADC Trigger input connections. array: @@ -103,201 +105,32 @@ block/Inputmux: stride: 4 byte_offset: 704 fieldset: AdcTrig - - name: adc3_trig - description: ADC Trigger input connections. - array: - len: 4 - stride: 4 - byte_offset: 736 - fieldset: AdcTrig - name: dac0_trig - description: DAC0 Trigger input connections. + description: DAC0 trigger. byte_offset: 768 fieldset: DacTrig - - name: qdc0_trig - description: QDC0 Trigger Input Connections. - byte_offset: 864 - fieldset: QdcTrig - - name: qdc0_home - description: QDC0 Trigger Input Connections. - byte_offset: 868 - fieldset: Qdc0Home - - name: qdc0_index - description: QDC0 Trigger Input Connections. - byte_offset: 872 - fieldset: Qdc0Index - - name: qdc0_phaseb - description: QDC0 Trigger Input Connections. - byte_offset: 876 - fieldset: Qdc0Phaseb - - name: qdc0_phasea - description: QDC0 Trigger Input Connections. - byte_offset: 880 - fieldset: Qdc0Phasea - - name: qdc0_icap1 - description: QDC0 Trigger Input Connections. - byte_offset: 884 - fieldset: Qdc0Icap1 - - name: qdc0_icap2 - description: QDC0 Trigger Input Connections. - byte_offset: 888 - fieldset: Qdc0Icap2 - - name: qdc0_icap3 - description: QDC0 Trigger Input Connections. - byte_offset: 892 - fieldset: Qdc0Icap3 - - name: qdc1_trig - description: QDC1 Trigger Input Connections. - byte_offset: 896 - fieldset: QdcTrig - - name: qdc1_home - description: QDC1 Trigger Input Connections. - byte_offset: 900 - fieldset: Qdc1Home - - name: qdc1_index - description: QDC1 Trigger Input Connections. - byte_offset: 904 - fieldset: Qdc1Index - - name: qdc1_phaseb - description: QDC1 Trigger Input Connections. - byte_offset: 908 - fieldset: Qdc1Phaseb - - name: qdc1_phasea - description: QDC1 Trigger Input Connections. - byte_offset: 912 - fieldset: Qdc1Phasea - - name: qdc1_icap1 - description: QDC1 Trigger Input Connections. - byte_offset: 916 - fieldset: Qdc1Icap1 - - name: qdc1_icap2 - description: QDC1 Trigger Input Connections. - byte_offset: 920 - fieldset: Qdc1Icap2 - - name: qdc1_icap3 - description: QDC1 Trigger Input Connections. - byte_offset: 924 - fieldset: Qdc1Icap3 - - name: flex_pwm0_sm0_exta0 - description: PWM0 input trigger connections. - byte_offset: 928 - fieldset: FlexPwm - - name: flex_pwm0_sm0_extsync - description: PWM0 input trigger connections. - byte_offset: 932 - fieldset: FlexPwm - - name: flex_pwm0_sm1_exta - description: PWM0 input trigger connections. - byte_offset: 936 - fieldset: FlexPwm - - name: flex_pwm0_sm1_extsync - description: PWM0 input trigger connections. - byte_offset: 940 - fieldset: FlexPwm - - name: flex_pwm0_sm2_exta - description: PWM0 input trigger connections. - byte_offset: 944 - fieldset: FlexPwm - - name: flex_pwm0_sm2_extsync - description: PWM0 input trigger connections. - byte_offset: 948 - fieldset: FlexPwm - - name: flex_pwm0_sm3_exta0 - description: PWM0 input trigger connections. - byte_offset: 952 - fieldset: FlexPwm - - name: flex_pwm0_sm3_extsync - description: PWM0 input trigger connections. - byte_offset: 956 - fieldset: FlexPwm - - name: flex_pwm0_fault - description: PWM0 Fault Input Trigger Connections. - array: - len: 4 - stride: 4 - byte_offset: 960 - fieldset: FlexPwm - - name: flex_pwm0_force - description: PWM0 input trigger connections. - byte_offset: 976 - fieldset: FlexPwm - - name: flex_pwm1_sm0_exta0 - description: PWM1 input trigger connections. - byte_offset: 992 - fieldset: FlexPwm - - name: flex_pwm1_sm0_extsync - description: PWM1 input trigger connections. - byte_offset: 996 - fieldset: FlexPwm - - name: flex_pwm1_sm1_exta - description: PWM1 input trigger connections. - byte_offset: 1000 - fieldset: FlexPwm - - name: flex_pwm1_sm1_extsync - description: PWM1 input trigger connections. - byte_offset: 1004 - fieldset: FlexPwm - - name: flex_pwm1_sm2_exta - description: PWM1 input trigger connections. - byte_offset: 1008 - fieldset: FlexPwm - - name: flex_pwm1_sm2_extsync - description: PWM1 input trigger connections. - byte_offset: 1012 - fieldset: FlexPwm - - name: flex_pwm1_sm3_exta0 - description: PWM1 input trigger connections. - byte_offset: 1016 - fieldset: FlexPwm - - name: flex_pwm1_sm3_extsync - description: PWM1 input trigger connections. - byte_offset: 1020 - fieldset: FlexPwm - - name: flex_pwm1_fault - description: PWM1 Fault Input Trigger Connections. - array: - len: 4 - stride: 4 - byte_offset: 1024 - fieldset: FlexPwm - - name: flex_pwm1_force - description: PWM1 input trigger connections. - byte_offset: 1040 - fieldset: FlexPwm - - name: pwm0_ext_clk - description: PWM0 external clock trigger. - byte_offset: 1056 - fieldset: Pwm0ExtClk - - name: pwm1_ext_clk - description: PWM1 external clock trigger. - byte_offset: 1060 - fieldset: Pwm1ExtClk + - name: dac1_trig + description: DAC1 trigger. + byte_offset: 800 + fieldset: DacTrig - name: aoi0_input description: AOI0 trigger input connections 0. array: len: 16 stride: 4 byte_offset: 1088 - fieldset: AoiInput - - name: usbfs_trig - description: USB-FS trigger input connections. - byte_offset: 1152 - fieldset: UsbfsTrig - - name: ext_trig + fieldset: Aoi0Input + - name: tsi0_trig_input + description: TSI0 trigger input connections. + byte_offset: 1184 + fieldset: Tsi0TrigInput + - name: trig_out description: EXT trigger connections. array: len: 8 stride: 4 byte_offset: 1216 - fieldset: ExtTrig - - name: cmp1_trig - description: CMP1 input connections. - byte_offset: 1248 - fieldset: CmpTrig - - name: cmp2_trig - description: CMP2 input connections. - byte_offset: 1280 - fieldset: CmpTrig + fieldset: TrigOut - name: lpi2c2_trig description: LPI2C2 trigger input connections. byte_offset: 1344 @@ -336,22 +169,6 @@ block/Inputmux: stride: 4 byte_offset: 1760 fieldset: FlexioTrig - - name: trigfil_prsc - description: Trigger filter prescaller. - byte_offset: 2560 - fieldset: TrigfilPrsc - - name: trigfil_stat0 - description: Trigger filter stat. - byte_offset: 2564 - access: Read - fieldset: TrigfilStat - - name: trigfil - description: TRIGFIL control. - array: - len: 12 - stride: 4 - byte_offset: 2576 - fieldset: Trigfil fieldset/AdcTrig: description: ADC Trigger input connections. fields: @@ -360,7 +177,7 @@ fieldset/AdcTrig: bit_offset: 0 bit_size: 6 enum: AdcTrigTrigin -fieldset/AoiInput: +fieldset/Aoi0Input: description: AOI0 trigger input connections 0. fields: - name: inp @@ -382,7 +199,7 @@ fieldset/Ctimer0cap: - name: inp description: Input number for CTIMER0. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Ctimer0capInp fieldset/Ctimer1cap: description: Capture select register for CTIMER inputs. @@ -390,7 +207,7 @@ fieldset/Ctimer1cap: - name: inp description: Input number for CTIMER1. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Ctimer1capInp fieldset/Ctimer2cap: description: Capture select register for CTIMER inputs. @@ -398,7 +215,7 @@ fieldset/Ctimer2cap: - name: inp description: Input number for CTIMER2. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Ctimer2capInp fieldset/Ctimer3cap: description: Capture select register for CTIMER inputs. @@ -406,7 +223,7 @@ fieldset/Ctimer3cap: - name: inp description: Input number for CTIMER3. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Ctimer3capInp fieldset/Ctimer4cap: description: Capture select register for CTIMER inputs. @@ -414,32 +231,16 @@ fieldset/Ctimer4cap: - name: inp description: Input number for CTIMER4. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Ctimer4capInp fieldset/DacTrig: - description: DAC0 Trigger input connections. + description: DAC0 trigger. fields: - name: trigin - description: DAC0 trigger input. + description: This register selects the DAC0 trigger inputs. bit_offset: 0 - bit_size: 6 + bit_size: 7 enum: DacTrigTrigin -fieldset/ExtTrig: - description: EXT trigger connections. - fields: - - name: inp - description: EXT trigger input connections. - bit_offset: 0 - bit_size: 5 - enum: ExtTrigInp -fieldset/FlexPwm: - description: PWM0 Fault Input Trigger Connections. - fields: - - name: trigin - description: FAULT input connections for PWM0. - bit_offset: 0 - bit_size: 6 - enum: FlexPwmTrigin fieldset/FlexioTrig: description: FlexIO Trigger Input Connections. fields: @@ -488,147 +289,11 @@ fieldset/Lpuart: bit_offset: 0 bit_size: 6 enum: LpuartInp -fieldset/Pwm0ExtClk: - description: PWM0 external clock trigger. - fields: - - name: trigin - description: Trigger input connections for PWM. - bit_offset: 0 - bit_size: 4 - enum: Pwm0ExtClkTrigin -fieldset/Pwm1ExtClk: - description: PWM1 external clock trigger. - fields: - - name: trigin - description: Trigger input connections for PWM. - bit_offset: 0 - bit_size: 4 - enum: Pwm1ExtClkTrigin -fieldset/Qdc0Home: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcHomeInp -fieldset/Qdc0Icap1: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc0Icap2: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc0Icap3: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc0Index: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIndexInp -fieldset/Qdc0Phasea: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: Qdc0PhaseaInp -fieldset/Qdc0Phaseb: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: Qdc0PhasebInp -fieldset/Qdc1Home: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcHomeInp -fieldset/Qdc1Icap1: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc1Icap2: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc1Icap3: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIcapInp -fieldset/Qdc1Index: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcIndexInp -fieldset/Qdc1Phasea: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: Qdc1PhaseaInp -fieldset/Qdc1Phaseb: - description: QDC1 Trigger Input Connections. - fields: - - name: inp - description: QDC1 input connections. - bit_offset: 0 - bit_size: 7 - enum: Qdc1PhasebInp -fieldset/QdcTrig: - description: QDC0 Trigger Input Connections. - fields: - - name: inp - description: QDC0 input connections. - bit_offset: 0 - bit_size: 7 - enum: QdcTrigInp fieldset/SmartDmaTrig: description: SmartDMA Trigger Input Connections. fields: - name: inp - description: Input number for SmartDMA. + description: Input number for FlexIO0. bit_offset: 0 bit_size: 7 enum: SmartDmaTrigInp @@ -638,7 +303,7 @@ fieldset/Timer0trig: - name: inp description: Input number for CTIMER0. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Timer0trigInp fieldset/Timer1trig: description: Trigger register for TIMER1. @@ -646,7 +311,7 @@ fieldset/Timer1trig: - name: inp description: Input number for CTIMER1. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Timer1trigInp fieldset/Timer2trig: description: Trigger register for TIMER2 inputs. @@ -654,7 +319,7 @@ fieldset/Timer2trig: - name: inp description: Input number for CTIMER2. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Timer2trigInp fieldset/Timer3trig: description: Trigger register for TIMER3. @@ -662,7 +327,7 @@ fieldset/Timer3trig: - name: inp description: Input number for CTIMER3. bit_offset: 0 - bit_size: 7 + bit_size: 8 enum: Timer3trigInp fieldset/Timer4trig: description: Trigger register for TIMER4. @@ -670,6949 +335,4500 @@ fieldset/Timer4trig: - name: inp description: Input number for CTIMER4. bit_offset: 0 - bit_size: 7 - enum: Timer4trigInp -fieldset/Trigfil: - description: TRIGFIL control. - fields: - - name: filt_per - description: Input Filter Sample Period. - bit_offset: 0 bit_size: 8 - - name: filt_cnt - description: Input Filter Sample Count. - bit_offset: 8 - bit_size: 3 -fieldset/TrigfilPrsc: - description: Trigger filter prescaller. - fields: - - name: filt_scale_val - description: Filter Prescaller Value. - bit_offset: 0 - bit_size: 2 - enum: FiltScaleVal - - name: filt_scale_en - description: Enable trigger filter prescaller. - bit_offset: 31 - bit_size: 1 - enum: FiltScaleEn -fieldset/TrigfilStat: - description: Trigger filter stat. + enum: Timer4trigInp +fieldset/TrigOut: + description: EXT trigger connections. fields: - - name: trig_in0_val - description: TRIG_IN value. + - name: inp + description: EXT trigger input connections. bit_offset: 0 - bit_size: 1 - enum: TrigInVal - - name: trig_in1_val - description: TRIG_IN value. - bit_offset: 1 - bit_size: 1 - enum: TrigInVal - - name: trig_in2_val - description: TRIG_IN value. - bit_offset: 2 - bit_size: 1 - enum: TrigInVal - - name: trig_in3_val - description: TRIG_IN value. - bit_offset: 3 - bit_size: 1 - enum: TrigInVal - - name: trig_in4_val - description: TRIG_IN value. - bit_offset: 4 - bit_size: 1 - enum: TrigInVal - - name: trig_in5_val - description: TRIG_IN value. - bit_offset: 5 - bit_size: 1 - enum: TrigInVal - - name: trig_in6_val - description: TRIG_IN value. - bit_offset: 6 - bit_size: 1 - enum: TrigInVal - - name: trig_in7_val - description: TRIG_IN value. - bit_offset: 7 - bit_size: 1 - enum: TrigInVal - - name: trig_in8_val - description: TRIG_IN value. - bit_offset: 8 - bit_size: 1 - enum: TrigInVal - - name: trig_in9_val - description: TRIG_IN value. - bit_offset: 9 - bit_size: 1 - enum: TrigInVal - - name: trig_in10_val - description: TRIG_IN value. - bit_offset: 10 - bit_size: 1 - enum: TrigInVal - - name: trig_in11_val - description: TRIG_IN value. - bit_offset: 11 - bit_size: 1 - enum: TrigInVal -fieldset/UsbfsTrig: - description: USB-FS trigger input connections. + bit_size: 7 + enum: TrigOutInp +fieldset/Tsi0TrigInput: + description: TSI0 trigger input connections. fields: - name: inp - description: USB-FS trigger input connections. + description: TSI0 trigger input connections. bit_offset: 0 - bit_size: 4 - enum: UsbfsTrigInp + bit_size: 6 + enum: Tsi0TrigInputInp enum/AdcTrigTrigin: bit_size: 6 variants: - - name: VAL1 + - name: Val1 description: ARM_TXEV input is selected. value: 1 - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CMP0_OUT input is selected. value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT1 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT0 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT1 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT0 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer2_MAT1 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: LPTMR0 input is selected. value: 15 - - name: VAL17 - description: QDC0_POS_MATCH0 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM0_OUT_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM0_OUT_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM1_OUT_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM1_OUT_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM2_OUT_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM2_OUT_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: PWM0_SM3_OUT_TRIG0 input is selected. - value: 24 - - name: VAL25 - description: PWM0_SM3_OUT_TRIG1 input is selected. - value: 25 - - name: VAL26 + - name: Val26 description: GPIO0 Pin Event Trig 0 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: GPIO1 Pin Event Trig 0 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: GPIO2 Pin Event Trig 0 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: GPIO3 Pin Event Trig 0 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: GPIO4 Pin Event Trig 0 input is selected. value: 30 - - name: VAL31 + - name: Val31 description: WUU. value: 31 - - name: VAL33 - description: AOI1_OUT0 input is selected. - value: 33 - - name: VAL34 - description: AOI1_OUT1 input is selected. - value: 34 - - name: VAL35 - description: AOI1_OUT2 input is selected. - value: 35 - - name: VAL36 - description: AOI1_OUT3 input is selected. - value: 36 - - name: VAL37 + - name: Val37 description: ADC1_tcomp[0] input is selected. value: 37 - - name: VAL38 + - name: Val38 description: ADC1_tcomp[1] input is selected. value: 38 - - name: VAL39 + - name: Val39 description: ADC1_tcomp[2] input is selected. value: 39 - - name: VAL40 + - name: Val40 description: ADC1_tcomp[3] input is selected. value: 40 - - name: VAL41 + - name: Val41 description: CTimer3_MAT0 input is selected. value: 41 - - name: VAL42 + - name: Val42 description: CTimer3_MAT1 input is selected. value: 42 - - name: VAL43 + - name: Val43 description: CTimer4_MAT0 input is selected. value: 43 - - name: VAL44 + - name: Val44 description: CTimer4_MAT1 input is selected. value: 44 - - name: VAL45 - description: FlexIO CH0 input is selected. + - name: Val45 + description: FlexIO0 CH0 input is selected. value: 45 - - name: VAL46 - description: FlexIO CH1 input is selected. + - name: Val46 + description: FlexIO0 CH1 input is selected. value: 46 - - name: VAL47 - description: FlexIO CH2 input is selected. + - name: Val47 + description: FlexIO0 CH2 input is selected. value: 47 - - name: VAL48 - description: FlexIO CH3 input is selected. + - name: Val48 + description: FlexIO0 CH3 input is selected. value: 48 - - name: VAL49 - description: QDC1_POS_MATCH0 input is selected. - value: 49 - - name: VAL50 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 50 - - name: VAL51 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 51 - - name: VAL52 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 52 - - name: VAL53 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 53 - - name: VAL54 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 54 - - name: VAL55 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 55 - - name: VAL56 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 56 - - name: VAL57 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 57 enum/AoiInputInp: bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: ADC0_tcomp[0] input is selected. value: 1 - - name: VAL2 + - name: Val2 description: ADC0_tcomp[1] input is selected. value: 2 - - name: VAL3 + - name: Val3 description: ADC0_tcomp[2] input is selected. value: 3 - - name: VAL4 + - name: Val4 description: ADC0_tcomp[3] input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CMP0_OUT input is selected. value: 5 - - name: VAL6 - description: CMP1_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP2_OUT input is selected. - value: 7 - - name: VAL8 + - name: Val8 description: CTimer0_MAT0 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT1 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT2 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer0_MAT3 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT0 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer1_MAT1 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer1_MAT2 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CTimer1_MAT3 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CTimer2_MAT0 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CTimer2_MAT1 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CTimer2_MAT2 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CTimer2_MAT3 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: LPTMR0 input is selected. value: 20 - - name: VAL22 - description: QDC0_CMP_FLAG0 input is selected. - value: 22 - - name: VAL23 - description: QDC0_CMP_FLAG1 input is selected. - value: 23 - - name: VAL24 - description: QDC0_CMP_FLAG2 input is selected. - value: 24 - - name: VAL25 - description: QDC0_CMP_FLAG3 input is selected. - value: 25 - - name: VAL26 - description: QDC0_POS_MATCH0 input is selected. - value: 26 - - name: VAL27 - description: PWM0_SM0_MUX_TRIG0 0 input is selected. - value: 27 - - name: VAL28 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 28 - - name: VAL29 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 29 - - name: VAL30 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 30 - - name: VAL31 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 31 - - name: VAL32 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 32 - - name: VAL33 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 33 - - name: VAL34 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 34 - - name: VAL35 + - name: Val35 description: TRIG_IN0 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: TRIG_IN1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: TRIG_IN2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: TRIG_IN3 input is selected. value: 38 - - name: VAL39 + - name: Val39 description: TRIG_IN4 input is selected. value: 39 - - name: VAL40 + - name: Val40 description: TRIG_IN5 input is selected. value: 40 - - name: VAL41 + - name: Val41 description: TRIG_IN6 input is selected. value: 41 - - name: VAL42 + - name: Val42 description: TRIG_IN7 input is selected. value: 42 - - name: VAL43 + - name: Val43 description: TRIG_IN8 input is selected. value: 43 - - name: VAL44 + - name: Val44 description: TRIG_IN9 input is selected. value: 44 - - name: VAL45 + - name: Val45 description: TRIG_IN10 input is selected. value: 45 - - name: VAL46 + - name: Val46 description: TRIG_IN11 input is selected. value: 46 - - name: VAL47 + - name: Val47 description: GPIO0 Pin Event Trig 0 input is selected. value: 47 - - name: VAL48 + - name: Val48 description: GPIO1 Pin Event Trig 0 input is selected. value: 48 - - name: VAL49 + - name: Val49 description: GPIO2 Pin Event Trig 0 input is selected. value: 49 - - name: VAL50 + - name: Val50 description: GPIO3 Pin Event Trig 0 input is selected. value: 50 - - name: VAL51 + - name: Val51 description: GPIO4 Pin Event Trig 0 input is selected. value: 51 - - name: VAL52 - description: ADC1_tcomp[0] input is selected. - value: 52 - - name: VAL53 - description: ADC1_tcomp[1] input is selected. - value: 53 - - name: VAL54 - description: ADC1_tcomp[2] input is selected. - value: 54 - - name: VAL55 - description: ADC1_tcomp[3] input is selected. - value: 55 - - name: VAL56 + - name: Val56 description: CTimer3_MAT0 input is selected. value: 56 - - name: VAL57 + - name: Val57 description: CTimer3_MAT1 input is selected. value: 57 - - name: VAL58 + - name: Val58 description: CTimer3_MAT2 input is selected. value: 58 - - name: VAL59 + - name: Val59 description: CTimer3_MAT3 input is selected. value: 59 - - name: VAL60 + - name: Val60 description: CTimer4_MAT0 input is selected. value: 60 - - name: VAL61 + - name: Val61 description: CTimer4_MAT1 input is selected. value: 61 - - name: VAL62 + - name: Val62 description: CTimer4_MAT2 input is selected. value: 62 - - name: VAL63 + - name: Val63 description: CTimer4_MAT3 input is selected. value: 63 - - name: VAL64 + - name: Val64 description: FlexIO CH0 input is selected. value: 64 - - name: VAL65 + - name: Val65 description: FlexIO CH1 input is selected. value: 65 - - name: VAL66 + - name: Val66 description: FlexIO CH2 input is selected. value: 66 - - name: VAL67 + - name: Val67 description: FlexIO CH3 input is selected. value: 67 - - name: VAL68 - description: QDC1_CMP_FLAG0 input is selected. - value: 68 - - name: VAL69 - description: QDC1_CMP_FLAG1 input is selected. - value: 69 - - name: VAL70 - description: QDC1_CMP_FLAG2 input is selected. - value: 70 - - name: VAL71 - description: QDC1_CMP_FLAG3 input is selected. - value: 71 - - name: VAL72 - description: QDC1_POS_MATCH0 input is selected. - value: 72 - - name: VAL73 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 73 - - name: VAL74 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 74 - - name: VAL75 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 75 - - name: VAL76 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 76 - - name: VAL77 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 77 - - name: VAL78 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 78 - - name: VAL79 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 79 - - name: VAL80 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 80 - - name: VAL81 - description: PWM0_SM0_A_Output. - value: 81 - - name: VAL82 - description: PWM0_SM0_B_Output. - value: 82 - - name: VAL83 - description: PWM0_SM1_A_Output. - value: 83 - - name: VAL84 - description: PWM0_SM1_B_Output. - value: 84 - - name: VAL85 - description: PWM0_SM2_A_Output. - value: 85 - - name: VAL86 - description: PWM0_SM2_B_Output. - value: 86 - - name: VAL87 - description: PWM0_SM3_A_Output. - value: 87 - - name: VAL88 - description: PWM0_SM3_B_Output. - value: 88 - - name: VAL89 - description: ADC2_tcomp[0] input is selected. - value: 89 - - name: VAL90 - description: ADC2_tcomp[1] input is selected. - value: 90 - - name: VAL91 - description: ADC2_tcomp[2] input is selected. - value: 91 - - name: VAL92 - description: ADC2_tcomp[3] input is selected. - value: 92 - - name: VAL93 - description: ADC3_tcomp[0] input is selected. - value: 93 - - name: VAL94 - description: ADC3_tcomp[1] input is selected. - value: 94 - - name: VAL95 - description: ADC3_tcomp[2] input is selected. - value: 95 - - name: VAL96 - description: ADC3_tcomp[3] input is selected. - value: 96 + - name: Val97 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 97 + - name: Val98 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 98 + - name: Val99 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 99 + - name: Val100 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 100 + - name: Val101 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 101 enum/CmpTrigTrigin: bit_size: 6 variants: - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 - description: CMP1_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP2_OUT input is selected. - value: 7 - - name: VAL8 + - name: Val8 description: CTimer0_MAT0 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT2 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer1_MAT0. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT2 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer2_MAT0 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT2 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: LPTMR0 input is selected. value: 14 - - name: VAL16 - description: QDC0_POS_MATCH0. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 23 - - name: VAL24 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 24 - - name: VAL25 + - name: Val25 description: GPIO0 Pin Event Trig 0 input is selected. value: 25 - - name: VAL26 + - name: Val26 description: GPIO1 Pin Event Trig 0 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: GPIO2 Pin Event Trig 0 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: GPIO3 Pin Event Trig 0 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: GPIO4 Pin Event Trig 0 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: WUU input is selected. value: 30 - - name: VAL31 - description: AOI1_OUT0 input is selected. - value: 31 - - name: VAL32 - description: AOI1_OUT1 input is selected. - value: 32 - - name: VAL33 - description: AOI1_OUT2 input is selected. - value: 33 - - name: VAL34 - description: AOI1_OUT3 input is selected. - value: 34 - - name: VAL39 - description: CTimer3_MAT0. + - name: Val39 + description: CTimer3_MAT0 input is selected. value: 39 - - name: VAL40 - description: CTimer3_MAT1. + - name: Val40 + description: CTimer3_MAT1 input is selected. value: 40 - - name: VAL41 + - name: Val41 description: CTimer4_MAT0 input is selected. value: 41 - - name: VAL42 + - name: Val42 description: CTimer4_MAT1 input is selected. value: 42 - - name: VAL47 - description: QDC1_POS_MATCH0 input is selected. - value: 47 - - name: VAL48 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 48 - - name: VAL49 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 49 - - name: VAL50 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 50 - - name: VAL51 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 51 - - name: VAL52 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 52 - - name: VAL53 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 53 - - name: VAL54 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 54 - - name: VAL55 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 55 + - name: Val56 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 56 + - name: Val57 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 57 + - name: Val58 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 58 + - name: Val59 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 59 + - name: Val60 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 60 enum/Ctimer0capInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CMP0_OUT is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer1_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer1_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer1_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer2_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer2_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer2_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer3_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer3_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Ctimer1capInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 - description: CMP0_OUT is selected. + - name: Val30 + description: CMP0_OUT input is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer2_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer2_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer2_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 - description: CTimer3_MAT1 input is selected. + - name: Val79 + description: CTimer3_MAT1 is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer3_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Ctimer2capInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CMP0_OUT is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer3_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer3_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Ctimer3capInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 - description: CMP0_OUT is selected. + - name: Val30 + description: CMP0_OUT input is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer2_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer2_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer2_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 - - name: VAL113 + - name: Val102 + description: TMPR_OUT0 input is selected. + value: 102 + - name: Val103 + description: TMPR_OUT1 input is selected. + value: 103 + - name: Val113 description: TRIG_IN0 input is selected. value: 113 - - name: VAL114 + - name: Val114 description: TRIG_IN1 input is selected. value: 114 - - name: VAL115 + - name: Val115 description: TRIG_IN2 input is selected. value: 115 - - name: VAL116 + - name: Val116 description: TRIG_IN3 input is selected. value: 116 - - name: VAL117 + - name: Val117 description: TRIG_IN4 input is selected. value: 117 - - name: VAL118 + - name: Val118 description: TRIG_IN5 input is selected. value: 118 - - name: VAL119 + - name: Val119 description: TRIG_IN6 input is selected. value: 119 - - name: VAL120 + - name: Val120 description: TRIG_IN7 input is selected. value: 120 - - name: VAL121 + - name: Val121 description: TRIG_IN8 input is selected. value: 121 - - name: VAL122 + - name: Val122 description: TRIG_IN9 input is selected. value: 122 - - name: VAL123 + - name: Val123 description: TRIG_IN10 input is selected. value: 123 - - name: VAL124 + - name: Val124 description: TRIG_IN11 input is selected. value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Ctimer4capInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CMP0_OUT is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer2_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer2_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer2_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer3_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer3_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer3_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 - - name: VAL113 + - name: Val102 + description: TMPR_OUT0 input is selected. + value: 102 + - name: Val103 + description: TMPR_OUT1 input is selected. + value: 103 + - name: Val113 description: TRIG_IN0 input is selected. value: 113 - - name: VAL114 + - name: Val114 description: TRIG_IN1 input is selected. value: 114 - - name: VAL115 + - name: Val115 description: TRIG_IN2 input is selected. value: 115 - - name: VAL116 + - name: Val116 description: TRIG_IN3 input is selected. value: 116 - - name: VAL117 + - name: Val117 description: TRIG_IN4 input is selected. value: 117 - - name: VAL118 + - name: Val118 description: TRIG_IN5 input is selected. value: 118 - - name: VAL119 + - name: Val119 description: TRIG_IN6 input is selected. value: 119 - - name: VAL120 + - name: Val120 description: TRIG_IN7 input is selected. value: 120 - - name: VAL121 + - name: Val121 description: TRIG_IN8 input is selected. value: 121 - - name: VAL122 + - name: Val122 description: TRIG_IN9 input is selected. value: 122 - - name: VAL123 + - name: Val123 description: TRIG_IN10 input is selected. value: 123 - - name: VAL124 + - name: Val124 description: TRIG_IN11 input is selected. value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/DacTrigTrigin: - bit_size: 6 + bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: ARM_TXEV. value: 1 - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CMP0_OUT input is selected. value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT1 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT0 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT1 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT0 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer2_MAT1 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: LPTMR0 input is selected. value: 15 - - name: VAL18 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 21 - - name: VAL26 + - name: Val26 description: GPIO0 Pin Event Trig 0 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: GPIO1 Pin Event Trig 0 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: GPIO2 Pin Event Trig 0 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: GPIO3 Pin Event Trig 0 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: GPIO4 Pin Event Trig 0 input is selected. value: 30 - - name: VAL31 + - name: Val31 description: WUU input is selected. value: 31 - - name: VAL33 - description: AOI1_OUT0 input is selected. - value: 33 - - name: VAL34 - description: AOI1_OUT1 input is selected. - value: 34 - - name: VAL35 - description: AOI1_OUT2 input is selected. - value: 35 - - name: VAL36 - description: AOI1_OUT3 input is selected. - value: 36 - - name: VAL37 - description: ADC0_tcomp[0] input is selected. - value: 37 - - name: VAL38 - description: ADC0_tcomp[1] input is selected. - value: 38 - - name: VAL39 - description: ADC1_tcomp[0] input is selected. - value: 39 - - name: VAL40 - description: ADC1_tcomp[1] input is selected. - value: 40 - - name: VAL41 + - name: Val41 description: CTimer3_MAT0 input is selected. value: 41 - - name: VAL42 + - name: Val42 description: CTimer3_MAT1 input is selected. value: 42 - - name: VAL43 + - name: Val43 description: CTimer4_MAT0 input is selected. value: 43 - - name: VAL44 + - name: Val44 description: CTimer4_MAT1 input is selected. value: 44 - - name: VAL50 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 50 - - name: VAL51 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 51 - - name: VAL52 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 52 - - name: VAL53 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 53 - - name: VAL58 - description: ADC2_tcomp[0] input is selected. - value: 58 - - name: VAL59 - description: ADC2_tcomp[1] input is selected. - value: 59 - - name: VAL60 - description: ADC3_tcomp[0] input is selected. - value: 60 - - name: VAL61 - description: ADC3_tcomp[1] input is selected. - value: 61 -enum/ExtTrigInp: - bit_size: 5 - variants: - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: LPUART0 ipp_do_lpuart_txd input is selected. - value: 9 - - name: VAL10 - description: LPUART1 ipp_do_lpuart_txd input is selected. - value: 10 - - name: VAL11 - description: LPUART2 ipp_do_lpuart_txd input is selected. - value: 11 - - name: VAL12 - description: LPUART3 ipp_do_lpuart_txd input is selected. - value: 12 - - name: VAL13 - description: LPUART4 ipp_do_lpuart_txd input is selected. - value: 13 - - name: VAL14 - description: AOI1_OUT0 input is selected. - value: 14 - - name: VAL15 - description: AOI1_OUT1 input is selected. - value: 15 - - name: VAL16 - description: AOI1_OUT2 input is selected. - value: 16 - - name: VAL17 - description: RTC_1Hz_CLK input is selected. - value: 17 - - name: VAL18 - description: LPUART5 ipp_do_lpuart_txd input is selected. - value: 18 -enum/FiltScaleEn: - bit_size: 1 - variants: - - name: VAL2 - description: Disable prescaller. - value: 0 - - name: VAL1 - description: Enabled prescaller. - value: 1 -enum/FiltScaleVal: - bit_size: 2 - variants: - - name: VAL0 - description: Bypass the clock. - value: 0 - - name: VAL1 - description: Divide 2. - value: 1 - - name: VAL2 - description: Divide 4. - value: 2 - - name: VAL3 - description: Divide 8. - value: 3 -enum/FlexPwmTrigin: - bit_size: 6 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3 input is selected. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL15 - description: QDC0_CMP_FLAG0 input is selected. - value: 15 - - name: VAL16 - description: QDC0_CMP_FLAG1 input is selected. - value: 16 - - name: VAL17 - description: QDC0_CMP_FLAG2 input is selected. - value: 17 - - name: VAL18 - description: QDC0_CMP_FLAG3 input is selected. - value: 18 - - name: VAL19 - description: QDC0_POS_MATCH0 input is selected. - value: 19 - - name: VAL20 - description: TRIG_IN0 input is selected. - value: 20 - - name: VAL21 - description: TRIG_IN1 input is selected. - value: 21 - - name: VAL22 - description: TRIG_IN2 input is selected. - value: 22 - - name: VAL23 - description: TRIG_IN3 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN4 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN5 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN6 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN7 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN8 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN9 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN10 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN11 input is selected. - value: 31 - - name: VAL32 - description: GPIO0 Pin Event Trig 0 input is selected. - value: 32 - - name: VAL33 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 33 - - name: VAL34 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 34 - - name: VAL35 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 35 - - name: VAL36 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 36 - - name: VAL37 - description: AOI1_OUT0 input is selected. - value: 37 - - name: VAL38 - description: AOI1_OUT1 input is selected. - value: 38 - - name: VAL39 - description: AOI1_OUT2 input is selected. - value: 39 - - name: VAL40 - description: AOI1_OUT3 input is selected. - value: 40 - - name: VAL45 - description: CTimer3_MAT2 input is selected. - value: 45 - - name: VAL46 - description: CTimer3_MAT3 input is selected. - value: 46 - - name: VAL47 - description: CTimer4_MAT2 input is selected. - value: 47 - - name: VAL48 - description: CTimer4_MAT3 input is selected. - value: 48 - - name: VAL49 - description: QDC1_CMP_FLAG0 input is selected. - value: 49 - - name: VAL50 - description: QDC1_CMP_FLAG1 input is selected. - value: 50 - - name: VAL51 - description: QDC1_CMP_FLAG2 input is selected. - value: 51 - - name: VAL52 - description: QDC1_CMP_FLAG3 input is selected. - value: 52 - - name: VAL53 - description: QDC1_POS_MATCH0 input is selected. - value: 53 - - name: VAL54 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 54 - - name: VAL55 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 55 - - name: VAL56 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 56 - - name: VAL57 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 57 - - name: VAL58 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 58 - - name: VAL59 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 59 - - name: VAL60 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 60 - - name: VAL61 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 61 + - name: Val62 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 62 + - name: Val63 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 63 + - name: Val64 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 64 + - name: Val65 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 65 + - name: Val66 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 66 enum/FlexioTrigInp: bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: AOI0_OUT0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: AOI0_OUT1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: ADC0_tcomp[0] input is selected. value: 5 - - name: VAL6 + - name: Val6 description: ADC0_tcomp[1] input is selected. value: 6 - - name: VAL7 + - name: Val7 description: ADC0_tcomp[2] input is selected. value: 7 - - name: VAL8 + - name: Val8 description: ADC0_tcomp[3] input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CMP0_OUT input is selected. value: 9 - - name: VAL10 - description: CMP1_OUT input is selected. - value: 10 - - name: VAL11 - description: CMP2_OUT input is selected. - value: 11 - - name: VAL12 + - name: Val12 description: CTimer0_MAT1 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer0_MAT2 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer1_MAT1 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CTimer1_MAT2 input is selected. value: 15 - - name: VAL16 - description: CTimer2_MAT1 input is selected. - value: 16 - - name: VAL17 + - name: Val17 description: CTimer2_MAT2 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: LPTMR0 input is selected. value: 18 - - name: VAL20 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 23 - - name: VAL24 + - name: Val24 description: TRIG_IN0 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: TRIG_IN1 input is selected. value: 25 - - name: VAL26 + - name: Val26 description: TRIG_IN2 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: TRIG_IN3 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: TRIG_IN4 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: TRIG_IN5 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: TRIG_IN6 input is selected. value: 30 - - name: VAL31 + - name: Val31 description: TRIG_IN7 input is selected. value: 31 - - name: VAL32 + - name: Val32 description: GPIO0 Pin Event Trig 0 input is selected. value: 32 - - name: VAL33 + - name: Val33 description: GPIO1 Pin Event Trig 0 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: GPIO2 Pin Event Trig 0 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: GPIO3 Pin Event Trig 0 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: GPIO4 Pin Event Trig 0 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: WUU input is selected. value: 37 - - name: VAL38 + - name: Val38 description: LPI2C0 Master End of Packet. value: 38 - - name: VAL39 + - name: Val39 description: LPI2C0 Slave End of Packet. value: 39 - - name: VAL40 + - name: Val40 description: LPI2C1 Master End of Packet. value: 40 - - name: VAL41 + - name: Val41 description: LPI2C1 Slave End of Packet. value: 41 - - name: VAL42 + - name: Val42 description: LPSPI0 End of Frame. value: 42 - - name: VAL43 + - name: Val43 description: LPSPI0 Received Data Word. value: 43 - - name: VAL44 + - name: Val44 description: LPSPI1 End of Frame. value: 44 - - name: VAL45 + - name: Val45 description: LPSPI1 Received Data Word. value: 45 - - name: VAL46 + - name: Val46 description: LPUART0 Received Data Word. value: 46 - - name: VAL47 + - name: Val47 description: LPUART0 Transmitted Data Word. value: 47 - - name: VAL48 + - name: Val48 description: LPUART0 Receive Line Idle. value: 48 - - name: VAL49 + - name: Val49 description: LPUART1 Received Data Word. value: 49 - - name: VAL50 + - name: Val50 description: LPUART1 Transmitted Data Word. value: 50 - - name: VAL51 + - name: Val51 description: LPUART1 Receive Line Idle. value: 51 - - name: VAL52 + - name: Val52 description: LPUART2 Received Data Word. value: 52 - - name: VAL53 + - name: Val53 description: LPUART2 Transmitted Data Word. value: 53 - - name: VAL54 + - name: Val54 description: LPUART2 Receive Line Idle. value: 54 - - name: VAL55 + - name: Val55 description: LPUART3 Received Data Word. value: 55 - - name: VAL56 + - name: Val56 description: LPUART3 Transmitted Data Word. value: 56 - - name: VAL57 + - name: Val57 description: LPUART3 Receive Line Idle. value: 57 - - name: VAL58 + - name: Val58 description: LPUART4 Received Data Word. value: 58 - - name: VAL59 + - name: Val59 description: LPUART4 Transmitted Data Word. value: 59 - - name: VAL60 + - name: Val60 description: LPUART4 Receive Line Idle. value: 60 - - name: VAL61 - description: AOI1_OUT0 input is selected. - value: 61 - - name: VAL62 - description: AOI1_OUT1 input is selected. - value: 62 - - name: VAL63 - description: AOI1_OUT2 input is selected. - value: 63 - - name: VAL64 - description: AOI1_OUT3 input is selected. - value: 64 - - name: VAL65 + - name: Val65 description: ADC1_tcomp[0] input is selected. value: 65 - - name: VAL66 + - name: Val66 description: ADC1_tcomp[1] input is selected. value: 66 - - name: VAL67 + - name: Val67 description: ADC1_tcomp[2] input is selected. value: 67 - - name: VAL68 + - name: Val68 description: ADC1_tcomp[3] input is selected. value: 68 - - name: VAL69 + - name: Val69 description: CTimer3_MAT2 input is selected. value: 69 - - name: VAL70 + - name: Val70 description: CTimer3_MAT3 input is selected. value: 70 - - name: VAL71 + - name: Val71 description: CTimer4_MAT2 input is selected. value: 71 - - name: VAL72 + - name: Val72 description: CTimer4_MAT3 input is selected. value: 72 - - name: VAL73 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 73 - - name: VAL74 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 74 - - name: VAL75 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 75 - - name: VAL76 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 76 - - name: VAL77 + - name: Val77 description: LPI2C2 Master End of Packet. value: 77 - - name: VAL78 + - name: Val78 description: LPI2C2 Slave End of Packet. value: 78 - - name: VAL79 + - name: Val79 description: LPI2C3 Master End of Packet. value: 79 - - name: VAL80 + - name: Val80 description: LPI2C3 Slave End of Packet. value: 80 + - name: Val81 + description: LPSPI2 End of Frame input is selected. + value: 81 + - name: Val82 + description: LPSPI2 Received Data Word input is selected. + value: 82 + - name: Val83 + description: LPSPI3 End of Frame input is selected. + value: 83 + - name: Val84 + description: LPSPI3 Received Data Word input is selected. + value: 84 + - name: Val85 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 85 + - name: Val86 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 86 + - name: Val87 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 87 + - name: Val88 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 88 + - name: Val89 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 89 enum/FreqmeasRefInp: bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: clk_in input is selected. value: 1 - - name: VAL2 + - name: Val2 description: FRO_OSC_12M input is selected. value: 2 - - name: VAL3 + - name: Val3 description: fro_hf_div input is selected. value: 3 - - name: VAL5 + - name: Val4 + description: OSC32K[1] input is selected. + value: 4 + - name: Val5 description: clk_16k[1] input is selected. value: 5 - - name: VAL6 + - name: Val6 description: SLOW_CLK input is selected. value: 6 - - name: VAL7 + - name: Val7 description: FREQME_CLK_IN0 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: FREQME_CLK_IN1 input is selected input is selected. value: 8 - - name: VAL9 + - name: Val9 description: AOI0_OUT0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: AOI0_OUT1. value: 10 - - name: VAL11 - description: PWM0_SM0_MUX_TRIG0. - value: 11 - - name: VAL12 - description: PWM0_SM0_MUX_TRIG1. - value: 12 - - name: VAL13 - description: PWM0_SM1_MUX_TRIG0. - value: 13 - - name: VAL14 - description: PWM0_SM1_MUX_TRIG1. - value: 14 - - name: VAL15 - description: PWM0_SM2_MUX_TRIG0. - value: 15 - - name: VAL16 - description: PWM0_SM2_MUX_TRIG1. - value: 16 - - name: VAL17 - description: PWM0_SM3_MUX_TRIG0. - value: 17 - - name: VAL18 - description: PWM0_SM3_MUX_TRIG1. - value: 18 - - name: VAL32 - description: AOI1_OUT0 input is selected. - value: 32 - - name: VAL33 - description: AOI1_OUT1 input is selected. - value: 33 - - name: VAL34 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 34 - - name: VAL35 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 35 - - name: VAL36 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 36 - - name: VAL37 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 37 - - name: VAL38 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 38 - - name: VAL39 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 39 - - name: VAL40 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 40 - - name: VAL41 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 41 + - name: Val31 + description: pll1_clk_div input is selected. + value: 31 enum/FreqmeasTarInp: bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: clk_in input is selected. value: 1 - - name: VAL2 + - name: Val2 description: FRO_OSC_12M input is selected. value: 2 - - name: VAL3 + - name: Val3 description: fro_hf_div input is selected. value: 3 - - name: VAL5 + - name: Val4 + description: OSC32K[1] input is selected. + value: 4 + - name: Val5 description: clk_16k[1] input is selected. value: 5 - - name: VAL6 + - name: Val6 description: SLOW_CLK input is selected. value: 6 - - name: VAL7 + - name: Val7 description: FREQME_CLK_IN0 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: FREQME_CLK_IN1 input is selected input is selected. value: 8 - - name: VAL9 + - name: Val9 description: AOI0_OUT0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: AOI0_OUT1. value: 10 - - name: VAL11 - description: PWM0_SM0_MUX_TRIG0. - value: 11 - - name: VAL12 - description: PWM0_SM0_MUX_TRIG1. - value: 12 - - name: VAL13 - description: PWM0_SM1_MUX_TRIG0. - value: 13 - - name: VAL14 - description: PWM0_SM1_MUX_TRIG1. - value: 14 - - name: VAL15 - description: PWM0_SM2_MUX_TRIG0. - value: 15 - - name: VAL16 - description: PWM0_SM2_MUX_TRIG1. - value: 16 - - name: VAL17 - description: PWM0_SM3_MUX_TRIG0. - value: 17 - - name: VAL18 - description: PWM0_SM3_MUX_TRIG1. - value: 18 - - name: VAL32 - description: AOI1_OUT0 input is selected. - value: 32 - - name: VAL33 - description: AOI1_OUT1 input is selected. - value: 33 - - name: VAL34 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 34 - - name: VAL35 - description: PWM1_SM0_MUX_TRIG1 input is selected. - value: 35 - - name: VAL36 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 36 - - name: VAL37 - description: PWM1_SM1_MUX_TRIG1 input is selected. - value: 37 - - name: VAL38 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 38 - - name: VAL39 - description: PWM1_SM2_MUX_TRIG1 input is selected. - value: 39 - - name: VAL40 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 40 - - name: VAL41 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 41 + - name: Val31 + description: pll1_clk_div input is selected. + value: 31 enum/Lpi2cTrigInp: bit_size: 6 variants: - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CMP0_OUT input is selected. value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT1 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT0 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT1 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT0 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer2_MAT1 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: LPTMR0 input is selected. value: 15 - - name: VAL17 + - name: Val17 description: TRIG_IN0 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: TRIG_IN1 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: TRIG_IN2 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: TRIG_IN3 input is selected. value: 20 - - name: VAL21 + - name: Val21 description: TRIG_IN4 input is selected. value: 21 - - name: VAL22 + - name: Val22 description: TRIG_IN5 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: TRIG_IN6 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: TRIG_IN7 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: GPIO0 Pin Event Trig 0 input is selected. value: 25 - - name: VAL26 + - name: Val26 description: GPIO1 Pin Event Trig 0 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: GPIO2 Pin Event Trig 0 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: GPIO3 Pin Event Trig 0 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: GPIO4 Pin Event Trig 0 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: WUU input is selected. value: 30 - - name: VAL31 - description: AOI1_OUT0 input is selected. - value: 31 - - name: VAL32 - description: AOI1_OUT1 input is selected. - value: 32 - - name: VAL33 - description: AOI1_OUT2 input is selected. - value: 33 - - name: VAL34 - description: AOI1_OUT3 input is selected. - value: 34 - - name: VAL35 + - name: Val35 description: CTimer3_MAT2 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer3_MAT3 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer4_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer4_MAT3 input is selected. value: 38 - - name: VAL39 - description: FlexIO CH0 input is selected. + - name: Val39 + description: FlexIO0 CH0 input is selected. value: 39 - - name: VAL40 - description: FlexIO CH1 input is selected. + - name: Val40 + description: FlexIO0 CH1 input is selected. value: 40 - - name: VAL41 - description: FlexIO CH2 input is selected. + - name: Val41 + description: FlexIO0 CH2 input is selected. value: 41 - - name: VAL42 - description: FlexIO CH3 input is selected. + - name: Val42 + description: FlexIO0 CH3 input is selected. value: 42 + - name: Val43 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 43 + - name: Val44 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 44 + - name: Val45 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 45 + - name: Val46 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 46 + - name: Val47 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 47 enum/LpspiTrigInp: bit_size: 6 variants: - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CMP0_OUT input is selected. value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT1 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT2 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT1 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT2 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT1 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer2_MAT2 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: LPTMR0 input is selected. value: 15 - - name: VAL17 + - name: Val17 description: TRIG_IN0 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: TRIG_IN1 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: TRIG_IN2 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: TRIG_IN3 input is selected. value: 20 - - name: VAL21 + - name: Val21 description: TRIG_IN4 input is selected. value: 21 - - name: VAL22 + - name: Val22 description: TRIG_IN5 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: TRIG_IN6 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: TRIG_IN7 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: GPIO0 Pin Event Trig 0 input is selected. value: 25 - - name: VAL26 + - name: Val26 description: GPIO1 Pin Event Trig 0 input is selected. value: 26 - - name: VAL27 + - name: Val27 description: GPIO2 Pin Event Trig 0 input is selected. value: 27 - - name: VAL28 + - name: Val28 description: GPIO3 Pin Event Trig 0 input is selected. value: 28 - - name: VAL29 + - name: Val29 description: GPIO4 Pin Event Trig 0 input is selected. value: 29 - - name: VAL30 + - name: Val30 description: WUU input is selected. value: 30 - - name: VAL31 - description: AOI1_OUT0 input is selected. - value: 31 - - name: VAL32 - description: AOI1_OUT1 input is selected. - value: 32 - - name: VAL33 - description: AOI1_OUT2 input is selected. - value: 33 - - name: VAL34 - description: AOI1_OUT3 input is selected. - value: 34 - - name: VAL35 - description: CTimer3_MAT2 input is selected. + - name: Val35 + description: CTimer3_MAT2 inputs is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer3_MAT3 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer4_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer4_MAT3 input is selected. value: 38 - - name: VAL39 - description: FlexIO CH0 input is selected. + - name: Val39 + description: FlexIO0 CH0 input is selected. value: 39 - - name: VAL40 - description: FlexIO CH1 input is selected. + - name: Val40 + description: FlexIO0 CH1 input is selected. value: 40 - - name: VAL41 - description: FlexIO CH2 input is selected. + - name: Val41 + description: FlexIO0 CH2 input is selected. value: 41 - - name: VAL42 - description: FlexIO CH3 input is selected. + - name: Val42 + description: FlexIO0 CH3 input is selected. value: 42 + - name: Val43 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 43 + - name: Val44 + description: GPIO1 Pin Event Trig 1 input is selected. + value: 44 + - name: Val45 + description: GPIO2 Pin Event Trig 1 input is selected. + value: 45 + - name: Val46 + description: GPIO3 Pin Event Trig 1 input is selected. + value: 46 + - name: Val47 + description: GPIO4 Pin Event Trig 1 input is selected. + value: 47 enum/LpuartInp: bit_size: 6 variants: - - name: VAL2 + - name: Val2 description: AOI0_OUT0 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: AOI0_OUT1 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: AOI0_OUT2 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: AOI0_OUT3 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CMP0_OUT input is selected. value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 + - name: Val9 description: CTimer0_MAT2 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CTimer0_MAT3 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CTimer1_MAT2 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: CTimer1_MAT3 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: CTimer2_MAT2 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CTimer2_MAT3 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: LPTMR0 input is selected. value: 15 - - name: VAL17 + - name: Val17 description: TRIG_IN0 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: TRIG_IN1 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: TRIG_IN2 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: TRIG_IN3 input is selected. value: 20 - - name: VAL21 + - name: Val21 description: TRIG_IN4 input is selected. value: 21 - - name: VAL22 + - name: Val22 description: TRIG_IN5 input is selected. value: 22 - - name: VAL23 - description: TRIG_IN6 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN7 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN8 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN9 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN10 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN11 input is selected. - value: 28 - - name: VAL29 - description: GPIO0 Pin Event Trig 0 input is selected. - value: 29 - - name: VAL30 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 30 - - name: VAL31 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 31 - - name: VAL32 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 32 - - name: VAL33 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 33 - - name: VAL34 - description: WUU selected. - value: 34 - - name: VAL35 - description: USB0 ipp_ind_uart_rxd_usbmux input is selected. - value: 35 - - name: VAL36 - description: AOI1_OUT0 input is selected. - value: 36 - - name: VAL37 - description: AOI1_OUT1 input is selected. - value: 37 - - name: VAL38 - description: AOI1_OUT2 input is selected. - value: 38 - - name: VAL39 - description: AOI1_OUT3 input is selected. - value: 39 - - name: VAL40 - description: CTimer3_MAT2 input is selected. - value: 40 - - name: VAL41 - description: CTimer3_MAT3 input is selected. - value: 41 - - name: VAL42 - description: CTimer4_MAT2 input is selected. - value: 42 - - name: VAL43 - description: CTimer4_MAT3 input is selected. - value: 43 - - name: VAL44 - description: FlexIO CH0 input is selected. - value: 44 - - name: VAL45 - description: FlexIO CH1 input is selected. - value: 45 - - name: VAL46 - description: FlexIO CH2 input is selected. - value: 46 - - name: VAL47 - description: FlexIO CH3 input is selected. - value: 47 -enum/Pwm0ExtClkTrigin: - bit_size: 4 - variants: - - name: VAL1 - description: clk_16k[1] input is selected. - value: 1 - - name: VAL2 - description: clk_in input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT0 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT1 input is selected. - value: 4 - - name: VAL5 - description: EXTTRIG_IN0 input is selected. - value: 5 - - name: VAL6 - description: EXTTRIG_IN7 input is selected. - value: 6 - - name: VAL7 - description: AOI1_OUT0 input is selected. - value: 7 - - name: VAL8 - description: AOI1_OUT1 input is selected. - value: 8 -enum/Pwm1ExtClkTrigin: - bit_size: 4 - variants: - - name: VAL1 - description: clk_16k[1] input is selected. - value: 1 - - name: VAL2 - description: clk_in input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT0 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT1 input is selected. - value: 4 - - name: VAL5 - description: EXTTRIG_IN0 input is selected. - value: 5 - - name: VAL6 - description: EXTTRIG_IN7 input is selected. - value: 6 - - name: VAL7 - description: AOI1_OUT0 input is selected. - value: 7 - - name: VAL8 - description: AOI1_OUT1 input is selected. - value: 8 -enum/Qdc0PhaseaInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/Qdc0PhasebInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/Qdc1PhaseaInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/Qdc1PhasebInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 inout is selected. - value: 69 -enum/QdcHomeInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/QdcIcapInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/QdcIndexInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 - description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 - description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 - description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 - description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 - description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 - description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 - description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 - description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 - description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 - description: GPIO4 Pin Event Trig 0 input is selected. - value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. - value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. - value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. - value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. - value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. - value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. - value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. - value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. - value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 -enum/QdcTrigInp: - bit_size: 7 - variants: - - name: VAL1 - description: ARM_TXEV input is selected. - value: 1 - - name: VAL2 - description: AOI0_OUT0 input is selected. - value: 2 - - name: VAL3 - description: AOI0_OUT1 input is selected. - value: 3 - - name: VAL4 - description: AOI0_OUT2 input is selected. - value: 4 - - name: VAL5 - description: AOI0_OUT3 input is selected. - value: 5 - - name: VAL6 - description: CMP0_OUT input is selected. - value: 6 - - name: VAL7 - description: CMP1_OUT input is selected. - value: 7 - - name: VAL8 - description: CMP2_OUT input is selected. - value: 8 - - name: VAL9 - description: CTimer0_MAT2 input is selected. - value: 9 - - name: VAL10 - description: CTimer0_MAT3. - value: 10 - - name: VAL11 - description: CTimer1_MAT2 input is selected. - value: 11 - - name: VAL12 - description: CTimer1_MAT3 input is selected. - value: 12 - - name: VAL13 - description: CTimer2_MAT2 input is selected. - value: 13 - - name: VAL14 - description: CTimer2_MAT3 input is selected. - value: 14 - - name: VAL16 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 16 - - name: VAL17 - description: PWM0_SM0_MUX_TRIG1 input is selected. - value: 17 - - name: VAL18 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 18 - - name: VAL19 - description: PWM0_SM1_MUX_TRIG1 input is selected. - value: 19 - - name: VAL20 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 20 - - name: VAL21 - description: PWM0_SM2_MUX_TRIG1 input is selected. - value: 21 - - name: VAL22 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 22 - - name: VAL23 - description: PWM0_SM3_MUX_TRIG1 input is selected. - value: 23 - - name: VAL24 - description: TRIG_IN0 input is selected. - value: 24 - - name: VAL25 - description: TRIG_IN1 input is selected. - value: 25 - - name: VAL26 - description: TRIG_IN2 input is selected. - value: 26 - - name: VAL27 - description: TRIG_IN3 input is selected. - value: 27 - - name: VAL28 - description: TRIG_IN4 input is selected. - value: 28 - - name: VAL29 - description: TRIG_IN5 input is selected. - value: 29 - - name: VAL30 + - name: Val23 description: TRIG_IN6 input is selected. - value: 30 - - name: VAL31 + value: 23 + - name: Val24 description: TRIG_IN7 input is selected. - value: 31 - - name: VAL32 + value: 24 + - name: Val25 description: TRIG_IN8 input is selected. - value: 32 - - name: VAL33 + value: 25 + - name: Val26 description: TRIG_IN9 input is selected. - value: 33 - - name: VAL34 + value: 26 + - name: Val27 description: TRIG_IN10 input is selected. - value: 34 - - name: VAL35 + value: 27 + - name: Val28 description: TRIG_IN11 input is selected. - value: 35 - - name: VAL36 - description: GPIO0 Pin Event Trig 0 is selected. - value: 36 - - name: VAL37 + value: 28 + - name: Val29 + description: GPIO0 Pin Event Trig 0 input is selected. + value: 29 + - name: Val30 description: GPIO1 Pin Event Trig 0 input is selected. - value: 37 - - name: VAL38 + value: 30 + - name: Val31 description: GPIO2 Pin Event Trig 0 input is selected. - value: 38 - - name: VAL39 + value: 31 + - name: Val32 description: GPIO3 Pin Event Trig 0 input is selected. - value: 39 - - name: VAL40 + value: 32 + - name: Val33 description: GPIO4 Pin Event Trig 0 input is selected. + value: 33 + - name: Val34 + description: WUU selected. + value: 34 + - name: Val40 + description: CTimer3_MAT2 input is selected. value: 40 - - name: VAL41 - description: AOI1_OUT0 input is selected. + - name: Val41 + description: CTimer3_MAT3 input is selected. value: 41 - - name: VAL42 - description: AOI1_OUT1 input is selected. + - name: Val42 + description: CTimer4_MAT2 input is selected. value: 42 - - name: VAL43 - description: AOI1_OUT2 input is selected. + - name: Val43 + description: CTimer4_MAT3 input is selected. value: 43 - - name: VAL44 - description: AOI1_OUT3 input is selected. + - name: Val44 + description: FlexIO0 CH0 input is selected. value: 44 - - name: VAL49 - description: CTimer3_MAT2 input is selected. + - name: Val45 + description: FlexIO0 CH1 input is selected. + value: 45 + - name: Val46 + description: FlexIO0 CH2 input is selected. + value: 46 + - name: Val47 + description: FlexIO0 CH3 input is selected. + value: 47 + - name: Val48 + description: GPIO0 Pin Event Trig 1 input is selected. + value: 48 + - name: Val49 + description: GPIO1 Pin Event Trig 1 input is selected. value: 49 - - name: VAL50 - description: CTimer3_MAT3 input is selected. + - name: Val50 + description: GPIO2 Pin Event Trig 1 input is selected. value: 50 - - name: VAL51 - description: CTimer4_MAT2 input is selected. + - name: Val51 + description: GPIO3 Pin Event Trig 1 input is selected. value: 51 - - name: VAL52 - description: CTimer4_MAT3 input is selected. + - name: Val52 + description: GPIO4 Pin Event Trig 1 input is selected. value: 52 - - name: VAL62 - description: PWM1_SM0_OUT_TRIG0 input is selected. - value: 62 - - name: VAL63 - description: PWM1_SM0_OUT_TRIG1 input is selected. - value: 63 - - name: VAL64 - description: PWM1_SM1_OUT_TRIG0 input is selected. - value: 64 - - name: VAL65 - description: PWM1_SM1_OUT_TRIG1 input is selected. - value: 65 - - name: VAL66 - description: PWM1_SM2_OUT_TRIG0 input is selected. - value: 66 - - name: VAL67 - description: PWM1_SM2_OUT_TRIG1 input is selected. - value: 67 - - name: VAL68 - description: PWM1_SM3_MUX_TRIG0 input is selected. - value: 68 - - name: VAL69 - description: PWM1_SM3_MUX_TRIG1 input is selected. - value: 69 enum/SmartDmaTrigInp: bit_size: 7 variants: - - name: VAL1 + - name: Val1 description: GPIO P0_16 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: GPIO P0_17 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: GPIO P1_8 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: GPIO P1_9 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: GPIO P1_10 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: GPIO P1_11 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: GPIO P1_12 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: GPIO P1_13 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: GPIO P2_0 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: GPIO P2_1 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: GPIO P2_2 input is selected. value: 11 - - name: VAL12 + - name: Val12 description: GPIO P2_3 input is selected. value: 12 - - name: VAL13 + - name: Val13 description: GPIO P2_6 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: GPIO P3_8 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: GPIO P3_9 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: GPIO P3_10 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: GPIO P3_11 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: GPIO P3_12 input is seclected. value: 18 - - name: VAL19 + - name: Val19 description: GPIO0 Pin Event Trig input is selected. value: 19 - - name: VAL20 + - name: Val20 description: GPIO1 Pin Event Trig input is selected. value: 20 - - name: VAL21 + - name: Val21 description: GPIO2 Pin Event Trig input is selected. value: 21 - - name: VAL22 + - name: Val22 description: GPIO3 Pin Event Trig input is selected. value: 22 - - name: VAL23 + - name: Val23 description: GPIO4 Pin Event Trig input is selected. value: 23 - - name: VAL24 + - name: Val24 description: ARM_TXEV input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT0 input is selected. value: 25 - - name: VAL26 - description: AOI1_OUT1 input is selected. - value: 26 - - name: VAL27 + - name: Val27 description: DMA_IRQ input is selected. value: 27 - - name: VAL28 - description: MAU_IRQ input is selected. - value: 28 - - name: VAL29 + - name: Val29 description: WUU_IRQ input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CTimer0_MAT2 input is selected. value: 30 - - name: VAL31 + - name: Val31 description: CTimer0_MAT3 input is selected. value: 31 - - name: VAL32 + - name: Val32 description: CTimer1_MAT2 input is selected. value: 32 - - name: VAL33 + - name: Val33 description: CTimer1_MAT3 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer2_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer2_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer3_MAT2 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer3_MAT3 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer4_MAT2 input is selected. value: 38 - - name: VAL39 + - name: Val39 description: CTimer4_MAT3 input is selected. value: 39 - - name: VAL40 + - name: Val40 description: OSTIMER_IRQ input is selected. value: 40 - - name: VAL41 - description: PWM0_IRQ input is selected. - value: 41 - - name: VAL42 - description: PWM1_IRQ input is selected. - value: 42 - - name: VAL43 - description: QDC0_IRQ input is selected. - value: 43 - - name: VAL44 - description: QDC1_IRQ input is selected. - value: 44 - - name: VAL45 + - name: Val45 description: RTC_Alarm_IRQ input is selected. value: 45 - - name: VAL46 + - name: Val46 description: RTC_1Hz_IRQ input is selected. value: 46 - - name: VAL47 + - name: Val47 description: uTICK_IRQ input is selected. value: 47 - - name: VAL48 + - name: Val48 description: WDT_IRQ input is selected. value: 48 - - name: VAL49 + - name: Val49 description: Wakeup_Timer_IRQ input is selected. value: 49 - - name: VAL50 + - name: Val50 description: CAN0_IRQ input is selected. value: 50 - - name: VAL51 + - name: Val51 description: CAN1_IRQ input is selected. value: 51 - - name: VAL52 - description: FlexIO_IRQ input is selected. + - name: Val52 + description: FlexIO0_IRQ input is selected. value: 52 - - name: VAL53 - description: FlexIO_Shifer0_DMA_Req input is selected. + - name: Val53 + description: FlexIO0_Shifer0_DMA_Req input is selected. value: 53 - - name: VAL54 - description: FlexIO_Shifer1_DMA_Req input is selected. + - name: Val54 + description: FlexIO0_Shifer1_DMA_Req input is selected. value: 54 - - name: VAL55 - description: FlexIO_Shifer2_DMA_Req input is selected. + - name: Val55 + description: FlexIO0_Shifer2_DMA_Req input is selected. value: 55 - - name: VAL56 - description: FlexIO_Shifer3_DMA_Req input is selected. + - name: Val56 + description: FlexIO0_Shifer3_DMA_Req input is selected. value: 56 - - name: VAL57 + - name: Val57 description: I3C0_IRQ input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPI2C0_IRQ input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPI2C1_IRQ input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPSPI0_IRQ input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPSPI1_IRQ input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART0_IRQ input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART1_IRQ input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2_IRQ input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3_IRQ input is selected. value: 65 - - name: VAL66 - description: USB0_SOF input is selected. - value: 66 - - name: VAL68 + - name: Val67 + description: USB1 Start of Frame input is selected. + value: 67 + - name: Val68 description: ADC0_IRQ input is selected. value: 68 - - name: VAL69 + - name: Val69 description: ADC1_IRQ input is selected. value: 69 - - name: VAL70 - description: ADC2_IRQ input is selected. - value: 70 - - name: VAL71 - description: ADC3_IRQ input is selected. - value: 71 - - name: VAL72 + - name: Val72 description: CMP0_IRQ input is selected. value: 72 - - name: VAL73 - description: CMP1_IRQ input is selected. - value: 73 - - name: VAL74 - description: CMP2_IRQ input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: CMP0_OUT input is selected. value: 75 - - name: VAL76 - description: CMP1_OUT input is selected. - value: 76 - - name: VAL77 - description: CMP2_OUT input is selected. - value: 77 - - name: VAL78 + - name: Val78 description: DAC0_IRQ input is selected. value: 78 - - name: VAL79 - description: SLCD_IRQ input is selected. - value: 79 + - name: Val80 + description: DMA1_IRQ input is selected. + value: 80 + - name: Val81 + description: DAC1_IRQ input is selected. + value: 81 + - name: Val82 + description: TSI0_End_of_Scan_IRQ input is selected. + value: 82 + - name: Val83 + description: TSI0_Out_of_Range_IRQ input is selected. + value: 83 + - name: Val84 + description: ENET QOS IRQ input is selected. + value: 84 + - name: Val85 + description: 10BASE_T1S IRQ input is selected. + value: 85 + - name: Val86 + description: ERM Interrupt input is selected. + value: 86 + - name: Val87 + description: TMPR_OUT0 input is selected. + value: 87 + - name: Val88 + description: TMPR_OUT1 input is selected. + value: 88 enum/Timer0trigInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CMP0_OUT is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer1_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer1_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer1_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer2_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer2_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer2_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer3_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer3_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Timer1trigInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 - description: CMP0_OUT is selected. + - name: Val30 + description: CMP0_OUT input is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer2_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer2_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer2_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 - description: CTimer3_MAT1 input is selected. + - name: Val79 + description: CTimer3_MAT1 is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer3_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 - description: LPI2C2 Master End of Packet input is selected. + - name: Val94 + description: LPI2C2 Master End of Packet is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Timer2trigInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 + - name: Val26 description: ADC0_tcomp[0]. value: 26 - - name: VAL27 + - name: Val27 description: ADC0_tcomp[1]. value: 27 - - name: VAL28 + - name: Val28 description: ADC0_tcomp[2]. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 + - name: Val30 description: CMP0_OUT is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer3_MAT1 input is selected. value: 79 - - name: VAL80 - description: CTimer3_MAT2 input is selected. + - name: Val80 + description: CTimer3_MAT2 is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer3_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 + - name: Val113 + description: TRIG_IN0 input is selected. + value: 113 + - name: Val114 + description: TRIG_IN1 input is selected. + value: 114 + - name: Val115 + description: TRIG_IN2 input is selected. + value: 115 + - name: Val116 + description: TRIG_IN3 input is selected. + value: 116 + - name: Val117 + description: TRIG_IN4 input is selected. + value: 117 + - name: Val118 + description: TRIG_IN5 input is selected. + value: 118 + - name: Val119 + description: TRIG_IN6 input is selected. + value: 119 + - name: Val120 + description: TRIG_IN7 input is selected. + value: 120 + - name: Val121 + description: TRIG_IN8 input is selected. + value: 121 + - name: Val122 + description: TRIG_IN9 input is selected. + value: 122 + - name: Val123 + description: TRIG_IN10 input is selected. + value: 123 + - name: Val124 + description: TRIG_IN11 input is selected. + value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Timer3trigInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 - description: CMP0_OUT is selected. + - name: Val30 + description: CMP0_OUT input is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 - description: LPUART4 Transmitted Data Word input is selected. + - name: Val69 + description: LPUART4 Transmitted Data Word is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer2_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer2_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer2_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer4_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer4_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer4_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 - - name: VAL113 + - name: Val102 + description: TMPR_OUT0 input is selected. + value: 102 + - name: Val103 + description: TMPR_OUT1 input is selected. + value: 103 + - name: Val113 description: TRIG_IN0 input is selected. value: 113 - - name: VAL114 + - name: Val114 description: TRIG_IN1 input is selected. value: 114 - - name: VAL115 + - name: Val115 description: TRIG_IN2 input is selected. value: 115 - - name: VAL116 + - name: Val116 description: TRIG_IN3 input is selected. value: 116 - - name: VAL117 + - name: Val117 description: TRIG_IN4 input is selected. value: 117 - - name: VAL118 + - name: Val118 description: TRIG_IN5 input is selected. value: 118 - - name: VAL119 + - name: Val119 description: TRIG_IN6 input is selected. value: 119 - - name: VAL120 + - name: Val120 description: TRIG_IN7 input is selected. value: 120 - - name: VAL121 + - name: Val121 description: TRIG_IN8 input is selected. value: 121 - - name: VAL122 + - name: Val122 description: TRIG_IN9 input is selected. value: 122 - - name: VAL123 + - name: Val123 description: TRIG_IN10 input is selected. value: 123 - - name: VAL124 + - name: Val124 description: TRIG_IN11 input is selected. value: 124 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 enum/Timer4trigInp: - bit_size: 7 + bit_size: 8 variants: - - name: VAL1 + - name: Val1 description: CT_INP0 input is selected. value: 1 - - name: VAL2 + - name: Val2 description: CT_INP1 input is selected. value: 2 - - name: VAL3 + - name: Val3 description: CT_INP2 input is selected. value: 3 - - name: VAL4 + - name: Val4 description: CT_INP3 input is selected. value: 4 - - name: VAL5 + - name: Val5 description: CT_INP4 input is selected. value: 5 - - name: VAL6 + - name: Val6 description: CT_INP5 input is selected. value: 6 - - name: VAL7 + - name: Val7 description: CT_INP6 input is selected. value: 7 - - name: VAL8 + - name: Val8 description: CT_INP7 input is selected. value: 8 - - name: VAL9 + - name: Val9 description: CT_INP8 input is selected. value: 9 - - name: VAL10 + - name: Val10 description: CT_INP9 input is selected. value: 10 - - name: VAL11 + - name: Val11 description: CT_INP10 input is selected. value: 11 - - name: VAL12 - description: CT_INP11 input is selected. - value: 12 - - name: VAL13 + - name: Val13 description: CT_INP12 input is selected. value: 13 - - name: VAL14 + - name: Val14 description: CT_INP13 input is selected. value: 14 - - name: VAL15 + - name: Val15 description: CT_INP14 input is selected. value: 15 - - name: VAL16 + - name: Val16 description: CT_INP15 input is selected. value: 16 - - name: VAL17 + - name: Val17 description: CT_INP16 input is selected. value: 17 - - name: VAL18 + - name: Val18 description: CT_INP17 input is selected. value: 18 - - name: VAL19 + - name: Val19 description: CT_INP18 input is selected. value: 19 - - name: VAL20 + - name: Val20 description: CT_INP19 input is selected. value: 20 - - name: VAL21 - description: USB0 usb0 start of frame input is selected. - value: 21 - - name: VAL22 + - name: Val22 description: AOI0_OUT0 input is selected. value: 22 - - name: VAL23 + - name: Val23 description: AOI0_OUT1 input is selected. value: 23 - - name: VAL24 + - name: Val24 description: AOI0_OUT2 input is selected. value: 24 - - name: VAL25 + - name: Val25 description: AOI0_OUT3 input is selected. value: 25 - - name: VAL26 - description: ADC0_tcomp[0]. + - name: Val26 + description: ADC0_tcomp[0] input is selected. value: 26 - - name: VAL27 - description: ADC0_tcomp[1]. + - name: Val27 + description: ADC0_tcomp[1] input is selected. value: 27 - - name: VAL28 - description: ADC0_tcomp[2]. + - name: Val28 + description: ADC0_tcomp[2] input is selected. value: 28 - - name: VAL29 + - name: Val29 description: ADC0_tcomp[3] input is selected. value: 29 - - name: VAL30 - description: CMP0_OUT is selected. + - name: Val30 + description: CMP0_OUT input is selected. value: 30 - - name: VAL31 - description: CMP1_OUT is selected. - value: 31 - - name: VAL32 - description: CMP2_OUT is selected. - value: 32 - - name: VAL33 + - name: Val33 description: CTimer0_MAT1 input is selected. value: 33 - - name: VAL34 + - name: Val34 description: CTimer0_MAT2 input is selected. value: 34 - - name: VAL35 + - name: Val35 description: CTimer0_MAT3 input is selected. value: 35 - - name: VAL36 + - name: Val36 description: CTimer1_MAT1 input is selected. value: 36 - - name: VAL37 + - name: Val37 description: CTimer1_MAT2 input is selected. value: 37 - - name: VAL38 + - name: Val38 description: CTimer1_MAT3 input is selected. value: 38 - - name: VAL39 - description: QDC0_CMP_FLAG0 is selected. - value: 39 - - name: VAL40 - description: QDC0_CMP_FLAG1 input is selected. - value: 40 - - name: VAL41 - description: QDC0_CMP_FLAG2 input is selected. - value: 41 - - name: VAL42 - description: QDC0_CMP_FLAG3 input is selected. - value: 42 - - name: VAL43 - description: QDC0_POS_MATCH0 input is selected. - value: 43 - - name: VAL44 - description: PWM0_SM0_MUX_TRIG0 input is selected. - value: 44 - - name: VAL45 - description: PWM0_SM1_MUX_TRIG0 input is selected. - value: 45 - - name: VAL46 - description: PWM0_SM2_MUX_TRIG0 input is selected. - value: 46 - - name: VAL47 - description: PWM0_SM3_MUX_TRIG0 input is selected. - value: 47 - - name: VAL48 + - name: Val48 description: LPI2C0 Master End of Packet input is selected. value: 48 - - name: VAL49 + - name: Val49 description: LPI2C0 Slave End of Packet input is selected. value: 49 - - name: VAL50 + - name: Val50 description: LPI2C1 Master End of Packet input is selected. value: 50 - - name: VAL51 + - name: Val51 description: LPI2C1 Slave End of Packet input is selected. value: 51 - - name: VAL52 + - name: Val52 description: LPSPI0 End of Frame input is selected. value: 52 - - name: VAL53 + - name: Val53 description: LPSPI0 Received Data Word input is selected. value: 53 - - name: VAL54 + - name: Val54 description: LPSPI1 End of Frame input is selected. value: 54 - - name: VAL55 + - name: Val55 description: LPSPI1 Received Data Word input is selected. value: 55 - - name: VAL56 + - name: Val56 description: LPUART0 Received Data Word input is selected. value: 56 - - name: VAL57 + - name: Val57 description: LPUART0 Transmitted Data Word input is selected. value: 57 - - name: VAL58 + - name: Val58 description: LPUART0 Receive Line Idle input is selected. value: 58 - - name: VAL59 + - name: Val59 description: LPUART1 Received Data Word input is selected. value: 59 - - name: VAL60 + - name: Val60 description: LPUART1 Transmitted Data Word input is selected. value: 60 - - name: VAL61 + - name: Val61 description: LPUART1 Receive Line Idle input is selected. value: 61 - - name: VAL62 + - name: Val62 description: LPUART2 Received Data Word input is selected. value: 62 - - name: VAL63 + - name: Val63 description: LPUART2 Transmitted Data Word input is selected. value: 63 - - name: VAL64 + - name: Val64 description: LPUART2 Receive Line Idle input is selected. value: 64 - - name: VAL65 + - name: Val65 description: LPUART3 Received Data Word input is selected. value: 65 - - name: VAL66 + - name: Val66 description: LPUART3 Transmitted Data Word input is selected. value: 66 - - name: VAL67 + - name: Val67 description: LPUART3 Receive Line Idle input is selected. value: 67 - - name: VAL68 + - name: Val68 description: LPUART4 Received Data Word input is selected. value: 68 - - name: VAL69 + - name: Val69 description: LPUART4 Transmitted Data Word input is selected. value: 69 - - name: VAL70 + - name: Val70 description: LPUART4 Receive Line Idle input is selected. value: 70 - - name: VAL71 - description: AOI1_OUT0 input is selected. - value: 71 - - name: VAL72 - description: AOI1_OUT1 input is selected. - value: 72 - - name: VAL73 - description: AOI1_OUT2 input is selected. - value: 73 - - name: VAL74 - description: AOI1_OUT3 input is selected. - value: 74 - - name: VAL75 + - name: Val75 description: ADC1_tcomp[0] input is selected. value: 75 - - name: VAL76 + - name: Val76 description: ADC1_tcomp[1] input is selected. value: 76 - - name: VAL77 + - name: Val77 description: ADC1_tcomp[2] input is selected. value: 77 - - name: VAL78 + - name: Val78 description: ADC1_tcomp[3] input is selected. value: 78 - - name: VAL79 + - name: Val79 description: CTimer2_MAT1 input is selected. value: 79 - - name: VAL80 + - name: Val80 description: CTimer2_MAT2 input is selected. value: 80 - - name: VAL81 + - name: Val81 description: CTimer2_MAT3 input is selected. value: 81 - - name: VAL82 + - name: Val82 description: CTimer3_MAT1 input is selected. value: 82 - - name: VAL83 + - name: Val83 description: CTimer3_MAT2 input is selected. value: 83 - - name: VAL84 + - name: Val84 description: CTimer3_MAT3 input is selected. value: 84 - - name: VAL85 - description: QDC1_CMP_FLAG0 input is selected. - value: 85 - - name: VAL86 - description: QDC1_CMP_FLAG1 input is selected. - value: 86 - - name: VAL87 - description: QDC1_CMP_FLAG2 input is selected. - value: 87 - - name: VAL88 - description: QDC1_CMP_FLAG3 input is selected. - value: 88 - - name: VAL89 - description: QDC1_POS_MATCH0 input is selected. - value: 89 - - name: VAL90 - description: PWM1_SM0_MUX_TRIG0 input is selected. - value: 90 - - name: VAL91 - description: PWM1_SM1_MUX_TRIG0 input is selected. - value: 91 - - name: VAL92 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 92 - - name: VAL93 - description: PWM1_SM2_MUX_TRIG0 input is selected. - value: 93 - - name: VAL94 + - name: Val94 description: LPI2C2 Master End of Packet input is selected. value: 94 - - name: VAL95 + - name: Val95 description: LPI2C2 Slave End of Packet input is selected. value: 95 - - name: VAL96 + - name: Val96 description: LPI2C3 Master End of Packet input is selected. value: 96 - - name: VAL97 + - name: Val97 description: LPI2C3 Slave End of Packet input is selected. value: 97 - - name: VAL98 + - name: Val98 description: LPUART5 Received Data Word input is selected. value: 98 - - name: VAL99 + - name: Val99 description: LPUART5 Transmitted Data Word input is selected. value: 99 - - name: VAL100 + - name: Val100 description: LPUART5 Receive Line Idle input is selected. value: 100 - - name: VAL105 - description: ADC2_tcomp[0] input is selected. - value: 105 - - name: VAL106 - description: ADC2_tcomp[1] input is selected. - value: 106 - - name: VAL107 - description: ADC2_tcomp[2] input is selected. - value: 107 - - name: VAL108 - description: ADC2_tcomp[3] input is selected. - value: 108 - - name: VAL109 - description: ADC3_tcomp[0] input is selected. - value: 109 - - name: VAL110 - description: ADC3_tcomp[1] input is selected. - value: 110 - - name: VAL111 - description: ADC3_tcomp[2] input is selected. - value: 111 - - name: VAL112 - description: ADC3_tcomp[3] input is selected. - value: 112 - - name: VAL113 + - name: Val102 + description: TMPR_OUT0 input is selected. + value: 102 + - name: Val103 + description: TMPR_OUT1 input is selected. + value: 103 + - name: Val113 description: TRIG_IN0 input is selected. value: 113 - - name: VAL114 + - name: Val114 description: TRIG_IN1 input is selected. value: 114 - - name: VAL115 + - name: Val115 description: TRIG_IN2 input is selected. value: 115 - - name: VAL116 + - name: Val116 description: TRIG_IN3 input is selected. value: 116 - - name: VAL117 - description: TRIG_IN4 input is selected. + - name: Val117 + description: TRIG_IN4 is selected. value: 117 - - name: VAL118 - description: TRIG_IN5 input is selected. + - name: Val118 + description: TRIG_IN5 is selected. value: 118 - - name: VAL119 + - name: Val119 description: TRIG_IN6 input is selected. value: 119 - - name: VAL120 + - name: Val120 description: TRIG_IN7 input is selected. value: 120 - - name: VAL121 + - name: Val121 description: TRIG_IN8 input is selected. value: 121 - - name: VAL122 + - name: Val122 description: TRIG_IN9 input is selected. value: 122 - - name: VAL123 + - name: Val123 description: TRIG_IN10 input is selected. value: 123 - - name: VAL124 + - name: Val124 description: TRIG_IN11 input is selected. value: 124 -enum/TrigInVal: - bit_size: 1 + - name: Val125 + description: USB1 Start of Frame input is selected. + value: 125 + - name: Val126 + description: LPSPI2 End of Frame input is selected. + value: 126 + - name: Val127 + description: LPSPI2 Received Data Word input is selected. + value: 127 + - name: Val128 + description: LPSPI3 End of Frame input is selected. + value: 128 + - name: Val129 + description: LPSPI3 Received Data Word input is selected. + value: 129 + - name: Val130 + description: LPSPI4 End of Frame input is selected. + value: 130 + - name: Val131 + description: LPSPI4 Received Data Word input is selected. + value: 131 + - name: Val132 + description: LPSPI5 End of Frame input is selected. + value: 132 + - name: Val133 + description: LPSPI5 Received Data Word input is selected. + value: 133 +enum/TrigOutInp: + bit_size: 7 variants: - - name: VAL0 - description: TRIG_IN0 is 0. - value: 0 - - name: VAL1 - description: TRIG_IN0 is 1. - value: 1 -enum/UsbfsTrigInp: - bit_size: 4 + - name: Val2 + description: AOI0_OUT0 input is selected. + value: 2 + - name: Val3 + description: AOI0_OUT1 input is selected. + value: 3 + - name: Val4 + description: AOI0_OUT2 input is selected. + value: 4 + - name: Val5 + description: AOI0_OUT3 input is selected. + value: 5 + - name: Val6 + description: CMP0_OUT input is selected. + value: 6 + - name: Val9 + description: LPUART0 ipp_do_lpuart_txd input is selected. + value: 9 + - name: Val10 + description: LPUART1 ipp_do_lpuart_txd input is selected. + value: 10 + - name: Val11 + description: LPUART2 ipp_do_lpuart_txd input is selected. + value: 11 + - name: Val12 + description: LPUART3 ipp_do_lpuart_txd input is selected. + value: 12 + - name: Val13 + description: LPUART4 ipp_do_lpuart_txd input is selected. + value: 13 + - name: Val16 + description: ARM_TXEV input is selected. + value: 16 + - name: Val18 + description: LPUART5 ipp_do_lpuart_txd input is selected. + value: 18 + - name: Val19 + description: RTC_1Hz_CLK input is selected. + value: 19 + - name: Val21 + description: USB1 Start of Frame input is selected. + value: 21 + - name: Val22 + description: PWM0_SM2_MUX_TRIG0 input is selected. + value: 22 + - name: Val23 + description: PWM0_SM3_MUX_TRIG0 input is selected. + value: 23 + - name: Val24 + description: TRIG_IN0 input is selected. + value: 24 + - name: Val25 + description: TRIG_IN1 input is selected. + value: 25 + - name: Val26 + description: TRIG_IN2 input is selected. + value: 26 + - name: Val27 + description: TRIG_IN3 input is selected. + value: 27 + - name: Val28 + description: TRIG_IN4 input is selected. + value: 28 + - name: Val29 + description: TRIG_IN5 input is selected. + value: 29 + - name: Val30 + description: TRIG_IN6 input is selected. + value: 30 + - name: Val31 + description: TRIG_IN7 input is selected. + value: 31 + - name: Val32 + description: GPIO0 Pin Event Trig 0 input is selected. + value: 32 + - name: Val33 + description: GPIO2 Pin Event Trig 0 input is selected. + value: 33 + - name: Val34 + description: GPIO3 Pin Event Trig 0 input is selected. + value: 34 + - name: Val35 + description: GPIO4 Pin Event Trig 0 input is selected. + value: 35 + - name: Val36 + description: WUU input is selected. + value: 36 + - name: Val37 + description: PWM1_A0_TRIG0 input is selected. + value: 37 + - name: Val38 + description: LPI2C0 Master End of Packet. + value: 38 + - name: Val39 + description: LPI2C0 Slave End of Packet. + value: 39 + - name: Val40 + description: LPI2C1 Master End of Packet. + value: 40 + - name: Val41 + description: LPI2C1 Slave End of Packet. + value: 41 + - name: Val42 + description: LPSPI0 End of Frame. + value: 42 + - name: Val43 + description: LPSPI0 Received Data Word. + value: 43 + - name: Val44 + description: LPSPI1 End of Frame. + value: 44 + - name: Val45 + description: LPSPI1 Received Data Word. + value: 45 + - name: Val46 + description: LPUART0 Received Data Word. + value: 46 + - name: Val47 + description: LPUART0 Transmitted Data Word. + value: 47 + - name: Val48 + description: LPUART0 Receive Line Idle. + value: 48 + - name: Val49 + description: LPUART1 Received Data Word. + value: 49 + - name: Val50 + description: LPUART1 Transmitted Data Word. + value: 50 + - name: Val51 + description: LPUART1 Receive Line Idle. + value: 51 + - name: Val52 + description: LPUART2 Received Data Word. + value: 52 + - name: Val53 + description: LPUART2 Transmitted Data Word. + value: 53 + - name: Val54 + description: LPUART2 Receive Line Idle. + value: 54 + - name: Val55 + description: LPUART3 Received Data Word. + value: 55 + - name: Val56 + description: LPUART3 Transmitted Data Word. + value: 56 + - name: Val57 + description: LPUART3 Receive Line Idle. + value: 57 + - name: Val58 + description: LPUART4 Received Data Word. + value: 58 + - name: Val59 + description: LPUART4 Transmitted Data Word. + value: 59 + - name: Val60 + description: LPUART4 Receive Line Idle. + value: 60 + - name: Val61 + description: AOI1_OUT0 input is selected. + value: 61 + - name: Val62 + description: AOI1_OUT1 input is selected. + value: 62 + - name: Val63 + description: AOI1_OUT2 input is selected. + value: 63 + - name: Val64 + description: AOI1_OUT3 input is selected. + value: 64 + - name: Val65 + description: ADC1_tcomp[0] input is selected. + value: 65 + - name: Val66 + description: ADC1_tcomp[1] input is selected. + value: 66 + - name: Val67 + description: ADC1_tcomp[2] input is selected. + value: 67 + - name: Val68 + description: ADC1_tcomp[3] input is selected. + value: 68 + - name: Val69 + description: CTimer3_MAT2 input is selected. + value: 69 + - name: Val70 + description: CTimer3_MAT3 input is selected. + value: 70 + - name: Val71 + description: CTimer4_MAT2 input is selected. + value: 71 + - name: Val72 + description: CTimer4_MAT3 input is selected. + value: 72 + - name: Val73 + description: PWM1_SM0_MUX_TRIG0 input is selected. + value: 73 + - name: Val74 + description: PWM1_SM1_MUX_TRIG0 input is selected. + value: 74 + - name: Val75 + description: PWM1_SM2_MUX_TRIG0 input is selected. + value: 75 + - name: Val76 + description: PWM1_SM3_MUX_TRIG0 input is selected. + value: 76 + - name: Val77 + description: LPI2C2 Master End of Packet. + value: 77 + - name: Val78 + description: LPI2C2 Slave End of Packet. + value: 78 + - name: Val79 + description: LPI2C3 Master End of Packet. + value: 79 + - name: Val80 + description: LPI2C3 Slave End of Packet. + value: 80 +enum/Tsi0TrigInputInp: + bit_size: 6 variants: - - name: VAL1 - description: LPUART0 lpuart_trg_txdata input is selected. + - name: Val1 + description: CTimer0_MAT2 input is selected. value: 1 - - name: VAL2 - description: LPUART1 lpuart_trg_txdata input is selected. + - name: Val2 + description: CTimer0_MAT3 input is selected. value: 2 - - name: VAL3 - description: LPUART2 lpuart_trg_txdata input is selected. + - name: Val3 + description: CTimer1_MAT2 input is selected. value: 3 - - name: VAL4 - description: LPUART3 lpuart_trg_txdata input is selected. + - name: Val4 + description: CTimer1_MAT3 input is selected. value: 4 - - name: VAL5 - description: LPUART4 lpuart_trg_txdata input is selected. + - name: Val5 + description: CTimer2_MAT2 input is selected. value: 5 - - name: VAL6 - description: LPUART5 lpuart_trg_txdata input is selected. + - name: Val6 + description: CTimer2_MAT3 input is selected. value: 6 + - name: Val7 + description: CTimer3_MAT2 input is selected. + value: 7 + - name: Val8 + description: CTimer3_MAT3 input is selected. + value: 8 + - name: Val9 + description: CTimer4_MAT2 input is selected. + value: 9 + - name: Val10 + description: CTimer4_MAT3 input is selected. + value: 10 + - name: Val11 + description: LPTMR0 input is selected. + value: 11 + - name: Val12 + description: WUU input is selected. + value: 12 diff --git a/data/metadata/peripherals/mcxa/LPI2C.yaml b/data/metadata/peripherals/mcxa/LPI2C.yaml index f83eef6..514002c 100644 --- a/data/metadata/peripherals/mcxa/LPI2C.yaml +++ b/data/metadata/peripherals/mcxa/LPI2C.yaml @@ -252,6 +252,10 @@ fieldset/Mcfgr1: bit_offset: 24 bit_size: 3 enum: Pincfg + - name: frchs + description: Force HS Mode. + bit_offset: 27 + bit_size: 1 fieldset/Mcfgr2: description: Controller Configuration 2. fields: @@ -857,46 +861,46 @@ fieldset/Verid: enum/Addrcfg: bit_size: 3 variants: - - name: ADDRESS_MATCH0_7_BIT + - name: AddressMatch07Bit description: Address match 0 (7-bit). value: 0 - - name: ADDRESS_MATCH0_10_BIT + - name: AddressMatch010Bit description: Address match 0 (10-bit). value: 1 - - name: ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_7_BIT + - name: AddressMatch07BitOrAddressMatch17Bit description: Address match 0 (7-bit) or address match 1 (7-bit). value: 2 - - name: ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_10_BIT + - name: AddressMatch010BitOrAddressMatch110Bit description: Address match 0 (10-bit) or address match 1 (10-bit). value: 3 - - name: ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_10_BIT + - name: AddressMatch07BitOrAddressMatch110Bit description: Address match 0 (7-bit) or address match 1 (10-bit). value: 4 - - name: ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_7_BIT + - name: AddressMatch010BitOrAddressMatch17Bit description: Address match 0 (10-bit) or address match 1 (7-bit). value: 5 - - name: FROM_ADDRESS_MATCH0_7_BIT_TO_ADDRESS_MATCH1_7_BIT + - name: FromAddressMatch07BitToAddressMatch17Bit description: From address match 0 (7-bit) to address match 1 (7-bit). value: 6 - - name: FROM_ADDRESS_MATCH0_10_BIT_TO_ADDRESS_MATCH1_10_BIT + - name: FromAddressMatch010BitToAddressMatch110Bit description: From address match 0 (10-bit) to address match 1 (10-bit). value: 7 enum/Alf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: Controller did not lose arbitration. value: 0 - - name: INT_YES + - name: IntYes description: Controller lost arbitration. value: 1 enum/Anv: bit_size: 1 variants: - - name: VALID + - name: Valid description: Valid. value: 0 - - name: NOT_VALID + - name: NotValid description: Not valid. value: 1 enum/Cmd: @@ -929,357 +933,357 @@ enum/Cmd: enum/Dmf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: Matching data not received. value: 0 - - name: INT_YES + - name: IntYes description: Matching data received. value: 1 enum/Dozen: bit_size: 1 variants: - - name: ENABLED + - name: Enabled description: Enable. value: 0 - - name: DISABLED + - name: Disabled description: Disable. value: 1 enum/Epf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: No Stop or repeated Start generated. value: 0 - - name: INT_YES + - name: IntYes description: Stop or repeated Start generated. value: 1 enum/Feature: bit_size: 16 variants: - - name: MASTER_ONLY + - name: MasterOnly description: Controller only, with standard feature set. value: 2 - - name: MASTER_AND_SLAVE + - name: MasterAndSlave description: Controller and target, with standard feature set. value: 3 enum/Filtdz: bit_size: 1 variants: - - name: FILTER_ENABLED + - name: FilterEnabled description: Enable. value: 0 - - name: FILTER_DISABLED + - name: FilterDisabled description: Disable. value: 1 enum/Hrdir: bit_size: 1 variants: - - name: INPUT + - name: Input description: HREQ pin is input (for LPI2C controller). value: 0 - - name: OUTPUT + - name: Output description: HREQ pin is output (for LPI2C target). value: 1 enum/Hrpol: bit_size: 1 variants: - - name: ACTIVE_LOW + - name: ActiveLow description: Active low. value: 0 - - name: ACTIVE_HIGH + - name: ActiveHigh description: Active high. value: 1 enum/Matcfg: bit_size: 3 variants: - - name: DISABLED + - name: Disabled description: Match is disabled. value: 0 - - name: FIRST_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 + - name: FirstDataWordEqualsMatch0OrMatch1 description: 'Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1].' value: 2 - - name: ANY_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 + - name: AnyDataWordEqualsMatch0OrMatch1 description: 'Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1].' value: 3 - - name: FIRST_DATA_WORD_MATCH0_AND_SECOND_DATA_WORD_MATCH1 + - name: FirstDataWordMatch0AndSecondDataWordMatch1 description: 'Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1).' value: 4 - - name: ANY_DATA_WORD_MATCH0_NEXT_DATA_WORD_MATCH1 + - name: AnyDataWordMatch0NextDataWordMatch1 description: 'Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1).' value: 5 - - name: FIRST_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 + - name: FirstDataWordAndMatch1EqualsMatch0AndMatch1 description: 'Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]).' value: 6 - - name: ANY_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 + - name: AnyDataWordAndMatch1EqualsMatch0AndMatch1 description: 'Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]).' value: 7 enum/Mbf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/McrRrf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: RESET + - name: Reset description: Reset receive FIFO. value: 1 enum/McrRtf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: RESET + - name: Reset description: Reset transmit FIFO. value: 1 enum/MsrBbf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/MsrFef: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: No FIFO error. value: 0 - - name: INT_YES + - name: IntYes description: FIFO error. value: 1 enum/MsrSdf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: No Stop condition generated. value: 0 - - name: INT_YES + - name: IntYes description: Stop condition generated. value: 1 enum/Ndf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: No unexpected NACK detected. value: 0 - - name: INT_YES + - name: IntYes description: Unexpected NACK detected. value: 1 enum/Pincfg: bit_size: 3 variants: - - name: OPEN_DRAIN_2_PIN + - name: OpenDrain2Pin description: Two-pin open drain mode. value: 0 - - name: OUTPUT_2_PIN_ONLY + - name: Output2PinOnly description: Two-pin output only mode (Ultra-Fast mode). value: 1 - - name: PUSH_PULL_2_PIN + - name: PushPull2Pin description: Two-pin push-pull mode. value: 2 - - name: PUSH_PULL_4_PIN + - name: PushPull4Pin description: Four-pin push-pull mode. value: 3 - - name: OPEN_DRAIN_2_PIN_W_LPI2C_SLAVE + - name: OpenDrain2PinWLpi2cSlave description: Two-pin open-drain mode with separate LPI2C target. value: 4 - - name: OUTPUT_2_PIN_ONLY_W_LPI2C_SLAVE + - name: Output2PinOnlyWLpi2cSlave description: Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target. value: 5 - - name: PUSH_PULL_2_PIN_W_LPI2C_SLAVE + - name: PushPull2PinWLpi2cSlave description: Two-pin push-pull mode with separate LPI2C target. value: 6 - - name: PUSH_PULL_4_PIN_W_LPI2C_SLAVE + - name: PushPull4PinWLpi2cSlave description: Four-pin push-pull mode (inverted outputs). value: 7 enum/Pltf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: Pin low timeout did not occur. value: 0 - - name: INT_YES + - name: IntYes description: Pin low timeout occurred. value: 1 enum/Prescale: bit_size: 3 variants: - - name: DIVIDE_BY_1 + - name: DivideBy1 description: Divide by 1. value: 0 - - name: DIVIDE_BY_2 + - name: DivideBy2 description: Divide by 2. value: 1 - - name: DIVIDE_BY_4 + - name: DivideBy4 description: Divide by 4. value: 2 - - name: DIVIDE_BY_8 + - name: DivideBy8 description: Divide by 8. value: 3 - - name: DIVIDE_BY_16 + - name: DivideBy16 description: Divide by 16. value: 4 - - name: DIVIDE_BY_32 + - name: DivideBy32 description: Divide by 32. value: 5 - - name: DIVIDE_BY_64 + - name: DivideBy64 description: Divide by 64. value: 6 - - name: DIVIDE_BY_128 + - name: DivideBy128 description: Divide by 128. value: 7 enum/Relax: bit_size: 1 variants: - - name: NORMAL_TRANSFER + - name: NormalTransfer description: Normal transfer. value: 0 - - name: RELAXED_TRANSFER + - name: RelaxedTransfer description: Relaxed transfer. value: 1 enum/Rscfg: bit_size: 1 variants: - - name: ANY_REPEATED_START_AFTER_ADDRESS_MATCH + - name: AnyRepeatedStartAfterAddressMatch description: Any repeated Start condition following an address match. value: 0 - - name: ANY_REPEATED_START + - name: AnyRepeatedStart description: Any repeated Start condition. value: 1 enum/Rxcfg: bit_size: 1 variants: - - name: RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG - description: Return received data, clear MSR[RDF]. + - name: ReturnsReceivedDataAndClearsRxDataFlag + description: Return received data, clear SSR[RDF]. value: 0 - - name: WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG - description: Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set. + - name: WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag + description: Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear SSR[RDF] when SSR[AFV] is not set. value: 1 enum/Rxnack: bit_size: 1 variants: - - name: SET_BY_TXNACK + - name: SetByTxnack description: ACK or NACK always determined by STAR[TXNACK]. value: 0 - - name: ALWAYS_GENERATED_ON_ADDRESS_OR_RECEIVE_DATA_OVERRUN + - name: AlwaysGeneratedOnAddressOrReceiveDataOverrun description: NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]. value: 1 enum/Sbf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/Scfgr1Ignack: bit_size: 1 variants: - - name: ENDS_TRANSFER_ON_NACK + - name: EndsTransferOnNack description: End transfer on NACK. value: 0 - - name: DOES_NOT_END_TRANSFER_ON_NACK + - name: DoesNotEndTransferOnNack description: Do not end transfer on NACK. value: 1 enum/ScrRrf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: NOW_EMPTY + - name: NowEmpty description: SRDR is now empty. value: 1 enum/ScrRtf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: NOW_EMPTY + - name: NowEmpty description: STDR is now empty. value: 1 enum/Sdcfg: bit_size: 1 variants: - - name: ANY_STOP_AFTER_ADDRESS_MATCH + - name: AnyStopAfterAddressMatch description: Any Stop condition following an address match. value: 0 - - name: ANY_STOP + - name: AnyStop description: Any Stop condition. value: 1 enum/SsrBbf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: BUSY + - name: Busy description: Busy. value: 1 enum/Startcfg: bit_size: 1 variants: - - name: BOTH_I2C_AND_LPI2C_IDLE + - name: BothI2cAndLpi2cIdle description: Sets when both I2C bus and LPI2C controller are idle. value: 0 - - name: I2C_IDLE + - name: I2cIdle description: Sets when I2C bus is idle. value: 1 enum/Stf: bit_size: 1 variants: - - name: INT_NO + - name: IntNo description: Start condition not detected. value: 0 - - name: INT_YES + - name: IntYes description: Start condition detected. value: 1 enum/Stopcfg: bit_size: 1 variants: - - name: ANY_STOP + - name: AnyStop description: Any Stop condition. value: 0 - - name: LAST_STOP + - name: LastStop description: Last Stop condition. value: 1 enum/Timecfg: bit_size: 1 variants: - - name: IF_SCL_LOW + - name: IfSclLow description: SCL. value: 0 - - name: IF_SCL_OR_SDA_LOW + - name: IfSclOrSdaLow description: SCL or SDA. value: 1 enum/Txcfg: bit_size: 1 variants: - - name: ASSERTS_DURING_SLAVE_TRANSMIT_TRANSFER_WHEN_TX_DATA_EMPTY - description: MSR[TDF] is set only during a target-transmit transfer when STDR is empty. + - name: AssertsDuringSlaveTransmitTransferWhenTxDataEmpty + description: SSR[TDF] is set only during a target-transmit transfer when STDR is empty. value: 0 - - name: ASSERTS_WHEN_TX_DATA_EMPTY - description: MSR[TDF] is set whenever STDR is empty. + - name: AssertsWhenTxDataEmpty + description: SSR[TDF] is set whenever STDR is empty. value: 1 enum/Txnack: bit_size: 1 variants: - - name: TRANSMIT_ACK + - name: TransmitAck description: Transmit ACK. value: 0 - - name: TRANSMIT_NACK + - name: TransmitNack description: Transmit NACK. value: 1 diff --git a/data/metadata/peripherals/mcxa/LPSPI.yaml b/data/metadata/peripherals/mcxa/LPSPI.yaml index 52279a4..7797e29 100644 --- a/data/metadata/peripherals/mcxa/LPSPI.yaml +++ b/data/metadata/peripherals/mcxa/LPSPI.yaml @@ -1,802 +1,816 @@ -block/LPSPI: +block/Lpspi: description: Low-Power Serial Peripheral Interface. items: - - name: VERID + - name: verid description: Version ID. byte_offset: 0 access: Read - fieldset: VERID - - name: PARAM + fieldset: Verid + - name: param description: Parameter. byte_offset: 4 access: Read - fieldset: PARAM - - name: CR + fieldset: Param + - name: cr description: Control. byte_offset: 16 - fieldset: CR - - name: SR + fieldset: Cr + - name: sr description: Status. byte_offset: 20 - fieldset: SR - - name: IER + fieldset: Sr + - name: ier description: Interrupt Enable. byte_offset: 24 - fieldset: IER - - name: DER + fieldset: Ier + - name: der description: DMA Enable. byte_offset: 28 - fieldset: DER - - name: CFGR0 + fieldset: Der + - name: cfgr0 description: Configuration 0. byte_offset: 32 - fieldset: CFGR0 - - name: CFGR1 + fieldset: Cfgr0 + - name: cfgr1 description: Configuration 1. byte_offset: 36 - fieldset: CFGR1 - - name: DMR0 + fieldset: Cfgr1 + - name: dmr0 description: Data Match 0. byte_offset: 48 - fieldset: DMR0 - - name: DMR1 + fieldset: Dmr0 + - name: dmr1 description: Data Match 1. byte_offset: 52 - fieldset: DMR1 - - name: CCR + fieldset: Dmr1 + - name: ccr description: Clock Configuration. byte_offset: 64 - fieldset: CCR - - name: CCR1 + fieldset: Ccr + - name: ccr1 description: Clock Configuration 1. byte_offset: 68 - fieldset: CCR1 - - name: FCR + fieldset: Ccr1 + - name: fcr description: FIFO Control. byte_offset: 88 - fieldset: FCR - - name: FSR + fieldset: Fcr + - name: fsr description: FIFO Status. byte_offset: 92 access: Read - fieldset: FSR - - name: TCR + fieldset: Fsr + - name: tcr description: Transmit Command. byte_offset: 96 - fieldset: TCR - - name: TDR + fieldset: Tcr + - name: tdr description: Transmit Data. byte_offset: 100 access: Write - fieldset: TDR - - name: RSR + fieldset: Tdr + - name: rsr description: Receive Status. byte_offset: 112 access: Read - fieldset: RSR - - name: RDR + fieldset: Rsr + - name: rdr description: Receive Data. byte_offset: 116 access: Read - fieldset: RDR - - name: RDROR + fieldset: Rdr + - name: rdror description: Receive Data Read Only. byte_offset: 120 access: Read - fieldset: RDROR - - name: TCBR + fieldset: Rdror + - name: tcbr description: Transmit Command Burst. byte_offset: 1020 access: Write - fieldset: TCBR - - name: TDBR + fieldset: Tcbr + - name: tdbr description: Transmit Data Burst. array: len: 128 stride: 4 byte_offset: 1024 access: Write - fieldset: TDBR - - name: RDBR + fieldset: Tdbr + - name: rdbr description: Receive Data Burst. array: len: 128 stride: 4 byte_offset: 1536 access: Read - fieldset: RDBR -fieldset/CCR: + fieldset: Rdbr +fieldset/Ccr: description: Clock Configuration. fields: - - name: SCKDIV + - name: sckdiv description: SCK Divider. bit_offset: 0 bit_size: 8 - - name: DBT + - name: dbt description: Delay Between Transfers. bit_offset: 8 bit_size: 8 - - name: PCSSCK + - name: pcssck description: PCS-to-SCK Delay. bit_offset: 16 bit_size: 8 - - name: SCKPCS + - name: sckpcs description: SCK-to-PCS Delay. bit_offset: 24 bit_size: 8 -fieldset/CCR1: +fieldset/Ccr1: description: Clock Configuration 1. fields: - - name: SCKSET + - name: sckset description: SCK Setup. bit_offset: 0 bit_size: 8 - - name: SCKHLD + - name: sckhld description: SCK Hold. bit_offset: 8 bit_size: 8 - - name: PCSPCS + - name: pcspcs description: PCS to PCS Delay. bit_offset: 16 bit_size: 8 - - name: SCKSCK + - name: scksck description: SCK Inter-Frame Delay. bit_offset: 24 bit_size: 8 -fieldset/CFGR0: +fieldset/Cfgr0: description: Configuration 0. fields: - - name: HREN + - name: hren description: Host Request Enable. bit_offset: 0 bit_size: 1 - - name: HRPOL + - name: hrpol description: Host Request Polarity. bit_offset: 1 bit_size: 1 - - name: HRSEL + - name: hrsel description: Host Request Select. bit_offset: 2 bit_size: 1 - enum: HRSEL - - name: HRDIR + enum: Hrsel + - name: hrdir description: Host Request Direction. bit_offset: 3 bit_size: 1 - enum: HRDIR - - name: CIRFIFO + enum: Hrdir + - name: cirfifo description: Circular FIFO Enable. bit_offset: 8 bit_size: 1 - - name: RDMO + - name: rdmo description: Receive Data Match Only. bit_offset: 9 bit_size: 1 - enum: RDMO -fieldset/CFGR1: + enum: Rdmo +fieldset/Cfgr1: description: Configuration 1. fields: - - name: MASTER + - name: master description: Controller Mode. bit_offset: 0 bit_size: 1 - enum: MASTER - - name: SAMPLE + enum: Master + - name: sample description: Sample Point. bit_offset: 1 bit_size: 1 - enum: SAMPLE - - name: AUTOPCS + enum: Sample + - name: autopcs description: Automatic PCS. bit_offset: 2 bit_size: 1 - - name: NOSTALL + - name: nostall description: No Stall. bit_offset: 3 bit_size: 1 - - name: PARTIAL + - name: partial description: Partial Enable. bit_offset: 4 bit_size: 1 - enum: PARTIAL - - name: PCSPOL + enum: Partial + - name: pcspol description: Peripheral Chip Select Polarity. bit_offset: 8 bit_size: 4 - enum: PCSPOL - - name: MATCFG + enum: Pcspol + - name: matcfg description: Match Configuration. bit_offset: 16 bit_size: 3 - enum: MATCFG - - name: PINCFG + enum: Matcfg + - name: pincfg description: Pin Configuration. bit_offset: 24 bit_size: 2 - enum: PINCFG - - name: OUTCFG + enum: Pincfg + - name: outcfg description: Output Configuration. bit_offset: 26 bit_size: 1 - enum: OUTCFG - - name: PCSCFG + enum: Outcfg + - name: pcscfg description: Peripheral Chip Select Configuration. bit_offset: 27 bit_size: 1 - enum: PCSCFG -fieldset/CR: + enum: Pcscfg +fieldset/Cr: description: Control. fields: - - name: MEN + - name: men description: Module Enable. bit_offset: 0 bit_size: 1 - - name: RST + - name: rst description: Software Reset. bit_offset: 1 bit_size: 1 - - name: DBGEN + - name: dozen + description: Doze Mode Enable. + bit_offset: 2 + bit_size: 1 + enum: Dozen + - name: dbgen description: Debug Enable. bit_offset: 3 bit_size: 1 - - name: RTF + - name: rtf description: Reset Transmit FIFO. bit_offset: 8 bit_size: 1 - enum: RTF - - name: RRF + enum: Rtf + - name: rrf description: Reset Receive FIFO. bit_offset: 9 bit_size: 1 - enum: RRF -fieldset/DER: + enum: Rrf +fieldset/Der: description: DMA Enable. fields: - - name: TDDE + - name: tdde description: Transmit Data DMA Enable. bit_offset: 0 bit_size: 1 - - name: RDDE + - name: rdde description: Receive Data DMA Enable. bit_offset: 1 bit_size: 1 - - name: FCDE + - name: fcde description: Frame Complete DMA Enable. bit_offset: 9 bit_size: 1 -fieldset/DMR0: +fieldset/Dmr0: description: Data Match 0. fields: - - name: MATCH0 + - name: match0 description: Match 0 Value. bit_offset: 0 bit_size: 32 -fieldset/DMR1: +fieldset/Dmr1: description: Data Match 1. fields: - - name: MATCH1 + - name: match1 description: Match 1 Value. bit_offset: 0 bit_size: 32 -fieldset/FCR: +fieldset/Fcr: description: FIFO Control. fields: - - name: TXWATER + - name: txwater description: Transmit FIFO Watermark. bit_offset: 0 bit_size: 2 - - name: RXWATER + - name: rxwater description: Receive FIFO Watermark. bit_offset: 16 bit_size: 2 -fieldset/FSR: +fieldset/Fsr: description: FIFO Status. fields: - - name: TXCOUNT + - name: txcount description: Transmit FIFO Count. bit_offset: 0 bit_size: 3 - - name: RXCOUNT + - name: rxcount description: Receive FIFO Count. bit_offset: 16 bit_size: 3 -fieldset/IER: +fieldset/Ier: description: Interrupt Enable. fields: - - name: TDIE + - name: tdie description: Transmit Data Interrupt Enable. bit_offset: 0 bit_size: 1 - - name: RDIE + - name: rdie description: Receive Data Interrupt Enable. bit_offset: 1 bit_size: 1 - - name: WCIE + - name: wcie description: Word Complete Interrupt Enable. bit_offset: 8 bit_size: 1 - - name: FCIE + - name: fcie description: Frame Complete Interrupt Enable. bit_offset: 9 bit_size: 1 - - name: TCIE + - name: tcie description: Transfer Complete Interrupt Enable. bit_offset: 10 bit_size: 1 - - name: TEIE + - name: teie description: Transmit Error Interrupt Enable. bit_offset: 11 bit_size: 1 - - name: REIE + - name: reie description: Receive Error Interrupt Enable. bit_offset: 12 bit_size: 1 - - name: DMIE + - name: dmie description: Data Match Interrupt Enable. bit_offset: 13 bit_size: 1 -fieldset/PARAM: +fieldset/Param: description: Parameter. fields: - - name: TXFIFO + - name: txfifo description: Transmit FIFO Size. bit_offset: 0 bit_size: 8 - - name: RXFIFO + - name: rxfifo description: Receive FIFO Size. bit_offset: 8 bit_size: 8 - - name: PCSNUM + - name: pcsnum description: PCS Number. bit_offset: 16 bit_size: 8 -fieldset/RDBR: +fieldset/Rdbr: description: Receive Data Burst. fields: - - name: DATA + - name: data description: Data. bit_offset: 0 bit_size: 32 -fieldset/RDR: +fieldset/Rdr: description: Receive Data. fields: - - name: DATA + - name: data description: Receive Data. bit_offset: 0 bit_size: 32 -fieldset/RDROR: +fieldset/Rdror: description: Receive Data Read Only. fields: - - name: DATA + - name: data description: Receive Data. bit_offset: 0 bit_size: 32 -fieldset/RSR: +fieldset/Rsr: description: Receive Status. fields: - - name: SOF + - name: sof description: Start of Frame. bit_offset: 0 bit_size: 1 - enum: SOF - - name: RXEMPTY + enum: Sof + - name: rxempty description: RX FIFO Empty. bit_offset: 1 bit_size: 1 -fieldset/SR: +fieldset/Sr: description: Status. fields: - - name: TDF + - name: tdf description: Transmit Data Flag. bit_offset: 0 bit_size: 1 - enum: TDF - - name: RDF + enum: Tdf + - name: rdf description: Receive Data Flag. bit_offset: 1 bit_size: 1 - - name: WCF + - name: wcf description: Word Complete Flag. bit_offset: 8 bit_size: 1 - - name: FCF + - name: fcf description: Frame Complete Flag. bit_offset: 9 bit_size: 1 - - name: TCF + - name: tcf description: Transfer Complete Flag. bit_offset: 10 bit_size: 1 - - name: TEF + - name: tef description: Transmit Error Flag. bit_offset: 11 bit_size: 1 - - name: REF + - name: ref_ description: Receive Error Flag. bit_offset: 12 bit_size: 1 - - name: DMF + - name: dmf description: Data Match Flag. bit_offset: 13 bit_size: 1 - - name: MBF + - name: mbf description: Module Busy Flag. bit_offset: 24 bit_size: 1 - enum: MBF -fieldset/TCBR: + enum: Mbf +fieldset/Tcbr: description: Transmit Command Burst. fields: - - name: DATA + - name: data description: Command Data. bit_offset: 0 bit_size: 32 -fieldset/TCR: +fieldset/Tcr: description: Transmit Command. fields: - - name: FRAMESZ + - name: framesz description: Frame Size. bit_offset: 0 bit_size: 12 - - name: WIDTH + - name: width description: Transfer Width. bit_offset: 16 bit_size: 2 - enum: WIDTH - - name: TXMSK + enum: Width + - name: txmsk description: Transmit Data Mask. bit_offset: 18 bit_size: 1 - enum: TXMSK - - name: RXMSK + enum: Txmsk + - name: rxmsk description: Receive Data Mask. bit_offset: 19 bit_size: 1 - enum: RXMSK - - name: CONTC + enum: Rxmsk + - name: contc description: Continuing Command. bit_offset: 20 bit_size: 1 - enum: CONTC - - name: CONT + enum: Contc + - name: cont description: Continuous Transfer. bit_offset: 21 bit_size: 1 - - name: BYSW + - name: bysw description: Byte Swap. bit_offset: 22 bit_size: 1 - - name: LSBF + - name: lsbf description: LSB First. bit_offset: 23 bit_size: 1 - enum: LSBF - - name: PCS + enum: Lsbf + - name: pcs description: Peripheral Chip Select. bit_offset: 24 bit_size: 2 - enum: PCS - - name: PRESCALE + enum: Pcs + - name: prescale description: Prescaler Value. bit_offset: 27 bit_size: 3 - enum: PRESCALE - - name: CPHA + enum: Prescale + - name: cpha description: Clock Phase. bit_offset: 30 bit_size: 1 - enum: CPHA - - name: CPOL + enum: Cpha + - name: cpol description: Clock Polarity. bit_offset: 31 bit_size: 1 - enum: CPOL -fieldset/TDBR: + enum: Cpol +fieldset/Tdbr: description: Transmit Data Burst. fields: - - name: DATA + - name: data description: Data. bit_offset: 0 bit_size: 32 -fieldset/TDR: +fieldset/Tdr: description: Transmit Data. fields: - - name: DATA + - name: data description: Transmit Data. bit_offset: 0 bit_size: 32 -fieldset/VERID: +fieldset/Verid: description: Version ID. fields: - - name: FEATURE + - name: feature description: Module Identification Number. bit_offset: 0 bit_size: 16 - enum: FEATURE - - name: MINOR + enum: Feature + - name: minor description: Minor Version Number. bit_offset: 16 bit_size: 8 - - name: MAJOR + - name: major description: Major Version Number. bit_offset: 24 bit_size: 8 -enum/CONTC: +enum/Contc: bit_size: 1 variants: - - name: START + - name: Start description: Command word for start of new transfer. value: 0 - - name: CONTINUE + - name: Continue description: Command word for continuing transfer. value: 1 -enum/CPHA: +enum/Cpha: bit_size: 1 variants: - - name: CAPTURED + - name: Captured description: Captured. value: 0 - - name: CHANGED + - name: Changed description: Changed. value: 1 -enum/CPOL: +enum/Cpol: bit_size: 1 variants: - - name: INACTIVE_LOW + - name: InactiveLow description: Inactive low. value: 0 - - name: INACTIVE_HIGH + - name: InactiveHigh description: Inactive high. value: 1 -enum/FEATURE: +enum/Dozen: + bit_size: 1 + variants: + - name: Enabled + description: Enable. + value: 0 + - name: Disabled + description: Disable. + value: 1 +enum/Feature: bit_size: 16 variants: - - name: STANDARD + - name: Standard description: Standard feature set supporting a 32-bit shift register. value: 4 -enum/HRDIR: +enum/Hrdir: bit_size: 1 variants: - - name: INPUT + - name: Input description: Input. value: 0 - - name: OUTPUT + - name: Output description: Output. value: 1 -enum/HRSEL: +enum/Hrsel: bit_size: 1 variants: - - name: HREQPIN + - name: Hreqpin description: HREQ pin. value: 0 - - name: INPUT_TRIGGER + - name: InputTrigger description: Input trigger. value: 1 -enum/LSBF: +enum/Lsbf: bit_size: 1 variants: - - name: MSB_FIRST + - name: MsbFirst description: MSB first. value: 0 - - name: LSB_FIRST + - name: LsbFirst description: LSB first. value: 1 -enum/MASTER: +enum/Master: bit_size: 1 variants: - - name: SLAVE_MODE + - name: SlaveMode description: Peripheral mode. value: 0 - - name: MASTER_MODE + - name: MasterMode description: Controller mode. value: 1 -enum/MATCFG: +enum/Matcfg: bit_size: 3 variants: - - name: DISABLED + - name: Disabled description: Match is disabled. value: 0 - - name: ENABLED_FIRSTDATAMATCH + - name: EnabledFirstdatamatch description: Match first data word with compare word. value: 2 - - name: ENABLED_ANYDATAMATCH + - name: EnabledAnydatamatch description: Match any data word with compare word. value: 3 - - name: ENABLED_DATAMATCH_100 + - name: EnabledDatamatch100 description: Sequential match, first data word. value: 4 - - name: ENABLED_DATAMATCH_101 + - name: EnabledDatamatch101 description: Sequential match, any data word. value: 5 - - name: ENABLED_DATAMATCH_110 + - name: EnabledDatamatch110 description: Match first data word (masked) with compare word (masked). value: 6 - - name: ENABLED_DATAMATCH_111 + - name: EnabledDatamatch111 description: Match any data word (masked) with compare word (masked). value: 7 -enum/MBF: +enum/Mbf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: LPSPI is idle. value: 0 - - name: BUSY + - name: Busy description: LPSPI is busy. value: 1 -enum/OUTCFG: +enum/Outcfg: bit_size: 1 variants: - - name: RETAIN_LASTVALUE + - name: RetainLastvalue description: Retain last value. value: 0 - - name: TRISTATED + - name: Tristated description: 3-stated. value: 1 -enum/PARTIAL: +enum/Partial: bit_size: 1 variants: - - name: DISCARDED + - name: Discarded description: Discard. value: 0 - - name: STORED + - name: Stored description: Store. value: 1 -enum/PCS: +enum/Pcs: bit_size: 2 variants: - - name: TX_PCS0 + - name: TxPcs0 description: Transfer using PCS[0]. value: 0 - - name: TX_PCS1 + - name: TxPcs1 description: Transfer using PCS[1]. value: 1 - - name: TX_PCS2 + - name: TxPcs2 description: Transfer using PCS[2]. value: 2 - - name: TX_PCS3 + - name: TxPcs3 description: Transfer using PCS[3]. value: 3 -enum/PCSCFG: +enum/Pcscfg: bit_size: 1 variants: - - name: CHIP_SELECT + - name: ChipSelect description: PCS[3:2] configured for chip select function. value: 0 - - name: HALFDUPLEX4BIT + - name: Halfduplex4bit description: PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]). value: 1 -enum/PCSPOL: +enum/Pcspol: bit_size: 4 variants: - - name: DISCARDED + - name: Discarded description: Active low. value: 0 - - name: STORED + - name: Stored description: Active high. value: 1 -enum/PINCFG: +enum/Pincfg: bit_size: 2 variants: - - name: SIN_IN_SOUT_OUT + - name: SinInSoutOut description: SIN is used for input data; SOUT is used for output data. value: 0 - - name: SIN_BOTH_IN_OUT + - name: SinBothInOut description: SIN is used for both input and output data; only half-duplex serial transfers are supported. value: 1 - - name: SOUT_BOTH_IN_OUT + - name: SoutBothInOut description: SOUT is used for both input and output data; only half-duplex serial transfers are supported. value: 2 - - name: SOUT_IN_SIN_OUT + - name: SoutInSinOut description: SOUT is used for input data; SIN is used for output data. value: 3 -enum/PRESCALE: +enum/Prescale: bit_size: 3 variants: - - name: DIVIDEBY1 + - name: Divideby1 description: Divide by 1. value: 0 - - name: DIVIDEBY2 + - name: Divideby2 description: Divide by 2. value: 1 - - name: DIVIDEBY4 + - name: Divideby4 description: Divide by 4. value: 2 - - name: DIVIDEBY8 + - name: Divideby8 description: Divide by 8. value: 3 - - name: DIVIDEBY16 + - name: Divideby16 description: Divide by 16. value: 4 - - name: DIVIDEBY32 + - name: Divideby32 description: Divide by 32. value: 5 - - name: DIVIDEBY64 + - name: Divideby64 description: Divide by 64. value: 6 - - name: DIVIDEBY128 + - name: Divideby128 description: Divide by 128. value: 7 -enum/RDMO: +enum/Rdmo: bit_size: 1 variants: - - name: STORED + - name: Stored description: Disable. value: 0 - - name: DISCARDED + - name: Discarded description: Enable. value: 1 -enum/RRF: +enum/Rrf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: RXFIFO_RST + - name: RxfifoRst description: Reset. value: 1 -enum/RTF: +enum/Rtf: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: TXFIFO_RST + - name: TxfifoRst description: Reset. value: 1 -enum/RXMSK: +enum/Rxmsk: bit_size: 1 variants: - - name: NORMAL + - name: Normal description: Normal transfer. value: 0 - - name: MASK + - name: Mask description: Mask receive data. value: 1 -enum/SAMPLE: +enum/Sample: bit_size: 1 variants: - - name: ON_SCK_EDGE + - name: OnSckEdge description: SCK edge. value: 0 - - name: ON_DELAYED_SCK_EDGE + - name: OnDelayedSckEdge description: Delayed SCK edge. value: 1 -enum/SOF: +enum/Sof: bit_size: 1 variants: - - name: NEXT_DATAWORD + - name: NextDataword description: Subsequent data word or RX FIFO is empty (RXEMPTY=1). value: 0 - - name: FIRST_DATAWORD + - name: FirstDataword description: First data word. value: 1 -enum/TDF: +enum/Tdf: bit_size: 1 variants: - - name: TXDATA_NOT_REQST + - name: TxdataNotReqst description: Transmit data not requested. value: 0 - - name: TXDATA_REQST + - name: TxdataReqst description: Transmit data requested. value: 1 -enum/TXMSK: +enum/Txmsk: bit_size: 1 variants: - - name: NORMAL + - name: Normal description: Normal transfer. value: 0 - - name: MASK + - name: Mask description: Mask transmit data. value: 1 -enum/WIDTH: +enum/Width: bit_size: 2 variants: - - name: ONEBIT + - name: Onebit description: 1-bit transfer. value: 0 - - name: TWOBIT + - name: Twobit description: 2-bit transfer. value: 1 - - name: FOURBIT + - name: Fourbit description: 4-bit transfer. value: 2 diff --git a/data/metadata/peripherals/mcxa/LPUART.yaml b/data/metadata/peripherals/mcxa/LPUART.yaml index b10cc1a..70ed117 100644 --- a/data/metadata/peripherals/mcxa/LPUART.yaml +++ b/data/metadata/peripherals/mcxa/LPUART.yaml @@ -98,6 +98,11 @@ fieldset/Baud: description: Receiver Full DMA Enable. bit_offset: 21 bit_size: 1 + - name: hlfm + description: Reduced Oversample Mode Selection. + bit_offset: 22 + bit_size: 1 + enum: Hlfm - name: tdmae description: Transmitter DMA Enable. bit_offset: 23 @@ -175,6 +180,11 @@ fieldset/Ctrl: bit_offset: 12 bit_size: 1 enum: Swap + - name: erlsmp + description: Early Sample Selection. + bit_offset: 13 + bit_size: 1 + enum: Erlsmp - name: ma2ie description: Match 2 (MA2F) Interrupt Enable. bit_offset: 14 @@ -592,396 +602,414 @@ fieldset/Water: enum/Brk13: bit_size: 1 variants: - - name: SHORT + - name: Short description: 9 to 13 bit times. value: 0 - - name: LONG + - name: Long description: 12 to 15 bit times. value: 1 enum/Dozeen: bit_size: 1 variants: - - name: ENABLED + - name: Enabled description: Enable. value: 0 - - name: DISABLED + - name: Disabled description: Disable. value: 1 +enum/Erlsmp: + bit_size: 1 + variants: + - name: Midpoint + description: Regular midpoint bit sampling. + value: 0 + - name: Reduced + description: Early bit sampling at 1/2 duration of bit timing. + value: 1 enum/Feature: bit_size: 16 variants: - - name: STANDARD + - name: Standard description: Standard feature set. value: 1 - - name: MODEM + - name: Modem description: Standard feature set with MODEM and IrDA support. value: 3 +enum/Hlfm: + bit_size: 1 + variants: + - name: Regular + description: Regular Oversampling. + value: 0 + - name: Reduced + description: Reduced Oversampling by 0.5. + value: 1 enum/Idlecfg: bit_size: 3 variants: - - name: IDLE_1 + - name: Idle1 description: '1.' value: 0 - - name: IDLE_2 + - name: Idle2 description: '2.' value: 1 - - name: IDLE_4 + - name: Idle4 description: '4.' value: 2 - - name: IDLE_8 + - name: Idle8 description: '8.' value: 3 - - name: IDLE_16 + - name: Idle16 description: '16.' value: 4 - - name: IDLE_32 + - name: Idle32 description: '32.' value: 5 - - name: IDLE_64 + - name: Idle64 description: '64.' value: 6 - - name: IDLE_128 + - name: Idle128 description: '128.' value: 7 enum/Ilt: bit_size: 1 variants: - - name: FROM_START + - name: FromStart description: After the start bit. value: 0 - - name: FROM_STOP + - name: FromStop description: After the stop bit. value: 1 enum/Loops: bit_size: 1 variants: - - name: NOFFECT + - name: Noffect description: 'Normal operation: RXD and TXD use separate pins.' value: 0 - - name: LOOPBACK + - name: Loopback description: Loop mode or Single-Wire mode. value: 1 enum/M: bit_size: 1 variants: - - name: DATA8 + - name: Data8 description: 8-bit. value: 0 - - name: DATA9 + - name: Data9 description: 9-bit. value: 1 enum/M7: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: 8-bit to 10-bit. value: 0 - - name: DATA7 + - name: Data7 description: 7-bit. value: 1 enum/Matcfg: bit_size: 2 variants: - - name: ADDR_MATCH + - name: AddrMatch description: Address match wake-up. value: 0 - - name: IDLE_MATCH + - name: IdleMatch description: Idle match wake-up. value: 1 - - name: ONOFF_MATCH + - name: OnoffMatch description: Match on and match off. value: 2 - - name: RWU_MATCH + - name: RwuMatch description: Enables RWU on data match and match on or off for the transmitter CTS input. value: 3 enum/Msbf: bit_size: 1 variants: - - name: LSB_FIRST + - name: LsbFirst description: LSB. value: 0 - - name: MSB_FIRST + - name: MsbFirst description: MSB. value: 1 enum/Pt: bit_size: 1 variants: - - name: EVEN + - name: Even description: Even parity. value: 0 - - name: ODD + - name: Odd description: Odd parity. value: 1 enum/Raf: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle, waiting for a start bit. value: 0 - - name: ACTIVE + - name: Active description: Receiver active (RXD pin input not idle). value: 1 enum/Resyncdis: bit_size: 1 variants: - - name: RESYNC + - name: Resync description: Enable. value: 0 - - name: NO_RESYNC + - name: NoResync description: Disable. value: 1 enum/Rsrc: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: Internal Loopback mode. value: 0 - - name: ONEWIRE + - name: Onewire description: Single-wire mode. value: 1 enum/Rst: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: Not reset. value: 0 - - name: RESET + - name: Reset description: Reset. value: 1 enum/Rwu: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: Normal receiver operation. value: 0 - - name: RX_WAKEUP + - name: RxWakeup description: LPUART receiver in standby, waiting for a wake-up condition. value: 1 enum/Rwuid: bit_size: 1 variants: - - name: IDLE_NOTSET + - name: IdleNotset description: STAT[IDLE] does not become 1. value: 0 - - name: IDLE_SET + - name: IdleSet description: STAT[IDLE] becomes 1. value: 1 enum/Rxfifosize: bit_size: 3 variants: - - name: FIFO_1 + - name: Fifo1 description: '1.' value: 0 - - name: FIFO_4 + - name: Fifo4 description: '4.' value: 1 - - name: FIFO_8 + - name: Fifo8 description: '8.' value: 2 - - name: FIFO_16 + - name: Fifo16 description: '16.' value: 3 - - name: FIFO_32 + - name: Fifo32 description: '32.' value: 4 - - name: FIFO_64 + - name: Fifo64 description: '64.' value: 5 - - name: FIFO_128 + - name: Fifo128 description: '128.' value: 6 - - name: FIFO_256 + - name: Fifo256 description: '256.' value: 7 enum/Rxflush: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: RXFIFO_RST + - name: RxfifoRst description: All data flushed out. value: 1 enum/Rxiden: bit_size: 3 variants: - - name: DISABLED + - name: Disabled description: Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle. value: 0 - - name: IDLE_1 + - name: Idle1 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character. value: 1 - - name: IDLE_2 + - name: Idle2 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters. value: 2 - - name: IDLE_4 + - name: Idle4 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters. value: 3 - - name: IDLE_8 + - name: Idle8 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters. value: 4 - - name: IDLE_16 + - name: Idle16 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters. value: 5 - - name: IDLE_32 + - name: Idle32 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters. value: 6 - - name: IDLE_64 + - name: Idle64 description: Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters. value: 7 enum/Sbk: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: Normal transmitter operation. value: 0 - - name: TX_BREAK + - name: TxBreak description: Queue break character(s) to be sent. value: 1 enum/Sbns: bit_size: 1 variants: - - name: ONE + - name: One description: One stop bit. value: 0 - - name: TWO + - name: Two description: Two stop bits. value: 1 enum/Swap: bit_size: 1 variants: - - name: STANDARD + - name: Standard description: Use the standard way. value: 0 - - name: SWAP + - name: Swap description: Swap. value: 1 enum/Tc: bit_size: 1 variants: - - name: ACTIVE + - name: Active description: Transmitter active. value: 0 - - name: COMPLETE + - name: Complete description: Transmitter idle. value: 1 enum/Tdre: bit_size: 1 variants: - - name: TXDATA + - name: Txdata description: Greater than watermark. value: 0 - - name: NO_TXDATA + - name: NoTxdata description: Equal to or less than watermark. value: 1 enum/Tnp: bit_size: 2 variants: - - name: ONE_SAMPLE + - name: OneSample description: 1 / OSR. value: 0 - - name: TWO_SAMPLE + - name: TwoSample description: 2 / OSR. value: 1 - - name: THREE_SAMPLE + - name: ThreeSample description: 3 / OSR. value: 2 - - name: FOUR_SAMPLE + - name: FourSample description: 4 / OSR. value: 3 enum/Trgsel: bit_size: 2 variants: - - name: DISABLED + - name: Disabled description: Input trigger disabled. value: 0 - - name: TRG_RXD + - name: TrgRxd description: Input trigger used instead of the RXD pin input. value: 1 - - name: TRG_CTS + - name: TrgCts description: Input trigger used instead of the CTS_B pin input. value: 2 - - name: TRG_TXD + - name: TrgTxd description: Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger. value: 3 enum/Txctsc: bit_size: 1 variants: - - name: START + - name: Start description: Sampled at the start of each character. value: 0 - - name: IDLE + - name: Idle description: Sampled when the transmitter is idle. value: 1 enum/Txctssrc: bit_size: 1 variants: - - name: CTS + - name: Cts description: The CTS_B pin. value: 0 - - name: MATCH + - name: Match description: An internal connection to the receiver address match result. value: 1 enum/Txdir: bit_size: 1 variants: - - name: TX_INPUT + - name: TxInput description: Input. value: 0 - - name: TX_OUTPUT + - name: TxOutput description: Output. value: 1 enum/Txfifosize: bit_size: 3 variants: - - name: FIFO_1 + - name: Fifo1 description: '1.' value: 0 - - name: FIFO_4 + - name: Fifo4 description: '4.' value: 1 - - name: FIFO_8 + - name: Fifo8 description: '8.' value: 2 - - name: FIFO_16 + - name: Fifo16 description: '16.' value: 3 - - name: FIFO_32 + - name: Fifo32 description: '32.' value: 4 - - name: FIFO_64 + - name: Fifo64 description: '64.' value: 5 - - name: FIFO_128 + - name: Fifo128 description: '128.' value: 6 - - name: FIFO_256 + - name: Fifo256 description: '256.' value: 7 enum/Txflush: bit_size: 1 variants: - - name: NO_EFFECT + - name: NoEffect description: No effect. value: 0 - - name: TXFIFO_RST + - name: TxfifoRst description: All data flushed out. value: 1 enum/Txrtspol: bit_size: 1 variants: - - name: LOW + - name: Low description: Active low. value: 0 - - name: HIGH + - name: High description: Active high. value: 1 enum/Wake: bit_size: 1 variants: - - name: IDLE + - name: Idle description: Idle. value: 0 - - name: MARK + - name: Mark description: Mark. value: 1 diff --git a/data/metadata/peripherals/mcxa/MBC.yaml b/data/metadata/peripherals/mcxa/MBC.yaml index ddb8e8f..7147e2f 100644 --- a/data/metadata/peripherals/mcxa/MBC.yaml +++ b/data/metadata/peripherals/mcxa/MBC.yaml @@ -641,36 +641,36 @@ fieldset/MemnGlbac7: enum/Mbacsel: bit_size: 3 variants: - - name: GLBAC0 + - name: Glbac0 description: select MBC_MEMN_GLBAC0 access control policy for block B. value: 0 - - name: GLBAC1 + - name: Glbac1 description: select MBC_MEMN_GLBAC1 access control policy for block B. value: 1 - - name: GLBAC2 + - name: Glbac2 description: select MBC_MEMN_GLBAC2 access control policy for block B. value: 2 - - name: GLBAC3 + - name: Glbac3 description: select MBC_MEMN_GLBAC3 access control policy for block B. value: 3 - - name: GLBAC4 + - name: Glbac4 description: select MBC_MEMN_GLBAC4 access control policy for block B. value: 4 - - name: GLBAC5 + - name: Glbac5 description: select MBC_MEMN_GLBAC5 access control policy for block B. value: 5 - - name: GLBAC6 + - name: Glbac6 description: select MBC_MEMN_GLBAC6 access control policy for block B. value: 6 - - name: GLBAC7 + - name: Glbac7 description: select MBC_MEMN_GLBAC7 access control policy for block B. value: 7 enum/Nse: bit_size: 1 variants: - - name: ALLOWED + - name: Allowed description: Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. value: 0 - - name: NOTALLOWED + - name: Notallowed description: Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). value: 1 diff --git a/data/metadata/peripherals/mcxa/MRCC2xx.yaml b/data/metadata/peripherals/mcxa/MRCC2xx.yaml index 5202dad..12cc6f7 100644 --- a/data/metadata/peripherals/mcxa/MRCC2xx.yaml +++ b/data/metadata/peripherals/mcxa/MRCC2xx.yaml @@ -4,7 +4,7 @@ block/Mrcc: - name: mrcc_glb_rst0 description: Peripheral Reset Control 0. byte_offset: 0 - fieldset: MrccGlbRst0 + fieldset: GlbRst0 - name: mrcc_glb_rst0_set description: Peripheral Reset Control Set 0. byte_offset: 4 @@ -18,7 +18,7 @@ block/Mrcc: - name: mrcc_glb_rst1 description: Peripheral Reset Control 1. byte_offset: 16 - fieldset: MrccGlbRst1 + fieldset: GlbRst1 - name: mrcc_glb_rst1_set description: Peripheral Reset Control Set 1. byte_offset: 20 @@ -32,7 +32,7 @@ block/Mrcc: - name: mrcc_glb_rst2 description: Peripheral Reset Control 2. byte_offset: 32 - fieldset: MrccGlbRst2 + fieldset: GlbRst2 - name: mrcc_glb_rst2_set description: Peripheral Reset Control Set 2. byte_offset: 36 @@ -46,7 +46,7 @@ block/Mrcc: - name: mrcc_glb_cc0 description: AHB Clock Control 0. byte_offset: 64 - fieldset: MrccGlbCc0 + fieldset: GlbCc0 - name: mrcc_glb_cc0_set description: AHB Clock Control Set 0. byte_offset: 68 @@ -60,7 +60,7 @@ block/Mrcc: - name: mrcc_glb_cc1 description: AHB Clock Control 1. byte_offset: 80 - fieldset: MrccGlbCc1 + fieldset: GlbCc1 - name: mrcc_glb_cc1_set description: AHB Clock Control Set 1. byte_offset: 84 @@ -74,7 +74,7 @@ block/Mrcc: - name: mrcc_glb_cc2 description: AHB Clock Control 2. byte_offset: 96 - fieldset: MrccGlbCc2 + fieldset: GlbCc2 - name: mrcc_glb_cc2_set description: AHB Clock Control Set 2. byte_offset: 100 @@ -88,15 +88,15 @@ block/Mrcc: - name: mrcc_glb_acc0 description: Control Automatic Clock Gating 0. byte_offset: 128 - fieldset: MrccGlbAcc0 + fieldset: GlbAcc0 - name: mrcc_glb_acc1 description: Control Automatic Clock Gating 1. byte_offset: 132 - fieldset: MrccGlbAcc1 + fieldset: GlbAcc1 - name: mrcc_glb_acc2 description: Control Automatic Clock Gating 2. byte_offset: 136 - fieldset: MrccGlbAcc2 + fieldset: GlbAcc2 - name: mrcc_i3c0_fclk_clksel description: I3C0_FCLK clock selection control. byte_offset: 160 @@ -104,7 +104,7 @@ block/Mrcc: - name: mrcc_i3c0_fclk_clkdiv description: I3C0_FCLK clock divider control. byte_offset: 164 - fieldset: I3cFclkClkdiv + fieldset: Clkdiv - name: mrcc_ctimer0_clksel description: CTIMER0 clock selection control. byte_offset: 168 @@ -112,7 +112,7 @@ block/Mrcc: - name: mrcc_ctimer0_clkdiv description: CTIMER0 clock divider control. byte_offset: 172 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer1_clksel description: CTIMER1 clock selection control. byte_offset: 176 @@ -120,7 +120,7 @@ block/Mrcc: - name: mrcc_ctimer1_clkdiv description: CTIMER1 clock divider control. byte_offset: 180 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer2_clksel description: CTIMER2 clock selection control. byte_offset: 184 @@ -128,7 +128,7 @@ block/Mrcc: - name: mrcc_ctimer2_clkdiv description: CTIMER2 clock divider control. byte_offset: 188 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer3_clksel description: CTIMER3 clock selection control. byte_offset: 192 @@ -136,7 +136,7 @@ block/Mrcc: - name: mrcc_ctimer3_clkdiv description: CTIMER3 clock divider control. byte_offset: 196 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer4_clksel description: CTIMER4 clock selection control. byte_offset: 200 @@ -144,11 +144,11 @@ block/Mrcc: - name: mrcc_ctimer4_clkdiv description: CTIMER4 clock divider control. byte_offset: 204 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_wwdt0_clkdiv description: WWDT0 clock divider control. byte_offset: 212 - fieldset: WwdtClkdiv + fieldset: Clkdiv - name: mrcc_flexio0_clksel description: FLEXIO0 clock selection control. byte_offset: 216 @@ -156,7 +156,7 @@ block/Mrcc: - name: mrcc_flexio0_clkdiv description: FLEXIO0 clock divider control. byte_offset: 220 - fieldset: FlexioClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c0_clksel description: LPI2C0 clock selection control. byte_offset: 224 @@ -164,7 +164,7 @@ block/Mrcc: - name: mrcc_lpi2c0_clkdiv description: LPI2C0 clock divider control. byte_offset: 228 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c1_clksel description: LPI2C1 clock selection control. byte_offset: 232 @@ -172,7 +172,7 @@ block/Mrcc: - name: mrcc_lpi2c1_clkdiv description: LPI2C1 clock divider control. byte_offset: 236 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpspi0_clksel description: LPSPI0 clock selection control. byte_offset: 240 @@ -180,7 +180,7 @@ block/Mrcc: - name: mrcc_lpspi0_clkdiv description: LPSPI0 clock divider control. byte_offset: 244 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi1_clksel description: LPSPI1 clock selection control. byte_offset: 248 @@ -188,7 +188,7 @@ block/Mrcc: - name: mrcc_lpspi1_clkdiv description: LPSPI1 clock divider control. byte_offset: 252 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpuart0_clksel description: LPUART0 clock selection control. byte_offset: 256 @@ -196,7 +196,7 @@ block/Mrcc: - name: mrcc_lpuart0_clkdiv description: LPUART0 clock divider control. byte_offset: 260 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart1_clksel description: LPUART1 clock selection control. byte_offset: 264 @@ -204,7 +204,7 @@ block/Mrcc: - name: mrcc_lpuart1_clkdiv description: LPUART1 clock divider control. byte_offset: 268 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart2_clksel description: LPUART2 clock selection control. byte_offset: 272 @@ -212,7 +212,7 @@ block/Mrcc: - name: mrcc_lpuart2_clkdiv description: LPUART2 clock divider control. byte_offset: 276 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart3_clksel description: LPUART3 clock selection control. byte_offset: 280 @@ -220,7 +220,7 @@ block/Mrcc: - name: mrcc_lpuart3_clkdiv description: LPUART3 clock divider control. byte_offset: 284 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart4_clksel description: LPUART4 clock selection control. byte_offset: 288 @@ -228,7 +228,7 @@ block/Mrcc: - name: mrcc_lpuart4_clkdiv description: LPUART4 clock divider control. byte_offset: 292 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_usb0_clksel description: USB0 clock selection control. byte_offset: 296 @@ -236,7 +236,7 @@ block/Mrcc: - name: mrcc_usb0_clkdiv description: USB0 clock divider control. byte_offset: 300 - fieldset: UsbClkdiv + fieldset: Clkdiv - name: mrcc_lptmr0_clksel description: LPTMR0 clock selection control. byte_offset: 304 @@ -244,7 +244,7 @@ block/Mrcc: - name: mrcc_lptmr0_clkdiv description: LPTMR0 clock divider control. byte_offset: 308 - fieldset: LptmrClkdiv + fieldset: Clkdiv - name: mrcc_ostimer0_clksel description: OSTIMER0 clock selection control. byte_offset: 312 @@ -252,15 +252,15 @@ block/Mrcc: - name: mrcc_adc_clksel description: ADCx clock selection control. byte_offset: 320 - fieldset: MrccAdcClksel + fieldset: AdcClksel - name: mrcc_adc_clkdiv description: ADCx clock divider control. byte_offset: 324 - fieldset: MrccAdcClkdiv + fieldset: Clkdiv - name: mrcc_cmp0_func_clkdiv description: CMP0_FUNC clock divider control. byte_offset: 332 - fieldset: CmpFuncClkdiv + fieldset: Clkdiv - name: mrcc_cmp0_rr_clksel description: CMP0_RR clock selection control. byte_offset: 336 @@ -268,11 +268,11 @@ block/Mrcc: - name: mrcc_cmp0_rr_clkdiv description: CMP0_RR clock divider control. byte_offset: 340 - fieldset: CmpRrClkdiv + fieldset: Clkdiv - name: mrcc_cmp1_func_clkdiv description: CMP1_FUNC clock divider control. byte_offset: 348 - fieldset: CmpFuncClkdiv + fieldset: Clkdiv - name: mrcc_cmp1_rr_clksel description: CMP1_RR clock selection control. byte_offset: 352 @@ -280,11 +280,11 @@ block/Mrcc: - name: mrcc_cmp1_rr_clkdiv description: CMP1_RR clock divider control. byte_offset: 356 - fieldset: CmpRrClkdiv + fieldset: Clkdiv - name: mrcc_cmp2_func_clkdiv description: CMP2_FUNC clock divider control. byte_offset: 364 - fieldset: CmpFuncClkdiv + fieldset: Clkdiv - name: mrcc_cmp2_rr_clksel description: CMP2_RR clock selection control. byte_offset: 368 @@ -292,7 +292,7 @@ block/Mrcc: - name: mrcc_cmp2_rr_clkdiv description: CMP2_RR clock divider control. byte_offset: 372 - fieldset: CmpRrClkdiv + fieldset: Clkdiv - name: mrcc_dac0_clksel description: DAC0 clock selection control. byte_offset: 376 @@ -300,7 +300,7 @@ block/Mrcc: - name: mrcc_dac0_clkdiv description: DAC0 clock divider control. byte_offset: 380 - fieldset: DacClkdiv + fieldset: Clkdiv - name: mrcc_flexcan0_clksel description: FLEXCAN0 clock selection control. byte_offset: 384 @@ -308,7 +308,7 @@ block/Mrcc: - name: mrcc_flexcan0_clkdiv description: FLEXCAN0 clock divider control. byte_offset: 388 - fieldset: FlexcanClkdiv + fieldset: Clkdiv - name: mrcc_flexcan1_clksel description: FLEXCAN1 clock selection control. byte_offset: 392 @@ -316,7 +316,7 @@ block/Mrcc: - name: mrcc_flexcan1_clkdiv description: FLEXCAN1 clock divider control. byte_offset: 396 - fieldset: FlexcanClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c2_clksel description: LPI2C2 clock selection control. byte_offset: 400 @@ -324,7 +324,7 @@ block/Mrcc: - name: mrcc_lpi2c2_clkdiv description: LPI2C2 clock divider control. byte_offset: 404 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c3_clksel description: LPI2C3 clock selection control. byte_offset: 408 @@ -332,7 +332,7 @@ block/Mrcc: - name: mrcc_lpi2c3_clkdiv description: LPI2C3 clock divider control. byte_offset: 412 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpuart5_clksel description: LPUART5 clock selection control. byte_offset: 416 @@ -340,55 +340,41 @@ block/Mrcc: - name: mrcc_lpuart5_clkdiv description: LPUART5 clock divider control. byte_offset: 420 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_dbg_trace_clksel description: DBG_TRACE clock selection control. byte_offset: 424 - fieldset: MrccDbgTraceClksel + fieldset: DbgTraceClksel - name: mrcc_dbg_trace_clkdiv description: DBG_TRACE clock divider control. byte_offset: 428 - fieldset: MrccDbgTraceClkdiv + fieldset: Clkdiv - name: mrcc_clkout_clksel description: CLKOUT clock selection control. byte_offset: 432 - fieldset: MrccClkoutClksel + fieldset: ClkoutClksel - name: mrcc_clkout_clkdiv description: CLKOUT clock divider control. byte_offset: 436 - fieldset: MrccClkoutClkdiv + fieldset: Clkdiv - name: mrcc_systick_clksel description: SYSTICK clock selection control. byte_offset: 440 - fieldset: MrccSystickClksel + fieldset: SystickClksel - name: mrcc_systick_clkdiv description: SYSTICK clock divider control. byte_offset: 444 - fieldset: MrccSystickClkdiv -fieldset/CmpFuncClkdiv: - description: CMP0_FUNC clock divider control. + fieldset: Clkdiv +fieldset/AdcClksel: + description: ADCx clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/CmpRrClkdiv: - description: CMP0_RR clock divider control. + bit_size: 3 + enum: AdcClkselMux +fieldset/Clkdiv: + description: ADCx clock divider control. fields: - name: div description: Functional Clock Divider. @@ -409,6 +395,14 @@ fieldset/CmpRrClkdiv: bit_offset: 31 bit_size: 1 enum: ClkdivUnstab +fieldset/ClkoutClksel: + description: CLKOUT clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: ClkoutClkselMux fieldset/CmpRrClksel: description: CMP0_RR clock selection control. fields: @@ -417,28 +411,6 @@ fieldset/CmpRrClksel: bit_offset: 0 bit_size: 3 enum: RrClkselMux -fieldset/CtimerClkdiv: - description: CTIMER0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/CtimerClksel: description: CTIMER0 clock selection control. fields: @@ -447,28 +419,6 @@ fieldset/CtimerClksel: bit_offset: 0 bit_size: 3 enum: CtimerClkselMux -fieldset/DacClkdiv: - description: DAC0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/DacClksel: description: DAC0 clock selection control. fields: @@ -477,28 +427,14 @@ fieldset/DacClksel: bit_offset: 0 bit_size: 3 enum: DacClkselMux -fieldset/FlexcanClkdiv: - description: FLEXCAN0 clock divider control. +fieldset/DbgTraceClksel: + description: DBG_TRACE clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab + bit_size: 2 + enum: DbgTraceClkselMux fieldset/FlexcanClksel: description: FLEXCAN0 clock selection control. fields: @@ -507,28 +443,6 @@ fieldset/FlexcanClksel: bit_offset: 0 bit_size: 3 enum: FlexcanClkselMux -fieldset/FlexioClkdiv: - description: FLEXIO0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/FlexioClksel: description: FLEXIO0 clock selection control. fields: @@ -537,275 +451,7 @@ fieldset/FlexioClksel: bit_offset: 0 bit_size: 3 enum: FlexioClkselMux -fieldset/GlbCcClr: - description: AHB Clock Control Clear 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_CCn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbCcSet: - description: AHB Clock Control Set 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_CCn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbRstClr: - description: Peripheral Reset Control Clear 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbRstSet: - description: Peripheral Reset Control Set 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. - bit_offset: 0 - bit_size: 32 -fieldset/I3cFclkClkdiv: - description: I3C0_FCLK clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/I3cFclkClksel: - description: I3C0_FCLK clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: FclkClkselMux -fieldset/Lpi2cClkdiv: - description: LPI2C0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/Lpi2cClksel: - description: LPI2C0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: Lpi2cClkselMux -fieldset/LpspiClkdiv: - description: LPSPI0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LpspiClksel: - description: LPSPI0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LpspiClkselMux -fieldset/LptmrClkdiv: - description: LPTMR0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LptmrClksel: - description: LPTMR0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LptmrClkselMux -fieldset/LpuartClkdiv: - description: LPUART0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LpuartClksel: - description: LPUART0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LpuartClkselMux -fieldset/MrccAdcClkdiv: - description: ADCx clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccAdcClksel: - description: ADCx clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: AdcClkselMux -fieldset/MrccClkoutClkdiv: - description: CLKOUT clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccClkoutClksel: - description: CLKOUT clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: ClkoutClkselMux -fieldset/MrccDbgTraceClkdiv: - description: DBG_TRACE clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccDbgTraceClksel: - description: DBG_TRACE clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 2 - enum: DbgTraceClkselMux -fieldset/MrccGlbAcc0: +fieldset/GlbAcc0: description: Control Automatic Clock Gating 0. fields: - name: inputmux0 @@ -872,6 +518,10 @@ fieldset/MrccGlbAcc0: description: ERM0. bit_offset: 15 bit_size: 1 + - name: fmc + description: FMC. + bit_offset: 16 + bit_size: 1 - name: aoi1 description: AOI1. bit_offset: 17 @@ -932,7 +582,7 @@ fieldset/MrccGlbAcc0: description: FLEXPWM0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbAcc1: +fieldset/GlbAcc1: description: Control Automatic Clock Gating 1. fields: - name: flexpwm1 @@ -1051,7 +701,7 @@ fieldset/MrccGlbAcc1: description: ADC3. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbAcc2: +fieldset/GlbAcc2: description: Control Automatic Clock Gating 2. fields: - name: rama @@ -1094,7 +744,7 @@ fieldset/MrccGlbAcc2: description: ROMC. bit_offset: 10 bit_size: 1 -fieldset/MrccGlbCc0: +fieldset/GlbCc0: description: AHB Clock Control 0. fields: - name: inputmux0 @@ -1161,6 +811,10 @@ fieldset/MrccGlbCc0: description: ERM0. bit_offset: 15 bit_size: 1 + - name: fmc + description: FMC. + bit_offset: 16 + bit_size: 1 - name: aoi1 description: AOI1. bit_offset: 17 @@ -1221,7 +875,7 @@ fieldset/MrccGlbCc0: description: FLEXPWM0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbCc1: +fieldset/GlbCc1: description: AHB Clock Control 1. fields: - name: flexpwm1 @@ -1344,7 +998,7 @@ fieldset/MrccGlbCc1: description: ADC3. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbCc2: +fieldset/GlbCc2: description: AHB Clock Control 2. fields: - name: rama @@ -1387,7 +1041,21 @@ fieldset/MrccGlbCc2: description: ROMC. bit_offset: 10 bit_size: 1 -fieldset/MrccGlbRst0: +fieldset/GlbCcClr: + description: AHB Clock Control Clear 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_CCn. + bit_offset: 0 + bit_size: 32 +fieldset/GlbCcSet: + description: AHB Clock Control Set 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_CCn. + bit_offset: 0 + bit_size: 32 +fieldset/GlbRst0: description: Peripheral Reset Control 0. fields: - name: inputmux0 @@ -1510,7 +1178,7 @@ fieldset/MrccGlbRst0: description: FLEXPWM0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbRst1: +fieldset/GlbRst1: description: Peripheral Reset Control 1. fields: - name: flexpwm1 @@ -1617,7 +1285,7 @@ fieldset/MrccGlbRst1: description: ADC3. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbRst2: +fieldset/GlbRst2: description: Peripheral Reset Control 2. fields: - name: gpio0 @@ -1644,36 +1312,60 @@ fieldset/MrccGlbRst2: description: MAU0. bit_offset: 9 bit_size: 1 -fieldset/MrccSystickClkdiv: - description: SYSTICK clock divider control. +fieldset/GlbRstClr: + description: Peripheral Reset Control Clear 0. fields: - - name: div - description: Functional Clock Divider. + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccSystickClksel: - description: SYSTICK clock selection control. + bit_size: 32 +fieldset/GlbRstSet: + description: Peripheral Reset Control Set 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. + bit_offset: 0 + bit_size: 32 +fieldset/I3cFclkClksel: + description: I3C0_FCLK clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 2 - enum: SystickClkselMux + bit_size: 3 + enum: FclkClkselMux +fieldset/Lpi2cClksel: + description: LPI2C0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: Lpi2cClkselMux +fieldset/LpspiClksel: + description: LPSPI0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: LpspiClkselMux +fieldset/LptmrClksel: + description: LPTMR0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: LptmrClkselMux +fieldset/LpuartClksel: + description: LPUART0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: LpuartClkselMux fieldset/OstimerClksel: description: OSTIMER0 clock selection control. fields: @@ -1682,28 +1374,14 @@ fieldset/OstimerClksel: bit_offset: 0 bit_size: 2 enum: OstimerClkselMux -fieldset/UsbClkdiv: - description: USB0 clock divider control. +fieldset/SystickClksel: + description: SYSTICK clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab + bit_size: 2 + enum: SystickClkselMux fieldset/UsbClksel: description: USB0 clock selection control. fields: @@ -1712,319 +1390,297 @@ fieldset/UsbClksel: bit_offset: 0 bit_size: 2 enum: UsbClkselMux -fieldset/WwdtClkdiv: - description: WWDT0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab enum/AdcClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_1 + - name: ClkrootFunc1 description: FRO_HF_GATED. value: 1 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/ClkdivHalt: bit_size: 1 variants: - - name: ON + - name: On description: Divider clock is running. value: 0 - - name: OFF + - name: Off description: Divider clock is stopped. value: 1 enum/ClkdivReset: bit_size: 1 variants: - - name: ON + - name: On description: Divider isn't reset. value: 0 - - name: OFF + - name: Off description: Divider is reset. value: 1 enum/ClkdivUnstab: bit_size: 1 variants: - - name: ON + - name: On description: Divider clock is stable. value: 0 - - name: OFF + - name: Off description: Clock frequency isn't stable. value: 1 enum/ClkoutClkselMux: bit_size: 3 variants: - - name: CLKROOT_12M + - name: Clkroot12m description: FRO_12M. value: 0 - - name: CLKROOT_FIRC_DIV + - name: ClkrootFircDiv description: FRO_HF_DIV. value: 1 - - name: CLKROOT_SOSC + - name: ClkrootSosc description: CLK_IN. value: 2 - - name: CLKROOT_16K + - name: Clkroot16k description: CLK_16K. value: 3 - - name: CLKROOT_SPLL + - name: ClkrootSpll description: PLL1_CLK. value: 5 - - name: CLKROOT_SLOW + - name: ClkrootSlow description: SLOW_CLK. value: 6 enum/CtimerClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_1 + - name: ClkrootFunc1 description: FRO_HF_GATED. value: 1 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_4 + - name: ClkrootFunc4 description: CLK_16K. value: 4 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/DacClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/DbgTraceClkselMux: bit_size: 2 variants: - - name: CLKROOT_CPU + - name: ClkrootCpu description: CPU_CLK. value: 0 - - name: CLKROOT_1M + - name: Clkroot1m description: CLK_1M. value: 1 - - name: CLKROOT_16K + - name: Clkroot16k description: CLK_16K. value: 2 enum/FclkClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/FlexcanClkselMux: bit_size: 3 variants: - - name: CLKROOT_FIRC_GATED + - name: ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: CLKROOT_FIRC_DIV + - name: ClkrootFircDiv description: FRO_HF_DIV. value: 2 - - name: CLKROOT_SOSC + - name: ClkrootSosc description: CLK_IN. value: 3 - - name: CLKROOT_SPLL + - name: ClkrootSpll description: PLL1_CLK. value: 6 enum/FlexioClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_1 + - name: ClkrootFunc1 description: FRO_HF_GATED. value: 1 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/Lpi2cClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LpspiClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LptmrClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LpuartClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_4 + - name: ClkrootFunc4 description: CLK_16K. value: 4 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/OstimerClkselMux: bit_size: 2 variants: - - name: CLKROOT_16K + - name: Clkroot16k description: CLK_16K. value: 0 - - name: CLKROOT_1M + - name: Clkroot1m description: CLK_1M. value: 2 enum/RrClkselMux: bit_size: 3 variants: - - name: CLKROOT_FUNC_0 + - name: ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: CLKROOT_FUNC_2 + - name: ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: CLKROOT_FUNC_3 + - name: ClkrootFunc3 description: CLK_IN. value: 3 - - name: CLKROOT_FUNC_5 + - name: ClkrootFunc5 description: CLK_1M. value: 5 - - name: CLKROOT_FUNC_6 + - name: ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/SystickClkselMux: bit_size: 2 variants: - - name: CLKROOT_CPU + - name: ClkrootCpu description: CPU_CLK. value: 0 - - name: CLKROOT_1M + - name: Clkroot1m description: CLK_1M. value: 1 - - name: CLKROOT_16K + - name: Clkroot16k description: CLK_16K. value: 2 enum/UsbClkselMux: bit_size: 2 variants: - - name: CLKROOT_SPLL + - name: ClkrootSpll description: PLL1_CLK. value: 0 - - name: SCG_SCG_FIRC_48MHZ_CLK + - name: ScgScgFirc48mhzClk description: CLK_48M. value: 1 - - name: CLKROOT_SOSC + - name: ClkrootSosc description: CLK_IN. value: 2 diff --git a/data/metadata/peripherals/mcxa/MRCC5xx.yaml b/data/metadata/peripherals/mcxa/MRCC5xx.yaml index 991f8db..8288355 100644 --- a/data/metadata/peripherals/mcxa/MRCC5xx.yaml +++ b/data/metadata/peripherals/mcxa/MRCC5xx.yaml @@ -4,7 +4,7 @@ block/Mrcc: - name: mrcc_glb_rst0 description: Peripheral Reset Control 0. byte_offset: 0 - fieldset: MrccGlbRst0 + fieldset: GlbRst0 - name: mrcc_glb_rst0_set description: Peripheral Reset Control Set 0. byte_offset: 4 @@ -18,7 +18,7 @@ block/Mrcc: - name: mrcc_glb_rst1 description: Peripheral Reset Control 1. byte_offset: 16 - fieldset: MrccGlbRst1 + fieldset: GlbRst1 - name: mrcc_glb_rst1_set description: Peripheral Reset Control Set 1. byte_offset: 20 @@ -32,7 +32,7 @@ block/Mrcc: - name: mrcc_glb_rst2 description: Peripheral Reset Control 2. byte_offset: 32 - fieldset: MrccGlbRst2 + fieldset: GlbRst2 - name: mrcc_glb_rst2_set description: Peripheral Reset Control Set 2. byte_offset: 36 @@ -46,7 +46,7 @@ block/Mrcc: - name: mrcc_glb_rst3 description: Peripheral Reset Control 3. byte_offset: 48 - fieldset: MrccGlbRst3 + fieldset: GlbRst3 - name: mrcc_glb_rst3_set description: Peripheral Reset Control Set 3. byte_offset: 52 @@ -60,7 +60,7 @@ block/Mrcc: - name: mrcc_glb_rst4 description: Peripheral Reset Control 4. byte_offset: 64 - fieldset: MrccGlbRst4 + fieldset: GlbRst4 - name: mrcc_glb_rst4_set description: Peripheral Reset Control Set 4. byte_offset: 68 @@ -74,7 +74,7 @@ block/Mrcc: - name: mrcc_glb_cc0 description: AHB Clock Control 0. byte_offset: 96 - fieldset: MrccGlbCc0 + fieldset: GlbCc0 - name: mrcc_glb_cc0_set description: AHB Clock Control Set 0. byte_offset: 100 @@ -88,7 +88,7 @@ block/Mrcc: - name: mrcc_glb_cc1 description: AHB Clock Control 1. byte_offset: 112 - fieldset: MrccGlbCc1 + fieldset: GlbCc1 - name: mrcc_glb_cc1_set description: AHB Clock Control Set 1. byte_offset: 116 @@ -102,7 +102,7 @@ block/Mrcc: - name: mrcc_glb_cc2 description: AHB Clock Control 2. byte_offset: 128 - fieldset: MrccGlbCc2 + fieldset: GlbCc2 - name: mrcc_glb_cc2_set description: AHB Clock Control Set 2. byte_offset: 132 @@ -116,7 +116,7 @@ block/Mrcc: - name: mrcc_glb_cc3 description: AHB Clock Control 3. byte_offset: 144 - fieldset: MrccGlbCc3 + fieldset: GlbCc3 - name: mrcc_glb_cc3_set description: AHB Clock Control Set 3. byte_offset: 148 @@ -130,7 +130,7 @@ block/Mrcc: - name: mrcc_glb_cc4 description: AHB Clock Control 4. byte_offset: 160 - fieldset: MrccGlbCc4 + fieldset: GlbCc4 - name: mrcc_glb_cc4_set description: AHB Clock Control Set 4. byte_offset: 164 @@ -144,43 +144,43 @@ block/Mrcc: - name: mrcc_glb_acc0 description: Control Automatic Clock Gating 0. byte_offset: 192 - fieldset: MrccGlbAcc0 + fieldset: GlbAcc0 - name: mrcc_glb_acc1 description: Control Automatic Clock Gating 1. byte_offset: 196 - fieldset: MrccGlbAcc1 + fieldset: GlbAcc1 - name: mrcc_glb_acc2 description: Control Automatic Clock Gating 2. byte_offset: 200 - fieldset: MrccGlbAcc2 + fieldset: GlbAcc2 - name: mrcc_glb_acc3 description: Control Automatic Clock Gating 3. byte_offset: 204 - fieldset: MrccGlbAcc3 + fieldset: GlbAcc3 - name: mrcc_glb_acc4 description: Control Automatic Clock Gating 4. byte_offset: 208 - fieldset: MrccGlbAcc4 + fieldset: GlbAcc4 - name: mrcc_glb_pr0 description: Peripheral Enable Configuration 0. Reset on POR only. byte_offset: 216 - fieldset: MrccGlbPr0 + fieldset: GlbPr0 - name: mrcc_glb_pr1 description: Peripheral Enable Configuration 1. Reset on POR only. byte_offset: 220 - fieldset: MrccGlbPr1 + fieldset: GlbPr1 - name: mrcc_glb_pr2 description: Peripheral Enable Configuration 2. Reset on POR only. byte_offset: 224 - fieldset: MrccGlbPr2 + fieldset: GlbPr2 - name: mrcc_glb_pr3 description: Peripheral Enable Configuration 3. Reset on POR only. byte_offset: 228 - fieldset: MrccGlbPr3 + fieldset: GlbPr3 - name: mrcc_glb_pr4 description: Peripheral Enable Configuration 4. Reset on POR only. byte_offset: 232 - fieldset: MrccGlbPr4 + fieldset: GlbPr4 - name: mrcc_i3c0_fclk_clksel description: I3C0_FCLK clock selection control. byte_offset: 256 @@ -188,7 +188,7 @@ block/Mrcc: - name: mrcc_i3c0_fclk_clkdiv description: I3C0_FCLK clock divider control. byte_offset: 260 - fieldset: I3cFclkClkdiv + fieldset: Clkdiv - name: mrcc_i3c1_fclk_clksel description: I3C1_FCLK clock selection control. byte_offset: 264 @@ -196,7 +196,7 @@ block/Mrcc: - name: mrcc_i3c1_fclk_clkdiv description: I3C1_FCLK clock divider control. byte_offset: 268 - fieldset: I3cFclkClkdiv + fieldset: Clkdiv - name: mrcc_ctimer0_clksel description: CTIMER0 clock selection control. byte_offset: 272 @@ -204,7 +204,7 @@ block/Mrcc: - name: mrcc_ctimer0_clkdiv description: CTIMER0 clock divider control. byte_offset: 276 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer1_clksel description: CTIMER1 clock selection control. byte_offset: 280 @@ -212,7 +212,7 @@ block/Mrcc: - name: mrcc_ctimer1_clkdiv description: CTIMER1 clock divider control. byte_offset: 284 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer2_clksel description: CTIMER2 clock selection control. byte_offset: 288 @@ -220,7 +220,7 @@ block/Mrcc: - name: mrcc_ctimer2_clkdiv description: CTIMER2 clock divider control. byte_offset: 292 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer3_clksel description: CTIMER3 clock selection control. byte_offset: 296 @@ -228,7 +228,7 @@ block/Mrcc: - name: mrcc_ctimer3_clkdiv description: CTIMER3 clock divider control. byte_offset: 300 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_ctimer4_clksel description: CTIMER4 clock selection control. byte_offset: 304 @@ -236,11 +236,11 @@ block/Mrcc: - name: mrcc_ctimer4_clkdiv description: CTIMER4 clock divider control. byte_offset: 308 - fieldset: CtimerClkdiv + fieldset: Clkdiv - name: mrcc_wwdt0_clkdiv description: WWDT0 clock divider control. byte_offset: 316 - fieldset: WwdtClkdiv + fieldset: Clkdiv - name: mrcc_wwdt1_clksel description: WWDT1 clock selection control. byte_offset: 320 @@ -248,7 +248,7 @@ block/Mrcc: - name: mrcc_wwdt1_clkdiv description: WWDT1 clock divider control. byte_offset: 324 - fieldset: WwdtClkdiv + fieldset: Clkdiv - name: mrcc_e1588_clksel description: E1588 clock selection control. byte_offset: 328 @@ -256,15 +256,15 @@ block/Mrcc: - name: mrcc_e1588_clkdiv description: E1588 clock divider control. byte_offset: 332 - fieldset: E158Clkdiv + fieldset: Clkdiv - name: mrcc_rmii_clksel description: RMII clock selection control. byte_offset: 336 - fieldset: MrccRmiiClksel + fieldset: RmiiClksel - name: mrcc_rmii_clkdiv description: RMII clock divider control. byte_offset: 340 - fieldset: MrccRmiiClkdiv + fieldset: Clkdiv - name: mrcc_espi0_clksel description: ESPI0 clock selection control. byte_offset: 344 @@ -272,7 +272,7 @@ block/Mrcc: - name: mrcc_espi0_clkdiv description: ESPI0 clock divider control. byte_offset: 348 - fieldset: EspiClkdiv + fieldset: Clkdiv - name: mrcc_flexspi0_clksel description: FLEXSPI0 clock selection control. byte_offset: 352 @@ -280,7 +280,7 @@ block/Mrcc: - name: mrcc_flexspi0_clkdiv description: FLEXSPI0 clock divider control. byte_offset: 356 - fieldset: FlexspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi2_clksel description: LPSPI2 clock selection control. byte_offset: 360 @@ -288,7 +288,7 @@ block/Mrcc: - name: mrcc_lpspi2_clkdiv description: LPSPI2 clock divider control. byte_offset: 364 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi3_clksel description: LPSPI3 clock selection control. byte_offset: 368 @@ -296,7 +296,7 @@ block/Mrcc: - name: mrcc_lpspi3_clkdiv description: LPSPI3 clock divider control. byte_offset: 372 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi4_clksel description: LPSPI4 clock selection control. byte_offset: 376 @@ -304,7 +304,7 @@ block/Mrcc: - name: mrcc_lpspi4_clkdiv description: LPSPI4 clock divider control. byte_offset: 380 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi5_clksel description: LPSPI5 clock selection control. byte_offset: 384 @@ -312,7 +312,7 @@ block/Mrcc: - name: mrcc_lpspi5_clkdiv description: LPSPI5 clock divider control. byte_offset: 388 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_t1s0_clksel description: T1S0 clock selection control. byte_offset: 392 @@ -320,7 +320,7 @@ block/Mrcc: - name: mrcc_t1s0_clkdiv description: T1S0 clock divider control. byte_offset: 396 - fieldset: T1sClkdiv + fieldset: Clkdiv - name: mrcc_usb1_clksel description: USB1 clock selection control. byte_offset: 400 @@ -332,7 +332,7 @@ block/Mrcc: - name: mrcc_usb1_phy_clkdiv description: USB1_PHY clock divider control. byte_offset: 412 - fieldset: UsbPhyClkdiv + fieldset: Clkdiv - name: mrcc_flexio0_clksel description: FLEXIO0 clock selection control. byte_offset: 416 @@ -340,7 +340,7 @@ block/Mrcc: - name: mrcc_flexio0_clkdiv description: FLEXIO0 clock divider control. byte_offset: 420 - fieldset: FlexioClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c0_clksel description: LPI2C0 clock selection control. byte_offset: 424 @@ -348,7 +348,7 @@ block/Mrcc: - name: mrcc_lpi2c0_clkdiv description: LPI2C0 clock divider control. byte_offset: 428 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c1_clksel description: LPI2C1 clock selection control. byte_offset: 432 @@ -356,7 +356,7 @@ block/Mrcc: - name: mrcc_lpi2c1_clkdiv description: LPI2C1 clock divider control. byte_offset: 436 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpspi0_clksel description: LPSPI0 clock selection control. byte_offset: 440 @@ -364,7 +364,7 @@ block/Mrcc: - name: mrcc_lpspi0_clkdiv description: LPSPI0 clock divider control. byte_offset: 444 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_lpspi1_clksel description: LPSPI1 clock selection control. byte_offset: 448 @@ -372,7 +372,7 @@ block/Mrcc: - name: mrcc_lpspi1_clkdiv description: LPSPI1 clock divider control. byte_offset: 452 - fieldset: LpspiClkdiv + fieldset: Clkdiv - name: mrcc_i3c2_fclk_clksel description: I3C2_FCLK clock selection control. byte_offset: 456 @@ -380,7 +380,7 @@ block/Mrcc: - name: mrcc_i3c2_fclk_clkdiv description: I3C2_FCLK clock divider control. byte_offset: 460 - fieldset: I3cFclkClkdiv + fieldset: Clkdiv - name: mrcc_lpuart0_clksel description: LPUART0 clock selection control. byte_offset: 464 @@ -388,7 +388,7 @@ block/Mrcc: - name: mrcc_lpuart0_clkdiv description: LPUART0 clock divider control. byte_offset: 468 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart1_clksel description: LPUART1 clock selection control. byte_offset: 472 @@ -396,7 +396,7 @@ block/Mrcc: - name: mrcc_lpuart1_clkdiv description: LPUART1 clock divider control. byte_offset: 476 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart2_clksel description: LPUART2 clock selection control. byte_offset: 480 @@ -404,7 +404,7 @@ block/Mrcc: - name: mrcc_lpuart2_clkdiv description: LPUART2 clock divider control. byte_offset: 484 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart3_clksel description: LPUART3 clock selection control. byte_offset: 488 @@ -412,7 +412,7 @@ block/Mrcc: - name: mrcc_lpuart3_clkdiv description: LPUART3 clock divider control. byte_offset: 492 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lpuart4_clksel description: LPUART4 clock selection control. byte_offset: 496 @@ -420,7 +420,7 @@ block/Mrcc: - name: mrcc_lpuart4_clkdiv description: LPUART4 clock divider control. byte_offset: 500 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_lptmr0_clksel description: LPTMR0 clock selection control. byte_offset: 504 @@ -428,7 +428,7 @@ block/Mrcc: - name: mrcc_lptmr0_clkdiv description: LPTMR0 clock divider control. byte_offset: 508 - fieldset: LptmrClkdiv + fieldset: Clkdiv - name: mrcc_ostimer0_clksel description: OSTIMER0 clock selection control. byte_offset: 512 @@ -436,15 +436,15 @@ block/Mrcc: - name: mrcc_adc_clksel description: ADCx clock selection control. byte_offset: 520 - fieldset: MrccAdcClksel + fieldset: AdcClksel - name: mrcc_adc_clkdiv description: ADCx clock divider control. byte_offset: 524 - fieldset: MrccAdcClkdiv + fieldset: Clkdiv - name: mrcc_cmp0_func_clkdiv description: CMP0_FUNC clock divider control. byte_offset: 532 - fieldset: CmpFuncClkdiv + fieldset: Clkdiv - name: mrcc_cmp0_rr_clksel description: CMP0_RR clock selection control. byte_offset: 536 @@ -452,7 +452,7 @@ block/Mrcc: - name: mrcc_cmp0_rr_clkdiv description: CMP0_RR clock divider control. byte_offset: 540 - fieldset: CmpRrClkdiv + fieldset: Clkdiv - name: mrcc_dac0_clksel description: DAC0 clock selection control. byte_offset: 544 @@ -460,7 +460,7 @@ block/Mrcc: - name: mrcc_dac0_clkdiv description: DAC0 clock divider control. byte_offset: 548 - fieldset: DacClkdiv + fieldset: Clkdiv - name: mrcc_dac1_clksel description: DAC1 clock selection control. byte_offset: 552 @@ -468,7 +468,7 @@ block/Mrcc: - name: mrcc_dac1_clkdiv description: DAC1 clock divider control. byte_offset: 556 - fieldset: DacClkdiv + fieldset: Clkdiv - name: mrcc_tsi0_clksel description: TSI0 clock selection control. byte_offset: 560 @@ -476,7 +476,7 @@ block/Mrcc: - name: mrcc_tsi0_clkdiv description: TSI0 clock divider control. byte_offset: 564 - fieldset: TsiClkdiv + fieldset: Clkdiv - name: mrcc_flexcan0_clksel description: FLEXCAN0 clock selection control. byte_offset: 568 @@ -484,7 +484,7 @@ block/Mrcc: - name: mrcc_flexcan0_clkdiv description: FLEXCAN0 clock divider control. byte_offset: 572 - fieldset: FlexcanClkdiv + fieldset: Clkdiv - name: mrcc_flexcan1_clksel description: FLEXCAN1 clock selection control. byte_offset: 576 @@ -492,7 +492,7 @@ block/Mrcc: - name: mrcc_flexcan1_clkdiv description: FLEXCAN1 clock divider control. byte_offset: 580 - fieldset: FlexcanClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c2_clksel description: LPI2C2 clock selection control. byte_offset: 584 @@ -500,7 +500,7 @@ block/Mrcc: - name: mrcc_lpi2c2_clkdiv description: LPI2C2 clock divider control. byte_offset: 588 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c3_clksel description: LPI2C3 clock selection control. byte_offset: 592 @@ -508,7 +508,7 @@ block/Mrcc: - name: mrcc_lpi2c3_clkdiv description: LPI2C3 clock divider control. byte_offset: 596 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpi2c4_clksel description: LPI2C4 clock selection control. byte_offset: 600 @@ -516,7 +516,7 @@ block/Mrcc: - name: mrcc_lpi2c4_clkdiv description: LPI2C4 clock divider control. byte_offset: 604 - fieldset: Lpi2cClkdiv + fieldset: Clkdiv - name: mrcc_lpuart5_clksel description: LPUART5 clock selection control. byte_offset: 608 @@ -524,7 +524,7 @@ block/Mrcc: - name: mrcc_lpuart5_clkdiv description: LPUART5 clock divider control. byte_offset: 612 - fieldset: LpuartClkdiv + fieldset: Clkdiv - name: mrcc_i3c3_fclk_clksel description: I3C3_FCLK clock selection control. byte_offset: 616 @@ -532,55 +532,41 @@ block/Mrcc: - name: mrcc_i3c3_fclk_clkdiv description: I3C3_FCLK clock divider control. byte_offset: 620 - fieldset: I3cFclkClkdiv + fieldset: Clkdiv - name: mrcc_dbg_trace_clksel description: DBG_TRACE clock selection control. byte_offset: 624 - fieldset: MrccDbgTraceClksel + fieldset: DbgTraceClksel - name: mrcc_dbg_trace_clkdiv description: DBG_TRACE clock divider control. byte_offset: 628 - fieldset: MrccDbgTraceClkdiv + fieldset: Clkdiv - name: mrcc_clkout_clksel description: CLKOUT clock selection control. byte_offset: 632 - fieldset: MrccClkoutClksel + fieldset: ClkoutClksel - name: mrcc_clkout_clkdiv description: CLKOUT clock divider control. byte_offset: 636 - fieldset: MrccClkoutClkdiv + fieldset: Clkdiv - name: mrcc_systick_clksel description: SYSTICK clock selection control. byte_offset: 640 - fieldset: MrccSystickClksel + fieldset: SystickClksel - name: mrcc_systick_clkdiv description: SYSTICK clock divider control. byte_offset: 644 - fieldset: MrccSystickClkdiv -fieldset/CmpFuncClkdiv: - description: CMP0_FUNC clock divider control. + fieldset: Clkdiv +fieldset/AdcClksel: + description: ADCx clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/CmpRrClkdiv: - description: CMP0_RR clock divider control. + bit_size: 3 + enum: AdcClkselMux +fieldset/Clkdiv: + description: ADCx clock divider control. fields: - name: div description: Functional Clock Divider. @@ -601,6 +587,14 @@ fieldset/CmpRrClkdiv: bit_offset: 31 bit_size: 1 enum: ClkdivUnstab +fieldset/ClkoutClksel: + description: CLKOUT clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: ClkoutClkselMux fieldset/CmpRrClksel: description: CMP0_RR clock selection control. fields: @@ -609,28 +603,6 @@ fieldset/CmpRrClksel: bit_offset: 0 bit_size: 3 enum: RrClkselMux -fieldset/CtimerClkdiv: - description: CTIMER0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/CtimerClksel: description: CTIMER0 clock selection control. fields: @@ -639,28 +611,6 @@ fieldset/CtimerClksel: bit_offset: 0 bit_size: 3 enum: CtimerClkselMux -fieldset/DacClkdiv: - description: DAC0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/DacClksel: description: DAC0 clock selection control. fields: @@ -669,425 +619,55 @@ fieldset/DacClksel: bit_offset: 0 bit_size: 3 enum: DacClkselMux -fieldset/E158Clkdiv: - description: E1588 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/E158Clksel: - description: E1588 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: E158ClkselMux -fieldset/EspiClkdiv: - description: ESPI0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/EspiClksel: - description: ESPI0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: EspiClkselMux -fieldset/FlexcanClkdiv: - description: FLEXCAN0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/FlexcanClksel: - description: FLEXCAN0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: FlexcanClkselMux -fieldset/FlexioClkdiv: - description: FLEXIO0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/FlexioClksel: - description: FLEXIO0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: FlexioClkselMux -fieldset/FlexspiClkdiv: - description: FLEXSPI0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/FlexspiClksel: - description: FLEXSPI0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: FlexspiClkselMux -fieldset/GlbCcClr: - description: AHB Clock Control Clear 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_CCn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbCcSet: - description: AHB Clock Control Set 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_CCn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbRstClr: - description: Peripheral Reset Control Clear 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. - bit_offset: 0 - bit_size: 32 -fieldset/GlbRstSet: - description: Peripheral Reset Control Set 0. - fields: - - name: data - description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. - bit_offset: 0 - bit_size: 32 -fieldset/I3cFclkClkdiv: - description: I3C0_FCLK clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/I3cFclkClksel: - description: I3C0_FCLK clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: FclkClkselMux -fieldset/Lpi2cClkdiv: - description: LPI2C0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/Lpi2cClksel: - description: LPI2C0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: Lpi2cClkselMux -fieldset/LpspiClkdiv: - description: LPSPI0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LpspiClksel: - description: LPSPI0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LpspiClkselMux -fieldset/LptmrClkdiv: - description: LPTMR0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LptmrClksel: - description: LPTMR0 clock selection control. - fields: - - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LptmrClkselMux -fieldset/LpuartClkdiv: - description: LPUART0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/LpuartClksel: - description: LPUART0 clock selection control. +fieldset/DbgTraceClksel: + description: DBG_TRACE clock selection control. fields: - name: mux - description: Functional Clock Mux Select. - bit_offset: 0 - bit_size: 3 - enum: LpuartClkselMux -fieldset/MrccAdcClkdiv: - description: ADCx clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccAdcClksel: - description: ADCx clock selection control. + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 2 + enum: DbgTraceClkselMux +fieldset/E158Clksel: + description: E1588 clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 bit_size: 3 - enum: AdcClkselMux -fieldset/MrccClkoutClkdiv: - description: CLKOUT clock divider control. + enum: E158ClkselMux +fieldset/EspiClksel: + description: ESPI0 clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccClkoutClksel: - description: CLKOUT clock selection control. + bit_size: 3 + enum: EspiClkselMux +fieldset/FlexcanClksel: + description: FLEXCAN0 clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 bit_size: 3 - enum: ClkoutClkselMux -fieldset/MrccDbgTraceClkdiv: - description: DBG_TRACE clock divider control. + enum: FlexcanClkselMux +fieldset/FlexioClksel: + description: FLEXIO0 clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccDbgTraceClksel: - description: DBG_TRACE clock selection control. + bit_size: 3 + enum: FlexioClkselMux +fieldset/FlexspiClksel: + description: FLEXSPI0 clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 2 - enum: DbgTraceClkselMux -fieldset/MrccGlbAcc0: + bit_size: 3 + enum: FlexspiClkselMux +fieldset/GlbAcc0: description: Control Automatic Clock Gating 0. fields: - name: inputmux0 @@ -1206,7 +786,7 @@ fieldset/MrccGlbAcc0: description: OSTIMER0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbAcc1: +fieldset/GlbAcc1: description: Control Automatic Clock Gating 1. fields: - name: lpspi0 @@ -1281,7 +861,7 @@ fieldset/MrccGlbAcc1: description: TSI0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbAcc2: +fieldset/GlbAcc2: description: Control Automatic Clock Gating 2. fields: - name: i3c0 @@ -1348,7 +928,7 @@ fieldset/MrccGlbAcc2: description: EWM0. bit_offset: 20 bit_size: 1 -fieldset/MrccGlbAcc3: +fieldset/GlbAcc3: description: Control Automatic Clock Gating 3. fields: - name: rama @@ -1387,7 +967,7 @@ fieldset/MrccGlbAcc3: description: SMARTDMA0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbAcc4: +fieldset/GlbAcc4: description: Control Automatic Clock Gating 4. fields: - name: seccon @@ -1422,7 +1002,7 @@ fieldset/MrccGlbAcc4: description: ATX0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbCc0: +fieldset/GlbCc0: description: AHB Clock Control 0. fields: - name: inputmux0 @@ -1541,7 +1121,7 @@ fieldset/MrccGlbCc0: description: OSTIMER0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbCc1: +fieldset/GlbCc1: description: AHB Clock Control 1. fields: - name: lpspi0 @@ -1620,7 +1200,7 @@ fieldset/MrccGlbCc1: description: TSI0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbCc2: +fieldset/GlbCc2: description: AHB Clock Control 2. fields: - name: i3c0 @@ -1687,7 +1267,7 @@ fieldset/MrccGlbCc2: description: EWM0. bit_offset: 20 bit_size: 1 -fieldset/MrccGlbCc3: +fieldset/GlbCc3: description: AHB Clock Control 3. fields: - name: rama @@ -1730,7 +1310,7 @@ fieldset/MrccGlbCc3: description: SMARTDMA0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbCc4: +fieldset/GlbCc4: description: AHB Clock Control 4. fields: - name: seccon @@ -1781,7 +1361,21 @@ fieldset/MrccGlbCc4: description: TCU. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbPr0: +fieldset/GlbCcClr: + description: AHB Clock Control Clear 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_CCn. + bit_offset: 0 + bit_size: 32 +fieldset/GlbCcSet: + description: AHB Clock Control Set 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_CCn. + bit_offset: 0 + bit_size: 32 +fieldset/GlbPr0: description: Peripheral Enable Configuration 0. Reset on POR only. fields: - name: freqme @@ -1896,7 +1490,7 @@ fieldset/MrccGlbPr0: description: OSTIMER0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbPr1: +fieldset/GlbPr1: description: Peripheral Enable Configuration 1. Reset on POR only. fields: - name: lpspi0 @@ -1975,7 +1569,7 @@ fieldset/MrccGlbPr1: description: TSI0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbPr2: +fieldset/GlbPr2: description: Peripheral Enable Configuration 2. Reset on POR only. fields: - name: i3c0 @@ -2042,7 +1636,7 @@ fieldset/MrccGlbPr2: description: EWM0. bit_offset: 20 bit_size: 1 -fieldset/MrccGlbPr3: +fieldset/GlbPr3: description: Peripheral Enable Configuration 3. Reset on POR only. fields: - name: gpio0 @@ -2073,7 +1667,7 @@ fieldset/MrccGlbPr3: description: SMARTDMA0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbPr4: +fieldset/GlbPr4: description: Peripheral Enable Configuration 4. Reset on POR only. fields: - name: seccon @@ -2124,7 +1718,7 @@ fieldset/MrccGlbPr4: description: TCU. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbRst0: +fieldset/GlbRst0: description: Peripheral Reset Control 0. fields: - name: inputmux0 @@ -2235,7 +1829,7 @@ fieldset/MrccGlbRst0: description: OSTIMER0. bit_offset: 31 bit_size: 1 -fieldset/MrccGlbRst1: +fieldset/GlbRst1: description: Peripheral Reset Control 1. fields: - name: lpspi0 @@ -2302,7 +1896,7 @@ fieldset/MrccGlbRst1: description: VREF0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbRst2: +fieldset/GlbRst2: description: Peripheral Reset Control 2. fields: - name: i3c0 @@ -2361,7 +1955,7 @@ fieldset/MrccGlbRst2: description: EWM0. bit_offset: 20 bit_size: 1 -fieldset/MrccGlbRst3: +fieldset/GlbRst3: description: Peripheral Reset Control 3. fields: - name: gpio0 @@ -2388,7 +1982,7 @@ fieldset/MrccGlbRst3: description: SMARTDMA0. bit_offset: 29 bit_size: 1 -fieldset/MrccGlbRst4: +fieldset/GlbRst4: description: Peripheral Reset Control 4. fields: - name: glikey0 @@ -2411,66 +2005,60 @@ fieldset/MrccGlbRst4: description: ATX0. bit_offset: 29 bit_size: 1 -fieldset/MrccRmiiClkdiv: - description: RMII clock divider control. +fieldset/GlbRstClr: + description: Peripheral Reset Control Clear 0. fields: - - name: div - description: Functional Clock Divider. + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccRmiiClksel: - description: RMII clock selection control. + bit_size: 32 +fieldset/GlbRstSet: + description: Peripheral Reset Control Set 0. + fields: + - name: data + description: Data array value, refer to corresponding position in MRCC_GLB_RSTn. + bit_offset: 0 + bit_size: 32 +fieldset/I3cFclkClksel: + description: I3C0_FCLK clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 bit_size: 3 - enum: RmiiClkselMux -fieldset/MrccSystickClkdiv: - description: SYSTICK clock divider control. + enum: FclkClkselMux +fieldset/Lpi2cClksel: + description: LPI2C0 clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab -fieldset/MrccSystickClksel: - description: SYSTICK clock selection control. + bit_size: 3 + enum: Lpi2cClkselMux +fieldset/LpspiClksel: + description: LPSPI0 clock selection control. fields: - name: mux description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 2 - enum: SystickClkselMux + bit_size: 3 + enum: LpspiClkselMux +fieldset/LptmrClksel: + description: LPTMR0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: LptmrClkselMux +fieldset/LpuartClksel: + description: LPUART0 clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 3 + enum: LpuartClkselMux fieldset/OstimerClksel: description: OSTIMER0 clock selection control. fields: @@ -2479,28 +2067,22 @@ fieldset/OstimerClksel: bit_offset: 0 bit_size: 2 enum: OstimerClkselMux -fieldset/T1sClkdiv: - description: T1S0 clock divider control. +fieldset/RmiiClksel: + description: RMII clock selection control. fields: - - name: div - description: Functional Clock Divider. + - name: mux + description: Functional Clock Mux Select. bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab + bit_size: 3 + enum: RmiiClkselMux +fieldset/SystickClksel: + description: SYSTICK clock selection control. + fields: + - name: mux + description: Functional Clock Mux Select. + bit_offset: 0 + bit_size: 2 + enum: SystickClkselMux fieldset/T1sClksel: description: T1S0 clock selection control. fields: @@ -2509,28 +2091,6 @@ fieldset/T1sClksel: bit_offset: 0 bit_size: 3 enum: T1sClkselMux -fieldset/TsiClkdiv: - description: TSI0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/TsiClksel: description: TSI0 clock selection control. fields: @@ -2547,28 +2107,6 @@ fieldset/UsbClksel: bit_offset: 0 bit_size: 2 enum: UsbClkselMux -fieldset/UsbPhyClkdiv: - description: USB1_PHY clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/UsbPhyClksel: description: USB1_PHY clock selection control. fields: @@ -2577,28 +2115,6 @@ fieldset/UsbPhyClksel: bit_offset: 0 bit_size: 2 enum: PhyClkselMux -fieldset/WwdtClkdiv: - description: WWDT0 clock divider control. - fields: - - name: div - description: Functional Clock Divider. - bit_offset: 0 - bit_size: 4 - - name: reset - description: Reset divider counter. - bit_offset: 29 - bit_size: 1 - enum: ClkdivReset - - name: halt - description: Halt divider counter. - bit_offset: 30 - bit_size: 1 - enum: ClkdivHalt - - name: unstab - description: Divider status flag. - bit_offset: 31 - bit_size: 1 - enum: ClkdivUnstab fieldset/WwdtClksel: description: WWDT1 clock selection control. fields: @@ -2610,402 +2126,402 @@ fieldset/WwdtClksel: enum/AdcClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_SIRC_DIV + - name: I0ClkrootSircDiv description: FRO_LF_DIV. value: 0 - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_CLKROOT_USBPFD - description: USB_PFD_CLK. + - name: I4ClkrootUsbpll + description: USB_PLL_CLK. value: 4 - - name: I5_CLKROOT_1M + - name: I5Clkroot1m description: CLK_1M. value: 5 - - name: I6_CLKROOT_SPLL_DIV + - name: I6ClkrootSpllDiv description: PLL1_CLK_DIV. value: 6 enum/ClkdivHalt: bit_size: 1 variants: - - name: ON + - name: On description: Divider clock is running. value: 0 - - name: OFF + - name: Off description: Divider clock is stopped. value: 1 enum/ClkdivReset: bit_size: 1 variants: - - name: ON + - name: On description: Divider isn't reset. value: 0 - - name: OFF + - name: Off description: Divider is reset. value: 1 enum/ClkdivUnstab: bit_size: 1 variants: - - name: ON + - name: On description: Divider clock is stable. value: 0 - - name: OFF + - name: Off description: Clock frequency isn't stable. value: 1 enum/ClkoutClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_12M + - name: I0Clkroot12m description: FRO_12M. value: 0 - - name: I1_CLKROOT_FIRC_DIV + - name: I1ClkrootFircDiv description: FRO_HF_DIV. value: 1 - - name: I2_CLKROOT_SOSC + - name: I2ClkrootSosc description: CLK_IN. value: 2 - - name: I3_CLKROOT_LPOSC + - name: I3ClkrootLposc description: LP_OSC. value: 3 - - name: I5_CLKROOT_SPLL_DIV + - name: I5ClkrootSpllDiv description: PLL1_CLK_DIV. value: 5 - - name: I6_CLKROOT_SLOW + - name: I6ClkrootSlow description: SLOW_CLK. value: 6 enum/CtimerClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_SIRC_DIV + - name: I0ClkrootSircDiv description: FRO_LF_DIV. value: 0 - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_CLKROOT_LPOSC + - name: I4ClkrootLposc description: LP_OSC. value: 4 - - name: I5_CLKROOT_1M + - name: I5Clkroot1m description: CLK_1M. value: 5 - - name: I6_CLKROOT_SPLL_DIV + - name: I6ClkrootSpllDiv description: PLL1_CLK_DIV. value: 6 enum/DacClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/DbgTraceClkselMux: bit_size: 2 variants: - - name: I0_CLKROOT_CPU_ALIAS + - name: I0ClkrootCpuAlias description: CPU_CLK. value: 0 - - name: I1_CLKROOT_1M + - name: I1Clkroot1m description: CLK_1M. value: 1 - - name: I2_CLKROOT_16K + - name: I2Clkroot16k description: CLK_16K. value: 2 enum/E158ClkselMux: bit_size: 3 variants: - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_IPP__ENET0__CLK_TX_I + - name: I4IppEnet0ClkTxI description: ENET0_TX_CLK. value: 4 - - name: I6_CLKROOT_SPLL + - name: I6ClkrootSpll description: PLL1_CLK. value: 6 enum/EspiClkselMux: bit_size: 3 variants: - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_CLKROOT_USBPLL + - name: I4ClkrootUsbpll description: USB_PLL_CLK. value: 4 - - name: I6_CLKROOT_SPLL_DIV + - name: I6ClkrootSpllDiv description: PLL1_CLK_DIV. value: 6 enum/FclkClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/FlexcanClkselMux: bit_size: 3 variants: - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I2_CLKROOT_FIRC_DIV + - name: I2ClkrootFircDiv description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_CLKROOT_USBPLL + - name: I4ClkrootUsbpll description: USB_PLL_CLK. value: 4 - - name: I6_CLKROOT_SPLL + - name: I6ClkrootSpll description: PLL1_CLK. value: 6 enum/FlexioClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I1_CLKROOT_FUNC_1 + - name: I1ClkrootFunc1 description: FRO_HF_GATED. value: 1 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/FlexspiClkselMux: bit_size: 3 variants: - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I4_CLKROOT_USBPFD + - name: I4ClkrootUsbpfd description: USB_PFD_CLK. value: 4 - - name: I6_CLKROOT_SPLL + - name: I6ClkrootSpll description: PLL1_CLK. value: 6 enum/Lpi2cClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LpspiClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LptmrClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/LpuartClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_SIRC_DIV + - name: I0ClkrootSircDiv description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FIRC_DIV + - name: I2ClkrootFircDiv description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I4_CLKROOT_LPOSC + - name: I4ClkrootLposc description: LP_OSC. value: 4 - - name: I5_CLKROOT_1M + - name: I5Clkroot1m description: CLK_1M. value: 5 - - name: I6_CLKROOT_SPLL_DIV + - name: I6ClkrootSpllDiv description: PLL1_CLK_DIV. value: 6 enum/OstimerClkselMux: bit_size: 2 variants: - - name: I0_CLKROOT_16K + - name: I0Clkroot16k description: CLK_16K. value: 0 - - name: I1_CLKROOT_32K + - name: I1Clkroot32k description: CLK_32K. value: 1 - - name: I2_CLKROOT_1M + - name: I2Clkroot1m description: CLK_1M. value: 2 enum/PhyClkselMux: bit_size: 2 variants: - - name: I1_CLKROOT_FIRC_GATED + - name: I1ClkrootFircGated description: FRO_HF_GATED. value: 1 - - name: I2_CLKROOT_SOSC + - name: I2ClkrootSosc description: CLK_IN. value: 2 enum/RmiiClkselMux: bit_size: 3 variants: - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I6_CLKROOT_SPLL + - name: I6ClkrootSpll description: PLL1_CLK. value: 6 enum/RrClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/SystickClkselMux: bit_size: 2 variants: - - name: I0_CLKROOT_CPU + - name: I0ClkrootCpu description: CPU_CLK. value: 0 - - name: I1_CLKROOT_1M + - name: I1Clkroot1m description: CLK_1M. value: 1 - - name: I2_CLKROOT_16K + - name: I2Clkroot16k description: CLK_16K. value: 2 enum/T1sClkselMux: bit_size: 3 variants: - - name: I3_CLKROOT_SOSC + - name: I3ClkrootSosc description: CLK_IN. value: 3 - - name: I6_CLKROOT_SPLL + - name: I6ClkrootSpll description: PLL1_CLK. value: 6 enum/TsiClkselMux: bit_size: 3 variants: - - name: I0_CLKROOT_FUNC_0 + - name: I0ClkrootFunc0 description: FRO_LF_DIV. value: 0 - - name: I2_CLKROOT_FUNC_2 + - name: I2ClkrootFunc2 description: FRO_HF_DIV. value: 2 - - name: I3_CLKROOT_FUNC_3 + - name: I3ClkrootFunc3 description: CLK_IN. value: 3 - - name: I5_CLKROOT_FUNC_5 + - name: I5ClkrootFunc5 description: CLK_1M. value: 5 - - name: I6_CLKROOT_FUNC_6 + - name: I6ClkrootFunc6 description: PLL1_CLK_DIV. value: 6 enum/UsbClkselMux: bit_size: 2 variants: - - name: I0_CLKROOT_32K + - name: I0Clkroot32k description: CLK_32K. value: 0 - - name: I1_CLKROOT_1M + - name: I1Clkroot1m description: CLK_1M. value: 1 - - name: I2_CLK__USBHS0_PHY__CLK_XTAL + - name: I2ClkUsbhs0PhyClkXtal description: CLK__usbhs0_phy__clk_xtal. value: 2 enum/WwdtClkselMux: bit_size: 2 variants: - - name: I0_CLKROOT_16K + - name: I0Clkroot16k description: CLK_16K. value: 0 - - name: I1_CLKROOT_FIRC_DIV + - name: I1ClkrootFircDiv description: FRO_HF_DIV. value: 1 - - name: I2_CLKROOT_1M + - name: I2Clkroot1m description: CLK_1M. value: 2 - - name: I3_CLKROOT_1M + - name: I3Clkroot1m description: CLK_1M. value: 3 diff --git a/data/metadata/peripherals/mcxa/OSTIMER.yaml b/data/metadata/peripherals/mcxa/OSTIMER.yaml index 6ae97a6..651e6cb 100644 --- a/data/metadata/peripherals/mcxa/OSTIMER.yaml +++ b/data/metadata/peripherals/mcxa/OSTIMER.yaml @@ -90,7 +90,3 @@ fieldset/OseventCtrl: description: EVTimer Match Write Ready. bit_offset: 2 bit_size: 1 - - name: debug_en - description: Debug Enable. - bit_offset: 3 - bit_size: 1 diff --git a/data/metadata/peripherals/mcxa/PORT.yaml b/data/metadata/peripherals/mcxa/PORT.yaml index 92a088d..dfc7265 100644 --- a/data/metadata/peripherals/mcxa/PORT.yaml +++ b/data/metadata/peripherals/mcxa/PORT.yaml @@ -1,5 +1,5 @@ block/Port: - description: PORT. + description: Port Control. items: - name: verid description: Version ID. @@ -18,14 +18,6 @@ block/Port: description: Configuration. byte_offset: 32 fieldset: Config - - name: calib0 - description: Calibration 0. - byte_offset: 96 - fieldset: Calib0 - - name: calib1 - description: Calibration 1. - byte_offset: 100 - fieldset: Calib1 - name: pcr description: Pin Control 0. array: @@ -33,28 +25,6 @@ block/Port: stride: 4 byte_offset: 128 fieldset: Pcr -fieldset/Calib0: - description: Calibration 0. - fields: - - name: ncal - description: Calibration of NMOS Output Driver. - bit_offset: 0 - bit_size: 6 - - name: pcal - description: Calibration of PMOS Output Driver. - bit_offset: 16 - bit_size: 6 -fieldset/Calib1: - description: Calibration 1. - fields: - - name: ncal - description: Calibration of NMOS Output Driver. - bit_offset: 0 - bit_size: 6 - - name: pcal - description: Calibration of PMOS Output Driver. - bit_offset: 16 - bit_size: 6 fieldset/Config: description: Configuration. fields: @@ -160,127 +130,127 @@ fieldset/Verid: enum/Dse: bit_size: 1 variants: - - name: DSE0 + - name: Dse0 description: Low. value: 0 - - name: DSE1 + - name: Dse1 description: High. value: 1 enum/Feature: bit_size: 16 variants: - - name: FEATURE0 + - name: Feature0 description: Basic implementation. value: 0 enum/Gpwe: bit_size: 1 variants: - - name: GPWE0 + - name: Gpwe0 description: Not updated. value: 0 - - name: GPWE1 + - name: Gpwe1 description: Updated. value: 1 enum/Ibe: bit_size: 1 variants: - - name: IBE0 + - name: Ibe0 description: Disables. value: 0 - - name: IBE1 + - name: Ibe1 description: Enables. value: 1 enum/Inv: bit_size: 1 variants: - - name: INV0 + - name: Inv0 description: Does not invert. value: 0 - - name: INV1 + - name: Inv1 description: Inverts. value: 1 enum/Lk: bit_size: 1 variants: - - name: LK0 + - name: Lk0 description: Does not lock. value: 0 - - name: LK1 + - name: Lk1 description: Locks. value: 1 enum/Mux: bit_size: 4 variants: - - name: MUX0 + - name: Mux0 value: 0 - - name: MUX1 + - name: Mux1 value: 1 - - name: MUX2 + - name: Mux2 value: 2 - - name: MUX3 + - name: Mux3 value: 3 - - name: MUX4 + - name: Mux4 value: 4 - - name: MUX5 + - name: Mux5 value: 5 - - name: MUX6 + - name: Mux6 value: 6 - - name: MUX7 + - name: Mux7 value: 7 - - name: MUX8 + - name: Mux8 value: 8 - - name: MUX9 + - name: Mux9 value: 9 - - name: MUX10 + - name: Mux10 value: 10 - - name: MUX11 + - name: Mux11 value: 11 - - name: MUX12 + - name: Mux12 value: 12 - - name: MUX13 + - name: Mux13 value: 13 enum/Ode: bit_size: 1 variants: - - name: ODE0 + - name: Ode0 description: Disables. value: 0 - - name: ODE1 + - name: Ode1 description: Enables. value: 1 enum/Pe: bit_size: 1 variants: - - name: PE0 + - name: Pe0 description: Disables. value: 0 - - name: PE1 + - name: Pe1 description: Enables. value: 1 enum/Ps: bit_size: 1 variants: - - name: PS0 + - name: Ps0 description: Enables internal pulldown resistor. value: 0 - - name: PS1 + - name: Ps1 description: Enables internal pullup resistor. value: 1 enum/Range: bit_size: 1 variants: - - name: RANGE0 + - name: Range0 description: 1.71 V-3.6 V. value: 0 - - name: RANGE1 + - name: Range1 description: 2.70 V-3.6 V. value: 1 enum/Sre: bit_size: 1 variants: - - name: SRE0 + - name: Sre0 description: Fast. value: 0 - - name: SRE1 + - name: Sre1 description: Slow. value: 1 diff --git a/data/metadata/peripherals/mcxa/RTC2xx.yaml b/data/metadata/peripherals/mcxa/RTC2xx.yaml index ca0cc44..2e7bb59 100644 --- a/data/metadata/peripherals/mcxa/RTC2xx.yaml +++ b/data/metadata/peripherals/mcxa/RTC2xx.yaml @@ -131,7 +131,6 @@ fieldset/Tcr: description: Time Compensation Register. bit_offset: 0 bit_size: 8 - enum: TcrVal - name: cir description: Compensation Interval Register. bit_offset: 8 @@ -161,114 +160,90 @@ fieldset/Tsr: enum/Crl: bit_size: 1 variants: - - name: CRL_0 + - name: Crl0 description: Control Register is locked and writes are ignored. value: 0 - - name: CRL_1 + - name: Crl1 description: Control Register is not locked and writes complete as normal. value: 1 enum/Lpos: bit_size: 1 variants: - - name: LPOS_0 + - name: Lpos0 description: RTC prescaler increments using 32.768 kHz clock. value: 0 - - name: LPOS_1 + - name: Lpos1 description: RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. value: 1 enum/Lrl: bit_size: 1 variants: - - name: LRL_0 + - name: Lrl0 description: Lock Register is locked and writes are ignored. value: 0 - - name: LRL_1 + - name: Lrl1 description: Lock Register is not locked and writes complete as normal. value: 1 enum/Srl: bit_size: 1 variants: - - name: SRL_0 + - name: Srl0 description: Status Register is locked and writes are ignored. value: 0 - - name: SRL_1 + - name: Srl1 description: Status Register is not locked and writes complete as normal. value: 1 enum/Swr: bit_size: 1 variants: - - name: SWR_0 + - name: Swr0 description: No effect. value: 0 - - name: SWR_1 + - name: Swr1 description: Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. value: 1 enum/Tcl: bit_size: 1 variants: - - name: TCL_0 + - name: Tcl0 description: Time Compensation Register is locked and writes are ignored. value: 0 - - name: TCL_1 + - name: Tcl1 description: Time Compensation Register is not locked and writes complete as normal. value: 1 -enum/TcrVal: - bit_size: 8 - variants: - - name: TCR_0 - description: Time Prescaler Register overflows every 32768 clock cycles. - value: 0 - - name: TCR_1 - description: Time Prescaler Register overflows every 32767 clock cycles. - value: 1 - - name: TCR_126 - description: Time Prescaler Register overflows every 32642 clock cycles. - value: 126 - - name: TCR_127 - description: Time Prescaler Register overflows every 32641 clock cycles. - value: 127 - - name: TCR_128 - description: Time Prescaler Register overflows every 32896 clock cycles. - value: 128 - - name: TCR_129 - description: Time Prescaler Register overflows every 32895 clock cycles. - value: 129 - - name: TCR_255 - description: Time Prescaler Register overflows every 32769 clock cycles. - value: 255 enum/Tsic: bit_size: 3 variants: - - name: TSIC_0 + - name: Tsic0 description: 1 Hz. value: 0 - - name: TSIC_1 + - name: Tsic1 description: 2 Hz. value: 1 - - name: TSIC_2 + - name: Tsic2 description: 4 Hz. value: 2 - - name: TSIC_3 + - name: Tsic3 description: 8 Hz. value: 3 - - name: TSIC_4 + - name: Tsic4 description: 16 Hz. value: 4 - - name: TSIC_5 + - name: Tsic5 description: 32 Hz. value: 5 - - name: TSIC_6 + - name: Tsic6 description: 64 Hz. value: 6 - - name: TSIC_7 + - name: Tsic7 description: 128 Hz. value: 7 enum/Um: bit_size: 1 variants: - - name: UM_0 + - name: Um0 description: Registers cannot be written when locked. value: 0 - - name: UM_1 + - name: Um1 description: Registers can be written when locked under limited conditions. value: 1 diff --git a/data/metadata/peripherals/mcxa/RTC5xx.yaml b/data/metadata/peripherals/mcxa/RTC5xx.yaml index 649bd26..ebe9096 100644 --- a/data/metadata/peripherals/mcxa/RTC5xx.yaml +++ b/data/metadata/peripherals/mcxa/RTC5xx.yaml @@ -66,11 +66,11 @@ block/Rtc: byte_offset: 22 bit_size: 16 fieldset: Ier - - name: alm_subseconds - description: Sub Second Alarm. - byte_offset: 30 + - name: cntdwn_timer + description: Minutes Count Down Timer. + byte_offset: 24 bit_size: 16 - fieldset: AlmSubseconds + fieldset: CntdwnTimer - name: dst_hour description: Daylight Saving Hour. byte_offset: 34 @@ -91,6 +91,53 @@ block/Rtc: byte_offset: 40 bit_size: 16 fieldset: Compen + - name: tamper_qscr + description: Tamper Queue Status and Control. + byte_offset: 46 + bit_size: 16 + fieldset: TamperQscr + - name: ttsr_year + description: Tamper Time Stamp Year. + byte_offset: 48 + access: Read + bit_size: 16 + fieldset: TtsrYear + - name: tamper_scr + description: Tamper Status and Control. + byte_offset: 50 + bit_size: 16 + fieldset: TamperScr + - name: filter01_cfg + description: Tamper 01 Filter Configuration. + byte_offset: 52 + bit_size: 16 + fieldset: Filter01Cfg + - name: filter23_cfg + description: Tamper 23 Filter Configuration. + byte_offset: 54 + bit_size: 16 + fieldset: Filter23Cfg + - name: filter45_cfg + description: Tamper 05 Filter Configuration. + byte_offset: 56 + bit_size: 16 + fieldset: Filter45Cfg + - name: filter67_cfg + description: Tamper 67 Filter Configuration. + byte_offset: 58 + bit_size: 16 + fieldset: Filter67Cfg + - name: tamper_queue + description: Tamper Queue. + byte_offset: 64 + access: Read + bit_size: 16 + fieldset: TamperQueue + - name: ctrl2 + description: Control 2. + byte_offset: 66 + bit_size: 16 + fieldset: Ctrl2 fieldset/AlmDays: description: Days Alarm. bit_size: 16 @@ -127,14 +174,6 @@ fieldset/AlmSeconds: description: Increment Seconds Counter by 1. bit_offset: 9 bit_size: 1 -fieldset/AlmSubseconds: - description: Sub Second Alarm. - bit_size: 16 - fields: - - name: alm_subsecs - description: Alarm Sub Second Counter Value. - bit_offset: 0 - bit_size: 16 fieldset/AlmYearmon: description: Year and Months Alarm. bit_size: 16 @@ -147,6 +186,14 @@ fieldset/AlmYearmon: description: Year Value for Alarm. bit_offset: 8 bit_size: 8 +fieldset/CntdwnTimer: + description: Minutes Count Down Timer. + bit_size: 16 + fields: + - name: count_down_timer + description: Count Down Timer Value. + bit_offset: 0 + bit_size: 8 fieldset/Compen: description: Compensation. bit_size: 16 @@ -171,14 +218,15 @@ fieldset/Ctrl: description: Alarm Match. bit_offset: 2 bit_size: 2 - - name: alm_subsecs_match_en - description: Alarm Subseconds Match Enable Signal. - bit_offset: 5 - bit_size: 1 - name: dst_en description: Daylight Saving Enable. bit_offset: 6 bit_size: 1 + - name: bcd_en + description: BCD Mode Enable. + bit_offset: 7 + bit_size: 1 + enum: BcdEn - name: swr description: Software Reset. bit_offset: 8 @@ -196,6 +244,24 @@ fieldset/Ctrl: description: RTC Clock Output Selection. bit_offset: 13 bit_size: 2 +fieldset/Ctrl2: + description: Control 2. + bit_size: 16 + fields: + - name: tamp_cfg_over + description: Tamper Configuration Over. + bit_offset: 0 + bit_size: 1 + - name: wakeup_status + description: Wakeup Status. + bit_offset: 5 + bit_size: 2 + enum: WakeupStatus + - name: wakeup_mode + description: Wakeup Mode. + bit_offset: 7 + bit_size: 1 + enum: WakeupMode fieldset/Days: description: Days and Day-of-Week Counters. bit_size: 16 @@ -244,6 +310,142 @@ fieldset/DstMonth: description: Daylight Saving Time (DST) Month Start Value. bit_offset: 8 bit_size: 4 +fieldset/Filter01Cfg: + description: Tamper 01 Filter Configuration. + bit_size: 16 + fields: + - name: fil_dur1 + description: Tamper Detect Bit 1 Filter Duration. + bit_offset: 0 + bit_size: 4 + enum: FilDur1 + - name: clk_sel1 + description: Tamper Filter 1 Clock Select. + bit_offset: 4 + bit_size: 3 + enum: ClkSel1 + - name: pol1 + description: Tamper Detect Input Bit 1 Polarity Control. + bit_offset: 7 + bit_size: 1 + enum: Pol1 + - name: fil_dur0 + description: Tamper Detect Bit 0 Filter Duration. + bit_offset: 8 + bit_size: 4 + enum: FilDur0 + - name: clk_sel0 + description: Tamper Filter 0 Clock Select. + bit_offset: 12 + bit_size: 3 + enum: ClkSel0 + - name: pol0 + description: Tamper Detect Input Bit 0 Polarity Control. + bit_offset: 15 + bit_size: 1 + enum: Pol0 +fieldset/Filter23Cfg: + description: Tamper 23 Filter Configuration. + bit_size: 16 + fields: + - name: fil_dur3 + description: Tamper Detect Bit 3 Filter Duration. + bit_offset: 0 + bit_size: 4 + enum: FilDur3 + - name: clk_sel3 + description: Tamper Filter 3 Clock Select. + bit_offset: 4 + bit_size: 3 + enum: ClkSel3 + - name: pol3 + description: Tamper Detect Input Bit 3 Polarity Control. + bit_offset: 7 + bit_size: 1 + enum: Pol3 + - name: fil_dur2 + description: Tamper Detect Bit 2 Filter Duration. + bit_offset: 8 + bit_size: 4 + enum: FilDur2 + - name: clk_sel2 + description: Tamper Filter 2 Clock Select. + bit_offset: 12 + bit_size: 3 + enum: ClkSel2 + - name: pol2 + description: Tamper Detect Input Bit 2 Polarity Control. + bit_offset: 15 + bit_size: 1 + enum: Pol2 +fieldset/Filter45Cfg: + description: Tamper 05 Filter Configuration. + bit_size: 16 + fields: + - name: fil_dur5 + description: Tamper Detect Bit 5 Filter Duration. + bit_offset: 0 + bit_size: 4 + enum: FilDur5 + - name: clk_sel5 + description: Tamper Filter 5 Clock Select. + bit_offset: 4 + bit_size: 3 + enum: ClkSel5 + - name: pol5 + description: Tamper Detect Input Bit 5 Polarity Control. + bit_offset: 7 + bit_size: 1 + enum: Pol5 + - name: fil_dur4 + description: Tamper Detect Bit 4 Filter Duration. + bit_offset: 8 + bit_size: 4 + enum: FilDur4 + - name: clk_sel4 + description: Tamper Filter 4 Clock Select. + bit_offset: 12 + bit_size: 3 + enum: ClkSel4 + - name: pol4 + description: Tamper Detect Input Bit 4 Polarity Control. + bit_offset: 15 + bit_size: 1 + enum: Pol4 +fieldset/Filter67Cfg: + description: Tamper 67 Filter Configuration. + bit_size: 16 + fields: + - name: fil_dur7 + description: Tamper Detect Bit 7 Filter Duration. + bit_offset: 0 + bit_size: 4 + enum: FilDur7 + - name: clk_sel7 + description: Tamper Filter 7 Clock Select. + bit_offset: 4 + bit_size: 3 + enum: ClkSel7 + - name: pol7 + description: Tamper Detect Input Bit 7 Polarity Control. + bit_offset: 7 + bit_size: 1 + enum: Pol7 + - name: fil_dur6 + description: Tamper Detect Bit 6 Filter Duration. + bit_offset: 8 + bit_size: 4 + enum: FilDur6 + - name: clk_sel6 + description: Tamper Filter 6 Clock Select. + bit_offset: 12 + bit_size: 3 + enum: ClkSel6 + - name: pol6 + description: Tamper Detect Input Bit 6 Polarity Control. + bit_offset: 15 + bit_size: 1 + enum: Pol6 fieldset/Hourmin: description: Hours and Minutes Counters. bit_size: 16 @@ -260,6 +462,14 @@ fieldset/Ier: description: Interrupt Enable. bit_size: 16 fields: + - name: tamper_ie + description: Tamper Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: cnt_dn_timeout_ie + description: Count Down Timer Timeout Interrupt Enable. + bit_offset: 1 + bit_size: 1 - name: alm_ie description: Alarm Interrupt Enable. bit_offset: 2 @@ -320,6 +530,14 @@ fieldset/Isr: description: Interrupt Status. bit_size: 16 fields: + - name: tamper_is + description: Tamper Interrupt Status. + bit_offset: 0 + bit_size: 1 + - name: cnt_dn_timeout_is + description: Count Down Timer Timeout Interrupt Status. + bit_offset: 1 + bit_size: 1 - name: alm_is description: Alarm Interrupt Status. bit_offset: 2 @@ -396,6 +614,11 @@ fieldset/Status: description: Write Protect Enable Status. bit_offset: 1 bit_size: 1 + - name: dwn_cntr_inval_bit + description: Down Counter Invalidate Read/Write Access. + bit_offset: 4 + bit_size: 1 + enum: DwnCntrInvalBit - name: cmp_int description: Compensation Interval. bit_offset: 5 @@ -413,6 +636,61 @@ fieldset/Status: description: Compensation Done. bit_offset: 11 bit_size: 1 +fieldset/TamperQscr: + description: Tamper Queue Status and Control. + bit_size: 16 + fields: + - name: q_full + description: Q_FULL. + bit_offset: 0 + bit_size: 1 + - name: q_full_int_en + description: Q_FULL_INT_EN. + bit_offset: 1 + bit_size: 1 + - name: q_clear + description: Q_CLEAR. + bit_offset: 2 + bit_size: 1 + - name: lfsr_clk_sel + description: LFSR_CLK_SEL. + bit_offset: 8 + bit_size: 3 + enum: LfsrClkSel + - name: lfsr_duration + description: LFSR_DURATION. + bit_offset: 12 + bit_size: 4 +fieldset/TamperQueue: + description: Tamper Queue. + bit_size: 16 + fields: + - name: tamper_data + description: Tamper type stamp and pin number information register. + bit_offset: 0 + bit_size: 16 +fieldset/TamperScr: + description: Tamper Status and Control. + bit_size: 16 + fields: + - name: tmpr_en + description: Tamper Control. + bit_offset: 0 + bit_size: 4 + enum: TmprEn + - name: tmpr_sts + description: Tamper Status. + bit_offset: 8 + bit_size: 4 + enum: TmprSts +fieldset/TtsrYear: + description: Tamper Time Stamp Year. + bit_size: 16 + fields: + - name: ts_yrofst + description: Year Value for Tamper Time Stamp. + bit_offset: 8 + bit_size: 8 fieldset/Yearmon: description: Year and Month Counters. bit_size: 16 @@ -425,21 +703,585 @@ fieldset/Yearmon: description: Year Offset Count Value. bit_offset: 8 bit_size: 8 +enum/BcdEn: + bit_size: 1 + variants: + - name: BinaryMode + description: Binary mode. + value: 0 + - name: BcdMode + description: BCD mode. + value: 1 enum/BusErr: bit_size: 1 variants: - - name: NORMAL + - name: Normal description: Read and write accesses are normal. value: 0 - - name: ASSERTED + - name: Asserted description: Read or write accesses occurred when STATUS[INVAL_BIT] was asserted. value: 1 +enum/ClkSel0: + bit_size: 3 + variants: + - name: Clk32khz + description: 32/16 kHz clock. + value: 0 + - name: Clk512hz + description: 512 Hz clock. + value: 1 + - name: Clk128hz + description: 128 Hz clock. + value: 2 + - name: Clk64hz + description: 64 Hz clock. + value: 3 + - name: Clk16hz + description: 16 Hz clock. + value: 4 + - name: Clk8hz + description: 8 Hz clock. + value: 5 + - name: Clk4hz + description: 4 Hz clock. + value: 6 + - name: Clk2hz + description: 2 Hz clock. + value: 7 +enum/ClkSel1: + bit_size: 3 + variants: + - name: Clk32khz + description: 32/16 kHz clock. + value: 0 + - name: Clk512hz + description: 512 Hz clock. + value: 1 + - name: Clk128hz + description: 128 Hz clock. + value: 2 + - name: Clk64hz + description: 64 Hz clock. + value: 3 + - name: Clk16hz + description: 16 Hz clock. + value: 4 + - name: Clk8hz + description: 8 Hz clock. + value: 5 + - name: Clk4hz + description: 4 Hz clock. + value: 6 + - name: Clk2hz + description: 2 Hz clock. + value: 7 +enum/ClkSel2: + bit_size: 3 + variants: + - name: Clk32khz + description: 32/16 kHz clock. + value: 0 + - name: Clk512hz + description: 512 Hz clock. + value: 1 + - name: Clk128hz + description: 128 Hz clock. + value: 2 + - name: Clk64hz + description: 64 Hz clock. + value: 3 + - name: Clk16hz + description: 16 Hz clock. + value: 4 + - name: Clk8hz + description: 8 Hz clock. + value: 5 + - name: Clk4hz + description: 4 Hz clock. + value: 6 + - name: Clk2hz + description: 2 Hz clock. + value: 7 +enum/ClkSel3: + bit_size: 3 + variants: + - name: Clk32khz + description: 32/16 kHz clock. + value: 0 + - name: Clk512hz + description: 512 Hz clock. + value: 1 + - name: Clk128hz + description: 128 Hz clock. + value: 2 + - name: Clk64hz + description: 64 Hz clock. + value: 3 + - name: Clk16hz + description: 16 Hz clock. + value: 4 + - name: Clk8hz + description: 8 Hz clock. + value: 5 + - name: Clk4hz + description: 4 Hz clock. + value: 6 + - name: Clk2hz + description: 2 Hz clock. + value: 7 +enum/ClkSel4: + bit_size: 3 + variants: + - name: Clk32768khz + description: Clock to tamper filter 4 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us. + value: 0 + - name: Clk512hz + description: Clock to tamper filter 4 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms. + value: 1 +enum/ClkSel5: + bit_size: 3 + variants: + - name: Clk32768khz + description: Clock to tamper filter 5 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us. + value: 0 + - name: Clk512hz + description: Clock to tamper filter 5 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms. + value: 1 +enum/ClkSel6: + bit_size: 3 + variants: + - name: Clk32768khz + description: Clock to tamper filter 6 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us. + value: 0 + - name: Clk512hz + description: Clock to tamper filter 6 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms. + value: 1 +enum/ClkSel7: + bit_size: 3 + variants: + - name: Clk32768khz + description: Clock to tamper filter 7 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us. + value: 0 + - name: Clk512hz + description: Clock to tamper filter 7 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms. + value: 1 +enum/DwnCntrInvalBit: + bit_size: 1 + variants: + - name: Valid + description: Count down timer can be changed or read. + value: 0 + - name: Invalid + description: Count down timer (if running) is changing value and cannot be read or written. + value: 1 +enum/FilDur0: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur1: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: Enabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: Enabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: Enabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: Enabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: Enabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: Enabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: Enabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: Enabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: Enabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur2: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur3: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur4: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur5: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur6: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/FilDur7: + bit_size: 4 + variants: + - name: Disabled + description: Filtering operation disabled. + value: 0 + - name: NumberOfClkCyclesEnabled1 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 1 + - name: NumberOfClkCyclesEnabled2 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 2 + - name: NumberOfClkCyclesEnabled3 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 3 + - name: NumberOfClkCyclesEnabled4 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 4 + - name: NumberOfClkCyclesEnabled5 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 5 + - name: NumberOfClkCyclesEnabled6 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 6 + - name: NumberOfClkCyclesEnabled7 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 7 + - name: NumberOfClkCyclesEnabled8 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 8 + - name: NumberOfClkCyclesEnabled9 + description: Number of tamper filter clock cycles to be counted when tamper is asserted. + value: 9 +enum/LfsrClkSel: + bit_size: 3 + variants: + - name: Clk3216khz + description: 32/16 KHz. + value: 0 + - name: Clk512hz + description: 512 Hz. + value: 1 + - name: Clk128hz + description: 128 Hz. + value: 2 + - name: Clk64hz + description: 64 Hz. + value: 3 + - name: Clk16hz + description: 16 Hz. + value: 4 + - name: Clk8hz + description: 8 Hz. + value: 5 + - name: Clk4hz + description: 4 Hz. + value: 6 + - name: Clk2hz + description: 2 Hz. + value: 7 +enum/Pol0: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 0 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 0 is active low. + value: 1 +enum/Pol1: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 1 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 1 is active low. + value: 1 +enum/Pol2: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 2 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 2 is active low. + value: 1 +enum/Pol3: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 3 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 3 is active low. + value: 1 +enum/Pol4: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 4is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 4 is active low. + value: 1 +enum/Pol5: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 5 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 5 is active low. + value: 1 +enum/Pol6: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 6 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 6 is active low. + value: 1 +enum/Pol7: + bit_size: 1 + variants: + - name: ActiveHigh + description: Tamper detect input bit 7 is active high. + value: 0 + - name: ActiveLow + description: Tamper detect input bit 7 is active low. + value: 1 enum/Swr: bit_size: 1 variants: - - name: CLEARED + - name: Cleared description: Software Reset cleared. value: 0 - - name: ASSERTED + - name: Asserted description: Software Reset asserted. value: 1 +enum/TmprEn: + bit_size: 4 + variants: + - name: Disabled + description: Tamper Status reporting disabled. + value: 0 + - name: Enabled + description: Tamper Status reporting enabled. + value: 1 +enum/TmprSts: + bit_size: 4 + variants: + - name: NoTamper + description: No Tamper Detected. + value: 0 + - name: TamperDetected + description: Tamper Event Detected. + value: 1 +enum/WakeupMode: + bit_size: 1 + variants: + - name: TamperPin + description: Tamper pin 0 is used as the tamper pin. + value: 0 + - name: WakeupPin + description: Tamper pin 0 is used as a wakeup and hibernation pin. + value: 1 +enum/WakeupStatus: + bit_size: 2 + variants: + - name: HiZMode + description: The wakeup and hibernation pin is in HiZ mode. + value: 0 + - name: Logic0 + description: The wakeup and hibernation pin is at logic 0. MCU is in sleep mode. + value: 1 + - name: Logic1 + description: The wakeup and hibernation pin is at logic 1. MCU is in sleep mode. + value: 2 diff --git a/data/metadata/peripherals/mcxa/SCG.yaml b/data/metadata/peripherals/mcxa/SCG.yaml index c87bb65..2d6aafb 100644 --- a/data/metadata/peripherals/mcxa/SCG.yaml +++ b/data/metadata/peripherals/mcxa/SCG.yaml @@ -32,6 +32,10 @@ block/Scg: description: SOSC Configuration Register. byte_offset: 264 fieldset: Sosccfg + - name: sosctest + description: SOSC Test Register. + byte_offset: 508 + fieldset: Sosctest - name: sirccsr description: SIRC Control Status Register. byte_offset: 512 @@ -48,6 +52,10 @@ block/Scg: description: SIRC Auto-trimming Status Register. byte_offset: 536 fieldset: Sircstat + - name: sirctest + description: SIRC Test Register. + byte_offset: 764 + fieldset: Sirctest - name: firccsr description: FIRC Control Status Register. byte_offset: 768 @@ -56,14 +64,76 @@ block/Scg: description: FIRC Configuration Register. byte_offset: 776 fieldset: Firccfg + - name: firctcfg + description: FIRC Trim Configuration Register. + byte_offset: 780 + fieldset: Firctcfg - name: firctrim description: FIRC Trim Register. byte_offset: 784 fieldset: Firctrim + - name: fircstat + description: FIRC Auto-trimming Status Register. + byte_offset: 792 + fieldset: Fircstat + - name: firctest + description: FIRC Test Register. + byte_offset: 1020 + fieldset: Firctest - name: rosccsr description: ROSC Control Status Register. byte_offset: 1024 fieldset: Rosccsr + - name: apllcsr + description: APLL Control Status Register. + byte_offset: 1280 + fieldset: Apllcsr + - name: apllctrl + description: APLL Control Register. + byte_offset: 1284 + fieldset: Apllctrl + - name: apllstat + description: APLL Status Register. + byte_offset: 1288 + access: Read + fieldset: Apllstat + - name: apllndiv + description: APLL N Divider Register. + byte_offset: 1292 + fieldset: Apllndiv + - name: apllmdiv + description: APLL M Divider Register. + byte_offset: 1296 + fieldset: Apllmdiv + - name: apllpdiv + description: APLL P Divider Register. + byte_offset: 1300 + fieldset: Apllpdiv + - name: aplllock_cnfg + description: APLL LOCK Configuration Register. + byte_offset: 1304 + fieldset: AplllockCnfg + - name: apllsscgstat + description: APLL SSCG Status Register. + byte_offset: 1312 + access: Read + fieldset: Apllsscgstat + - name: apllsscg0 + description: APLL Spread Spectrum Control 0 Register. + byte_offset: 1316 + fieldset: Apllsscg0 + - name: apllsscg1 + description: APLL Spread Spectrum Control 1 Register. + byte_offset: 1320 + fieldset: Apllsscg1 + - name: apllteststat + description: APLL Test Status Register. + byte_offset: 1528 + fieldset: Apllteststat + - name: aplltestctrl + description: APLL Test Control Register. + byte_offset: 1532 + fieldset: Aplltestctrl - name: spllcsr description: SPLL Control Status Register. byte_offset: 1536 @@ -106,25 +176,309 @@ block/Scg: description: SPLL Spread Spectrum Control 1 Register. byte_offset: 1576 fieldset: Spllsscg1 + - name: spllteststat + description: SPLL Test Status Register. + byte_offset: 1784 + fieldset: Spllteststat + - name: splltestctrl + description: SPLL Test Control Register. + byte_offset: 1788 + fieldset: Splltestctrl + - name: upllcsr + description: UPLL Control Status Register. + byte_offset: 1792 + fieldset: Upllcsr - name: ldocsr description: LDO Control and Status Register. byte_offset: 2048 fieldset: Ldocsr + - name: ldotest + description: LDO Test Register. + byte_offset: 2300 + fieldset: Ldotest +fieldset/Apllcsr: + description: APLL Control Status Register. + fields: + - name: apllpwren + description: APLL Power Enable. + bit_offset: 0 + bit_size: 1 + - name: apllclken + description: APLL Clock Enable. + bit_offset: 1 + bit_size: 1 + - name: apllsten + description: APLL Stop Enable. + bit_offset: 2 + bit_size: 1 + enum: Apllsten + - name: frm_clockstable + description: Free running mode clock stable. + bit_offset: 3 + bit_size: 1 + - name: apllcm + description: APLL Clock Monitor. + bit_offset: 16 + bit_size: 1 + - name: apllcmre + description: APLL Clock Monitor Reset Enable. + bit_offset: 17 + bit_size: 1 + enum: Apllcmre + - name: lk + description: Lock Register. + bit_offset: 23 + bit_size: 1 + enum: ApllcsrLk + - name: apll_lock + description: APLL LOCK. + bit_offset: 24 + bit_size: 1 + enum: ApllLock + - name: apllsel + description: APLL Selected. + bit_offset: 25 + bit_size: 1 + - name: apllerr + description: APLL Clock Error. + bit_offset: 26 + bit_size: 1 + enum: Apllerr + - name: apll_lock_ie + description: APLL LOCK Interrupt Enable. + bit_offset: 30 + bit_size: 1 +fieldset/Apllctrl: + description: APLL Control Register. + fields: + - name: selr + description: Bandwidth select R (resistor) value. + bit_offset: 0 + bit_size: 4 + - name: seli + description: Bandwidth select I (integration) value. + bit_offset: 4 + bit_size: 6 + - name: selp + description: Bandwidth select P (proportional) value. + bit_offset: 10 + bit_size: 5 + - name: bypasspostdiv2 + description: Bypass of Divide-by-2 Divider. + bit_offset: 16 + bit_size: 1 + - name: limupoff + description: Up Limiter. + bit_offset: 17 + bit_size: 1 + - name: banddirect + description: Control of the bandwidth of the PLL. + bit_offset: 18 + bit_size: 1 + - name: bypassprediv + description: Bypass of the predivider. + bit_offset: 19 + bit_size: 1 + - name: bypasspostdiv + description: Bypass of the postdivider. + bit_offset: 20 + bit_size: 1 + - name: frm + description: Free Running Mode Enable. + bit_offset: 22 + bit_size: 1 + - name: skew_en + description: Skew mode. + bit_offset: 24 + bit_size: 1 + - name: source + description: Clock Source. + bit_offset: 25 + bit_size: 2 + enum: ApllctrlSource +fieldset/AplllockCnfg: + description: APLL LOCK Configuration Register. + fields: + - name: lock_time + description: Configures the number of reference clocks to count before APLL is considered locked. + bit_offset: 0 + bit_size: 17 +fieldset/Apllmdiv: + description: APLL M Divider Register. + fields: + - name: mdiv + description: Feedback divider divider ratio (M-divider). + bit_offset: 0 + bit_size: 16 + - name: mreq + description: Feedback ratio change request. + bit_offset: 31 + bit_size: 1 +fieldset/Apllndiv: + description: APLL N Divider Register. + fields: + - name: ndiv + description: Predivider divider ratio (N-divider). + bit_offset: 0 + bit_size: 8 + - name: nreq + description: Predivider ratio change request. + bit_offset: 31 + bit_size: 1 +fieldset/Apllpdiv: + description: APLL P Divider Register. + fields: + - name: pdiv + description: Postdivider divider ratio (P-divider). + bit_offset: 0 + bit_size: 5 + - name: preq + description: Postdivider ratio change request. + bit_offset: 31 + bit_size: 1 +fieldset/Apllsscg0: + description: APLL Spread Spectrum Control 0 Register. + fields: + - name: ss_mdiv_lsb + description: SS_MDIV. + bit_offset: 0 + bit_size: 32 +fieldset/Apllsscg1: + description: APLL Spread Spectrum Control 1 Register. + fields: + - name: ss_mdiv_msb + description: SS_MDIV[32]. + bit_offset: 0 + bit_size: 1 + - name: ss_mdiv_req + description: SS_MDIV[32:0] change request. + bit_offset: 1 + bit_size: 1 + - name: mf + description: Modulation Frequency Control. + bit_offset: 2 + bit_size: 3 + - name: mr + description: Modulation Depth Control. + bit_offset: 5 + bit_size: 3 + - name: mc + description: Modulation Waveform Control. + bit_offset: 8 + bit_size: 2 + enum: Apllsscg1Mc + - name: dither + description: Dither Enable. + bit_offset: 10 + bit_size: 1 + - name: sel_ss_mdiv + description: SS_MDIV select. + bit_offset: 11 + bit_size: 1 + - name: ss_pd + description: SSCG Power Down. + bit_offset: 31 + bit_size: 1 +fieldset/Apllsscgstat: + description: APLL SSCG Status Register. + fields: + - name: ss_mdiv_ack + description: SS_MDIV change acknowledge. + bit_offset: 0 + bit_size: 1 +fieldset/Apllstat: + description: APLL Status Register. + fields: + - name: lock + description: Lock detector output (active high). + bit_offset: 0 + bit_size: 1 + - name: ndivack + description: Predivider(N) ratio change acknowledge. + bit_offset: 1 + bit_size: 1 + - name: mdivack + description: Feedback(M) divider ratio change acknowledge. + bit_offset: 2 + bit_size: 1 + - name: pdivack + description: Postdivider(P) ratio change acknowledge. + bit_offset: 3 + bit_size: 1 + - name: frmdet + description: Free running detector (active high). + bit_offset: 4 + bit_size: 1 +fieldset/Aplltestctrl: + description: APLL Test Control Register. + fields: + - name: nfunctest + description: Input to functional test the predivider (N-divider). + bit_offset: 0 + bit_size: 7 + - name: mfunctest + description: Input to functional test the feedback-divider (M-divider). + bit_offset: 7 + bit_size: 15 + - name: pfunctest + description: Input to functional test the postdivider (P-divider). + bit_offset: 22 + bit_size: 4 + - name: testv_en + description: Enable test mux. + bit_offset: 26 + bit_size: 1 + - name: testv_sel + description: Select analog signal channel that need to be test. + bit_offset: 27 + bit_size: 3 + enum: AplltestctrlTestvSel + - name: bypasspll + description: Bypass PLL. + bit_offset: 31 + bit_size: 1 +fieldset/Apllteststat: + description: APLL Test Status Register. + fields: + - name: nmotest + description: Output to observe the functional predivider test. + bit_offset: 0 + bit_size: 2 + - name: mmotest + description: Output to observe the functional feedback-divider test. + bit_offset: 2 + bit_size: 2 + - name: pmotest + description: Output to observe the functional postdivider test. + bit_offset: 4 + bit_size: 2 + - name: pll_xfunc_test_pulse + description: PLL functional divider test clock pulse. + bit_offset: 29 + bit_size: 1 + - name: pll_xfunc_test_en + description: Enable PLL functional divider test clock pulse. + bit_offset: 30 + bit_size: 1 + - name: pll_xmo_test_en + description: Enable to observe the xMOTEST flags. + bit_offset: 31 + bit_size: 1 fieldset/Csr: description: Clock Status Register. fields: - name: scs description: System Clock Source. bit_offset: 24 - bit_size: 3 + bit_size: 4 enum: Scs fieldset/Firccfg: description: FIRC Configuration Register. fields: - name: freq_sel - description: Frequency select. - bit_offset: 1 - bit_size: 3 + description: Frequency Range. + bit_offset: 0 + bit_size: 4 enum: FreqSel fieldset/Firccsr: description: FIRC Control Status Register. @@ -139,13 +493,30 @@ fieldset/Firccsr: bit_size: 1 enum: Fircsten - name: firc_sclk_periph_en - description: FIRC 45 MHz Clock to peripherals Enable. + description: FIRC 48 MHz Clock to peripherals Enable. bit_offset: 4 bit_size: 1 - name: firc_fclk_periph_en - description: FRO_HF Clock to peripherals Enable. + description: FIRC 144 MHz Clock to peripherals Enable. bit_offset: 5 bit_size: 1 + - name: firctren + description: FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1). + bit_offset: 8 + bit_size: 1 + - name: firctrup + description: FIRC Trim Update. + bit_offset: 9 + bit_size: 1 + - name: trim_lock + description: FIRC TRIM LOCK. + bit_offset: 10 + bit_size: 1 + enum: FirccsrTrimLock + - name: coarse_trim_bypass + description: Coarse Auto Trim Bypass. + bit_offset: 11 + bit_size: 1 - name: lk description: Lock Register. bit_offset: 23 @@ -180,6 +551,67 @@ fieldset/Firccsr: bit_offset: 31 bit_size: 1 enum: Fircacc +fieldset/Fircstat: + description: FIRC Auto-trimming Status Register. + fields: + - name: trimfine + description: Trim Fine. + bit_offset: 0 + bit_size: 8 + - name: trimcoar + description: Trim Coarse. + bit_offset: 8 + bit_size: 6 +fieldset/Firctcfg: + description: FIRC Trim Configuration Register. + fields: + - name: trimsrc + description: Trim Source. + bit_offset: 0 + bit_size: 2 + enum: FirctcfgTrimsrc + - name: trimdiv + description: FIRC Trim Predivider. + bit_offset: 16 + bit_size: 7 +fieldset/Firctest: + description: FIRC Test Register. + fields: + - name: testen + description: Test Enable. + bit_offset: 0 + bit_size: 1 + enum: Testen + - name: testsel + description: Test Select. + bit_offset: 3 + bit_size: 2 + enum: Testsel + - name: overstress + description: Over Stress Test. + bit_offset: 5 + bit_size: 1 + enum: Overstress + - name: test_buf_en + description: Test Buffer Enable. + bit_offset: 6 + bit_size: 1 + enum: TestBufEn + - name: test_buf_flip + description: Test Buffer Flip. + bit_offset: 7 + bit_size: 1 + enum: TestBufFlip + - name: clk_valid + description: Analog output clk_valid_lv. + bit_offset: 16 + bit_size: 1 + enum: ClkValid + - name: start_valid + description: Analog output start_valid_lv. + bit_offset: 17 + bit_size: 1 + enum: StartValid fieldset/Firctrim: description: FIRC Trim Register. fields: @@ -194,7 +626,7 @@ fieldset/Firctrim: - name: trimtemp description: Trim Temperature. bit_offset: 16 - bit_size: 4 + bit_size: 2 - name: trimstart description: Trim Start. bit_offset: 24 @@ -219,6 +651,14 @@ fieldset/Ldocsr: description: LDO VOUT OK Inform. bit_offset: 31 bit_size: 1 +fieldset/Ldotest: + description: LDO Test Register. + fields: + - name: sel_atx + description: Select analog test bus. + bit_offset: 0 + bit_size: 2 + enum: SelAtx fieldset/Param: description: Parameter Register. fields: @@ -238,21 +678,38 @@ fieldset/Param: description: ROSC Clock Present. bit_offset: 4 bit_size: 1 + - name: apllclkpres + description: APLL Clock Present. + bit_offset: 5 + bit_size: 1 - name: spllclkpres description: SPLL Clock Present. bit_offset: 6 bit_size: 1 + - name: upllclkpres + description: UPLL Clock Present. + bit_offset: 7 + bit_size: 1 fieldset/Rccr: description: Run Clock Control Register. fields: - name: scs description: System Clock Source. bit_offset: 24 - bit_size: 3 + bit_size: 4 enum: Scs fieldset/Rosccsr: description: ROSC Control Status Register. fields: + - name: rosccm + description: ROSC Clock Monitor. + bit_offset: 16 + bit_size: 1 + - name: rosccmre + description: ROSC Clock Monitor Reset Enable. + bit_offset: 17 + bit_size: 1 + enum: Rosccmre - name: lk description: Lock Register. bit_offset: 23 @@ -295,7 +752,7 @@ fieldset/Sirccsr: description: SIRC TRIM LOCK. bit_offset: 10 bit_size: 1 - enum: TrimLockVal + enum: SirccsrTrimLock - name: coarse_trim_bypass description: Coarse Auto Trim Bypass. bit_offset: 11 @@ -342,11 +799,38 @@ fieldset/Sirctcfg: description: Trim Source. bit_offset: 0 bit_size: 2 - enum: Trimsrc + enum: SirctcfgTrimsrc - name: trimdiv - description: SIRC Trim Pre-divider. + description: SIRC Trim Predivider. bit_offset: 16 bit_size: 7 +fieldset/Sirctest: + description: SIRC Test Register. + fields: + - name: test + description: SIRC ATX Test Enable. + bit_offset: 0 + bit_size: 1 + - name: div16en + description: SIRC Div-by-16 Output Enable. + bit_offset: 4 + bit_size: 1 + enum: Div16en + - name: flip_buf_in + description: SIRC Flip Buffer Inputs Enable. + bit_offset: 5 + bit_size: 1 + enum: FlipBufIn + - name: test_buf_bypass + description: SIRC Buffer Bypass. + bit_offset: 6 + bit_size: 1 + enum: TestBufBypass + - name: test_sel + description: SIRC Test Select. + bit_offset: 8 + bit_size: 2 + enum: TestSel fieldset/Sirctrim: description: SIRC Trim Register. fields: @@ -370,12 +854,12 @@ fieldset/Sosccfg: description: SOSC Configuration Register. fields: - name: erefs - description: External Reference Select. + description: External Reference Select(connect to analog pin ~en_byp_lv). bit_offset: 2 bit_size: 1 enum: Erefs - name: range - description: SOSC Range Select. + description: SOSC Range Select(connect to analog pin gm_lv[1:0]). bit_offset: 4 bit_size: 2 enum: Range @@ -421,9 +905,21 @@ fieldset/Sosccsr: description: SOSC Valid Interrupt Enable. bit_offset: 30 bit_size: 1 - - name: sosc_safe_en - description: SOSC clock safety enable. - bit_offset: 31 +fieldset/Sosctest: + description: SOSC Test Register. + fields: + - name: sosc_xtm_test_mode_en + description: SOSC XTM Test Mode Enable (connect to analog pin xtm_lv). + bit_offset: 4 + bit_size: 1 + - name: tstmd + description: OSC Test Select (connect to analog pin tst_md_lv[1:0]). + bit_offset: 8 + bit_size: 2 + enum: Tstmd + - name: xo_ok_lv + description: The analog output xo_ok_lv. + bit_offset: 16 bit_size: 1 fieldset/Spllcsr: description: SPLL Control Status Register. @@ -485,7 +981,7 @@ fieldset/Spllctrl: bit_offset: 0 bit_size: 4 - name: seli - description: Bandwidth select I (interation) value. + description: Bandwidth select I (integration) value. bit_offset: 4 bit_size: 6 - name: selp @@ -493,7 +989,7 @@ fieldset/Spllctrl: bit_offset: 10 bit_size: 5 - name: bypasspostdiv2 - description: Bypass of the divide-by-2 divider. + description: Bypass of Divide-by-2 Divider. bit_offset: 16 bit_size: 1 - name: limupoff @@ -505,17 +1001,21 @@ fieldset/Spllctrl: bit_offset: 18 bit_size: 1 - name: bypassprediv - description: Bypass of the pre-divider. + description: Bypass of the predivider. bit_offset: 19 bit_size: 1 - name: bypasspostdiv - description: Bypass of the post-divider. + description: Bypass of the postdivider. bit_offset: 20 bit_size: 1 - name: frm description: Free Running Mode Enable. bit_offset: 22 bit_size: 1 + - name: skew_en + description: Skew mode. + bit_offset: 24 + bit_size: 1 - name: source description: Clock Source. bit_offset: 25 @@ -532,7 +1032,7 @@ fieldset/Spllmdiv: description: SPLL M Divider Register. fields: - name: mdiv - description: Feedback divider ratio (M-divider). + description: Feedback divider divider ratio (M-divider). bit_offset: 0 bit_size: 16 - name: mreq @@ -543,22 +1043,22 @@ fieldset/Spllndiv: description: SPLL N Divider Register. fields: - name: ndiv - description: Pre-divider divider ratio (N-divider). + description: Predivider divider ratio (N-divider). bit_offset: 0 bit_size: 8 - name: nreq - description: Pre-divider ratio change request. + description: Predivider ratio change request. bit_offset: 31 bit_size: 1 fieldset/Spllpdiv: description: SPLL P Divider Register. fields: - name: pdiv - description: Post-divider divider ratio (P-divider). + description: Postdivider divider ratio (P-divider). bit_offset: 0 bit_size: 5 - name: preq - description: Post-divider ratio change request. + description: Postdivider ratio change request. bit_offset: 31 bit_size: 1 fieldset/Spllsscg0: @@ -591,6 +1091,7 @@ fieldset/Spllsscg1: description: Modulation Waveform Control. bit_offset: 8 bit_size: 2 + enum: Spllsscg1Mc - name: dither description: Dither Enable. bit_offset: 10 @@ -613,8 +1114,12 @@ fieldset/Spllsscgstat: fieldset/Spllstat: description: SPLL Status Register. fields: + - name: lock + description: Lock detector output (active high). + bit_offset: 0 + bit_size: 1 - name: ndivack - description: Pre-divider (N) ratio change acknowledge. + description: Predivider (N) ratio change acknowledge. bit_offset: 1 bit_size: 1 - name: mdivack @@ -622,13 +1127,68 @@ fieldset/Spllstat: bit_offset: 2 bit_size: 1 - name: pdivack - description: Post-divider (P) ratio change acknowledge. + description: Postdivider (P) ratio change acknowledge. bit_offset: 3 bit_size: 1 - name: frmdet description: Free running detector (active high). bit_offset: 4 bit_size: 1 +fieldset/Splltestctrl: + description: SPLL Test Control Register. + fields: + - name: nfunctest + description: Input to functional test the predivider (N-divider). + bit_offset: 0 + bit_size: 7 + - name: mfunctest + description: Input to functional test the feedback divider (M-divider). + bit_offset: 7 + bit_size: 15 + - name: pfunctest + description: Input to functional test the postdivider (P-divider). + bit_offset: 22 + bit_size: 4 + - name: testv_en + description: Enable test mux. + bit_offset: 26 + bit_size: 1 + - name: testv_sel + description: Select analog signal channel that need to be test. + bit_offset: 27 + bit_size: 3 + enum: SplltestctrlTestvSel + - name: bypasspll + description: Bypass PLL. + bit_offset: 31 + bit_size: 1 +fieldset/Spllteststat: + description: SPLL Test Status Register. + fields: + - name: nmotest + description: Output to observe the functional predivider test. + bit_offset: 0 + bit_size: 2 + - name: mmotest + description: Output to observe the functional feedback divider test. + bit_offset: 2 + bit_size: 2 + - name: pmotest + description: Output to observe the functional postdivider test. + bit_offset: 4 + bit_size: 2 + - name: pll_xfunc_test_pulse + description: PLL functional divider test clock pulse. + bit_offset: 29 + bit_size: 1 + - name: pll_xfunc_test_en + description: Enable PLL functional divider test clock pulse. + bit_offset: 30 + bit_size: 1 + - name: pll_xmo_test_en + description: Enable to observe the xMOTEST flags. + bit_offset: 31 + bit_size: 1 fieldset/TrimLock: description: Trim Lock register. fields: @@ -646,6 +1206,37 @@ fieldset/TrimLock: description: TRIM_LOCK_KEY. bit_offset: 16 bit_size: 16 +fieldset/Upllcsr: + description: UPLL Control Status Register. + fields: + - name: upllcm + description: UPLL Clock Monitor. + bit_offset: 16 + bit_size: 1 + - name: upllcmre + description: UPLL Clock Monitor Reset Enable. + bit_offset: 17 + bit_size: 1 + enum: Upllcmre + - name: lk + description: Lock Register. + bit_offset: 23 + bit_size: 1 + enum: UpllcsrLk + - name: upllvld + description: UPLL Valid. + bit_offset: 24 + bit_size: 1 + enum: Upllvld + - name: upllsel + description: UPLL Selected. + bit_offset: 25 + bit_size: 1 + - name: upllerr + description: UPLL Clock Error. + bit_offset: 26 + bit_size: 1 + enum: Upllerr fieldset/Verid: description: Version ID Register. fields: @@ -653,333 +1244,641 @@ fieldset/Verid: description: SCG Version Number. bit_offset: 0 bit_size: 32 +enum/ApllLock: + bit_size: 1 + variants: + - name: DisabledOrNotValid + description: APLL is not powered on or not locked. + value: 0 + - name: EnabledAndValid + description: APLL is locked. + value: 1 +enum/Apllcmre: + bit_size: 1 + variants: + - name: GenerateInterrupt + description: Clock monitor generates an interrupt when an error is detected. + value: 0 + - name: GenerateReset + description: Clock monitor generates a reset when an error is detected. + value: 1 +enum/ApllcsrLk: + bit_size: 1 + variants: + - name: WriteEnabled + description: Control Status Register can be written. + value: 0 + - name: WriteDisabled + description: Control Status Register cannot be written. + value: 1 +enum/ApllctrlSource: + bit_size: 2 + variants: + - name: Sosc + description: SOSC. + value: 0 + - name: Firc + description: FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + value: 1 + - name: Rsvd + description: No clock. + value: 3 +enum/Apllerr: + bit_size: 1 + variants: + - name: DisabledOrNoError + description: APLL Clock Monitor is disabled or has not detected an error. + value: 0 + - name: EnabledAndError + description: APLL Clock Monitor is enabled and detected an error. + value: 1 +enum/Apllsscg1Mc: + bit_size: 2 + variants: + - name: NoComp + description: MC[1:0] no compensation. + value: 0 + - name: MaxComp + description: MC[1:0] maximum compensation. + value: 3 +enum/Apllsten: + bit_size: 1 + variants: + - name: DisabledInStop + description: APLL is disabled in Deep Sleep mode. + value: 0 + - name: EnabledInStop + description: APLL is enabled in Deep Sleep mode. + value: 1 +enum/AplltestctrlTestvSel: + bit_size: 3 + variants: + - name: PllBias + description: pll_bias_source. + value: 0 + - name: PllCco + description: pll_cco_current. + value: 1 + - name: Ldo + description: ldo_ldo1p1. + value: 4 +enum/ClkValid: + bit_size: 1 + variants: + - name: ClkValid0 + description: clk_valid_lv is not set. + value: 0 + - name: ClkValid1 + description: clk_valid_lv is set. + value: 1 +enum/Div16en: + bit_size: 1 + variants: + - name: Div16Disabled + description: Divide-by-16 disabled, 12 MHz clock output. + value: 0 + - name: Div16Enabled + description: Divide-by-16 enabled, 750 kHz clock output. + value: 1 enum/Erefs: bit_size: 1 variants: - - name: EXTERNAL - description: External reference clock selected. + - name: External + description: External reference clock from PAD pin selected. LDO can be disabled in this case. value: 0 - - name: INTERNAL + - name: Internal description: Internal crystal oscillator of OSC selected. value: 1 enum/Fircacc: bit_size: 1 variants: - - name: NOT_ENABLED_OR_NOT_VALID + - name: NotEnabledOrNotValid description: FIRC is not enabled or clock is not accurate. value: 0 - - name: ENABLED_AND_VALID - description: FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock. + - name: EnabledAndValid + description: FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog. value: 1 enum/FircaccIe: bit_size: 1 variants: - - name: FIRCACCNOT + - name: Fircaccnot description: FIRCACC interrupt is not enabled. value: 0 - - name: FIRCACCYES + - name: Fircaccyes description: FIRCACC interrupt is enabled. value: 1 enum/FirccsrLk: bit_size: 1 variants: - - name: WRITE_ENABLED + - name: WriteEnabled description: Control Status Register can be written. value: 0 - - name: WRITE_DISABLED + - name: WriteDisabled description: Control Status Register cannot be written. value: 1 +enum/FirccsrTrimLock: + bit_size: 1 + variants: + - name: FircNotLocked + description: FIRC auto trim not locked to target frequency range. + value: 0 + - name: FircLocked + description: FIRC auto trim locked to target frequency range. + value: 1 enum/Fircerr: bit_size: 1 variants: - - name: ERROR_NOT_DETECTED + - name: ErrorNotDetected description: Error not detected with the FIRC trimming. value: 0 - - name: ERROR_DETECTED + - name: ErrorDetected description: Error detected with the FIRC trimming. value: 1 enum/FircerrIe: bit_size: 1 variants: - - name: ERROR_NOT_DETECTED + - name: ErrorNotDetected description: FIRCERR interrupt is not enabled. value: 0 - - name: ERROR_DETECTED + - name: ErrorDetected description: FIRCERR interrupt is enabled. value: 1 enum/Fircsten: bit_size: 1 variants: - - name: DISABLED_IN_STOP_MODES + - name: DisabledInStopModes description: FIRC is disabled in Deep Sleep mode. value: 0 - - name: ENABLED_IN_STOP_MODES + - name: EnabledInStopModes description: FIRC is enabled in Deep Sleep mode. value: 1 +enum/FirctcfgTrimsrc: + bit_size: 2 + variants: + - name: Usb0 + description: USB0 Start of Frame (1 kHz). This option does not use TRIMDIV because the clock came externally from USB. + value: 0 + - name: Sosc + description: SOSC. + value: 2 + - name: Rosc + description: ROSC. + value: 3 enum/Fircvld: bit_size: 1 variants: - - name: NOT_ENABLED_OR_NOT_VALID + - name: NotEnabledOrNotValid description: FIRC is not enabled or clock is not valid. value: 0 - - name: ENABLED_AND_VALID + - name: EnabledAndValid description: FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. value: 1 +enum/FlipBufIn: + bit_size: 1 + variants: + - name: FlipBufInDisabled + description: Flip Buffer Inputs disabled. + value: 0 + - name: FlipBufInEnabled + description: Flip Buffer Inputs enabled. + value: 1 enum/FreqSel: - bit_size: 3 + bit_size: 4 variants: - - name: FIRC_48MHZ_192S - description: 45 MHz FIRC clock selected, divided from 180 MHz. + - name: Firc45_48mhz value: 1 - - name: FIRC_64MHZ - description: 60 MHz FIRC clock selected. + - name: Firc60_64mhz value: 3 - - name: FIRC_96MHZ - description: 90 MHz FIRC clock selected. + - name: Firc90_96mhz value: 5 - - name: FIRC_192MHZ - description: 180 MHz FIRC clock selected. + - name: Firc180_192mhz value: 7 enum/IfrDisable: bit_size: 1 variants: - - name: ENABLED + - name: Enabled description: IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. value: 0 - - name: DISABLED + - name: Disabled description: IFR write access to SCG trim registers during system reset is blocked. value: 1 +enum/Overstress: + bit_size: 1 + variants: + - name: OverstressDis + description: Over stress test is disabled. + value: 0 + - name: OverstressEn + description: Over stress test is enabled. + value: 1 enum/Range: bit_size: 2 variants: - - name: FREQ_16TO20MHZ - description: Frequency range select of 8-16 MHz. + - name: Freq16to20mhz + description: Frequency range select of 16-20 MHz. value: 0 - - name: LOW_FREQ - description: Frequency range select of 16-25 MHz. + - name: LowFreq + description: Frequency range select of 20-30 MHz. value: 1 - - name: MEDIUM_FREQ - description: Frequency range select of 25-40 MHz. + - name: MediumFreq + description: Frequency range select of 30-50 MHz. value: 2 - - name: HIGH_FREQ - description: Frequency range select of 40-50 MHz. + - name: HighFreq + description: Frequency range select of 50-66 MHz. value: 3 +enum/Rosccmre: + bit_size: 1 + variants: + - name: GenerateInterrupt + description: Clock monitor generates an interrupt when an error is detected. + value: 0 + - name: GenerateReset + description: Clock monitor generates a reset when an error is detected. + value: 1 enum/RosccsrLk: bit_size: 1 variants: - - name: WRITE_ENABLED + - name: WriteEnabled description: Control Status Register can be written. value: 0 - - name: WRITE_DISABLED + - name: WriteDisabled description: Control Status Register cannot be written. value: 1 enum/Roscerr: bit_size: 1 variants: - - name: DISABLED_OR_NO_ERROR - description: ROSC Clock has not detected an error. + - name: DisabledOrNoError + description: ROSC Clock Monitor is disabled or has not detected an error. value: 0 - - name: ENABLED_AND_ERROR - description: ROSC Clock has detected an error. + - name: EnabledAndError + description: ROSC Clock Monitor is enabled and detected an RTC loss of clock error. value: 1 enum/Roscvld: bit_size: 1 variants: - - name: DISABLED_OR_NOT_VALID + - name: DisabledOrNotValid description: ROSC is not enabled or clock is not valid. value: 0 - - name: ENABLED_AND_VALID + - name: EnabledAndValid description: ROSC is enabled and output clock is valid. value: 1 enum/Scs: - bit_size: 3 + bit_size: 4 variants: - - name: SOSC + - name: Sosc description: SOSC. value: 1 - - name: SIRC + - name: Sirc description: SIRC. value: 2 - - name: FIRC + - name: Firc description: FIRC. value: 3 - - name: ROSC + - name: Rosc description: ROSC. value: 4 - - name: SPLL + - name: Apll + description: APLL. + value: 5 + - name: Spll description: SPLL. value: 6 + - name: Upll + description: UPLL. + value: 7 +enum/SelAtx: + bit_size: 2 + variants: + - name: Floating + description: 'ldo1p1v_atxout_ana_atx3v_a: floating; ldo1p1v_atxout_ana_atx3v_b: floating.' + value: 0 + - name: Vbiasn + description: 'ldo1p1v_atxout_ana_atx3v_a: ref_1v; ldo1p1v_atxout_ana_atx3v_b: vbiasn.' + value: 1 + - name: Vgate + description: 'ldo1p1v_atxout_ana_atx3v_a: vea; ldo1p1v_atxout_ana_atx3v_b: vgate.' + value: 2 + - name: LdoP8v + description: 'ldo1p1v_atxout_ana_atx3v_a: ldo1p1v_vout_ok_lv; ldo1p1v_atxout_ana_atx3v_b: ldo1p1v_vout_1p1v_ana_1p8v.' + value: 3 enum/SirccsrLk: bit_size: 1 variants: - - name: WRITE_ENABLED + - name: WriteEnabled description: Control Status Register can be written. value: 0 - - name: WRITE_DISABLED + - name: WriteDisabled description: Control Status Register cannot be written. value: 1 +enum/SirccsrTrimLock: + bit_size: 1 + variants: + - name: SircNotLocked + description: SIRC auto trim not locked to target frequency range. + value: 0 + - name: SircLocked + description: SIRC auto trim locked to target frequency range. + value: 1 enum/Sircerr: bit_size: 1 variants: - - name: ERROR_NOT_DETECTED + - name: ErrorNotDetected description: Error not detected with the SIRC trimming. value: 0 - - name: ERROR_DETECTED + - name: ErrorDetected description: Error detected with the SIRC trimming. value: 1 enum/SircerrIe: bit_size: 1 variants: - - name: ERROR_NOT_DETECTED + - name: ErrorNotDetected description: SIRCERR interrupt is not enabled. value: 0 - - name: ERROR_DETECTED + - name: ErrorDetected description: SIRCERR interrupt is enabled. value: 1 +enum/SirctcfgTrimsrc: + bit_size: 2 + variants: + - name: Sosc + description: SOSC. + value: 2 + - name: Rosc + description: ROSC (32.768 kHz). + value: 3 enum/Sircvld: bit_size: 1 variants: - - name: DISABLED_OR_NOT_VALID + - name: DisabledOrNotValid description: SIRC is not enabled or clock is not valid. value: 0 - - name: ENABLED_AND_VALID + - name: EnabledAndValid description: SIRC is enabled and output clock is valid. value: 1 enum/Sosccmre: bit_size: 1 variants: - - name: GENERATE_INTERRUPT + - name: GenerateInterrupt description: Clock monitor generates an interrupt when an error is detected. value: 0 - - name: GENERATE_RESET + - name: GenerateReset description: Clock monitor generates a reset when an error is detected. value: 1 enum/SosccsrLk: bit_size: 1 variants: - - name: WRITE_ENABLED + - name: WriteEnabled description: This Control Status Register can be written. value: 0 - - name: WRITE_DISABLED + - name: WriteDisabled description: This Control Status Register cannot be written. value: 1 enum/Soscerr: bit_size: 1 variants: - - name: DISABLED_OR_NO_ERROR + - name: DisabledOrNoError description: SOSC Clock Monitor is disabled or has not detected an error. value: 0 - - name: ENABLED_AND_ERROR + - name: EnabledAndError description: SOSC Clock Monitor is enabled and detected an error. value: 1 enum/Source: bit_size: 2 variants: - - name: SOSC - description: SOSC. + - name: Sosc + description: SOSC value: 0 - - name: FIRC + - name: Firc description: FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock. value: 1 - - name: ROSC - description: ROSC. + - name: Rosc + description: ROSC value: 2 - - name: SIRC - description: SIRC 12 MHz clock. + - name: Sirc + description: SIRC 12 MHz clock value: 3 enum/SpllLock: bit_size: 1 variants: - - name: DISABLED_OR_NOT_VALID + - name: DisabledOrNotValid description: SPLL is not powered on or not locked. value: 0 - - name: ENABLED_AND_VALID + - name: EnabledAndValid description: SPLL is locked. value: 1 enum/Spllcmre: bit_size: 1 variants: - - name: GENERATE_INTERRUPT + - name: GenerateInterrupt description: Clock monitor generates an interrupt when an error is detected. value: 0 - - name: GENERATE_RESET + - name: GenerateReset description: Clock monitor generates a reset when an error is detected. value: 1 enum/SpllcsrLk: bit_size: 1 variants: - - name: WRITE_ENABLED + - name: WriteEnabled description: Control Status Register can be written. value: 0 - - name: WRITE_DISABLED + - name: WriteDisabled description: Control Status Register cannot be written. value: 1 enum/Spllerr: bit_size: 1 variants: - - name: DISABLED_OR_NO_ERROR + - name: DisabledOrNoError description: SPLL Clock Monitor is disabled or has not detected an error. value: 0 - - name: ENABLED_AND_ERROR + - name: EnabledAndError description: SPLL Clock Monitor is enabled and detected an error. value: 1 +enum/Spllsscg1Mc: + bit_size: 2 + variants: + - name: NoComp + description: MC[1:0] no compensation. + value: 0 + - name: MaxComp + description: MC[1:0] maximum compensation. + value: 3 enum/Spllsten: bit_size: 1 variants: - - name: DISABLED_IN_STOP + - name: DisabledInStop description: SPLL is disabled in Deep Sleep mode. value: 0 - - name: ENABLED_IN_STOP + - name: EnabledInStop description: SPLL is enabled in Deep Sleep mode. value: 1 -enum/TrimLockVal: +enum/SplltestctrlTestvSel: + bit_size: 3 + variants: + - name: PllBias + description: pll_bias_source. + value: 0 + - name: PllCco + description: pll_cco_current. + value: 1 + - name: Ldo + description: ldo_ldo1p1. + value: 4 +enum/StartValid: bit_size: 1 variants: - - name: SIRC_NOT_LOCKED - description: SIRC auto trim not locked to target frequency range. + - name: StartValid0 + description: start_valid_lv is not set. value: 0 - - name: SIRC_LOCKED - description: SIRC auto trim locked to target frequency range. + - name: StartValid1 + description: start_valid_lv is set. + value: 1 +enum/TestBufBypass: + bit_size: 1 + variants: + - name: TestBufBypassDisabled + description: Not bypass buffer. + value: 0 + - name: TestBufBypassEnabled + description: Bypass buffer. + value: 1 +enum/TestBufEn: + bit_size: 1 + variants: + - name: TestBufEnDis + description: Test buffer is disabled. + value: 0 + - name: TestBufEnEn + description: Test buffer is enabled. + value: 1 +enum/TestBufFlip: + bit_size: 1 + variants: + - name: TestBufFlipDis + description: Input of the buffer is not flipped. + value: 0 + - name: TestBufFlipEn + description: Input of the buffer is flipped. + value: 1 +enum/TestSel: + bit_size: 2 + variants: + - name: TestSel00 + description: VREF. + value: 0 + - name: TestSel01 + description: VFB. + value: 1 + - name: TestSel10 + description: BP. + value: 2 + - name: TestSel11 + description: VCCO. + value: 3 +enum/Testen: + bit_size: 1 + variants: + - name: FircTestDis + description: FIRC test is disabled. + value: 0 + - name: FircTestEn + description: FIRC test is enabled. value: 1 +enum/Testsel: + bit_size: 2 + variants: + - name: Regout + description: VREGOUT test. + value: 1 + - name: Vsw + description: VSW test. + value: 2 + - name: Vref + description: VREF test. + value: 3 enum/TrimUnlock: bit_size: 1 variants: - - name: LOCKED - description: SCG Trim Registers locked and not writable. + - name: Locked + description: SCG Trim /Test registers are locked and not writable. value: 0 - - name: NOT_LOCKED - description: SCG Trim registers unlocked and writable. + - name: NotLocked + description: SCG Trim /Test registers are unlocked and writable. value: 1 -enum/Trimsrc: +enum/Tstmd: bit_size: 2 variants: - - name: SOSC - description: SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + - name: Tstmd00 + description: ipt_test_ana_atx3v_a=High-Z; ipt_test_ana_atx3v_b=High-Z. + value: 0 + - name: Tstmd01 + description: ipt_test_ana_atx3v_a=osc_in(EXTAL); ipt_test_ana_atx3v_b=High-Z. + value: 1 + - name: Tstmd10 + description: ipt_test_ana_atx3v_a=High-Z; ipt_test_ana_atx3v_b=osc_out(XTAL). value: 2 + - name: Tstmd11 + description: ipt_test_ana_atx3v_a=osc_in(EXTAL); ipt_test_ana_atx3v_b=osc_out(XTAL). + value: 3 +enum/Upllcmre: + bit_size: 1 + variants: + - name: GenerateInterrupt + description: Clock monitor generates an interrupt when an error is detected. + value: 0 + - name: GenerateReset + description: Clock monitor generates a reset when an error is detected. + value: 1 +enum/UpllcsrLk: + bit_size: 1 + variants: + - name: WriteEnabled + description: Control Status Register can be written. + value: 0 + - name: WriteDisabled + description: Control Status Register cannot be written. + value: 1 +enum/Upllerr: + bit_size: 1 + variants: + - name: DisabledOrNoError + description: UPLL Clock Monitor is disabled or has not detected an error. + value: 0 + - name: EnabledAndError + description: UPLL Clock Monitor is enabled and detected an error. + value: 1 +enum/Upllvld: + bit_size: 1 + variants: + - name: DisabledOrNotValid + description: UPLL is not enabled or clock is not valid. + value: 0 + - name: EnabledAndValid + description: UPLL is enabled and output clock is valid. + value: 1 enum/VoutSel: bit_size: 3 variants: - - name: VOUT_1V_1 + - name: Vout1v1 description: VOUT = 1V. value: 0 - - name: VOUT_1V_2 + - name: Vout1v2 description: VOUT = 1V. value: 1 - - name: VOUT_1V_3 + - name: Vout1v3 description: VOUT = 1V. value: 2 - - name: VOUT_105V + - name: Vout105v description: VOUT = 1.05V. value: 3 - - name: VOUT_11V + - name: Vout11v description: VOUT = 1.1V. value: 4 - - name: VOUT_115V + - name: Vout115v description: VOUT = 1.15V. value: 5 - - name: VOUT_12V + - name: Vout12v description: VOUT = 1.2V. value: 6 - - name: VOUT_125V + - name: Vout125v description: VOUT = 1.25V. value: 7 diff --git a/data/metadata/peripherals/mcxa/SGI.yaml b/data/metadata/peripherals/mcxa/SGI.yaml index 62d4931..46f5dc7 100644 --- a/data/metadata/peripherals/mcxa/SGI.yaml +++ b/data/metadata/peripherals/mcxa/SGI.yaml @@ -1,1643 +1,1643 @@ -block/SGI: +block/Sgi: description: no description available. items: - - name: SGI_DATIN0A + - name: sgi_datin0a description: Input Data register 0 - Word-3. byte_offset: 512 - fieldset: SGI_DATIN0A - - name: SGI_DATIN0B + fieldset: SgiDatin0a + - name: sgi_datin0b description: Input Data register 0 - Word-2. byte_offset: 516 - fieldset: SGI_DATIN0B - - name: SGI_DATIN0C + fieldset: SgiDatin0b + - name: sgi_datin0c description: Input Data register 0 - Word-1. byte_offset: 520 - fieldset: SGI_DATIN0C - - name: SGI_DATIN0D + fieldset: SgiDatin0c + - name: sgi_datin0d description: Input Data register 0 - Word-0. byte_offset: 524 - fieldset: SGI_DATIN0D - - name: SGI_DATIN1A + fieldset: SgiDatin0d + - name: sgi_datin1a description: Input Data register 1 - Word-3. byte_offset: 528 - fieldset: SGI_DATIN1A - - name: SGI_DATIN1B + fieldset: SgiDatin1a + - name: sgi_datin1b description: Input Data register 1 - Word-2. byte_offset: 532 - fieldset: SGI_DATIN1B - - name: SGI_DATIN1C + fieldset: SgiDatin1b + - name: sgi_datin1c description: Input Data register 1 - Word-1. byte_offset: 536 - fieldset: SGI_DATIN1C - - name: SGI_DATIN1D + fieldset: SgiDatin1c + - name: sgi_datin1d description: Input Data register 1 - Word-0. byte_offset: 540 - fieldset: SGI_DATIN1D - - name: SGI_DATIN2A + fieldset: SgiDatin1d + - name: sgi_datin2a description: Input Data register 2 - Word-3. byte_offset: 544 - fieldset: SGI_DATIN2A - - name: SGI_DATIN2B + fieldset: SgiDatin2a + - name: sgi_datin2b description: Input Data register 2 - Word-2. byte_offset: 548 - fieldset: SGI_DATIN2B - - name: SGI_DATIN2C + fieldset: SgiDatin2b + - name: sgi_datin2c description: Input Data register 2 - Word-1. byte_offset: 552 - fieldset: SGI_DATIN2C - - name: SGI_DATIN2D + fieldset: SgiDatin2c + - name: sgi_datin2d description: Input Data register 2 - Word-0. byte_offset: 556 - fieldset: SGI_DATIN2D - - name: SGI_DATIN3A + fieldset: SgiDatin2d + - name: sgi_datin3a description: Input Data register 3 - Word-3. byte_offset: 560 - fieldset: SGI_DATIN3A - - name: SGI_DATIN3B + fieldset: SgiDatin3a + - name: sgi_datin3b description: Input Data register 3 - Word-2. byte_offset: 564 - fieldset: SGI_DATIN3B - - name: SGI_DATIN3C + fieldset: SgiDatin3b + - name: sgi_datin3c description: Input Data register 3 - Word-1. byte_offset: 568 - fieldset: SGI_DATIN3C - - name: SGI_DATIN3D + fieldset: SgiDatin3c + - name: sgi_datin3d description: Input Data register 3 - Word-0. byte_offset: 572 - fieldset: SGI_DATIN3D - - name: SGI_KEY0A + fieldset: SgiDatin3d + - name: sgi_key0a description: Input Key register 0 - Word-3. byte_offset: 576 - fieldset: SGI_KEY0A - - name: SGI_KEY0B + fieldset: SgiKey0a + - name: sgi_key0b description: Input Key register 0 - Word-2. byte_offset: 580 - fieldset: SGI_KEY0B - - name: SGI_KEY0C + fieldset: SgiKey0b + - name: sgi_key0c description: Input Key register 0 - Word-1. byte_offset: 584 - fieldset: SGI_KEY0C - - name: SGI_KEY0D + fieldset: SgiKey0c + - name: sgi_key0d description: Input Key register 0 - Word-0. byte_offset: 588 - fieldset: SGI_KEY0D - - name: SGI_KEY1A + fieldset: SgiKey0d + - name: sgi_key1a description: Input Key register 1 - Word-3. byte_offset: 592 - fieldset: SGI_KEY1A - - name: SGI_KEY1B + fieldset: SgiKey1a + - name: sgi_key1b description: Input Key register 1 - Word-2. byte_offset: 596 - fieldset: SGI_KEY1B - - name: SGI_KEY1C + fieldset: SgiKey1b + - name: sgi_key1c description: Input Key register 1 - Word-1. byte_offset: 600 - fieldset: SGI_KEY1C - - name: SGI_KEY1D + fieldset: SgiKey1c + - name: sgi_key1d description: Input Key register 1 - Word-0. byte_offset: 604 - fieldset: SGI_KEY1D - - name: SGI_KEY2A + fieldset: SgiKey1d + - name: sgi_key2a description: Input Key register 2 - Word-3. byte_offset: 608 - fieldset: SGI_KEY2A - - name: SGI_KEY2B + fieldset: SgiKey2a + - name: sgi_key2b description: Input Key register 2 - Word-2. byte_offset: 612 - fieldset: SGI_KEY2B - - name: SGI_KEY2C + fieldset: SgiKey2b + - name: sgi_key2c description: Input Key register 2 - Word-1. byte_offset: 616 - fieldset: SGI_KEY2C - - name: SGI_KEY2D + fieldset: SgiKey2c + - name: sgi_key2d description: Input Key register 2 - Word-0. byte_offset: 620 - fieldset: SGI_KEY2D - - name: SGI_KEY3A + fieldset: SgiKey2d + - name: sgi_key3a description: Input Key register 3 - Word-3. byte_offset: 624 - fieldset: SGI_KEY3A - - name: SGI_KEY3B + fieldset: SgiKey3a + - name: sgi_key3b description: Input Key register 3 - Word-2. byte_offset: 628 - fieldset: SGI_KEY3B - - name: SGI_KEY3C + fieldset: SgiKey3b + - name: sgi_key3c description: Input Key register 3 - Word-1. byte_offset: 632 - fieldset: SGI_KEY3C - - name: SGI_KEY3D + fieldset: SgiKey3c + - name: sgi_key3d description: Input Key register 3 - Word-0. byte_offset: 636 - fieldset: SGI_KEY3D - - name: SGI_KEY4A + fieldset: SgiKey3d + - name: sgi_key4a description: Input Key register 4 - Word-3. byte_offset: 640 - fieldset: SGI_KEY4A - - name: SGI_KEY4B + fieldset: SgiKey4a + - name: sgi_key4b description: Input Key register 4 - Word-2. byte_offset: 644 - fieldset: SGI_KEY4B - - name: SGI_KEY4C + fieldset: SgiKey4b + - name: sgi_key4c description: Input Key register 4 - Word-1. byte_offset: 648 - fieldset: SGI_KEY4C - - name: SGI_KEY4D + fieldset: SgiKey4c + - name: sgi_key4d description: Input Key register 4 - Word-0. byte_offset: 652 - fieldset: SGI_KEY4D - - name: SGI_KEY5A + fieldset: SgiKey4d + - name: sgi_key5a description: Input Key register 5 - Word-3. byte_offset: 656 - fieldset: SGI_KEY5A - - name: SGI_KEY5B + fieldset: SgiKey5a + - name: sgi_key5b description: Input Key register 5 - Word-2. byte_offset: 660 - fieldset: SGI_KEY5B - - name: SGI_KEY5C + fieldset: SgiKey5b + - name: sgi_key5c description: Input Key register 5 - Word-1. byte_offset: 664 - fieldset: SGI_KEY5C - - name: SGI_KEY5D + fieldset: SgiKey5c + - name: sgi_key5d description: Input Key register 5 - Word-0. byte_offset: 668 - fieldset: SGI_KEY5D - - name: SGI_KEY6A + fieldset: SgiKey5d + - name: sgi_key6a description: Input Key register 6 - Word-3. byte_offset: 672 - fieldset: SGI_KEY6A - - name: SGI_KEY6B + fieldset: SgiKey6a + - name: sgi_key6b description: Input Key register 6 - Word-2. byte_offset: 676 - fieldset: SGI_KEY6B - - name: SGI_KEY6C + fieldset: SgiKey6b + - name: sgi_key6c description: Input Key register 6 - Word-1. byte_offset: 680 - fieldset: SGI_KEY6C - - name: SGI_KEY6D + fieldset: SgiKey6c + - name: sgi_key6d description: Input Key register 6 - Word-0. byte_offset: 684 - fieldset: SGI_KEY6D - - name: SGI_KEY7A + fieldset: SgiKey6d + - name: sgi_key7a description: Input Key register 7 - Word-3. byte_offset: 688 - fieldset: SGI_KEY7A - - name: SGI_KEY7B + fieldset: SgiKey7a + - name: sgi_key7b description: Input Key register 7 - Word-2. byte_offset: 692 - fieldset: SGI_KEY7B - - name: SGI_KEY7C + fieldset: SgiKey7b + - name: sgi_key7c description: Input Key register 7 - Word-1. byte_offset: 696 - fieldset: SGI_KEY7C - - name: SGI_KEY7D + fieldset: SgiKey7c + - name: sgi_key7d description: Input Key register 7 - Word-0. byte_offset: 700 - fieldset: SGI_KEY7D - - name: SGI_DATOUTA + fieldset: SgiKey7d + - name: sgi_datouta description: Output Data register - Word-3. byte_offset: 704 - fieldset: SGI_DATOUTA - - name: SGI_DATOUTB + fieldset: SgiDatouta + - name: sgi_datoutb description: Output Data register - Word-2. byte_offset: 708 - fieldset: SGI_DATOUTB - - name: SGI_DATOUTC + fieldset: SgiDatoutb + - name: sgi_datoutc description: Output Data register - Word-1. byte_offset: 712 - fieldset: SGI_DATOUTC - - name: SGI_DATOUTD + fieldset: SgiDatoutc + - name: sgi_datoutd description: Output Data register - Word-0. byte_offset: 716 - fieldset: SGI_DATOUTD - - name: SGI_STATUS + fieldset: SgiDatoutd + - name: sgi_status description: Status register. byte_offset: 3072 - fieldset: SGI_STATUS - - name: SGI_COUNT + fieldset: SgiStatus + - name: sgi_count description: Calculation counter. byte_offset: 3076 - fieldset: SGI_COUNT - - name: SGI_KEYCHK + fieldset: SgiCount + - name: sgi_keychk description: Key checksum register. byte_offset: 3080 - fieldset: SGI_KEYCHK - - name: SGI_CTRL + fieldset: SgiKeychk + - name: sgi_ctrl description: SGI Control register. byte_offset: 3328 - fieldset: SGI_CTRL - - name: SGI_CTRL2 + fieldset: SgiCtrl + - name: sgi_ctrl2 description: SGI Control register 2. byte_offset: 3332 - fieldset: SGI_CTRL2 - - name: SGI_DUMMY_CTRL + fieldset: SgiCtrl2 + - name: sgi_dummy_ctrl description: Configuration of dummy controls. byte_offset: 3336 - fieldset: SGI_DUMMY_CTRL - - name: SGI_SFRSEED + fieldset: SgiDummyCtrl + - name: sgi_sfrseed description: SFRSEED register for SFRMASK feature. byte_offset: 3344 - fieldset: SGI_SFRSEED - - name: SGI_SHA2_CTRL + fieldset: SgiSfrseed + - name: sgi_sha2_ctrl description: SHA Control Register. byte_offset: 3348 - fieldset: SGI_SHA2_CTRL - - name: SGI_SHA_FIFO + fieldset: SgiSha2Ctrl + - name: sgi_sha_fifo description: SHA FIFO lower-bank low. byte_offset: 3352 - fieldset: SGI_SHA_FIFO - - name: SGI_CONFIG + fieldset: SgiShaFifo + - name: sgi_config description: SHA Configuration Reg. byte_offset: 3356 access: Read - fieldset: SGI_CONFIG - - name: SGI_CONFIG2 + fieldset: SgiConfig + - name: sgi_config2 description: SHA Configuration 2 Reg. byte_offset: 3360 access: Read - fieldset: SGI_CONFIG2 - - name: SGI_AUTO_MODE + fieldset: SgiConfig2 + - name: sgi_auto_mode description: SGI Auto Mode Control register. byte_offset: 3364 - fieldset: SGI_AUTO_MODE - - name: SGI_AUTO_DMA_CTRL + fieldset: SgiAutoMode + - name: sgi_auto_dma_ctrl description: SGI Auto Mode Control register. byte_offset: 3368 - fieldset: SGI_AUTO_DMA_CTRL - - name: SGI_PRNG_SW_SEED + fieldset: SgiAutoDmaCtrl + - name: sgi_prng_sw_seed description: SGI internal PRNG SW seeding register. byte_offset: 3376 - fieldset: SGI_PRNG_SW_SEED - - name: SGI_KEY_CTRL + fieldset: SgiPrngSwSeed + - name: sgi_key_ctrl description: SGI Key Control SFR. byte_offset: 3392 - fieldset: SGI_KEY_CTRL - - name: SGI_KEY_WRAP + fieldset: SgiKeyCtrl + - name: sgi_key_wrap description: Wrapped key read SFR. byte_offset: 3408 access: Read - fieldset: SGI_KEY_WRAP - - name: SGI_VERSION + fieldset: SgiKeyWrap + - name: sgi_version description: SGI Version. byte_offset: 3848 access: Read - fieldset: SGI_VERSION - - name: SGI_ACCESS_ERR + fieldset: SgiVersion + - name: sgi_access_err description: Access Error. byte_offset: 4032 - fieldset: SGI_ACCESS_ERR - - name: SGI_ACCESS_ERR_CLR + fieldset: SgiAccessErr + - name: sgi_access_err_clr description: Clear Access Error. byte_offset: 4036 - fieldset: SGI_ACCESS_ERR_CLR - - name: SGI_INT_STATUS + fieldset: SgiAccessErrClr + - name: sgi_int_status description: Interrupt status. byte_offset: 4064 access: Read - fieldset: SGI_INT_STATUS - - name: SGI_INT_ENABLE + fieldset: SgiIntStatus + - name: sgi_int_enable description: Interrupt enable. byte_offset: 4068 - fieldset: SGI_INT_ENABLE - - name: SGI_INT_STATUS_CLR + fieldset: SgiIntEnable + - name: sgi_int_status_clr description: Interrupt status clear. byte_offset: 4072 - fieldset: SGI_INT_STATUS_CLR - - name: SGI_INT_STATUS_SET + fieldset: SgiIntStatusClr + - name: sgi_int_status_set description: Interrupt status set. byte_offset: 4076 - fieldset: SGI_INT_STATUS_SET - - name: SGI_MODULE_ID + fieldset: SgiIntStatusSet + - name: sgi_module_id description: Module ID. byte_offset: 4092 access: Read - fieldset: SGI_MODULE_ID -fieldset/SGI_ACCESS_ERR: + fieldset: SgiModuleId +fieldset/SgiAccessErr: description: Access Error. fields: - - name: APB_NOTAV + - name: apb_notav description: 'APB Error: address not available.' bit_offset: 0 bit_size: 1 - - name: APB_WRGMD + - name: apb_wrgmd description: 'APB Error: Wrong access mode.' bit_offset: 1 bit_size: 1 - - name: APB_MASTER + - name: apb_master description: APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV). bit_offset: 4 bit_size: 4 -fieldset/SGI_ACCESS_ERR_CLR: +fieldset/SgiAccessErrClr: description: Clear Access Error. fields: - - name: ERR_CLR + - name: err_clr description: Write to reset SGI_ACCESS_ERR SFR. bit_offset: 0 bit_size: 1 -fieldset/SGI_AUTO_DMA_CTRL: +fieldset/SgiAutoDmaCtrl: description: SGI Auto Mode Control register. fields: - - name: IFE + - name: ife description: Input FIFO DMA Enable. bit_offset: 0 bit_size: 1 - - name: OFE + - name: ofe description: Ouput FIFO DMA Enable. bit_offset: 8 bit_size: 1 -fieldset/SGI_AUTO_MODE: +fieldset/SgiAutoMode: description: SGI Auto Mode Control register. fields: - - name: AUTO_MODE_EN + - name: auto_mode_en description: auto_start_en. bit_offset: 0 bit_size: 1 - - name: AUTO_MODE_STOP + - name: auto_mode_stop description: auto_mode_stop. bit_offset: 1 bit_size: 1 - - name: INCR_MODE + - name: incr_mode description: CTR increment mode. bit_offset: 4 bit_size: 2 - enum: INCR_MODE - - name: CMD + enum: IncrMode + - name: cmd description: Auto mode of operation. bit_offset: 8 bit_size: 8 - enum: CMD -fieldset/SGI_CONFIG: + enum: Cmd +fieldset/SgiConfig: description: SHA Configuration Reg. fields: - - name: ROW + - name: row description: SGI Diversified for 'ROW'. bit_offset: 0 bit_size: 1 - - name: CHINA + - name: china description: SGI Diversified for 'CHINA'. bit_offset: 1 bit_size: 1 - - name: CC + - name: cc description: SGI Diversified for 'CC'. bit_offset: 2 bit_size: 1 - - name: HAS_AES + - name: has_aes description: HAS AES. bit_offset: 3 bit_size: 1 - - name: HAS_DES + - name: has_des description: HAS DES. bit_offset: 4 bit_size: 1 - - name: HAS_SHA + - name: has_sha description: HAS SHA. bit_offset: 5 bit_size: 1 - - name: HAS_MOVEM + - name: has_movem description: HAS MOVEM. bit_offset: 6 bit_size: 1 - - name: HAS_CMAC + - name: has_cmac description: HAS CMAC. bit_offset: 7 bit_size: 1 - - name: HAS_GFMUL + - name: has_gfmul description: HAS GFMUL. bit_offset: 8 bit_size: 1 - - name: INTERNAL_PRNG + - name: internal_prng description: HAS INTERNAL PRNG. bit_offset: 9 bit_size: 1 - - name: KEY_DIGEST + - name: key_digest description: HAS KEY DIGEST. bit_offset: 10 bit_size: 1 - - name: COUNT_SIZE + - name: count_size description: 0 - COUNT=16, 1 - COUNT=32. bit_offset: 11 bit_size: 1 - - name: FA + - name: fa description: HAS FA protection. bit_offset: 13 bit_size: 1 - - name: BUS_WIDTH + - name: bus_width description: 0 - BUS_WIDTH=16, 1 - BUS_WIDTH=32. bit_offset: 15 bit_size: 1 - - name: NUM_DATIN + - name: num_datin description: NUMBER OF DATIN REGBANKS. bit_offset: 16 bit_size: 2 - - name: NUM_KEY + - name: num_key description: NUMBER OR KEY REGBANKS. bit_offset: 18 bit_size: 3 - - name: EDC + - name: edc description: DATIN to KERNEL End-to-end EDC is enabled. bit_offset: 21 bit_size: 1 - - name: SHA_256_ONLY + - name: sha_256_only description: HAS SHA-256 ONLY. bit_offset: 24 bit_size: 1 - - name: SPB_SUPPORT + - name: spb_support description: ID_CFG_SGI_SPB_SUPPORT is set. bit_offset: 25 bit_size: 1 - - name: SPB_MASKING + - name: spb_masking description: ID_CFG_SGI_SPB_MASKING is set. bit_offset: 26 bit_size: 1 - - name: SFR_SW_MASK + - name: sfr_sw_mask description: ID_CFG_SGI_USE_SFR_SW_MASK is set. bit_offset: 27 bit_size: 1 -fieldset/SGI_CONFIG2: +fieldset/SgiConfig2: description: SHA Configuration 2 Reg. fields: - - name: AES_USED + - name: aes_used description: no description available. bit_offset: 0 bit_size: 4 - enum: AES_USED - - name: AES_NUM_SBOXES + enum: AesUsed + - name: aes_num_sboxes description: Number of AES sboxes. bit_offset: 4 bit_size: 5 - - name: AES_KEYSIZE + - name: aes_keysize description: Indicates which AES key size has been selected. bit_offset: 9 bit_size: 2 - enum: AES_KEYSIZE - - name: DES_USED + enum: AesKeysize + - name: des_used description: no description available. bit_offset: 16 bit_size: 4 - enum: DES_USED - - name: DES_NUM_SBOXES + enum: DesUsed + - name: des_num_sboxes description: Number of DES sboxes. bit_offset: 20 bit_size: 5 -fieldset/SGI_COUNT: +fieldset/SgiCount: description: Calculation counter. fields: - - name: COUNT + - name: count description: Calculation counter, incremented with each calculation start. bit_offset: 0 bit_size: 16 -fieldset/SGI_CTRL: +fieldset/SgiCtrl: description: SGI Control register. fields: - - name: START + - name: start description: Start crypto operation. bit_offset: 0 bit_size: 1 - enum: START - - name: DECRYPT + enum: Start + - name: decrypt description: Sets Cipher direction(AES and DES). bit_offset: 1 bit_size: 1 - enum: DECRYPT - - name: AESKEYSZ + enum: Decrypt + - name: aeskeysz description: Sets AES key size. bit_offset: 2 bit_size: 2 - enum: AESKEYSZ - - name: CRYPTO_OP + enum: Aeskeysz + - name: crypto_op description: Sets 'Crypto Operation' type. bit_offset: 4 bit_size: 3 - enum: CRYPTO_OP - - name: INSEL + enum: CryptoOp + - name: insel description: no description available. bit_offset: 7 bit_size: 4 - enum: INSEL - - name: OUTSEL + enum: Insel + - name: outsel description: no description available. bit_offset: 11 bit_size: 3 - enum: OUTSEL - - name: DATOUT_RES + enum: Outsel + - name: datout_res description: Kernels data out options. bit_offset: 14 bit_size: 2 - enum: DATOUT_RES - - name: AES_EN + enum: DatoutRes + - name: aes_en description: AES Kernel Enable. bit_offset: 16 bit_size: 1 - - name: DES_EN + - name: des_en description: DES Kernel Enable. bit_offset: 17 bit_size: 1 - - name: GCM_EN + - name: gcm_en description: GFMUL Kernel Enable. bit_offset: 18 bit_size: 1 - - name: PRNG_EN + - name: prng_en description: PRNG Enable (only if SGI has internal PRNG). bit_offset: 19 bit_size: 1 - - name: INKEYSEL + - name: inkeysel description: Input key selection. bit_offset: 20 bit_size: 5 - - name: TDESKEY + - name: tdeskey description: Triple-DES Key Configuration. bit_offset: 25 bit_size: 1 - enum: TDESKEY - - name: AES_NO_KL + enum: Tdeskey + - name: aes_no_kl description: AES No decryption key scheduleThis bit is only supported for select configurations of the SGI. bit_offset: 26 bit_size: 1 - enum: AES_NO_KL - - name: AES_SEL + enum: AesNoKl + - name: aes_sel description: AES Dual Selection. bit_offset: 27 bit_size: 1 - enum: AES_SEL -fieldset/SGI_CTRL2: + enum: AesSel +fieldset/SgiCtrl2: description: SGI Control register 2. fields: - - name: FLUSH + - name: flush description: Start Full SGI Flush. bit_offset: 0 bit_size: 1 - enum: FLUSH - - name: KEY_FLUSH + enum: Flush + - name: key_flush description: Start KEY register-bank Flush. bit_offset: 1 bit_size: 1 - enum: KEY_FLUSH - - name: DATIN_FLUSH + enum: KeyFlush + - name: datin_flush description: Start DATIN register-bank Flush. bit_offset: 2 bit_size: 1 - enum: DATIN_FLUSH - - name: INCR + enum: DatinFlush + - name: incr description: Increment(Triggered by SFR write). bit_offset: 3 bit_size: 1 - - name: XORWR + - name: xorwr description: Write-XOR control. bit_offset: 4 bit_size: 1 - - name: FLUSHWR + - name: flushwr description: Flush Write control. bit_offset: 5 bit_size: 1 - - name: INCR_CIN + - name: incr_cin description: Increment Carry-In control. bit_offset: 6 bit_size: 1 - enum: INCR_CIN - - name: SMASKEN + enum: IncrCin + - name: smasken description: SFRMASK Enable. bit_offset: 8 bit_size: 1 - - name: SMASKSTEP + - name: smaskstep description: SFRSEED increment control. bit_offset: 9 bit_size: 1 - enum: SMASKSTEP - - name: SMASKSW + enum: Smaskstep + - name: smasksw description: SFRMASK MASK control. bit_offset: 10 bit_size: 1 - enum: SMASKSW - - name: MOVEM + enum: Smasksw + - name: movem description: 4-bit optional input for MOVEM feature. bit_offset: 12 bit_size: 4 - - name: KEYRES + - name: keyres description: Selects key registers to be updated when rkey=1. bit_offset: 16 bit_size: 5 - - name: RKEY + - name: rkey description: Crypto result location. bit_offset: 21 bit_size: 1 - enum: RKEY - - name: BYTES_ORDER + enum: Rkey + - name: bytes_order description: Byte order of regbank read/write data. bit_offset: 22 bit_size: 1 - enum: BYTES_ORDER - - name: GCM_INXOR + enum: BytesOrder + - name: gcm_inxor description: GCM INXOR. bit_offset: 23 bit_size: 1 -fieldset/SGI_DATIN0A: +fieldset/SgiDatin0a: description: Input Data register 0 - Word-3. fields: - - name: DATIN0A + - name: datin0a description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN0B: +fieldset/SgiDatin0b: description: Input Data register 0 - Word-2. fields: - - name: DATIN0B + - name: datin0b description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN0C: +fieldset/SgiDatin0c: description: Input Data register 0 - Word-1. fields: - - name: DATIN0C + - name: datin0c description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN0D: +fieldset/SgiDatin0d: description: Input Data register 0 - Word-0. fields: - - name: DATIN0D + - name: datin0d description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN1A: +fieldset/SgiDatin1a: description: Input Data register 1 - Word-3. fields: - - name: DATIN1A + - name: datin1a description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN1B: +fieldset/SgiDatin1b: description: Input Data register 1 - Word-2. fields: - - name: DATIN1B + - name: datin1b description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN1C: +fieldset/SgiDatin1c: description: Input Data register 1 - Word-1. fields: - - name: DATIN1C + - name: datin1c description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN1D: +fieldset/SgiDatin1d: description: Input Data register 1 - Word-0. fields: - - name: DATIN1D + - name: datin1d description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN2A: +fieldset/SgiDatin2a: description: Input Data register 2 - Word-3. fields: - - name: DATIN2A + - name: datin2a description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN2B: +fieldset/SgiDatin2b: description: Input Data register 2 - Word-2. fields: - - name: DATIN2B + - name: datin2b description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN2C: +fieldset/SgiDatin2c: description: Input Data register 2 - Word-1. fields: - - name: DATIN2C + - name: datin2c description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN2D: +fieldset/SgiDatin2d: description: Input Data register 2 - Word-0. fields: - - name: DATIN2D + - name: datin2d description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN3A: +fieldset/SgiDatin3a: description: Input Data register 3 - Word-3. fields: - - name: DATIN3A + - name: datin3a description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN3B: +fieldset/SgiDatin3b: description: Input Data register 3 - Word-2. fields: - - name: DATIN3B + - name: datin3b description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN3C: +fieldset/SgiDatin3c: description: Input Data register 3 - Word-1. fields: - - name: DATIN3C + - name: datin3c description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATIN3D: +fieldset/SgiDatin3d: description: Input Data register 3 - Word-0. fields: - - name: DATIN3D + - name: datin3d description: Input Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATOUTA: +fieldset/SgiDatouta: description: Output Data register - Word-3. fields: - - name: DATOUTA + - name: datouta description: Output Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATOUTB: +fieldset/SgiDatoutb: description: Output Data register - Word-2. fields: - - name: DATOUTB + - name: datoutb description: Output Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATOUTC: +fieldset/SgiDatoutc: description: Output Data register - Word-1. fields: - - name: DATOUTC + - name: datoutc description: Output Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DATOUTD: +fieldset/SgiDatoutd: description: Output Data register - Word-0. fields: - - name: DATOUTD + - name: datoutd description: Output Data register. bit_offset: 0 bit_size: 32 -fieldset/SGI_DUMMY_CTRL: +fieldset/SgiDummyCtrl: description: Configuration of dummy controls. fields: - - name: DDCTRL + - name: ddctrl description: DES dummy controlPlease refer to the relevant kernel document for details on dummy ctrl. bit_offset: 0 bit_size: 10 - - name: ADCTRL + - name: adctrl description: AES dummy controlPlease refer to the relevant kernel document for details on dummy ctrl. bit_offset: 16 bit_size: 10 -fieldset/SGI_INT_ENABLE: +fieldset/SgiIntEnable: description: Interrupt enable. fields: - - name: INT_EN + - name: int_en description: Interrupt enable bit. bit_offset: 0 bit_size: 1 -fieldset/SGI_INT_STATUS: +fieldset/SgiIntStatus: description: Interrupt status. fields: - - name: INT_PDONE + - name: int_pdone description: 'Interrupt status flag: INT_PDONE is set independent from the interrupt enable SGI_INT_ENABLE.' bit_offset: 0 bit_size: 1 -fieldset/SGI_INT_STATUS_CLR: +fieldset/SgiIntStatusClr: description: Interrupt status clear. fields: - - name: INT_CLR + - name: int_clr description: Write to clear interrupt status flag (SGI_INT_STATUS.INT_PDONE=0). bit_offset: 0 bit_size: 1 -fieldset/SGI_INT_STATUS_SET: +fieldset/SgiIntStatusSet: description: Interrupt status set. fields: - - name: INT_SET + - name: int_set description: Write to set interrupt status flag (SGI_INT_STATUS.INT_PDONE=1) to trigger a SGI interrupt via software, e.g. for debug purposes. bit_offset: 0 bit_size: 1 -fieldset/SGI_KEY0A: +fieldset/SgiKey0a: description: Input Key register 0 - Word-3. fields: - - name: KEY0A + - name: key0a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY0B: +fieldset/SgiKey0b: description: Input Key register 0 - Word-2. fields: - - name: KEY0B + - name: key0b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY0C: +fieldset/SgiKey0c: description: Input Key register 0 - Word-1. fields: - - name: KEY0C + - name: key0c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY0D: +fieldset/SgiKey0d: description: Input Key register 0 - Word-0. fields: - - name: KEY0D + - name: key0d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY1A: +fieldset/SgiKey1a: description: Input Key register 1 - Word-3. fields: - - name: KEY1A + - name: key1a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY1B: +fieldset/SgiKey1b: description: Input Key register 1 - Word-2. fields: - - name: KEY1B + - name: key1b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY1C: +fieldset/SgiKey1c: description: Input Key register 1 - Word-1. fields: - - name: KEY1C + - name: key1c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY1D: +fieldset/SgiKey1d: description: Input Key register 1 - Word-0. fields: - - name: KEY1D + - name: key1d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY2A: +fieldset/SgiKey2a: description: Input Key register 2 - Word-3. fields: - - name: KEY2A + - name: key2a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY2B: +fieldset/SgiKey2b: description: Input Key register 2 - Word-2. fields: - - name: KEY2B + - name: key2b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY2C: +fieldset/SgiKey2c: description: Input Key register 2 - Word-1. fields: - - name: KEY2C + - name: key2c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY2D: +fieldset/SgiKey2d: description: Input Key register 2 - Word-0. fields: - - name: KEY2D + - name: key2d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY3A: +fieldset/SgiKey3a: description: Input Key register 3 - Word-3. fields: - - name: KEY3A + - name: key3a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY3B: +fieldset/SgiKey3b: description: Input Key register 3 - Word-2. fields: - - name: KEY3B + - name: key3b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY3C: +fieldset/SgiKey3c: description: Input Key register 3 - Word-1. fields: - - name: KEY3C + - name: key3c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY3D: +fieldset/SgiKey3d: description: Input Key register 3 - Word-0. fields: - - name: KEY3D + - name: key3d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY4A: +fieldset/SgiKey4a: description: Input Key register 4 - Word-3. fields: - - name: KEY4A + - name: key4a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY4B: +fieldset/SgiKey4b: description: Input Key register 4 - Word-2. fields: - - name: KEY4B + - name: key4b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY4C: +fieldset/SgiKey4c: description: Input Key register 4 - Word-1. fields: - - name: KEY4C + - name: key4c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY4D: +fieldset/SgiKey4d: description: Input Key register 4 - Word-0. fields: - - name: KEY4D + - name: key4d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY5A: +fieldset/SgiKey5a: description: Input Key register 5 - Word-3. fields: - - name: KEY5A + - name: key5a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY5B: +fieldset/SgiKey5b: description: Input Key register 5 - Word-2. fields: - - name: KEY5B + - name: key5b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY5C: +fieldset/SgiKey5c: description: Input Key register 5 - Word-1. fields: - - name: KEY5C + - name: key5c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY5D: +fieldset/SgiKey5d: description: Input Key register 5 - Word-0. fields: - - name: KEY5D + - name: key5d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY6A: +fieldset/SgiKey6a: description: Input Key register 6 - Word-3. fields: - - name: KEY6A + - name: key6a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY6B: +fieldset/SgiKey6b: description: Input Key register 6 - Word-2. fields: - - name: KEY6B + - name: key6b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY6C: +fieldset/SgiKey6c: description: Input Key register 6 - Word-1. fields: - - name: KEY6C + - name: key6c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY6D: +fieldset/SgiKey6d: description: Input Key register 6 - Word-0. fields: - - name: KEY6D + - name: key6d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY7A: +fieldset/SgiKey7a: description: Input Key register 7 - Word-3. fields: - - name: KEY7A + - name: key7a description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY7B: +fieldset/SgiKey7b: description: Input Key register 7 - Word-2. fields: - - name: KEY7B + - name: key7b description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY7C: +fieldset/SgiKey7c: description: Input Key register 7 - Word-1. fields: - - name: KEY7C + - name: key7c description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY7D: +fieldset/SgiKey7d: description: Input Key register 7 - Word-0. fields: - - name: KEY7D + - name: key7d description: Input Key register. bit_offset: 0 bit_size: 32 -fieldset/SGI_KEYCHK: - description: Key checksum register. - fields: - - name: KEYCHKSUM - description: Key checksum (32-bit). - bit_offset: 0 - bit_size: 32 -fieldset/SGI_KEY_CTRL: +fieldset/SgiKeyCtrl: description: SGI Key Control SFR. fields: - - name: KEY_WO + - name: key_wo description: SGI Key control register(1-bit per KEY SFR) 1'b0 - Key SFR is readable 1'b1 - Key SFR is not-readable(write-only). bit_offset: 0 bit_size: 32 -fieldset/SGI_KEY_WRAP: +fieldset/SgiKeyWrap: description: Wrapped key read SFR. fields: - - name: KW_DATA + - name: kw_data description: Field contains wrapped key, auto-updated by HW for each word. bit_offset: 0 bit_size: 32 -fieldset/SGI_MODULE_ID: +fieldset/SgiKeychk: + description: Key checksum register. + fields: + - name: keychksum + description: Key checksum (32-bit). + bit_offset: 0 + bit_size: 32 +fieldset/SgiModuleId: description: Module ID. fields: - - name: PLACEHOLDER + - name: placeholder description: Module ID. bit_offset: 0 bit_size: 32 -fieldset/SGI_PRNG_SW_SEED: +fieldset/SgiPrngSwSeed: description: SGI internal PRNG SW seeding register. fields: - - name: SEED + - name: seed description: 32-bits SEED field. A write to the SEED field will seed the internal PRNG. bit_offset: 0 bit_size: 32 -fieldset/SGI_SFRSEED: +fieldset/SgiSfrseed: description: SFRSEED register for SFRMASK feature. fields: - - name: SFRSEED + - name: sfrseed description: Seed/mask used for sw level masking. bit_offset: 0 bit_size: 32 -fieldset/SGI_SHA2_CTRL: +fieldset/SgiSha2Ctrl: description: SHA Control Register. fields: - - name: SHA2_EN + - name: sha2_en description: SHA enable. bit_offset: 0 bit_size: 1 - - name: SHA2_MODE + - name: sha2_mode description: SHA mode normal or automatic. bit_offset: 1 bit_size: 1 - enum: SHA2_MODE - - name: SHA2_SIZE + enum: Sha2Mode + - name: sha2_size description: Indicates SHA size. bit_offset: 2 bit_size: 2 - enum: SHA2_SIZE - - name: SHA2_LOW_LIM + enum: Sha2Size + - name: sha2_low_lim description: SHA FIFO low limit. bit_offset: 4 bit_size: 4 - - name: SHA2_HIGH_LIM + - name: sha2_high_lim description: SHA FIFO high limit. bit_offset: 8 bit_size: 4 - - name: SHA2_COUNT_EN + - name: sha2_count_en description: SHA Calculation counter enable. bit_offset: 12 bit_size: 1 - enum: SHA2_COUNT_EN - - name: HASH_RELOAD + enum: Sha2CountEn + - name: hash_reload description: SHA HASH reload. bit_offset: 13 bit_size: 1 - - name: SHA2_STOP + - name: sha2_stop description: STOP SHA AUTO mode. bit_offset: 14 bit_size: 1 - enum: SHA2_STOP - - name: NO_AUTO_INIT + enum: Sha2Stop + - name: no_auto_init description: SHA no automatic HASH initialisation. bit_offset: 15 bit_size: 1 - enum: NO_AUTO_INIT -fieldset/SGI_SHA_FIFO: + enum: NoAutoInit +fieldset/SgiShaFifo: description: SHA FIFO lower-bank low. fields: - - name: FIFO + - name: fifo description: SHA FIFO register. bit_offset: 0 bit_size: 32 -fieldset/SGI_STATUS: +fieldset/SgiStatus: description: Status register. fields: - - name: BUSY + - name: busy description: Combined busy flag that remains high until end of calculation. bit_offset: 0 bit_size: 1 - - name: OFLOW + - name: oflow description: Overflow in INCR operation flag. bit_offset: 1 bit_size: 1 - - name: PRNG_RDY + - name: prng_rdy description: prng is ready after boot-up-phase. bit_offset: 2 bit_size: 1 - - name: ERROR + - name: error description: Error detected. bit_offset: 3 bit_size: 3 - enum: ERROR - - name: SHA2_BUSY + enum: Error + - name: sha2_busy description: SHA2 is busy. bit_offset: 6 bit_size: 1 - - name: IRQ + - name: irq description: interrupt detected. bit_offset: 7 bit_size: 1 - - name: SHA_FIFO_FULL + - name: sha_fifo_full description: SHA FIFO is full(operates in SHA AUTO mode). bit_offset: 8 bit_size: 1 - - name: SHA_FIFO_LEVEL + - name: sha_fifo_level description: SHA FIFO level. bit_offset: 9 bit_size: 6 - - name: SHA_ERROR + - name: sha_error description: SHA ERROR. bit_offset: 15 bit_size: 1 - - name: KEY_READ_ERR + - name: key_read_err description: KEY SFR READ ERROR, sticky, cleared only with reset or flush. bit_offset: 16 bit_size: 1 - - name: KEY_UNWRAP_ERR + - name: key_unwrap_err description: KEY UNWRAP ERROR , sticky, cleared only with reset or flush. bit_offset: 17 bit_size: 1 -fieldset/SGI_VERSION: +fieldset/SgiVersion: description: SGI Version. fields: - - name: Z + - name: z description: Extended revision number in X.Y1Y2.Z, e.g. 1.20.3. bit_offset: 0 bit_size: 4 - - name: Y2 + - name: y2 description: Minor revision number 2 in X.Y1Y2.Z, e.g. 1.20.3. bit_offset: 4 bit_size: 4 - - name: Y1 + - name: y1 description: Minor revision number 1 in X.Y1Y2.Z, e.g. 1.20.3. bit_offset: 8 bit_size: 4 - - name: X + - name: x description: Major revision number in X.Y1Y2.Z, e.g. 1.20.3. bit_offset: 12 bit_size: 4 - - name: MILESTONE + - name: milestone description: Release milestone. bit_offset: 16 bit_size: 2 - enum: MILESTONE -enum/AESKEYSZ: - bit_size: 2 - variants: - - name: aes_128 - description: AES-128. - value: 0 - - name: aes_192 - description: AES-192. - value: 1 - - name: aes_256 - description: AES-256. - value: 2 - - name: rfu - description: RFU (defaults to AES-128). - value: 3 -enum/AES_KEYSIZE: + enum: Milestone +enum/AesKeysize: bit_size: 2 variants: - - name: aes_128_only + - name: Aes128Only description: 128 0nly. value: 0 - - name: aes_192_only + - name: Aes192Only description: 192 only. value: 1 - - name: aes_256_only + - name: Aes256Only description: 256 only. value: 2 - - name: all_keysize + - name: AllKeysize description: All key sizes. value: 3 -enum/AES_NO_KL: +enum/AesNoKl: bit_size: 1 variants: - - name: new + - name: New description: new AES key will be loaded. value: 0 - - name: no + - name: No description: No AES key will be loaded, and previously loaded key will be used. value: 1 -enum/AES_SEL: +enum/AesSel: bit_size: 1 variants: - - name: first_aes + - name: FirstAes description: First AES selected. value: 0 - - name: second_aes + - name: SecondAes description: Second AES selected (when enabled). value: 1 -enum/AES_USED: +enum/AesUsed: bit_size: 4 variants: - - name: apollo + - name: Apollo description: Apollo. value: 0 - - name: aegis + - name: Aegis description: Aegis. value: 1 - - name: ayna + - name: Ayna description: Ayna. value: 2 - - name: athenium + - name: Athenium description: Athenium. value: 3 - - name: ajax + - name: Ajax description: Ajax. value: 4 - - name: aegis_hs + - name: AegisHs description: Aegis_hs. value: 5 - - name: athenium_hs + - name: AtheniumHs description: Athenium_hs. value: 6 - - name: ate + - name: Ate description: ATE. value: 7 - - name: atom + - name: Atom description: ATOM. value: 8 - - name: asterix + - name: Asterix description: Asterix. value: 9 - - name: rfu_10 + - name: Rfu10 description: RFU. value: 10 - - name: rfu_11 + - name: Rfu11 description: RFU. value: 11 - - name: rfu_12 + - name: Rfu12 description: RFU. value: 12 - - name: rfu_13 + - name: Rfu13 description: RFU. value: 13 - - name: rfu_14 + - name: Rfu14 description: RFU. value: 14 - - name: rfu_15 + - name: Rfu15 description: RFU. value: 15 -enum/BYTES_ORDER: +enum/Aeskeysz: + bit_size: 2 + variants: + - name: Aes128 + description: AES-128. + value: 0 + - name: Aes192 + description: AES-192. + value: 1 + - name: Aes256 + description: AES-256. + value: 2 + - name: Rfu + description: RFU (defaults to AES-128). + value: 3 +enum/BytesOrder: bit_size: 1 variants: - - name: normal_order + - name: NormalOrder description: Normal. value: 0 - - name: swapped_order + - name: SwappedOrder description: Swapped. value: 1 -enum/CMD: +enum/Cmd: bit_size: 8 variants: - - name: ecb + - name: Ecb description: ECB mode. value: 0 - - name: ctr + - name: Ctr description: CTR mode. value: 1 - - name: cbc + - name: Cbc description: CBC mode. value: 2 - - name: cbcmac + - name: Cbcmac description: CBCMAC mode. value: 3 - - name: wrap_128_bit + - name: Wrap128Bit description: Key Wrap/Unwrap (128 bit key data). value: 16 - - name: wrap_256_bit + - name: Wrap256Bit description: Key Wrap/Unwrap (256 bit key data). value: 17 -enum/CRYPTO_OP: +enum/CryptoOp: bit_size: 3 variants: - - name: aes + - name: Aes description: AES. value: 0 - - name: des + - name: Des description: DES (If Included). value: 1 - - name: tdes + - name: Tdes description: TDES (If Included). value: 2 - - name: gfmul + - name: Gfmul description: GFMUL(If Included). value: 3 - - name: sha + - name: Sha description: SHA2 (If Included). value: 4 - - name: cmac + - name: Cmac description: CMAC (If Included). value: 5 - - name: others_6 + - name: Others6 description: others - RFU (Defaults to 1st available OP). value: 6 - - name: others_7 + - name: Others7 description: others - RFU (Defaults to 1st available OP). value: 7 -enum/DATIN_FLUSH: +enum/DatinFlush: bit_size: 1 variants: - - name: no_effect + - name: NoEffect description: Clr has no effect. value: 0 - - name: flush + - name: Flush description: Set to start flush. value: 1 -enum/DATOUT_RES: +enum/DatoutRes: bit_size: 2 variants: - - name: end_up + - name: EndUp description: END_UP. value: 0 - - name: start_up + - name: StartUp description: START_UP. value: 1 - - name: trigger_up + - name: TriggerUp description: TRIGGER_UP. value: 2 - - name: no_up + - name: NoUp description: NO_UP. value: 3 -enum/DECRYPT: +enum/Decrypt: bit_size: 1 variants: - - name: enc + - name: Enc description: Encryption. value: 0 - - name: dec + - name: Dec description: Decryption. value: 1 -enum/DES_USED: +enum/DesUsed: bit_size: 4 variants: - - name: dakar + - name: Dakar description: Dakar. value: 0 - - name: danube + - name: Danube description: Danube. value: 1 - - name: depicta + - name: Depicta description: Depicta. value: 2 - - name: digi + - name: Digi description: Digi. value: 3 - - name: date + - name: Date description: Date. value: 4 - - name: desert + - name: Desert description: Desert. value: 5 - - name: rfu_6 + - name: Rfu6 description: RFU. value: 6 - - name: rfu_7 + - name: Rfu7 description: RFU. value: 7 - - name: rfu_8 + - name: Rfu8 description: RFU. value: 8 - - name: rfu_9 + - name: Rfu9 description: RFU. value: 9 -enum/ERROR: +enum/Error: bit_size: 3 variants: - - name: error + - name: Error description: ERROR (all values other than 0x05 indicate ERROR). value: 0 - - name: no_error + - name: NoError description: NO_ERROR. value: 5 -enum/FLUSH: +enum/Flush: bit_size: 1 variants: - - name: no_effect + - name: NoEffect description: Clr has no effect. value: 0 - - name: flush + - name: Flush description: Set to start flush. value: 1 -enum/INCR_CIN: +enum/IncrCin: bit_size: 1 variants: - - name: incr_one + - name: IncrOne description: Carry-In for INCR is 1. value: 0 - - name: incr_previous + - name: IncrPrevious description: Carry-In for INCR is overflow from previous INCR operation. value: 1 -enum/INCR_MODE: +enum/IncrMode: bit_size: 2 variants: - - name: incr_mode_32 + - name: IncrMode32 description: 2**32 increment mode. value: 0 - - name: incr_mode_64 + - name: IncrMode64 description: 2**64 increment mode. value: 1 - - name: incr_mode_96 + - name: IncrMode96 description: 2**96 increment mode. value: 2 - - name: incr_mode_128 + - name: IncrMode128 description: 2**128 increment mode. value: 3 -enum/INSEL: +enum/Insel: bit_size: 4 variants: - - name: datin0 + - name: Datin0 description: DATIN[0]. value: 0 - - name: datin1 + - name: Datin1 description: DATIN[1]*. value: 1 - - name: datin2 + - name: Datin2 description: DATIN[2]*. value: 2 - - name: datin3 + - name: Datin3 description: DATIN[3]*. value: 3 - - name: datin0_datout + - name: Datin0Datout description: DATIN[0] ^ DATOUT. value: 4 - - name: datin1_datout + - name: Datin1Datout description: DATIN[1] ^ DATOUT*. value: 5 - - name: datin2_datout + - name: Datin2Datout description: DATIN[2] ^ DATOUT*. value: 6 - - name: datin3_datout + - name: Datin3Datout description: DATIN[3] ^ DATOUT*. value: 7 - - name: datout + - name: Datout description: DATOUT. value: 8 - - name: others_9 + - name: Others9 description: others - DATIN[0] * - only if DATIN[num] exists, else [0]. value: 9 -enum/KEY_FLUSH: +enum/KeyFlush: bit_size: 1 variants: - - name: no_effect + - name: NoEffect description: Clr has no effect. value: 0 - - name: flush + - name: Flush description: Set to start flush. value: 1 -enum/MILESTONE: +enum/Milestone: bit_size: 2 variants: - - name: PREL + - name: Prel description: PREL. value: 0 - - name: BR + - name: Br description: BR. value: 1 - - name: SI + - name: Si description: SI. value: 2 - - name: GO + - name: Go description: GO. value: 3 -enum/NO_AUTO_INIT: +enum/NoAutoInit: bit_size: 1 variants: - - name: sha_init + - name: ShaInit description: SHA automatic HASH initialisation. value: 0 - - name: no_sha_init + - name: NoShaInit description: No SHA automatic HASH initialisation. value: 1 -enum/OUTSEL: +enum/Outsel: bit_size: 3 variants: - - name: datout_ker_res + - name: DatoutKerRes description: DATOUT = 'Kernel Res'. value: 0 - - name: datout_datin0 + - name: DatoutDatin0 description: DATOUT = 'Kernel Res' ^ DATIN[0]. value: 1 - - name: datout_datin1 + - name: DatoutDatin1 description: DATOUT = 'Kernel Res' ^ DATIN[1]*. value: 2 - - name: datout_datin2 + - name: DatoutDatin2 description: DATOUT = 'Kernel Res' ^ DATIN[2]*. value: 3 - - name: datout_datin3 + - name: DatoutDatin3 description: DATOUT = 'Kernel Res' ^DATIN[3]*. value: 4 - - name: others_5 + - name: Others5 description: others - DATOUT = 'Kernel Res' * - only if DATIN[num] exists, else [0]. value: 5 - - name: others_6 + - name: Others6 description: others - DATOUT = 'Kernel Res' * - only if DATIN[num] exists, else [0]. value: 6 - - name: others_7 + - name: Others7 description: others - DATOUT = 'Kernel Res' * - only if DATIN[num] exists, else [0]. value: 7 -enum/RKEY: +enum/Rkey: bit_size: 1 variants: - - name: datout + - name: Datout description: DATOUT register bank. value: 0 - - name: key + - name: Key description: KEY register bank. value: 1 -enum/SHA2_COUNT_EN: +enum/Sha2CountEn: bit_size: 1 variants: - - name: count + - name: Count description: SHA operation DOES NOT increment COUNT. value: 0 - - name: no_count + - name: NoCount description: SHA operation DOES increment count. value: 1 -enum/SHA2_MODE: +enum/Sha2Mode: bit_size: 1 variants: - - name: normal + - name: Normal description: SHA NORM Mode. value: 0 - - name: auto + - name: Auto description: SHA AUTO Mode. value: 1 -enum/SHA2_SIZE: +enum/Sha2Size: bit_size: 2 variants: - - name: sha_224 + - name: Sha224 description: SHA-224. value: 0 - - name: sha_256 + - name: Sha256 description: SHA-256. value: 1 - - name: sha_384 + - name: Sha384 description: SHA-384(or SHA-224 if SHA-256 only). value: 2 - - name: sha_512 + - name: Sha512 description: SHA-512 (or SHA-256 if SHA-256 only). value: 3 -enum/SHA2_STOP: +enum/Sha2Stop: bit_size: 1 variants: - - name: running + - name: Running description: Keep running. value: 0 - - name: stop + - name: Stop description: Stop auto mode. value: 1 -enum/SMASKSTEP: +enum/Smaskstep: bit_size: 1 variants: - - name: regbank + - name: Regbank description: SFRSEED increments every regbank access. value: 0 - - name: regbank_and_plus + - name: RegbankAndPlus description: SFRSEED increments every regbank access PLUS when SFRSEED in read. value: 1 -enum/SMASKSW: +enum/Smasksw: bit_size: 1 variants: - - name: hw + - name: Hw description: SFR MASK output directly controlled by HW mask generator. value: 0 - - name: sw + - name: Sw description: SFR MASK output directly controlled by SW. value: 1 -enum/START: +enum/Start: bit_size: 1 variants: - - name: no_effect + - name: NoEffect description: Clr has no effect. value: 0 - - name: start_op + - name: StartOp description: Set to start operation. value: 1 -enum/TDESKEY: +enum/Tdeskey: bit_size: 1 variants: - - name: two_key + - name: TwoKey description: 2-key TDES. value: 0 - - name: three_key + - name: ThreeKey description: 3-key TDES. value: 1 diff --git a/data/metadata/peripherals/mcxa/SPC.yaml b/data/metadata/peripherals/mcxa/SPC.yaml index 45b5540..187fce5 100644 --- a/data/metadata/peripherals/mcxa/SPC.yaml +++ b/data/metadata/peripherals/mcxa/SPC.yaml @@ -73,7 +73,7 @@ block/Spc: - name: coreldo_cfg description: LDO_CORE Configuration. byte_offset: 768 - fieldset: CoreldoCfg + access: Read fieldset/ActiveCfg: description: Active Power Mode Configuration. fields: @@ -123,13 +123,6 @@ fieldset/ActiveVdelay: description: Active Voltage Delay. bit_offset: 0 bit_size: 16 -fieldset/CoreldoCfg: - description: LDO_CORE Configuration. - fields: - - name: coreldo_spare0 - description: CORELDO SPARE0. - bit_offset: 16 - bit_size: 1 fieldset/EvdCfg: description: External Voltage Domain Configuration. fields: @@ -364,213 +357,216 @@ fieldset/Verid: enum/ActiveCfgBgmode: bit_size: 2 variants: - - name: BGMODE0 + - name: Bgmode0 description: Bandgap disabled. value: 0 - - name: BGMODE01 + - name: Bgmode01 description: Bandgap enabled, buffer disabled. value: 1 - - name: BGMODE10 + - name: Bgmode10 description: Bandgap enabled, buffer enabled. value: 2 enum/ActiveCfgCoreldoVddDs: bit_size: 1 variants: - - name: LOW + - name: Low description: Low. value: 0 - - name: NORMAL + - name: Normal description: Normal. value: 1 enum/ActiveCfgCoreldoVddLvl: bit_size: 2 variants: - - name: MID + - name: Mid description: Regulate to mid voltage (1.0 V). value: 1 - - name: NORMAL + - name: Normal description: Regulate to normal voltage (1.1 V). value: 2 - - name: OVER + - name: Over description: Regulate to overdrive voltage (1.15 V). value: 3 enum/CorevddLvdf: bit_size: 1 variants: - - name: EVENT_NO + - name: EventNo description: Event not detected. value: 0 - - name: EVENT_YES + - name: EventYes description: Event detected. value: 1 enum/Feature: bit_size: 16 variants: - - name: STANDARD + - name: Standard description: Standard features. value: 0 enum/LpCfgBgmode: bit_size: 2 variants: - - name: BGMODE0 + - name: Bgmode0 description: Bandgap disabled. value: 0 - - name: BGMODE01 + - name: Bgmode01 description: Bandgap enabled, buffer disabled. value: 1 - - name: BGMODE10 + - name: Bgmode10 description: Bandgap enabled, buffer enabled. value: 2 enum/LpCfgCoreldoVddDs: bit_size: 1 variants: - - name: LOW + - name: Low description: Low. value: 0 - - name: NORMAL + - name: Normal description: Normal. value: 1 enum/LpCfgCoreldoVddLvl: bit_size: 2 variants: - - name: MID + - name: Mid description: Mid voltage (1.0 V). value: 1 - - name: NORMAL + - name: Normal description: Normal voltage (1.1 V). value: 2 - - name: OVER + - name: Over description: Overdrive voltage (1.15 V). value: 3 enum/LpMode: bit_size: 4 variants: - - name: MODE0 + - name: Mode0 description: SLEEP with system clock running. value: 0 - - name: MODE1 + - name: Mode1 description: DSLEEP with system clock off. value: 1 - - name: MODE2 + - name: Mode2 description: PDOWN with system clock off. value: 2 - - name: MODE8 + - name: Mode8 description: DPDOWN with system clock off. value: 8 enum/Lpreqov: bit_size: 2 variants: - - name: FORCE_NO + - name: ForceNo description: Not forced. value: 0 - - name: FORCE_LOW + - name: ForceLow description: Forced low (ignore LPREQPOL settings). value: 2 - - name: FORCE_HIGH + - name: ForceHigh description: Forced high (ignore LPREQPOL settings). value: 3 enum/Lpreqpol: bit_size: 1 variants: - - name: HIGH + - name: High description: High. value: 0 - - name: LOW + - name: Low description: Low. value: 1 enum/PdLpReq: bit_size: 1 variants: - - name: REQ_NO + - name: ReqNo description: Did not request. value: 0 - - name: REQ_YES + - name: ReqYes description: Requested. value: 1 enum/PwrReqStatus: bit_size: 1 variants: - - name: REQ_NO + - name: ReqNo description: Did not request. value: 0 - - name: REQ_YES + - name: ReqYes description: Requested. value: 1 enum/SpcLpMode: bit_size: 4 variants: - - name: MODE0 + - name: Mode0 description: Sleep mode with system clock running. value: 0 - - name: MODE1 + - name: Mode1 description: DSLEEP with system clock off. value: 1 - - name: MODE2 + - name: Mode2 description: PDOWN with system clock off. value: 2 - - name: MODE8 + - name: Mode8 description: DPDOWN with system clock off. value: 8 enum/SpcLpReq: bit_size: 1 variants: - - name: ACTIVE + - name: Active description: SPC is in Active mode; the ACTIVE_CFG register has control. value: 0 - - name: LOW_POWER + - name: LowPower description: All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register. value: 1 enum/SysvddHvdf: bit_size: 1 variants: - - name: EVENT_NO + - name: EventNo description: Event not detected. value: 0 - - name: EVENT_YES + - name: EventYes description: Event detected. value: 1 enum/SysvddLvdf: bit_size: 1 variants: - - name: EVENT_NO + - name: EventNo description: Event not detected. value: 0 - - name: EVENT_YES + - name: EventYes description: Event detected. value: 1 enum/VdCoreCfgLock: bit_size: 1 variants: - - name: ALLOW + - name: Allow description: Allow. value: 0 - - name: DENY + - name: Deny description: Deny. value: 1 enum/VdSysCfgLock: bit_size: 1 variants: - - name: ALLOW + - name: Allow description: Allow. value: 0 - - name: DENY + - name: Deny description: Deny. value: 1 enum/VddVdDisable: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enable. value: 0 - - name: DISABLE + - name: Disable description: Disable. value: 1 enum/Vsm: bit_size: 2 variants: - - name: SRAM1V0 + - name: Sram1v0 description: SRAM configured for 1.0V value: 1 - - name: SRAM1V2 + - name: Sram1v1 + description: SRAM configured for 1.1V + value: 2 + - name: Sram1v2 description: SRAM configured for 1.2V value: 3 diff --git a/data/metadata/peripherals/mcxa/SYSCON2xx.yaml b/data/metadata/peripherals/mcxa/SYSCON2xx.yaml index 041ecd7..a0728a1 100644 --- a/data/metadata/peripherals/mcxa/SYSCON2xx.yaml +++ b/data/metadata/peripherals/mcxa/SYSCON2xx.yaml @@ -1,1607 +1,1678 @@ -block/SYSCON: +block/Syscon: description: SYSCON. items: - - name: REMAP + - name: remap description: AHB Matrix Remap Control. byte_offset: 512 - fieldset: REMAP - - name: AHBMATPRIO + fieldset: Remap + - name: ahbmatprio description: AHB Matrix Priority Control. byte_offset: 528 - fieldset: AHBMATPRIO - - name: CPU0NSTCKCAL + fieldset: Ahbmatprio + - name: cpu0nstckcal description: Non-Secure CPU0 System Tick Calibration. byte_offset: 572 - fieldset: CPU0NSTCKCAL - - name: NMISRC + fieldset: Cpu0nstckcal + - name: nmisrc description: NMI Source Select. byte_offset: 584 - fieldset: NMISRC - - name: PROTLVL + fieldset: Nmisrc + - name: protlvl description: Protect Level Control. byte_offset: 588 - fieldset: PROTLVL - - name: SLOWCLKDIV + fieldset: Protlvl + - name: slowclkdiv description: SLOW_CLK Clock Divider. byte_offset: 888 - fieldset: SLOWCLKDIV - - name: BUSCLKDIV + fieldset: Slowclkdiv + - name: busclkdiv description: BUS_CLK Clock Divider. byte_offset: 892 - fieldset: BUSCLKDIV - - name: AHBCLKDIV + fieldset: Busclkdiv + - name: ahbclkdiv description: System Clock Divider. byte_offset: 896 - fieldset: AHBCLKDIV - - name: FROHFDIV + fieldset: Ahbclkdiv + - name: frohfdiv description: FRO_HF_DIV Clock Divider. byte_offset: 904 - fieldset: FROHFDIV - - name: FROLFDIV + fieldset: Frohfdiv + - name: frolfdiv description: FRO_LF_DIV Clock Divider. byte_offset: 908 - fieldset: FROLFDIV - - name: PLL1CLKDIV + fieldset: Frolfdiv + - name: pll1clkdiv description: PLL1_CLK_DIV Clock Divider. byte_offset: 996 - fieldset: PLL1CLKDIV - - name: CLKUNLOCK + fieldset: Pll1clkdiv + - name: clkunlock description: Clock Configuration Unlock. byte_offset: 1020 - fieldset: CLKUNLOCK - - name: NVM_CTRL + fieldset: Clkunlock + - name: nvm_ctrl description: NVM Control. byte_offset: 1024 - fieldset: NVM_CTRL - - name: SmartDMAINT + fieldset: NvmCtrl + - name: smart_dmaint description: SmartDMA Interrupt Hijack. byte_offset: 1044 - fieldset: SmartDMAINT - - name: RAM_INTERLEAVE + fieldset: SmartDmaint + - name: ram_interleave description: Controls RAM Interleave Integration. byte_offset: 1136 - fieldset: RAM_INTERLEAVE - - name: CPUSTAT + fieldset: RamInterleave + - name: cpustat description: CPU Status. byte_offset: 2060 access: Read - fieldset: CPUSTAT - - name: LPCAC_CTRL + fieldset: Cpustat + - name: lpcac_ctrl description: LPCAC Control. byte_offset: 2084 - fieldset: LPCAC_CTRL - - name: PWM0SUBCTL + fieldset: LpcacCtrl + - name: pwm0subctl description: PWM0 Submodule Control. byte_offset: 2360 - fieldset: PWM0SUBCTL - - name: PWM1SUBCTL + fieldset: Pwm0subctl + - name: pwm1subctl description: PWM1 Submodule Control. byte_offset: 2364 - fieldset: PWM1SUBCTL - - name: CTIMERGLOBALSTARTEN + fieldset: Pwm1subctl + - name: ctimerglobalstarten description: CTIMER Global Start Enable. byte_offset: 2368 - fieldset: CTIMERGLOBALSTARTEN - - name: RAM_CTRL + fieldset: Ctimerglobalstarten + - name: ram_ctrl description: RAM Control. byte_offset: 2372 - fieldset: RAM_CTRL - - name: GRAY_CODE_LSB + fieldset: RamCtrl + - name: gray_code_lsb description: Gray to Binary Converter Gray Code [31:0]. byte_offset: 2912 - fieldset: GRAY_CODE_LSB - - name: GRAY_CODE_MSB + fieldset: GrayCodeLsb + - name: gray_code_msb description: Gray to Binary Converter Gray Code [41:32]. byte_offset: 2916 - fieldset: GRAY_CODE_MSB - - name: BINARY_CODE_LSB + fieldset: GrayCodeMsb + - name: binary_code_lsb description: Gray to Binary Converter Binary Code [31:0]. byte_offset: 2920 access: Read - fieldset: BINARY_CODE_LSB - - name: BINARY_CODE_MSB + fieldset: BinaryCodeLsb + - name: binary_code_msb description: Gray to Binary Converter Binary Code [41:32]. byte_offset: 2924 access: Read - fieldset: BINARY_CODE_MSB - - name: MSFCFG + fieldset: BinaryCodeMsb + - name: els_udf + description: UDF Control. + byte_offset: 3600 + fieldset: ElsUdf + - name: msfcfg description: MSF Configuration. byte_offset: 3612 - fieldset: MSFCFG - - name: ROP_STATE + fieldset: Msfcfg + - name: els_uid + description: Device UID n. + array: + len: 4 + stride: 4 + byte_offset: 3616 + fieldset: ElsUid + - name: rop_state description: ROP State Register. byte_offset: 3644 access: Read - fieldset: ROP_STATE - - name: SRAM_XEN + fieldset: RopState + - name: sram_xen description: RAM XEN Control. byte_offset: 3672 - fieldset: SRAM_XEN - - name: SRAM_XEN_DP + fieldset: SramXen + - name: sram_xen_dp description: RAM XEN Control (Duplicate). byte_offset: 3676 - fieldset: SRAM_XEN_DP - - name: ELS_OTP_LC_STATE + fieldset: SramXenDp + - name: els_otp_lc_state description: Life Cycle State Register. byte_offset: 3712 access: Read - fieldset: ELS_OTP_LC_STATE - - name: ELS_OTP_LC_STATE_DP + fieldset: ElsOtpLcState + - name: els_otp_lc_state_dp description: Life Cycle State Register (Duplicate). byte_offset: 3716 access: Read - fieldset: ELS_OTP_LC_STATE_DP - - name: DEBUG_LOCK_EN + fieldset: ElsOtpLcStateDp + - name: debug_lock_en description: Control Write Access to Security. byte_offset: 4000 - fieldset: DEBUG_LOCK_EN - - name: DEBUG_FEATURES + fieldset: DebugLockEn + - name: debug_features description: Cortex Debug Features Control. byte_offset: 4004 - fieldset: DEBUG_FEATURES - - name: DEBUG_FEATURES_DP + fieldset: DebugFeatures + - name: debug_features_dp description: Cortex Debug Features Control (Duplicate). byte_offset: 4008 - fieldset: DEBUG_FEATURES_DP - - name: SWD_ACCESS_CPU0 + fieldset: DebugFeaturesDp + - name: swd_access_cpu0 description: CPU0 Software Debug Access. byte_offset: 4020 - fieldset: SWD_ACCESS_CPU0 - - name: DEBUG_AUTH_BEACON + fieldset: SwdAccessCpu0 + - name: debug_auth_beacon description: Debug Authentication BEACON. byte_offset: 4032 - fieldset: DEBUG_AUTH_BEACON - - name: JTAG_ID + fieldset: DebugAuthBeacon + - name: jtag_id description: JTAG Chip ID. byte_offset: 4080 access: Read - fieldset: JTAG_ID - - name: DEVICE_TYPE + fieldset: JtagId + - name: device_type description: Device Type. byte_offset: 4084 access: Read - fieldset: DEVICE_TYPE - - name: DEVICE_ID0 + fieldset: DeviceType + - name: device_id0 description: Device ID. byte_offset: 4088 access: Read - fieldset: DEVICE_ID0 - - name: DIEID + fieldset: DeviceId0 + - name: dieid description: Chip Revision ID and Number. byte_offset: 4092 access: Read - fieldset: DIEID -fieldset/AHBCLKDIV: + fieldset: Dieid +fieldset/Ahbclkdiv: description: System Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: UNSTAB + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: AHBCLKDIV_UNSTAB -fieldset/AHBMATPRIO: + enum: AhbclkdivUnstab +fieldset/Ahbmatprio: description: AHB Matrix Priority Control. fields: - - name: CPU0_CBUS + - name: cpu0_cbus description: CPU0 C-AHB bus master priority level. bit_offset: 0 bit_size: 2 - enum: CPU0_CBUS - - name: CPU0_SBUS + enum: Cpu0Cbus + - name: cpu0_sbus description: CPU0 S-AHB bus master priority level. bit_offset: 2 bit_size: 2 - enum: AHBMATPRIO_CPU0_SBUS - - name: CPU1_CBUS_SmartDMA_I + enum: AhbmatprioCpu0Sbus + - name: cpu1_cbus_smart_dma_i description: SmartDMA-I bus master priority level. bit_offset: 4 bit_size: 2 - enum: CPU1_CBUS_SmartDMA_I - - name: CPU1_SBUS_SmartDMA_D + enum: Cpu1CbusSmartDmaI + - name: cpu1_sbus_smart_dma_d description: SmartDMA-D bus master priority level. bit_offset: 6 bit_size: 2 - enum: CPU1_SBUS_SmartDMA_D - - name: DMA0 + enum: Cpu1SbusSmartDmaD + - name: dma0 description: DMA0 controller bus master priority level. bit_offset: 8 bit_size: 2 - enum: AHBMATPRIO_DMA0 - - name: PKC_ELS + enum: AhbmatprioDma0 + - name: pkc_els description: PKC and ELS bus master priority level. bit_offset: 12 bit_size: 2 - enum: PKC_ELS - - name: USB_FS_ENET + enum: PkcEls + - name: usb_fs_enet description: USB-FS bus master priority level. bit_offset: 24 bit_size: 2 - enum: USB_FS_ENET -fieldset/BINARY_CODE_LSB: + enum: UsbFsEnet +fieldset/BinaryCodeLsb: description: Gray to Binary Converter Binary Code [31:0]. fields: - name: code_bin_31_0 description: Binary code [31:0]. bit_offset: 0 bit_size: 32 -fieldset/BINARY_CODE_MSB: +fieldset/BinaryCodeMsb: description: Gray to Binary Converter Binary Code [41:32]. fields: - name: code_bin_41_32 description: Binary code [41:32]. bit_offset: 0 bit_size: 10 -fieldset/BUSCLKDIV: +fieldset/Busclkdiv: description: BUS_CLK Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: BUSCLKDIV_RESET - - name: HALT + enum: BusclkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: BUSCLKDIV_HALT - - name: UNSTAB + enum: BusclkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: BUSCLKDIV_UNSTAB -fieldset/CLKUNLOCK: + enum: BusclkdivUnstab +fieldset/Clkunlock: description: Clock Configuration Unlock. fields: - - name: UNLOCK + - name: unlock description: Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx). bit_offset: 0 bit_size: 1 - enum: UNLOCK -fieldset/CPU0NSTCKCAL: + enum: Unlock +fieldset/Cpu0nstckcal: description: Non-Secure CPU0 System Tick Calibration. fields: - - name: TENMS + - name: tenms description: Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. bit_offset: 0 bit_size: 24 - - name: SKEW + - name: skew description: Indicates whether the TENMS value is exact. bit_offset: 24 bit_size: 1 - enum: SKEW - - name: NOREF + enum: Skew + - name: noref description: Indicates whether the device provides a reference clock to the processor. bit_offset: 25 bit_size: 1 - enum: NOREF -fieldset/CPUSTAT: + enum: Noref +fieldset/Cpustat: description: CPU Status. fields: - - name: CPU0SLEEPING + - name: cpu0sleeping description: CPU0 sleeping state. bit_offset: 0 bit_size: 1 - enum: CPU0SLEEPING - - name: CPU0LOCKUP + enum: Cpu0sleeping + - name: cpu0lockup description: CPU0 lockup state. bit_offset: 2 bit_size: 1 - enum: CPU0LOCKUP -fieldset/CTIMERGLOBALSTARTEN: + enum: Cpu0lockup +fieldset/Ctimerglobalstarten: description: CTIMER Global Start Enable. fields: - - name: CTIMER0_CLK_EN + - name: ctimer0_clk_en description: Enables the CTIMER0 function clock. bit_offset: 0 bit_size: 1 - - name: CTIMER1_CLK_EN + - name: ctimer1_clk_en description: Enables the CTIMER1 function clock. bit_offset: 1 bit_size: 1 - - name: CTIMER2_CLK_EN + - name: ctimer2_clk_en description: Enables the CTIMER2 function clock. bit_offset: 2 bit_size: 1 - - name: CTIMER3_CLK_EN + - name: ctimer3_clk_en description: Enables the CTIMER3 function clock. bit_offset: 3 bit_size: 1 - - name: CTIMER4_CLK_EN + - name: ctimer4_clk_en description: Enables the CTIMER4 function clock. bit_offset: 4 bit_size: 1 -fieldset/DEBUG_AUTH_BEACON: +fieldset/DebugAuthBeacon: description: Debug Authentication BEACON. fields: - - name: BEACON + - name: beacon description: Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code. bit_offset: 0 bit_size: 32 -fieldset/DEBUG_FEATURES: +fieldset/DebugFeatures: description: Cortex Debug Features Control. fields: - - name: CPU0_DBGEN + - name: cpu0_dbgen description: CPU0 invasive debug control. bit_offset: 0 bit_size: 2 - enum: DEBUG_FEATURES_CPU0_DBGEN - - name: CPU0_NIDEN + enum: DebugFeaturesCpu0Dbgen + - name: cpu0_niden description: CPU0 non-invasive debug control. bit_offset: 2 bit_size: 2 - enum: DEBUG_FEATURES_CPU0_NIDEN -fieldset/DEBUG_FEATURES_DP: + enum: DebugFeaturesCpu0Niden +fieldset/DebugFeaturesDp: description: Cortex Debug Features Control (Duplicate). fields: - - name: CPU0_DBGEN + - name: cpu0_dbgen description: CPU0 invasive debug control. bit_offset: 0 bit_size: 2 - enum: DEBUG_FEATURES_DP_CPU0_DBGEN - - name: CPU0_NIDEN + enum: DebugFeaturesDpCpu0Dbgen + - name: cpu0_niden description: CPU0 non-invasive debug control. bit_offset: 2 bit_size: 2 - enum: DEBUG_FEATURES_DP_CPU0_NIDEN -fieldset/DEBUG_LOCK_EN: + enum: DebugFeaturesDpCpu0Niden +fieldset/DebugLockEn: description: Control Write Access to Security. fields: - - name: LOCK_ALL + - name: lock_all description: Controls write access to the security registers. bit_offset: 0 bit_size: 4 - enum: LOCK_ALL -fieldset/DEVICE_ID0: + enum: LockAll +fieldset/DeviceId0: description: Device ID. fields: - - name: RAM_SIZE + - name: ram_size description: Indicates the device's ram size. bit_offset: 0 bit_size: 4 - enum: RAM_SIZE - - name: FLASH_SIZE + enum: RamSize + - name: flash_size description: Indicates the device's flash size. bit_offset: 4 bit_size: 4 - enum: FLASH_SIZE - - name: ROM_REV_MINOR + enum: FlashSize + - name: rom_rev_minor description: Indicates the device's ROM revision. bit_offset: 20 bit_size: 4 - - name: SECURITY + - name: security description: no description available. bit_offset: 24 bit_size: 4 - enum: SECURITY -fieldset/DEVICE_TYPE: + enum: Security +fieldset/DeviceType: description: Device Type. fields: - - name: DEVICE_TYPE_NUM + - name: device_type_num description: Indicates the device part number. bit_offset: 0 bit_size: 16 - - name: DEVICE_TYPE_SEC + - name: device_type_sec description: Indicates the device type. bit_offset: 16 bit_size: 1 - enum: DEVICE_TYPE_SEC - - name: DEVICE_TYPE_PKG + enum: DeviceTypeSec + - name: device_type_pkg description: Indicates the device's package type. bit_offset: 20 bit_size: 4 - enum: DEVICE_TYPE_PKG - - name: DEVICE_TYPE_PIN + enum: DeviceTypePkg + - name: device_type_pin description: Indicates the device's pin number. bit_offset: 24 bit_size: 8 -fieldset/DIEID: +fieldset/Dieid: description: Chip Revision ID and Number. fields: - - name: MINOR_REVISION + - name: minor_revision description: Chip minor revision. bit_offset: 0 bit_size: 4 - - name: MAJOR_REVISION + - name: major_revision description: Chip major revision. bit_offset: 4 bit_size: 4 - - name: MCO_NUM_IN_DIE_ID + - name: mco_num_in_die_id description: Chip number. bit_offset: 8 bit_size: 20 -fieldset/ELS_OTP_LC_STATE: +fieldset/ElsOtpLcState: description: Life Cycle State Register. fields: - - name: OTP_LC_STATE + - name: otp_lc_state description: OTP life cycle state. bit_offset: 0 bit_size: 8 -fieldset/ELS_OTP_LC_STATE_DP: +fieldset/ElsOtpLcStateDp: description: Life Cycle State Register (Duplicate). fields: - - name: OTP_LC_STATE_DP + - name: otp_lc_state_dp description: OTP life cycle state. bit_offset: 0 bit_size: 8 -fieldset/FROHFDIV: +fieldset/ElsUdf: + description: UDF Control. + fields: + - name: key_sel + description: UDF KEY Select. + bit_offset: 0 + bit_size: 2 + enum: KeySel + - name: uid_hidden + description: UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset. + bit_offset: 24 + bit_size: 4 + enum: UidHidden + - name: udf_hidden + description: UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset. + bit_offset: 28 + bit_size: 4 + enum: UdfHidden +fieldset/ElsUid: + description: Device UID n. + fields: + - name: uid0 + description: UID. + bit_offset: 0 + bit_size: 32 +fieldset/Frohfdiv: description: FRO_HF_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: FROHFDIV_RESET - - name: HALT + enum: FrohfdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: FROHFDIV_HALT - - name: UNSTAB + enum: FrohfdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: FROHFDIV_UNSTAB -fieldset/FROLFDIV: + enum: FrohfdivUnstab +fieldset/Frolfdiv: description: FRO_LF_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: FROLFDIV_RESET - - name: HALT + enum: FrolfdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: FROLFDIV_HALT - - name: UNSTAB + enum: FrolfdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: FROLFDIV_UNSTAB -fieldset/GRAY_CODE_LSB: + enum: FrolfdivUnstab +fieldset/GrayCodeLsb: description: Gray to Binary Converter Gray Code [31:0]. fields: - name: code_gray_31_0 description: Gray code [31:0]. bit_offset: 0 bit_size: 32 -fieldset/GRAY_CODE_MSB: +fieldset/GrayCodeMsb: description: Gray to Binary Converter Gray Code [41:32]. fields: - name: code_gray_41_32 description: Gray code [41:32]. bit_offset: 0 bit_size: 10 -fieldset/JTAG_ID: +fieldset/JtagId: description: JTAG Chip ID. fields: - - name: JTAG_ID + - name: jtag_id description: Indicates the device ID. bit_offset: 0 bit_size: 32 -fieldset/LPCAC_CTRL: +fieldset/LpcacCtrl: description: LPCAC Control. fields: - - name: DIS_LPCAC + - name: dis_lpcac description: Disables/enables the cache function. bit_offset: 0 bit_size: 1 - enum: DIS_LPCAC - - name: CLR_LPCAC + enum: DisLpcac + - name: clr_lpcac description: Clears the cache function. bit_offset: 1 bit_size: 1 - enum: CLR_LPCAC - - name: FRC_NO_ALLOC + enum: ClrLpcac + - name: frc_no_alloc description: Forces no allocation. bit_offset: 2 bit_size: 1 - enum: FRC_NO_ALLOC - - name: DIS_LPCAC_WTBF + enum: FrcNoAlloc + - name: dis_lpcac_wtbf description: Disable LPCAC Write Through Buffer. bit_offset: 4 bit_size: 1 - - name: LIM_LPCAC_WTBF + - name: lim_lpcac_wtbf description: Limit LPCAC Write Through Buffer. bit_offset: 5 bit_size: 1 - - name: LPCAC_XOM + - name: lpcac_xom description: LPCAC XOM(eXecute-Only-Memory) attribute control. bit_offset: 7 bit_size: 1 - - name: LPCAC_MEM_REQ + - name: lpcac_mem_req description: Request LPCAC memories. bit_offset: 8 bit_size: 1 -fieldset/MSFCFG: +fieldset/Msfcfg: description: MSF Configuration. fields: - - name: IFR_ERASE_DIS0 + - name: ifr_erase_dis0 description: user IFR sector 0 erase control. bit_offset: 0 bit_size: 1 - enum: IFR_ERASE_DIS0 - - name: IFR_ERASE_DIS1 + enum: IfrEraseDis0 + - name: ifr_erase_dis1 description: user IFR sector 1 erase control. bit_offset: 1 bit_size: 1 - enum: IFR_ERASE_DIS1 - - name: IFR_ERASE_DIS2 + enum: IfrEraseDis1 + - name: ifr_erase_dis2 description: user IFR sector 2 erase control. bit_offset: 2 bit_size: 1 - enum: IFR_ERASE_DIS2 - - name: IFR_ERASE_DIS3 + enum: IfrEraseDis2 + - name: ifr_erase_dis3 description: user IFR sector 3 erase control. bit_offset: 3 bit_size: 1 - enum: IFR_ERASE_DIS3 - - name: MASS_ERASE_DIS + enum: IfrEraseDis3 + - name: mass_erase_dis description: Mass erase control. bit_offset: 8 bit_size: 1 - enum: MASS_ERASE_DIS -fieldset/NMISRC: + enum: MassEraseDis +fieldset/Nmisrc: description: NMI Source Select. fields: - - name: IRQCPU0 + - name: irqcpu0 description: The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. bit_offset: 0 bit_size: 8 - - name: NMIENCPU0 + - name: nmiencpu0 description: Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. bit_offset: 31 bit_size: 1 -fieldset/NVM_CTRL: +fieldset/NvmCtrl: description: NVM Control. fields: - - name: DIS_FLASH_SPEC + - name: dis_flash_spec description: Flash speculation control. bit_offset: 0 bit_size: 1 - enum: DIS_FLASH_SPEC - - name: DIS_DATA_SPEC + enum: DisFlashSpec + - name: dis_data_spec description: Flash data speculation control. bit_offset: 1 bit_size: 1 - enum: DIS_DATA_SPEC - - name: FLASH_STALL_EN + enum: DisDataSpec + - name: flash_stall_en description: FLASH stall on busy control. bit_offset: 10 bit_size: 1 - enum: FLASH_STALL_EN - - name: DIS_MBECC_ERR_INST + enum: FlashStallEn + - name: dis_mbecc_err_inst description: Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative. bit_offset: 16 bit_size: 1 - enum: DIS_MBECC_ERR_INST - - name: DIS_MBECC_ERR_DATA + enum: DisMbeccErrInst + - name: dis_mbecc_err_data description: Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative. bit_offset: 17 bit_size: 1 - enum: DIS_MBECC_ERR_DATA -fieldset/PLL1CLKDIV: + enum: DisMbeccErrData +fieldset/Pll1clkdiv: description: PLL1_CLK_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: PLL1CLKDIV_RESET - - name: HALT + enum: Pll1clkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: PLL1CLKDIV_HALT - - name: UNSTAB + enum: Pll1clkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: PLL1CLKDIV_UNSTAB -fieldset/PROTLVL: + enum: Pll1clkdivUnstab +fieldset/Protlvl: description: Protect Level Control. fields: - - name: PRIV + - name: priv_ description: Control privileged access of EIM, ERM, Flexcan, MBC, SCG. bit_offset: 0 bit_size: 1 - - name: LOCKNSMPU + - name: locknsmpu description: Control write access to Nonsecure MPU memory regions. bit_offset: 16 bit_size: 1 - enum: LOCKNSMPU - - name: LOCK - description: This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset. + enum: Locknsmpu + - name: lock + description: This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset. bit_offset: 31 bit_size: 1 - enum: PROTLVL_LOCK -fieldset/PWM0SUBCTL: + enum: ProtlvlLock +fieldset/Pwm0subctl: description: PWM0 Submodule Control. fields: - - name: CLK0_EN + - name: clk0_en description: Enables PWM0 SUB Clock0. bit_offset: 0 bit_size: 1 - - name: CLK1_EN + - name: clk1_en description: Enables PWM0 SUB Clock1. bit_offset: 1 bit_size: 1 - - name: CLK2_EN + - name: clk2_en description: Enables PWM0 SUB Clock2. bit_offset: 2 bit_size: 1 - - name: CLK3_EN + - name: clk3_en description: Enables PWM0 SUB Clock3. bit_offset: 3 bit_size: 1 -fieldset/PWM1SUBCTL: +fieldset/Pwm1subctl: description: PWM1 Submodule Control. fields: - - name: CLK0_EN + - name: clk0_en description: Enables PWM1 SUB Clock0. bit_offset: 0 bit_size: 1 - - name: CLK1_EN + - name: clk1_en description: Enables PWM1 SUB Clock1. bit_offset: 1 bit_size: 1 - - name: CLK2_EN + - name: clk2_en description: Enables PWM1 SUB Clock2. bit_offset: 2 bit_size: 1 - - name: CLK3_EN + - name: clk3_en description: Enables PWM1 SUB Clock3. bit_offset: 3 bit_size: 1 -fieldset/RAM_CTRL: +fieldset/RamCtrl: description: RAM Control. fields: - - name: RAMA_ECC_ENABLE + - name: rama_ecc_enable description: RAMA ECC enable. bit_offset: 0 bit_size: 1 - - name: RAMA_CG_OVERRIDE + - name: rama_cg_override description: RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. bit_offset: 16 bit_size: 1 - - name: RAMX_CG_OVERRIDE + - name: ramx_cg_override description: RAMX bank clock gating control. bit_offset: 17 bit_size: 1 - - name: RAMB_CG_OVERRIDE + - name: ramb_cg_override description: RAMB bank clock gating control. bit_offset: 18 bit_size: 1 - - name: RAMC_CG_OVERRIDE + - name: ramc_cg_override description: RAMC bank clock gating control. bit_offset: 19 bit_size: 1 -fieldset/RAM_INTERLEAVE: +fieldset/RamInterleave: description: Controls RAM Interleave Integration. fields: - - name: INTERLEAVE + - name: interleave description: Controls RAM access for RAMA1 and RAMA2. bit_offset: 0 bit_size: 1 - enum: INTERLEAVE -fieldset/REMAP: + enum: Interleave +fieldset/Remap: description: AHB Matrix Remap Control. fields: - - name: CPU0_SBUS + - name: cpu0_sbus description: RAMX0 address remap for CPU System bus. bit_offset: 2 bit_size: 2 - enum: REMAP_CPU0_SBUS - - name: SmartDMA_I - description: RAMX0 address remap for SmartDMA I-BUS. + enum: RemapCpu0Sbus + - name: smart_dma_d + description: RAMX0 address remap for SmartDMA D-BUS. bit_offset: 4 bit_size: 2 - enum: SmartDMA_I - - name: SmartDMA_D - description: RAMX0 address remap for SmartDMA D-BUS. + enum: SmartDmaD + - name: smart_dma_i + description: RAMX0 address remap for SmartDMA I-BUS. bit_offset: 6 bit_size: 2 - enum: SmartDMA_D - - name: DMA0 + enum: SmartDmaI + - name: dma0 description: RAMX0 address remap for DMA0. bit_offset: 8 bit_size: 2 - enum: REMAP_DMA0 - - name: PKC + enum: RemapDma0 + - name: pkc description: RAMX0 address remap for PKC. bit_offset: 12 bit_size: 2 - enum: PKC - - name: USB0 + enum: Pkc + - name: usb0 description: RAMX0 address remap for USB0. bit_offset: 24 bit_size: 2 - enum: USB0 - - name: LOCK - description: This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset. + enum: Usb0 + - name: lock + description: This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset. bit_offset: 31 bit_size: 1 - enum: REMAP_LOCK -fieldset/ROP_STATE: + enum: RemapLock +fieldset/RopState: description: ROP State Register. fields: - - name: ROP_STATE + - name: rop_state description: ROP state. bit_offset: 0 bit_size: 32 -fieldset/SLOWCLKDIV: +fieldset/Slowclkdiv: description: SLOW_CLK Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: SLOWCLKDIV_RESET - - name: HALT + enum: SlowclkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: SLOWCLKDIV_HALT - - name: UNSTAB + enum: SlowclkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: SLOWCLKDIV_UNSTAB -fieldset/SRAM_XEN: - description: RAM XEN Control. - fields: - - name: RAMX0_XEN - description: RAMX0 Execute permission control. - bit_offset: 0 - bit_size: 1 - - name: RAMX1_XEN - description: RAMX1 Execute permission control. - bit_offset: 1 - bit_size: 1 - - name: RAMA0_XEN - description: RAMA0 Execute permission control. - bit_offset: 2 - bit_size: 1 - - name: RAMA1_XEN - description: RAMAx (excepts RAMA0) Execute permission control. - bit_offset: 3 - bit_size: 1 - - name: RAMB_XEN - description: RAMBx Execute permission control. - bit_offset: 4 - bit_size: 1 - - name: RAMC_XEN - description: RAMCx Execute permission control. - bit_offset: 5 - bit_size: 1 - - name: LOCK - description: This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset. - bit_offset: 31 - bit_size: 1 - enum: SRAM_XEN_LOCK -fieldset/SRAM_XEN_DP: - description: RAM XEN Control (Duplicate). - fields: - - name: RAMX0_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 0 - bit_size: 1 - - name: RAMX1_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 1 - bit_size: 1 - - name: RAMA0_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 2 - bit_size: 1 - - name: RAMA1_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 3 - bit_size: 1 - - name: RAMB_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 4 - bit_size: 1 - - name: RAMC_XEN - description: Refer to SRAM_XEN for more details. - bit_offset: 5 - bit_size: 1 -fieldset/SWD_ACCESS_CPU0: - description: CPU0 Software Debug Access. - fields: - - name: SEC_CODE - description: 'CPU0 SWD-AP: 0x12345678.' - bit_offset: 0 - bit_size: 32 - enum: SEC_CODE -fieldset/SmartDMAINT: + enum: SlowclkdivUnstab +fieldset/SmartDmaint: description: SmartDMA Interrupt Hijack. fields: - - name: INT0 - description: SmartDMA hijack NVIC IRQ2. + - name: int0 + description: SmartDMA hijack NVIC IRQ1. bit_offset: 0 bit_size: 1 - - name: INT1 - description: SmartDMA hijack NVIC IRQ23. + - name: int1 + description: SmartDMA hijack NVIC IRQ17. bit_offset: 1 bit_size: 1 - - name: INT2 - description: SmartDMA hijack NVIC IRQ26. + - name: int2 + description: SmartDMA hijack NVIC IRQ18. bit_offset: 2 bit_size: 1 - - name: INT3 - description: SmartDMA hijack NVIC IRQ27. + - name: int3 + description: SmartDMA hijack NVIC IRQ29. bit_offset: 3 bit_size: 1 - - name: INT4 - description: SmartDMA hijack NVIC IRQ28. + - name: int4 + description: SmartDMA hijack NVIC IRQ30. bit_offset: 4 bit_size: 1 - - name: INT5 - description: SmartDMA hijack NVIC IRQ29. + - name: int5 + description: SmartDMA hijack NVIC IRQ31. bit_offset: 5 bit_size: 1 - - name: INT6 - description: SmartDMA hijack NVIC IRQ31. + - name: int6 + description: SmartDMA hijack NVIC IRQ32. bit_offset: 6 bit_size: 1 - - name: INT7 - description: SmartDMA hijack NVIC IRQ32. + - name: int7 + description: SmartDMA hijack NVIC IRQ33. bit_offset: 7 bit_size: 1 - - name: INT8 - description: SmartDMA hijack NVIC IRQ33. + - name: int8 + description: SmartDMA hijack NVIC IRQ34. bit_offset: 8 bit_size: 1 - - name: INT9 - description: SmartDMA hijack NVIC IRQ34. + - name: int9 + description: SmartDMA hijack NVIC IRQ35. bit_offset: 9 bit_size: 1 - - name: INT10 + - name: int10 description: SmartDMA hijack NVIC IRQ36. bit_offset: 10 bit_size: 1 - - name: INT11 - description: SmartDMA hijack NVIC IRQ39. + - name: int11 + description: SmartDMA hijack NVIC IRQ37. bit_offset: 11 bit_size: 1 - - name: INT12 - description: SmartDMA hijack NVIC IRQ40. + - name: int12 + description: SmartDMA hijack NVIC IRQ38. bit_offset: 12 bit_size: 1 - - name: INT13 - description: SmartDMA hijack NVIC IRQ41. + - name: int13 + description: SmartDMA hijack NVIC IRQ39. bit_offset: 13 bit_size: 1 - - name: INT14 - description: SmartDMA hijack NVIC IRQ59. + - name: int14 + description: SmartDMA hijack NVIC IRQ40. bit_offset: 14 bit_size: 1 - - name: INT15 - description: SmartDMA hijack NVIC IRQ62. + - name: int15 + description: SmartDMA hijack NVIC IRQ41. bit_offset: 15 bit_size: 1 - - name: INT16 - description: SmartDMA hijack NVIC IRQ64. + - name: int16 + description: SmartDMA hijack NVIC IRQ42. bit_offset: 16 bit_size: 1 - - name: INT17 - description: SmartDMA hijack NVIC IRQ71. + - name: int17 + description: SmartDMA hijack NVIC IRQ45. bit_offset: 17 bit_size: 1 - - name: INT18 - description: SmartDMA hijack NVIC IRQ72. + - name: int18 + description: SmartDMA hijack NVIC IRQ47. bit_offset: 18 bit_size: 1 - - name: INT19 - description: SmartDMA hijack NVIC IRQ73. + - name: int19 + description: SmartDMA hijack NVIC IRQ50. bit_offset: 19 bit_size: 1 - - name: INT20 - description: SmartDMA hijack NVIC IRQ74. + - name: int20 + description: SmartDMA hijack NVIC IRQ51. bit_offset: 20 bit_size: 1 - - name: INT21 - description: SmartDMA hijack NVIC IRQ75. + - name: int21 + description: SmartDMA hijack NVIC IRQ66. bit_offset: 21 bit_size: 1 -enum/AHBCLKDIV_UNSTAB: + - name: int22 + description: SmartDMA hijack NVIC IRQ67. + bit_offset: 22 + bit_size: 1 + - name: int23 + description: SmartDMA hijack NVIC IRQ77. + bit_offset: 23 + bit_size: 1 +fieldset/SramXen: + description: RAM XEN Control. + fields: + - name: ramx0_xen + description: RAMX0 Execute permission control. + bit_offset: 0 + bit_size: 1 + - name: ramx1_xen + description: RAMX1 Execute permission control. + bit_offset: 1 + bit_size: 1 + - name: rama0_xen + description: RAMA0 Execute permission control. + bit_offset: 2 + bit_size: 1 + - name: rama1_xen + description: RAMAx (excepts RAMA0) Execute permission control. + bit_offset: 3 + bit_size: 1 + - name: ramb_xen + description: RAMBx Execute permission control. + bit_offset: 4 + bit_size: 1 + - name: ramc_xen + description: RAMCx Execute permission control. + bit_offset: 5 + bit_size: 1 + - name: lock + description: This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset. + bit_offset: 31 + bit_size: 1 + enum: SramXenLock +fieldset/SramXenDp: + description: RAM XEN Control (Duplicate). + fields: + - name: ramx0_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 0 + bit_size: 1 + - name: ramx1_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 1 + bit_size: 1 + - name: rama0_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 2 + bit_size: 1 + - name: rama1_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 3 + bit_size: 1 + - name: ramb_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 4 + bit_size: 1 + - name: ramc_xen + description: Refer to SRAM_XEN for more details. + bit_offset: 5 + bit_size: 1 +fieldset/SwdAccessCpu0: + description: CPU0 Software Debug Access. + fields: + - name: sec_code + description: 'CPU0 SWD-AP: 0x12345678.' + bit_offset: 0 + bit_size: 32 + enum: SecCode +enum/AhbclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/AHBMATPRIO_CPU0_SBUS: +enum/AhbmatprioCpu0Sbus: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_DMA0: +enum/AhbmatprioDma0: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/BUSCLKDIV_HALT: +enum/BusclkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/BUSCLKDIV_RESET: +enum/BusclkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/BUSCLKDIV_UNSTAB: +enum/BusclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/CLR_LPCAC: +enum/ClrLpcac: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Unclears the cache. value: 0 - - name: DISABLE + - name: Disable description: Clears the cache. value: 1 -enum/CPU0LOCKUP: +enum/Cpu0Cbus: + bit_size: 2 + variants: + - name: Level0 + description: level 0. + value: 0 + - name: Level1 + description: level 1. + value: 1 + - name: Level2 + description: level 2. + value: 2 + - name: Level3 + description: level 3. + value: 3 +enum/Cpu0lockup: bit_size: 1 variants: - - name: AWAKE + - name: Awake description: CPU is not in lockup. value: 0 - - name: SLEEPING + - name: Sleeping description: CPU is in lockup. value: 1 -enum/CPU0SLEEPING: +enum/Cpu0sleeping: bit_size: 1 variants: - - name: AWAKE + - name: Awake description: CPU is not sleeping. value: 0 - - name: SLEEPING + - name: Sleeping description: CPU is sleeping. value: 1 -enum/CPU0_CBUS: +enum/Cpu1CbusSmartDmaI: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/CPU1_CBUS_SmartDMA_I: +enum/Cpu1SbusSmartDmaD: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/CPU1_SBUS_SmartDMA_D: +enum/DebugFeaturesCpu0Dbgen: bit_size: 2 variants: - - name: LEVEL0 - description: level 0. - value: 0 - - name: LEVEL1 - description: level 1. - value: 1 - - name: LEVEL2 - description: level 2. - value: 2 - - name: LEVEL3 - description: level 3. - value: 3 -enum/DEBUG_FEATURES_CPU0_DBGEN: - bit_size: 2 - variants: - - name: DISABLE + - name: Disable description: Disables debug. value: 1 - - name: ENABLE + - name: Enable description: Enables debug. value: 2 -enum/DEBUG_FEATURES_CPU0_NIDEN: +enum/DebugFeaturesCpu0Niden: bit_size: 2 variants: - - name: DISABLE + - name: Disable description: Disables debug. value: 1 - - name: ENABLE + - name: Enable description: Enables debug. value: 2 -enum/DEBUG_FEATURES_DP_CPU0_DBGEN: +enum/DebugFeaturesDpCpu0Dbgen: bit_size: 2 variants: - - name: DISABLE + - name: Disable description: Disables debug. value: 1 - - name: ENABLE + - name: Enable description: Enables debug. value: 2 -enum/DEBUG_FEATURES_DP_CPU0_NIDEN: +enum/DebugFeaturesDpCpu0Niden: bit_size: 2 variants: - - name: DISABLE + - name: Disable description: Disables debug. value: 1 - - name: ENABLE + - name: Enable description: Enables debug. value: 2 -enum/DEVICE_TYPE_PKG: +enum/DeviceTypePkg: bit_size: 4 variants: - - name: HLQFP + - name: Hlqfp description: HLQFP. value: 0 - - name: HTQFP + - name: Htqfp description: HTQFP. value: 1 - - name: BGA + - name: Bga description: BGA. value: 2 - - name: HDQFP + - name: Hdqfp description: HDQFP. value: 3 - - name: QFN + - name: Qfn description: QFN. value: 4 - - name: CSP + - name: Csp description: CSP. value: 5 - - name: LQFP + - name: Lqfp description: LQFP. value: 6 -enum/DEVICE_TYPE_SEC: +enum/DeviceTypeSec: bit_size: 1 variants: - - name: NON_SEC + - name: NonSec description: Non Secure. value: 0 - - name: SEC + - name: Sec description: Secure. value: 1 -enum/DIS_DATA_SPEC: +enum/DisDataSpec: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables data speculation. value: 0 - - name: DISABLE + - name: Disable description: Disables data speculation. value: 1 -enum/DIS_FLASH_SPEC: +enum/DisFlashSpec: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables flash speculation. value: 0 - - name: DISABLE + - name: Disable description: Disables flash speculation. value: 1 -enum/DIS_LPCAC: +enum/DisLpcac: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enabled. value: 0 - - name: DISABLE + - name: Disable description: Disabled. value: 1 -enum/DIS_MBECC_ERR_DATA: +enum/DisMbeccErrData: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables bus error on multi-bit ECC error for data. value: 0 - - name: DISABLE + - name: Disable description: Disables bus error on multi-bit ECC error for data. value: 1 -enum/DIS_MBECC_ERR_INST: +enum/DisMbeccErrInst: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables bus error on multi-bit ECC error for instruction. value: 0 - - name: DISABLE + - name: Disable description: Disables bus error on multi-bit ECC error for instruction. value: 1 -enum/FLASH_SIZE: +enum/FlashSize: bit_size: 4 variants: - - name: SIZE_32KB + - name: Size32kb description: 32KB. value: 0 - - name: SIZE_64KB + - name: Size64kb description: 64KB. value: 1 - - name: SIZE_128KB + - name: Size128kb description: 128KB. value: 2 - - name: SIZE_256KB + - name: Size256kb description: 256KB. value: 3 - - name: SIZE_512KB + - name: Size512kb description: 512KB. value: 4 - - name: SIZE_768KB + - name: Size768kb description: 768KB. value: 5 - - name: SIZE_1MB + - name: Size1mb description: 1MB. value: 6 - - name: SIZE_1P5MB + - name: Size1p5mb description: 1.5MB. value: 7 - - name: SIZE_2MB + - name: Size2mb description: 2MB. value: 8 -enum/FLASH_STALL_EN: +enum/FlashStallEn: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: No stall on FLASH busy. value: 0 - - name: DISABLE + - name: Disable description: Stall on FLASH busy. value: 1 -enum/FRC_NO_ALLOC: +enum/FrcNoAlloc: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Forces allocation. value: 0 - - name: DISABLE + - name: Disable description: Forces no allocation. value: 1 -enum/FROHFDIV_HALT: +enum/FrohfdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/FROHFDIV_RESET: +enum/FrohfdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/FROHFDIV_UNSTAB: +enum/FrohfdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/FROLFDIV_HALT: +enum/FrolfdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/FROLFDIV_RESET: +enum/FrolfdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/FROLFDIV_UNSTAB: +enum/FrolfdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/IFR_ERASE_DIS0: +enum/IfrEraseDis0: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enable IFR sector erase. value: 0 - - name: DISABLE + - name: Disable description: Disable IFR sector erase, write one lock until a system reset. value: 1 -enum/IFR_ERASE_DIS1: +enum/IfrEraseDis1: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enable IFR sector erase. value: 0 - - name: DISABLE + - name: Disable description: Disable IFR sector erase, write one lock until a system reset. value: 1 -enum/IFR_ERASE_DIS2: +enum/IfrEraseDis2: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enable IFR sector erase. value: 0 - - name: DISABLE + - name: Disable description: Disable IFR sector erase, write one lock until a system reset. value: 1 -enum/IFR_ERASE_DIS3: +enum/IfrEraseDis3: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enable IFR sector erase. value: 0 - - name: DISABLE + - name: Disable description: Disable IFR sector erase, write one lock until a system reset. value: 1 -enum/INTERLEAVE: +enum/Interleave: bit_size: 1 variants: - - name: NORMAL + - name: Normal description: RAM access is consecutive. value: 0 - - name: INTERLEAVE + - name: Interleave description: RAM access is interleaved. This setting is need for PKC L0 memory access. value: 1 -enum/LOCKNSMPU: - bit_size: 1 +enum/KeySel: + bit_size: 2 variants: - - name: ENABLE - description: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed. + - name: Duk0 + description: 'DUK: UID[127:0]^RTL_CONST1[127:0].' value: 0 - - name: DISABLE - description: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored. + - name: Duk1 + description: 'DUK: UID[127:0]^RTL_CONST1[127:0].' value: 1 -enum/LOCK_ALL: + - name: DeviceHsm + description: DeviceHSM. + value: 2 + - name: NxpMRoT + description: NXP_mRoT. + value: 3 +enum/LockAll: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: 'Any other value than b1010: disables write access to all registers.' value: 0 - - name: ENABLE + - name: Enable description: Enables write access to all registers. value: 10 -enum/MASS_ERASE_DIS: +enum/Locknsmpu: bit_size: 1 variants: - - name: ENABLE + - name: Enable + description: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed. + value: 0 + - name: Disable + description: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored. + value: 1 +enum/MassEraseDis: + bit_size: 1 + variants: + - name: Enable description: Enables mass erase. value: 0 - - name: DISABLE + - name: Disable description: Disables mass erase, write one lock until a system reset. value: 1 -enum/NOREF: +enum/Noref: bit_size: 1 variants: - - name: YES_REF + - name: YesRef description: Reference clock is provided. value: 0 - - name: NO_REF + - name: NoRef description: No reference clock is provided. value: 1 -enum/PKC: +enum/Pkc: bit_size: 2 variants: - - name: PKC_0 + - name: Pkc0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: PKC_1 + - name: Pkc1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/PKC_ELS: +enum/PkcEls: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/PLL1CLKDIV_HALT: +enum/Pll1clkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/PLL1CLKDIV_RESET: +enum/Pll1clkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/PLL1CLKDIV_UNSTAB: +enum/Pll1clkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/PROTLVL_LOCK: +enum/ProtlvlLock: bit_size: 1 variants: - - name: LOCK_0 + - name: Lock0 description: This register is not locked and can be altered. value: 0 - - name: LOCK_1 + - name: Lock1 description: This register is locked and cannot be altered until a system reset. value: 1 -enum/RAM_SIZE: +enum/RamSize: bit_size: 4 variants: - - name: SIZE_8KB + - name: Size8kb description: 8KB. value: 0 - - name: SIZE_16KB + - name: Size16kb description: 16KB. value: 1 - - name: SIZE_32KB + - name: Size32kb description: 32KB. value: 2 - - name: SIZE_64KB + - name: Size64kb description: 64KB. value: 3 - - name: SIZE_96KB + - name: Size96kb description: 96KB. value: 4 - - name: SIZE_128KB + - name: Size128kb description: 128KB. value: 5 - - name: SIZE_160KB + - name: Size160kb description: 160KB. value: 6 - - name: SIZE_192KB + - name: Size192kb description: 192KB. value: 7 - - name: SIZE_256KB + - name: Size256kb description: 256KB. value: 8 - - name: SIZE_288KB + - name: Size288kb description: 288KB. value: 9 - - name: SIZE_352KB + - name: Size352kb description: 352KB. value: 10 - - name: SIZE_512KB + - name: Size512kb description: 512KB. value: 11 -enum/REMAP_CPU0_SBUS: +enum/RemapCpu0Sbus: bit_size: 2 variants: - - name: CPU0_SBUS_0 + - name: Cpu0Sbus0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: CPU0_SBUS_1 + - name: Cpu0Sbus1 description: 'RAMX0: alias space is enabled. It''s linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024.' value: 1 -enum/REMAP_DMA0: +enum/RemapDma0: bit_size: 2 variants: - - name: DMA0_0 + - name: Dma00 description: 'RAMX0: alias space is disabled.' value: 0 - - name: DMA0_1 + - name: Dma01 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_LOCK: +enum/RemapLock: bit_size: 1 variants: - - name: LOCK_0 + - name: Lock0 description: This register is not locked and can be altered. value: 0 - - name: LOCK_1 + - name: Lock1 description: This register is locked and cannot be altered until a system reset. value: 1 -enum/SECURITY: - bit_size: 4 - variants: - - name: NON_SEC - description: Secure version. - value: 5 - - name: SECURITY_10 - description: Non secure version. - value: 10 -enum/SEC_CODE: +enum/SecCode: bit_size: 32 variants: - - name: DISABLE + - name: Disable description: CPU0 DAP is not allowed. Reading back register is read as 0x5. value: 0 - - name: ENABLE + - name: Enable description: Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. value: 305419896 -enum/SKEW: +enum/Security: + bit_size: 4 + variants: + - name: NonSec + description: Secure version. + value: 5 + - name: Security10 + description: Non secure version. + value: 10 +enum/Skew: bit_size: 1 variants: - - name: EXACT + - name: Exact description: TENMS value is exact. value: 0 - - name: INEXACT + - name: Inexact description: TENMS value is not exact or not given. value: 1 -enum/SLOWCLKDIV_HALT: +enum/SlowclkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/SLOWCLKDIV_RESET: +enum/SlowclkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/SLOWCLKDIV_UNSTAB: +enum/SlowclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/SRAM_XEN_LOCK: - bit_size: 1 - variants: - - name: LOCK_0 - description: This register is not locked and can be altered. - value: 0 - - name: LOCK_1 - description: This register is locked and cannot be altered. - value: 1 -enum/SmartDMA_D: +enum/SmartDmaD: bit_size: 2 variants: - - name: SmartDMA_D_0 + - name: SmartDmaD0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: SmartDMA_D_1 + - name: SmartDmaD1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/SmartDMA_I: +enum/SmartDmaI: bit_size: 2 variants: - - name: SmartDMA_I_0 + - name: SmartDmaI0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: SmartDMA_I_1 + - name: SmartDmaI1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/UNLOCK: +enum/SramXenLock: + bit_size: 1 + variants: + - name: Lock0 + description: This register is not locked and can be altered. + value: 0 + - name: Lock1 + description: This register is locked and cannot be altered. + value: 1 +enum/UdfHidden: + bit_size: 4 + variants: + - name: UdfHidden + description: Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus. + value: 10 +enum/UidHidden: + bit_size: 4 + variants: + - name: UidHidden + description: Enable the access of UID[127:0] register. All other value, disable the read/write of UID[127:0] register. + value: 10 +enum/Unlock: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Updates are allowed to all clock configuration registers. value: 0 - - name: FREEZE + - name: Freeze description: Freezes all clock configuration registers update. value: 1 -enum/USB0: +enum/Usb0: bit_size: 2 variants: - - name: USB0_0 + - name: Usb00 description: 'RAMX0: alias space is disabled.' value: 0 - - name: USB0_1 + - name: Usb01 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/USB_FS_ENET: +enum/UsbFsEnet: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 diff --git a/data/metadata/peripherals/mcxa/SYSCON5xx.yaml b/data/metadata/peripherals/mcxa/SYSCON5xx.yaml index ab9daa1..6e67085 100644 --- a/data/metadata/peripherals/mcxa/SYSCON5xx.yaml +++ b/data/metadata/peripherals/mcxa/SYSCON5xx.yaml @@ -1,1507 +1,1779 @@ -block/SYSCON: +block/Syscon: description: SYSCON. items: - - name: REMAP + - name: remap description: AHB Matrix Remap Control. byte_offset: 0 - fieldset: REMAP - - name: AHBMATPRIO + fieldset: Remap + - name: ahbmatprio description: AHB Matrix Priority Control. byte_offset: 16 - fieldset: AHBMATPRIO - - name: NMISRC + fieldset: Ahbmatprio + - name: bufferingahb2vpb0 + description: Buffering of write accesses on the Synchronous System configuration APB interface. + byte_offset: 32 + fieldset: Bufferingahb2vpb0 + - name: nmisrc description: NMI Source Select. byte_offset: 72 - fieldset: NMISRC - - name: PROTLVL + fieldset: Nmisrc + - name: protlvl description: Protect Level Control. byte_offset: 76 - fieldset: PROTLVL - - name: CPU0NSTCKCAL + fieldset: Protlvl + - name: cpu0nstckcal description: Non-Secure CPU0 System Tick Calibration. byte_offset: 84 - fieldset: CPU0NSTCKCAL - - name: AHBCLKDIV + fieldset: Cpu0nstckcal + - name: ahbclkdiv description: System Clock Divider. byte_offset: 128 - fieldset: AHBCLKDIV - - name: BUSCLKDIV + fieldset: Ahbclkdiv + - name: busclkdiv description: BUS_CLK Clock Divider. byte_offset: 132 - fieldset: BUSCLKDIV - - name: SLOWCLKDIV + fieldset: Busclkdiv + - name: slowclkdiv description: SLOW_CLK Clock Divider. byte_offset: 136 - fieldset: SLOWCLKDIV - - name: FROHFDIV + fieldset: Slowclkdiv + - name: frohfdiv description: FRO_HF_DIV Clock Divider. byte_offset: 144 - fieldset: FROHFDIV - - name: FROLFDIV + fieldset: Frohfdiv + - name: frolfdiv description: FRO_LF_DIV Clock Divider. byte_offset: 148 - fieldset: FROLFDIV - - name: PLL1CLKDIV + fieldset: Frolfdiv + - name: pll1clkdiv description: PLL1_CLK_DIV Clock Divider. byte_offset: 228 - fieldset: PLL1CLKDIV - - name: CLKUNLOCK + fieldset: Pll1clkdiv + - name: clkunlock description: Clock Configuration Unlock. byte_offset: 252 - fieldset: CLKUNLOCK - - name: GRAY_CODE_LSB + fieldset: Clkunlock + - name: gray_code_lsb description: Gray to Binary Converter Gray Code [31:0]. byte_offset: 352 - fieldset: GRAY_CODE_LSB - - name: GRAY_CODE_MSB + fieldset: GrayCodeLsb + - name: gray_code_msb description: Gray to Binary Converter Gray Code [41:32]. byte_offset: 356 - fieldset: GRAY_CODE_MSB - - name: BINARY_CODE_LSB + fieldset: GrayCodeMsb + - name: binary_code_lsb description: Gray to Binary Converter Binary Code [31:0]. byte_offset: 360 access: Read - fieldset: BINARY_CODE_LSB - - name: BINARY_CODE_MSB + fieldset: BinaryCodeLsb + - name: binary_code_msb description: Gray to Binary Converter Binary Code [41:32]. byte_offset: 364 access: Read - fieldset: BINARY_CODE_MSB - - name: ENET_CTRL + fieldset: BinaryCodeMsb + - name: enet_ctrl description: Ethernet Control. byte_offset: 448 - fieldset: ENET_CTRL - - name: ENET_SBD_FLOW_CTRL + fieldset: EnetCtrl + - name: enet_sbd_flow_ctrl description: Sideband Flow Control. byte_offset: 452 - fieldset: ENET_SBD_FLOW_CTRL - - name: NVM_CTRL + fieldset: EnetSbdFlowCtrl + - name: nvm_ctrl description: NVM Control. byte_offset: 512 - fieldset: NVM_CTRL - - name: SmartDMAINT + fieldset: NvmCtrl + - name: romcr + description: ROM Control and State. + byte_offset: 516 + fieldset: Romcr + - name: smart_dmaint description: SmartDMA Interrupt Hijack. byte_offset: 532 - fieldset: SmartDMAINT - - name: BOOTROM - description: Immediate cessation of execution following the completion of ROM execution. - byte_offset: 572 - access: Read - - name: RAM_CASP_CTRL + fieldset: SmartDmaint + - name: usb1needclkctrl + description: USB1-HS Need Clock Control. + byte_offset: 548 + fieldset: Usb1needclkctrl + - name: usb1needclkstat + description: USB1-HS Need Clock Status. + byte_offset: 552 + fieldset: Usb1needclkstat + - name: ram_casp_ctrl description: Controls Shared RAM Integration. byte_offset: 624 - fieldset: RAM_CASP_CTRL - - name: CPUSTAT + fieldset: RamCaspCtrl + - name: cpustat description: CPU Status. byte_offset: 780 access: Read - fieldset: CPUSTAT - - name: LPCAC_CTRL + fieldset: Cpustat + - name: lpcac_ctrl description: LPCAC Control. byte_offset: 804 - fieldset: LPCAC_CTRL - - name: I3C_MISC_CTRL - description: I3C Misc Control. + fieldset: LpcacCtrl + - name: i3c_misc_ctrl + description: Chip Special I3C Control. byte_offset: 808 - fieldset: I3C_MISC_CTRL - - name: CTIMERGLOBALSTARTEN + fieldset: I3cMiscCtrl + - name: ctimerglobalstarten description: CTIMER Global Start Enable. byte_offset: 1088 - fieldset: CTIMERGLOBALSTARTEN - - name: RAM_CTRL + fieldset: Ctimerglobalstarten + - name: ram_ctrl description: RAM Control. byte_offset: 1092 - fieldset: RAM_CTRL - - name: JTAG_ID + fieldset: RamCtrl + - name: ref_clk_ctrl + description: FRO 48MHz Reference Clock Control. + byte_offset: 1632 + fieldset: RefClkCtrl + - name: ref_clk_ctrl_set + description: FRO 48MHz Reference Clock Control Set. + byte_offset: 1636 + access: Write + fieldset: RefClkCtrlSet + - name: ref_clk_ctrl_clr + description: FRO 48MHz Reference Clock Control Clear. + byte_offset: 1640 + access: Write + fieldset: RefClkCtrlClr + - name: flashsizecfg + description: Flash size configuration. + byte_offset: 2016 + access: Read + fieldset: Flashsizecfg + - name: miscphantom + description: MISC Phantom control register. + byte_offset: 2024 + fieldset: Miscphantom + - name: jtag_id description: JTAG Chip ID. byte_offset: 2032 access: Read - fieldset: JTAG_ID - - name: DEVICE_TYPE + fieldset: JtagId + - name: device_type description: Device Type. byte_offset: 2036 access: Read - fieldset: DEVICE_TYPE - - name: DEVICE_ID0 + fieldset: DeviceType + - name: device_id0 description: Device ID. byte_offset: 2040 access: Read - fieldset: DEVICE_ID0 -fieldset/AHBCLKDIV: + fieldset: DeviceId0 + - name: dieid + description: Chip Revision ID and Number. + byte_offset: 2044 + access: Read + fieldset: Dieid +fieldset/Ahbclkdiv: description: System Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: UNSTAB + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: AHBCLKDIV_UNSTAB -fieldset/AHBMATPRIO: + enum: AhbclkdivUnstab +fieldset/Ahbmatprio: description: AHB Matrix Priority Control. fields: - - name: CPU0_CBUS + - name: cpu0_cbus description: CPU0 C-AHB bus master priority level. bit_offset: 0 bit_size: 2 - enum: CPU0_CBUS - - name: CPU0_SBUS + enum: Cpu0Cbus + - name: cpu0_sbus description: CPU0 S-AHB bus master priority level. bit_offset: 2 bit_size: 2 - enum: AHBMATPRIO_CPU0_SBUS - - name: CPU1_CBUS_SmartDMA_I + enum: AhbmatprioCpu0Sbus + - name: cpu1_cbus_smart_dma_i description: SmartDMA-I bus master priority level. bit_offset: 4 bit_size: 2 - enum: CPU1_CBUS_SmartDMA_I - - name: CPU1_SBUS_SmartDMA_D + enum: Cpu1CbusSmartDmaI + - name: cpu1_sbus_smart_dma_d description: SmartDMA-D bus master priority level. bit_offset: 6 bit_size: 2 - enum: CPU1_SBUS_SmartDMA_D - - name: DMA0 + enum: Cpu1SbusSmartDmaD + - name: dma0 description: DMA0 controller bus master priority level. bit_offset: 8 bit_size: 2 - enum: AHBMATPRIO_DMA0 - - name: DMA1 + enum: AhbmatprioDma0 + - name: dma1 description: DMA1 controller bus master priority level. bit_offset: 10 bit_size: 2 - enum: AHBMATPRIO_DMA1 - - name: PKC_ELS + enum: AhbmatprioDma1 + - name: pkc_els description: PKC and ELS bus master priority level. bit_offset: 12 bit_size: 2 - enum: AHBMATPRIO_PKC_ELS - - name: COOLFLUX_Y_ESPI + enum: AhbmatprioPkcEls + - name: coolflux_y_espi description: ESPI bus master priority level. bit_offset: 20 bit_size: 2 - enum: AHBMATPRIO_COOLFLUX_Y_ESPI - - name: USB_FS_ENET + enum: AhbmatprioCoolfluxYEspi + - name: usb_fs_enet description: ENET bus master priority level. bit_offset: 24 bit_size: 2 - enum: AHBMATPRIO_USB_FS_ENET - - name: USB_HS + enum: AhbmatprioUsbFsEnet + - name: usb_hs description: USB-HS bus master priority level. bit_offset: 26 bit_size: 2 - enum: AHBMATPRIO_USB_HS -fieldset/BINARY_CODE_LSB: + enum: AhbmatprioUsbHs +fieldset/BinaryCodeLsb: description: Gray to Binary Converter Binary Code [31:0]. fields: - name: code_bin_31_0 description: Binary code [31:0]. bit_offset: 0 bit_size: 32 -fieldset/BINARY_CODE_MSB: +fieldset/BinaryCodeMsb: description: Gray to Binary Converter Binary Code [41:32]. fields: - name: code_bin_41_32 description: Binary code [41:32]. bit_offset: 0 bit_size: 10 -fieldset/BUSCLKDIV: +fieldset/Bufferingahb2vpb0: + description: Buffering of write accesses on the Synchronous System configuration APB interface. + fields: + - name: inputmux0 + description: Enables buffering of write accesses on the peripheral input mux distribute APB interface:. + bit_offset: 1 + bit_size: 1 + - name: i3c0 + description: Enables buffering of write accesses on I3C0 APB interface. + bit_offset: 2 + bit_size: 1 + - name: ctimer0 + description: Enables buffering of write accesses on CTIMER0 APB interface. + bit_offset: 4 + bit_size: 1 + - name: ctimer1 + description: Enables buffering of write accesses on CTIMER1 APB interface. + bit_offset: 5 + bit_size: 1 + - name: ctimer2 + description: Enables buffering of write accesses on CTIMER2 APB interface. + bit_offset: 6 + bit_size: 1 + - name: ctimer3 + description: Enables buffering of write accesses on CTIMER3 APB interface. + bit_offset: 7 + bit_size: 1 + - name: ctimer4 + description: Enables buffering of write accesses on CTIMER4 APB interface. + bit_offset: 8 + bit_size: 1 + - name: freqme + description: Enables buffering of write accesses on freqme APB interface. + bit_offset: 9 + bit_size: 1 + - name: utick + description: Enables buffering of write accesses on micro Tick APB interface. + bit_offset: 11 + bit_size: 1 + - name: wwdt0 + description: Enables buffering of write accesses on wwdt0 APB interface. + bit_offset: 12 + bit_size: 1 + - name: wwdt1 + description: Enables buffering of write accesses on wwdt1 APB interface. + bit_offset: 13 + bit_size: 1 + - name: smart_dma0 + description: Enables buffering of write accesses on SmartDMA0 APB interface. + bit_offset: 14 + bit_size: 1 +fieldset/Busclkdiv: description: BUS_CLK Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: BUSCLKDIV_RESET - - name: HALT + enum: BusclkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: BUSCLKDIV_HALT - - name: UNSTAB + enum: BusclkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: BUSCLKDIV_UNSTAB -fieldset/CLKUNLOCK: + enum: BusclkdivUnstab +fieldset/Clkunlock: description: Clock Configuration Unlock. fields: - - name: UNLOCK + - name: unlock description: Controls clock configuration registers access (for example, SLOWCLKDIV, BUSCLKDIV, AHBCLKDIV, FROHFDIV, FROLFDIV, PLLxCLKDIV, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx). bit_offset: 0 bit_size: 1 - enum: UNLOCK -fieldset/CPU0NSTCKCAL: + enum: Unlock +fieldset/Cpu0nstckcal: description: Non-Secure CPU0 System Tick Calibration. fields: - - name: TENMS + - name: tenms description: Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. bit_offset: 0 bit_size: 24 - - name: SKEW + - name: skew description: Indicates whether the TENMS value is exact. bit_offset: 24 bit_size: 1 - enum: SKEW - - name: NOREF + enum: Skew + - name: noref description: Indicates whether the device provides a reference clock to the processor. bit_offset: 25 bit_size: 1 - enum: NOREF -fieldset/CPUSTAT: + enum: Noref +fieldset/Cpustat: description: CPU Status. fields: - - name: CPU0SLEEPING + - name: cpu0sleeping description: CPU0 sleeping state. bit_offset: 0 bit_size: 1 - enum: CPU0SLEEPING - - name: CPU0LOCKUP + enum: Cpu0sleeping + - name: cpu0lockup description: CPU0 lockup state. bit_offset: 2 bit_size: 1 - enum: CPU0LOCKUP -fieldset/CTIMERGLOBALSTARTEN: + enum: Cpu0lockup +fieldset/Ctimerglobalstarten: description: CTIMER Global Start Enable. fields: - - name: CTIMER0_CLK_EN + - name: ctimer0_clk_en description: Enables the CTIMER0 function clock. bit_offset: 0 bit_size: 1 - - name: CTIMER1_CLK_EN + - name: ctimer1_clk_en description: Enables the CTIMER1 function clock. bit_offset: 1 bit_size: 1 - - name: CTIMER2_CLK_EN + - name: ctimer2_clk_en description: Enables the CTIMER2 function clock. bit_offset: 2 bit_size: 1 - - name: CTIMER3_CLK_EN + - name: ctimer3_clk_en description: Enables the CTIMER3 function clock. bit_offset: 3 bit_size: 1 - - name: CTIMER4_CLK_EN + - name: ctimer4_clk_en description: Enables the CTIMER4 function clock. bit_offset: 4 bit_size: 1 -fieldset/DEVICE_ID0: +fieldset/DeviceId0: description: Device ID. fields: - - name: RAM_SIZE + - name: ram_size description: Indicates the device's ram size. bit_offset: 0 bit_size: 4 - enum: RAM_SIZE - - name: FLASH_SIZE + enum: DeviceId0RamSize + - name: flash_size description: Indicates the device's flash size. bit_offset: 4 bit_size: 4 - enum: FLASH_SIZE - - name: ROM_REV_MINOR + enum: FlashSize + - name: rom_rev_minor description: Indicates the device's ROM revision. bit_offset: 20 bit_size: 4 - - name: SECURITY - description: no description available. + - name: security + description: CM33_SECURITY_EXTENSION_DISABLE[3:0], which is loaded from soctrim0[87:84]. bit_offset: 24 bit_size: 4 - enum: SECURITY -fieldset/DEVICE_TYPE: + enum: Security +fieldset/DeviceType: description: Device Type. fields: - - name: DEVICE_TYPE_NUM + - name: device_type_num description: Indicates the device part number. bit_offset: 0 bit_size: 16 - - name: DEVICE_TYPE_SEC + - name: device_type_sec description: Indicates the device type. bit_offset: 16 bit_size: 1 - enum: DEVICE_TYPE_SEC - - name: DEVICE_TYPE_PKG + enum: DeviceTypeSec + - name: device_type_pkg description: Indicates the device's package type. bit_offset: 20 bit_size: 4 - enum: DEVICE_TYPE_PKG - - name: DEVICE_TYPE_PIN + enum: DeviceTypePkg + - name: device_type_pin description: Indicates the device's pin number. bit_offset: 24 bit_size: 8 -fieldset/ENET_CTRL: +fieldset/Dieid: + description: Chip Revision ID and Number. + fields: + - name: minor_revision + description: Chip minor revision. + bit_offset: 0 + bit_size: 4 + - name: major_revision + description: Chip major revision. + bit_offset: 4 + bit_size: 4 + - name: mco_num_in_die_id + description: Chip number. + bit_offset: 8 + bit_size: 20 +fieldset/EnetCtrl: description: Ethernet Control. fields: - - name: PHY_INTF + - name: phy_intf description: Selects external PHY interface. bit_offset: 2 bit_size: 1 - enum: PHY_INTF - - name: PHY_SEL + enum: PhyIntf + - name: phy_sel description: Selects external PHY or on-chip 10BASE-T1S. bit_offset: 3 bit_size: 1 - enum: PHY_SEL -fieldset/ENET_SBD_FLOW_CTRL: + enum: PhySel +fieldset/EnetSbdFlowCtrl: description: Sideband Flow Control. fields: - - name: SEL_ch0 + - name: sel_ch0 description: Sideband Flow Control for channel0. bit_offset: 0 bit_size: 1 -fieldset/FROHFDIV: +fieldset/Flashsizecfg: + description: Flash size configuration. + fields: + - name: maxaddr0 + description: Size of Flash Block 0. + bit_offset: 0 + bit_size: 8 + - name: maxaddr1 + description: Size of Flash Block 1. + bit_offset: 8 + bit_size: 8 +fieldset/Frohfdiv: description: FRO_HF_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: FROHFDIV_RESET - - name: HALT + enum: FrohfdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: FROHFDIV_HALT - - name: UNSTAB + enum: FrohfdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: FROHFDIV_UNSTAB -fieldset/FROLFDIV: + enum: FrohfdivUnstab +fieldset/Frolfdiv: description: FRO_LF_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: FROLFDIV_RESET - - name: HALT + enum: FrolfdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: FROLFDIV_HALT - - name: UNSTAB + enum: FrolfdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: FROLFDIV_UNSTAB -fieldset/GRAY_CODE_LSB: + enum: FrolfdivUnstab +fieldset/GrayCodeLsb: description: Gray to Binary Converter Gray Code [31:0]. fields: - name: code_gray_31_0 description: Gray code [31:0]. bit_offset: 0 bit_size: 32 -fieldset/GRAY_CODE_MSB: +fieldset/GrayCodeMsb: description: Gray to Binary Converter Gray Code [41:32]. fields: - name: code_gray_41_32 description: Gray code [41:32]. bit_offset: 0 bit_size: 10 -fieldset/I3C_MISC_CTRL: - description: I3C Misc Control. +fieldset/I3cMiscCtrl: + description: Chip Special I3C Control. fields: - - name: I3C0_SCL_FILT + - name: i3c0_scl_filt description: Disables/enables the I3C0 filter function on SCL pin. bit_offset: 0 bit_size: 4 - enum: I3C0_SCL_FILT - - name: I3C0_SDA_FILT + enum: I3c0SclFilt + - name: i3c0_sda_filt description: Disables/enables the I3C0 filter function on SDA pin. bit_offset: 4 bit_size: 4 - enum: I3C0_SDA_FILT - - name: I3C1_SCL_FILT + enum: I3c0SdaFilt + - name: i3c1_scl_filt description: Disables/enables the I3C1 filter I3C1 function on SCL pin. bit_offset: 8 bit_size: 4 - enum: I3C1_SCL_FILT - - name: I3C1_SDA_FILT + enum: I3c1SclFilt + - name: i3c1_sda_filt description: Disables/enables the I3C1 filter function on SDA pin. bit_offset: 12 bit_size: 4 - enum: I3C1_SDA_FILT - - name: I3C2_SCL_FILT + enum: I3c1SdaFilt + - name: i3c2_scl_filt description: Disables/enables the I3C2 filter function on SCL pin. bit_offset: 16 bit_size: 4 - enum: I3C2_SCL_FILT - - name: I3C2_SDA_FILT + enum: I3c2SclFilt + - name: i3c2_sda_filt description: Disables/enables the I3C2 filter function on SDA pin. bit_offset: 20 bit_size: 4 - enum: I3C2_SDA_FILT - - name: I3C3_SCL_FILT - description: Disables/enables the I3C3 filter function on SCL pin. - bit_offset: 24 - bit_size: 4 - enum: I3C3_SCL_FILT - - name: I3C3_SDA_FILT - description: Disables/enables the I3C3 filter function on SDA pin. - bit_offset: 28 - bit_size: 4 - enum: I3C3_SDA_FILT -fieldset/JTAG_ID: + enum: I3c2SdaFilt +fieldset/JtagId: description: JTAG Chip ID. fields: - - name: JTAG_ID + - name: jtag_id description: Indicates the device ID. bit_offset: 0 bit_size: 32 -fieldset/LPCAC_CTRL: +fieldset/LpcacCtrl: description: LPCAC Control. fields: - - name: DIS_LPCAC + - name: dis_lpcac description: Disables/enables the cache function. bit_offset: 0 bit_size: 1 - enum: DIS_LPCAC - - name: CLR_LPCAC + enum: DisLpcac + - name: clr_lpcac description: Clears the cache function. bit_offset: 1 bit_size: 1 - enum: CLR_LPCAC - - name: FRC_NO_ALLOC + enum: ClrLpcac + - name: frc_no_alloc description: Forces no allocation. bit_offset: 2 bit_size: 1 - enum: FRC_NO_ALLOC - - name: DIS_LPCAC_WTBF + enum: FrcNoAlloc + - name: dis_lpcac_wtbf description: Disable LPCAC Write Through Buffer. bit_offset: 4 bit_size: 1 - - name: LIM_LPCAC_WTBF + - name: lim_lpcac_wtbf description: Limit LPCAC Write Through Buffer. bit_offset: 5 bit_size: 1 - - name: LPCAC_XOM + - name: lpcac_xom description: LPCAC XOM(eXecute-Only-Memory) attribute control. bit_offset: 7 bit_size: 1 - - name: LPCAC_MEM_REQ + - name: lpcac_mem_req description: Request LPCAC memories. bit_offset: 8 bit_size: 1 -fieldset/NMISRC: +fieldset/Miscphantom: + description: MISC Phantom control register. + fields: + - name: ram_size + description: System RAM size phantom control. + bit_offset: 0 + bit_size: 2 + enum: MiscphantomRamSize + - name: rama_ecc + description: RAMA ECC enable. + bit_offset: 8 + bit_size: 1 + - name: flexcan_fd_en + description: FLEXCAN_FD enable. + bit_offset: 17 + bit_size: 1 +fieldset/Nmisrc: description: NMI Source Select. fields: - - name: IRQCPU0 + - name: irqcpu0 description: The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. bit_offset: 0 bit_size: 8 - - name: NMIENCPU0 + - name: nmiencpu0 description: Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. bit_offset: 31 bit_size: 1 -fieldset/NVM_CTRL: +fieldset/NvmCtrl: description: NVM Control. fields: - - name: DIS_FLASH_SPEC + - name: dis_flash_spec description: Flash speculation control. bit_offset: 0 bit_size: 1 - enum: DIS_FLASH_SPEC - - name: DIS_DATA_SPEC + enum: DisFlashSpec + - name: dis_data_spec description: Flash data speculation control. bit_offset: 1 bit_size: 1 - enum: DIS_DATA_SPEC - - name: FLASH_STALL_EN + enum: DisDataSpec + - name: lock_ifr1 + description: FLASH IFR1 lock access control. + bit_offset: 9 + bit_size: 1 + enum: LockIfr1 + - name: flash_stall_en description: FLASH stall on busy control. bit_offset: 10 bit_size: 1 - enum: FLASH_STALL_EN - - name: DIS_MBECC_ERR_INST + enum: FlashStallEn + - name: dis_mbecc_err_inst description: Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative. bit_offset: 16 bit_size: 1 - enum: DIS_MBECC_ERR_INST - - name: DIS_MBECC_ERR_DATA + enum: DisMbeccErrInst + - name: dis_mbecc_err_data description: Bus error on data multi-bit ECC error control Set this field to 0 if you want to enable flash speculative. bit_offset: 17 bit_size: 1 - enum: DIS_MBECC_ERR_DATA -fieldset/PLL1CLKDIV: + enum: DisMbeccErrData +fieldset/Pll1clkdiv: description: PLL1_CLK_DIV Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: PLL1CLKDIV_RESET - - name: HALT + enum: Pll1clkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: PLL1CLKDIV_HALT - - name: UNSTAB + enum: Pll1clkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: PLL1CLKDIV_UNSTAB -fieldset/PROTLVL: + enum: Pll1clkdivUnstab +fieldset/Protlvl: description: Protect Level Control. fields: - - name: PRIV - description: Control privileged access of EIM, ERM, Flexcan, MBC, SCG, DMA, ROMCP and Flexspi. + - name: priv_ + description: Control privileged access of EIM, ERM, Flexcan, MBC, SCG. bit_offset: 0 bit_size: 1 - - name: LOCKNSMPU + - name: locknsmpu description: Control write access to Nonsecure MPU memory regions. bit_offset: 16 bit_size: 1 - enum: LOCKNSMPU - - name: LOCK + enum: Locknsmpu + - name: lock description: This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset. bit_offset: 31 bit_size: 1 - enum: PROTLVL_LOCK -fieldset/RAM_CASP_CTRL: + enum: ProtlvlLock +fieldset/RamCaspCtrl: description: Controls Shared RAM Integration. fields: - - name: INTERLEAVE + - name: interleave description: Controls RAM access for RAMA1 and RAMA2. bit_offset: 0 bit_size: 1 - enum: INTERLEAVE - - name: CASP_REQ + enum: Interleave + - name: casp_req description: Request EZH memories. bit_offset: 16 bit_size: 1 -fieldset/RAM_CTRL: +fieldset/RamCtrl: description: RAM Control. fields: - - name: RAMA_ECC_ENABLE + - name: rama_ecc_enable description: RAMA ECC enable. bit_offset: 0 bit_size: 1 - - name: RAMA_CG_OVERRIDE + - name: rama_cg_override description: RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. bit_offset: 16 bit_size: 1 - - name: RAMX_CG_OVERRIDE + - name: ramx_cg_override description: RAMX bank clock gating control. bit_offset: 17 bit_size: 1 - - name: RAMB_CG_OVERRIDE + - name: ramb_cg_override description: RAMB bank clock gating control. bit_offset: 18 bit_size: 1 -fieldset/REMAP: +fieldset/RefClkCtrl: + description: FRO 48MHz Reference Clock Control. + fields: + - name: gdet_refclk_en + description: GDET reference clock enable bit. + bit_offset: 0 + bit_size: 1 + - name: trng_refclk_en + description: ELS TRNG reference clock enable bit. + bit_offset: 1 + bit_size: 1 +fieldset/RefClkCtrlClr: + description: FRO 48MHz Reference Clock Control Clear. + fields: + - name: gdet_refclk_en_clr + description: GDET reference clock enable clear bit. + bit_offset: 0 + bit_size: 1 + - name: trng_refclk_en_clr + description: ELS TRNG reference clock enable clear bit. + bit_offset: 1 + bit_size: 1 +fieldset/RefClkCtrlSet: + description: FRO 48MHz Reference Clock Control Set. + fields: + - name: gdet_refclk_en_set + description: GDET reference clock enable set bit. + bit_offset: 0 + bit_size: 1 + - name: trng_refclk_en_set + description: ELS TRNG reference clock enable set bit. + bit_offset: 1 + bit_size: 1 +fieldset/Remap: description: AHB Matrix Remap Control. fields: - - name: CPU0_SBUS + - name: cpu0_sbus description: RAMX0 address remap for CPU System bus. bit_offset: 2 bit_size: 2 - enum: REMAP_CPU0_SBUS - - name: SmartDMA_I + enum: RemapCpu0Sbus + - name: smart_dma_i description: RAMX0 address remap for SmartDMA I-BUS. bit_offset: 4 bit_size: 2 - enum: SmartDMA_I - - name: SmartDMA_D + enum: SmartDmaI + - name: smart_dma_d description: RAMX0 address remap for SmartDMA D-BUS. bit_offset: 6 bit_size: 2 - enum: SmartDMA_D - - name: DMA0 + enum: SmartDmaD + - name: dma0 description: RAMX0 address remap for DMA0. bit_offset: 8 bit_size: 2 - enum: REMAP_DMA0 - - name: DMA1 + enum: RemapDma0 + - name: dma1 description: RAMX0 address remap for DMA1. bit_offset: 10 bit_size: 2 - enum: REMAP_DMA1 - - name: PKC_ELS + enum: RemapDma1 + - name: pkc_els description: RAMX0 address remap for PKC_ELS. bit_offset: 12 bit_size: 2 - enum: REMAP_PKC_ELS - - name: COOLFLUX_Y_ESPI + enum: RemapPkcEls + - name: coolflux_y_espi description: RAMX0 address remap for ESPI. bit_offset: 20 bit_size: 2 - enum: REMAP_COOLFLUX_Y_ESPI - - name: USB_FS_ENET + enum: RemapCoolfluxYEspi + - name: usb_fs_enet description: RAMX0 address remap for ENET. bit_offset: 24 bit_size: 2 - enum: REMAP_USB_FS_ENET - - name: USB_HS + enum: RemapUsbFsEnet + - name: usb_hs description: RAMX0 address remap for USB-HS. bit_offset: 26 bit_size: 2 - enum: REMAP_USB_HS - - name: LOCK + enum: RemapUsbHs + - name: lock description: This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset. bit_offset: 31 bit_size: 1 - enum: REMAP_LOCK -fieldset/SLOWCLKDIV: + enum: RemapLock +fieldset/Romcr: + description: ROM Control and State. + fields: + - name: rom_wait + description: ROM waiting Arm core and other masters for one cycle. + bit_offset: 0 + bit_size: 1 +fieldset/Slowclkdiv: description: SLOW_CLK Clock Divider. fields: - - name: DIV + - name: div description: Clock divider value. bit_offset: 0 bit_size: 8 - - name: RESET + - name: reset description: Resets the divider counter. bit_offset: 29 bit_size: 1 - enum: SLOWCLKDIV_RESET - - name: HALT + enum: SlowclkdivReset + - name: halt description: Halts the divider counter. bit_offset: 30 bit_size: 1 - enum: SLOWCLKDIV_HALT - - name: UNSTAB + enum: SlowclkdivHalt + - name: unstab description: Divider status flag. bit_offset: 31 bit_size: 1 - enum: SLOWCLKDIV_UNSTAB -fieldset/SmartDMAINT: + enum: SlowclkdivUnstab +fieldset/SmartDmaint: description: SmartDMA Interrupt Hijack. fields: - - name: INT0 + - name: int0 description: SmartDMA hijack NVIC IRQ2. bit_offset: 0 bit_size: 1 - - name: INT1 + - name: int1 description: SmartDMA hijack NVIC IRQ23. bit_offset: 1 bit_size: 1 - - name: INT2 + - name: int2 description: SmartDMA hijack NVIC IRQ26. bit_offset: 2 bit_size: 1 - - name: INT3 + - name: int3 description: SmartDMA hijack NVIC IRQ27. bit_offset: 3 bit_size: 1 - - name: INT4 + - name: int4 description: SmartDMA hijack NVIC IRQ28. bit_offset: 4 bit_size: 1 - - name: INT5 + - name: int5 description: SmartDMA hijack NVIC IRQ29. bit_offset: 5 bit_size: 1 - - name: INT6 + - name: int6 description: SmartDMA hijack NVIC IRQ31. bit_offset: 6 bit_size: 1 - - name: INT7 + - name: int7 description: SmartDMA hijack NVIC IRQ32. bit_offset: 7 bit_size: 1 - - name: INT8 + - name: int8 description: SmartDMA hijack NVIC IRQ33. bit_offset: 8 bit_size: 1 - - name: INT9 + - name: int9 description: SmartDMA hijack NVIC IRQ34. bit_offset: 9 bit_size: 1 - - name: INT11 + - name: int11 description: SmartDMA hijack NVIC IRQ39. bit_offset: 11 bit_size: 1 - - name: INT12 + - name: int12 description: SmartDMA hijack NVIC IRQ40. bit_offset: 12 bit_size: 1 - - name: INT13 + - name: int13 description: SmartDMA hijack NVIC IRQ41. bit_offset: 13 bit_size: 1 - - name: INT14 + - name: int14 description: SmartDMA hijack NVIC IRQ59. bit_offset: 14 bit_size: 1 - - name: INT15 + - name: int15 description: SmartDMA hijack NVIC IRQ62. bit_offset: 15 bit_size: 1 - - name: INT16 + - name: int16 description: SmartDMA hijack NVIC IRQ64. bit_offset: 16 bit_size: 1 - - name: INT17 + - name: int17 description: SmartDMA hijack NVIC IRQ71. bit_offset: 17 bit_size: 1 - - name: INT18 + - name: int18 description: SmartDMA hijack NVIC IRQ72. bit_offset: 18 bit_size: 1 - - name: INT19 + - name: int19 description: SmartDMA hijack NVIC IRQ73. bit_offset: 19 bit_size: 1 - - name: INT20 + - name: int20 description: SmartDMA hijack NVIC IRQ74. bit_offset: 20 bit_size: 1 - - name: INT21 + - name: int21 description: SmartDMA hijack NVIC IRQ75. bit_offset: 21 bit_size: 1 - - name: INT22 + - name: int22 description: SmartDMA hijack NVIC IRQ103. bit_offset: 22 bit_size: 1 - - name: INT23 + - name: int23 description: SmartDMA hijack NVIC IRQ104. bit_offset: 23 bit_size: 1 -enum/AHBCLKDIV_UNSTAB: +fieldset/Usb1needclkctrl: + description: USB1-HS Need Clock Control. + fields: + - name: ap_hs_dev_needclk + description: USB1-HS device need_clock signal control. + bit_offset: 0 + bit_size: 1 + enum: ApHsDevNeedclk + - name: pol_hs_dev_needclk + description: USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + bit_offset: 1 + bit_size: 1 + enum: PolHsDevNeedclk + - name: ap_hs_host_needclk + description: USB1-HS Host need clock signal control. + bit_offset: 2 + bit_size: 1 + enum: ApHsHostNeedclk + - name: pol_hs_host_needclk + description: USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + bit_offset: 3 + bit_size: 1 + enum: PolHsHostNeedclk + - name: hs_dev_wakeup_n + description: Software override of device controller PHY wake up logic. + bit_offset: 4 + bit_size: 1 + enum: HsDevWakeupN +fieldset/Usb1needclkstat: + description: USB1-HS Need Clock Status. + fields: + - name: dev_needclk + description: USB1-HS device need_clock signal status. + bit_offset: 0 + bit_size: 1 + enum: DevNeedclk + - name: host_needclk + description: USB1-HS Host need_clock signal status. + bit_offset: 1 + bit_size: 1 + enum: HostNeedclk +enum/AhbclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/AHBMATPRIO_COOLFLUX_Y_ESPI: +enum/AhbmatprioCoolfluxYEspi: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_CPU0_SBUS: +enum/AhbmatprioCpu0Sbus: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_DMA0: +enum/AhbmatprioDma0: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_DMA1: +enum/AhbmatprioDma1: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_PKC_ELS: +enum/AhbmatprioPkcEls: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_USB_FS_ENET: +enum/AhbmatprioUsbFsEnet: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/AHBMATPRIO_USB_HS: +enum/AhbmatprioUsbHs: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/BUSCLKDIV_HALT: +enum/ApHsDevNeedclk: + bit_size: 1 + variants: + - name: HwCtrl + description: HOST_NEEDCLK is under hardware control. + value: 0 + - name: Forced + description: HOST_NEEDCLK is forced high. + value: 1 +enum/ApHsHostNeedclk: + bit_size: 1 + variants: + - name: HwCtrl + description: HOST_NEEDCLK is under hardware control. + value: 0 + - name: Forced + description: HOST_NEEDCLK is forced high. + value: 1 +enum/BusclkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/BUSCLKDIV_RESET: +enum/BusclkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/BUSCLKDIV_UNSTAB: +enum/BusclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/CLR_LPCAC: +enum/ClrLpcac: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Unclears the cache. value: 0 - - name: DISABLE + - name: Disable description: Clears the cache. value: 1 -enum/CPU0LOCKUP: +enum/Cpu0Cbus: + bit_size: 2 + variants: + - name: Level0 + description: level 0. + value: 0 + - name: Level1 + description: level 1. + value: 1 + - name: Level2 + description: level 2. + value: 2 + - name: Level3 + description: level 3. + value: 3 +enum/Cpu0lockup: bit_size: 1 variants: - - name: AWAKE + - name: Awake description: CPU is not in lockup. value: 0 - - name: SLEEPING + - name: Sleeping description: CPU is in lockup. value: 1 -enum/CPU0SLEEPING: +enum/Cpu0sleeping: bit_size: 1 variants: - - name: AWAKE + - name: Awake description: CPU is not sleeping. value: 0 - - name: SLEEPING + - name: Sleeping description: CPU is sleeping. value: 1 -enum/CPU0_CBUS: +enum/Cpu1CbusSmartDmaI: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/CPU1_CBUS_SmartDMA_I: +enum/Cpu1SbusSmartDmaD: bit_size: 2 variants: - - name: LEVEL0 + - name: Level0 description: level 0. value: 0 - - name: LEVEL1 + - name: Level1 description: level 1. value: 1 - - name: LEVEL2 + - name: Level2 description: level 2. value: 2 - - name: LEVEL3 + - name: Level3 description: level 3. value: 3 -enum/CPU1_SBUS_SmartDMA_D: - bit_size: 2 +enum/DevNeedclk: + bit_size: 1 variants: - - name: LEVEL0 - description: level 0. + - name: Low + description: DEV_NEEDCLK is low. value: 0 - - name: LEVEL1 - description: level 1. + - name: High + description: DEV_NEEDCLK is high. value: 1 - - name: LEVEL2 - description: level 2. +enum/DeviceId0RamSize: + bit_size: 4 + variants: + - name: Size8kb + description: 8KB. + value: 0 + - name: Size16kb + description: 16KB. + value: 1 + - name: Size32kb + description: 32KB. value: 2 - - name: LEVEL3 - description: level 3. + - name: Size64kb + description: 64KB. value: 3 -enum/DEVICE_TYPE_PKG: + - name: Size96kb + description: 96KB. + value: 4 + - name: Size128kb + description: 128KB. + value: 5 + - name: Size160kb + description: 160KB. + value: 6 + - name: Size192kb + description: 192KB. + value: 7 + - name: Size256kb + description: 256KB. + value: 8 + - name: Size288kb + description: 288KB. + value: 9 + - name: Size352kb + description: 352KB. + value: 10 + - name: Size512kb + description: 512KB. + value: 11 +enum/DeviceTypePkg: bit_size: 4 variants: - - name: HLQFP + - name: Hlqfp description: HLQFP. value: 0 - - name: HTQFP + - name: Htqfp description: HTQFP. value: 1 - - name: BGA + - name: Bga description: BGA. value: 2 - - name: HDQFP + - name: Hdqfp description: HDQFP. value: 3 - - name: QFN + - name: Qfn description: QFN. value: 4 - - name: CSP + - name: Csp description: CSP. value: 5 - - name: LQFP + - name: Lqfp description: LQFP. value: 6 -enum/DEVICE_TYPE_SEC: +enum/DeviceTypeSec: bit_size: 1 variants: - - name: NON_SEC + - name: NonSec description: Non Secure. value: 0 - - name: SEC + - name: Sec description: Secure. value: 1 -enum/DIS_DATA_SPEC: +enum/DisDataSpec: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables data speculation. value: 0 - - name: DISABLE + - name: Disable description: Disables data speculation. value: 1 -enum/DIS_FLASH_SPEC: +enum/DisFlashSpec: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables flash speculation. value: 0 - - name: DISABLE + - name: Disable description: Disables flash speculation. value: 1 -enum/DIS_LPCAC: +enum/DisLpcac: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enabled. value: 0 - - name: DISABLE + - name: Disable description: Disabled. value: 1 -enum/DIS_MBECC_ERR_DATA: +enum/DisMbeccErrData: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables bus error on multi-bit ECC error for data. value: 0 - - name: DISABLE + - name: Disable description: Disables bus error on multi-bit ECC error for data. value: 1 -enum/DIS_MBECC_ERR_INST: +enum/DisMbeccErrInst: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Enables bus error on multi-bit ECC error for instruction. value: 0 - - name: DISABLE + - name: Disable description: Disables bus error on multi-bit ECC error for instruction. value: 1 -enum/FLASH_SIZE: +enum/FlashSize: bit_size: 4 variants: - - name: SIZE_32KB + - name: Size32kb description: 32KB. value: 0 - - name: SIZE_64KB + - name: Size64kb description: 64KB. value: 1 - - name: SIZE_128KB + - name: Size128kb description: 128KB. value: 2 - - name: SIZE_256KB + - name: Size256kb description: 256KB. value: 3 - - name: SIZE_512KB + - name: Size512kb description: 512KB. value: 4 - - name: SIZE_768KB + - name: Size768kb description: 768KB. value: 5 - - name: SIZE_1MB + - name: Size1mb description: 1MB. value: 6 - - name: SIZE_1P5MB + - name: Size1p5mb description: 1.5MB. value: 7 - - name: SIZE_2MB + - name: Size2mb description: 2MB. value: 8 -enum/FLASH_STALL_EN: +enum/FlashStallEn: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: No stall on FLASH busy. value: 0 - - name: DISABLE + - name: Disable description: Stall on FLASH busy. value: 1 -enum/FRC_NO_ALLOC: +enum/FrcNoAlloc: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Forces allocation. value: 0 - - name: DISABLE + - name: Disable description: Forces no allocation. value: 1 -enum/FROHFDIV_HALT: +enum/FrohfdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/FROHFDIV_RESET: +enum/FrohfdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/FROHFDIV_UNSTAB: +enum/FrohfdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/FROLFDIV_HALT: +enum/FrolfdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/FROLFDIV_RESET: +enum/FrolfdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/FROLFDIV_UNSTAB: +enum/FrolfdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/I3C0_SCL_FILT: +enum/HostNeedclk: + bit_size: 1 + variants: + - name: Low + description: HOST_NEEDCLK is low. + value: 0 + - name: High + description: HOST_NEEDCLK is high. + value: 1 +enum/HsDevWakeupN: + bit_size: 1 + variants: + - name: ForceWup + description: Forces USB1_PHY to wake-up. + value: 0 + - name: NormalWup + description: Normal USB1_PHY behavior. + value: 1 +enum/I3c0SclFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when I3C0 SDA_FILT=0b0000. value: 0 - - name: FILT_CNT + - name: FiltCnt description: Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C0_SDA_FILT: +enum/I3c0SdaFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when I3C0 SCL_FILT=0b0000. value: 0 - - name: FILT_NUM + - name: FiltNum description: Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C1_SCL_FILT: +enum/I3c1SclFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when SDA_FILT=0b0000. value: 0 - - name: FILT_NUM + - name: FiltNum description: Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C1_SDA_FILT: +enum/I3c1SdaFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when I3C1 SCL_FILT=0b0000. value: 0 - - name: FILT_NUM + - name: FiltNum description: Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C2_SCL_FILT: +enum/I3c2SclFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when I3C2 SDA_FILT=0b0000. value: 0 - - name: FILT_NUM + - name: FiltNum description: Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C2_SDA_FILT: +enum/I3c2SdaFilt: bit_size: 4 variants: - - name: DISABLE + - name: Disable description: Disabled filter function when I3C2 SCL_FILT=0b0000. value: 0 - - name: FILT_NUM + - name: FiltNum description: Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT. value: 1 -enum/I3C3_SCL_FILT: - bit_size: 4 - variants: - - name: DISABLE - description: Disabled filter function when I3C3 SDA_FILT=0b0000. - value: 0 - - name: FILT_NUM - description: Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT. - value: 1 -enum/I3C3_SDA_FILT: - bit_size: 4 +enum/Interleave: + bit_size: 1 variants: - - name: DISABLE - description: Disabled filter function when I3C3 SCL_FILT=0b0000. + - name: Normal + description: RAM access is consecutive. value: 0 - - name: FILT_NUM - description: Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT. + - name: Interleave + description: RAM access is interleaved. This setting is need for PKC L0 memory access. value: 1 -enum/INTERLEAVE: +enum/LockIfr1: bit_size: 1 variants: - - name: NORMAL - description: RAM access is consecutive. + - name: Enable + description: No lock access to IFR1. value: 0 - - name: INTERLEAVE - description: RAM access is interleaved. This setting is need for PKC L0 memory access. + - name: Disable + description: Lock access to IFR1. value: 1 -enum/LOCKNSMPU: +enum/Locknsmpu: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed. value: 0 - - name: DISABLE + - name: Disable description: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored. value: 1 -enum/NOREF: +enum/MiscphantomRamSize: + bit_size: 2 + variants: + - name: Size256kb + description: 256KB (RAMX0~X3, RAMA0~A7). + value: 0 + - name: Size512kb + description: 512KB (RAMX0~X3, RAMA0~A11, RAMB0~B3). + value: 1 + - name: SizeMax + description: 640KB. + value: 3 +enum/Noref: bit_size: 1 variants: - - name: YES_REF + - name: YesRef description: Reference clock is provided. value: 0 - - name: NO_REF + - name: NoRef description: No reference clock is provided. value: 1 -enum/PHY_INTF: +enum/PhyIntf: bit_size: 1 variants: - - name: MII + - name: Mii description: Selects MII PHY Interface. value: 0 - - name: RMII + - name: Rmii description: Selects RMII PHY Interface. value: 1 -enum/PHY_SEL: +enum/PhySel: bit_size: 1 variants: - - name: PHY + - name: Phy description: Selects external PHY. value: 0 - - name: T1S + - name: T1s description: Selects on-chip 10BASE-T1S. value: 1 -enum/PLL1CLKDIV_HALT: +enum/Pll1clkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/PLL1CLKDIV_RESET: +enum/Pll1clkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/PLL1CLKDIV_UNSTAB: +enum/Pll1clkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/PROTLVL_LOCK: +enum/PolHsDevNeedclk: bit_size: 1 variants: - - name: ENABLE - description: This register is not locked and can be altered. + - name: Falling + description: Falling edge of DEV_NEEDCLK triggers wake-up. value: 0 - - name: DISABLE - description: This register is locked and cannot be altered until a system reset. + - name: Rising + description: Rising edge of DEV_NEEDCLK triggers wake-up. value: 1 -enum/RAM_SIZE: - bit_size: 4 +enum/PolHsHostNeedclk: + bit_size: 1 variants: - - name: SIZE_8KB - description: 8KB. + - name: Falling + description: Falling edge of HOST_NEEDCLK triggers wake-up. value: 0 - - name: SIZE_16KB - description: 16KB. + - name: Rising + description: Rising edge of HOST_NEEDCLK triggers wake-up. value: 1 - - name: SIZE_32KB - description: 32KB. - value: 2 - - name: SIZE_64KB - description: 64KB. - value: 3 - - name: SIZE_96KB - description: 96KB. - value: 4 - - name: SIZE_128KB - description: 128KB. - value: 5 - - name: SIZE_160KB - description: 160KB. - value: 6 - - name: SIZE_192KB - description: 192KB. - value: 7 - - name: SIZE_256KB - description: 256KB. - value: 8 - - name: SIZE_288KB - description: 288KB. - value: 9 - - name: SIZE_352KB - description: 352KB. - value: 10 - - name: SIZE_512KB - description: 512KB. - value: 11 - - name: SIZE_640KB - description: 640KB. - value: 12 -enum/REMAP_COOLFLUX_Y_ESPI: +enum/ProtlvlLock: + bit_size: 1 + variants: + - name: Lock0 + description: This register is not locked and can be altered. + value: 0 + - name: Lock1 + description: This register is locked and cannot be altered until a system reset. + value: 1 +enum/RemapCoolfluxYEspi: bit_size: 2 variants: - - name: DISABLE + - name: CoolfluxYEspi0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: CoolfluxYEspi1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_CPU0_SBUS: +enum/RemapCpu0Sbus: bit_size: 2 variants: - - name: DISABLE + - name: Cpu0Sbus0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: Cpu0Sbus1 description: 'RAMX0: alias space is enabled. It''s linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024.' value: 1 -enum/REMAP_DMA0: +enum/RemapDma0: bit_size: 2 variants: - - name: DISABLE + - name: Dma00 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: Dma01 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_DMA1: +enum/RemapDma1: bit_size: 2 variants: - - name: DISABLE + - name: Dma10 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: Dma11 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_LOCK: +enum/RemapLock: bit_size: 1 variants: - - name: ENABLE + - name: Lock0 description: This register is not locked and can be altered. value: 0 - - name: DISABLE + - name: Lock1 description: This register is locked and cannot be altered until a system reset. value: 1 -enum/REMAP_PKC_ELS: +enum/RemapPkcEls: bit_size: 2 variants: - - name: DISABLE + - name: PkcEls0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: PkcEls1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_USB_FS_ENET: +enum/RemapUsbFsEnet: bit_size: 2 variants: - - name: DISABLE + - name: UsbFsEnet0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: UsbFsEnet1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/REMAP_USB_HS: +enum/RemapUsbHs: bit_size: 2 variants: - - name: DISABLE + - name: UsbHs0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: UsbHs1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/SECURITY: +enum/Security: bit_size: 4 variants: - - name: SEC - description: Secure version. (All values other than 1010b represent the secure version.). + - name: NonSec + description: Secure version. value: 5 - - name: NON_SEC + - name: Security10 description: Non secure version. value: 10 -enum/SKEW: +enum/Skew: bit_size: 1 variants: - - name: EXACT + - name: Exact description: TENMS value is exact. value: 0 - - name: INEXACT + - name: Inexact description: TENMS value is not exact or not given. value: 1 -enum/SLOWCLKDIV_HALT: +enum/SlowclkdivHalt: bit_size: 1 variants: - - name: RUN + - name: Run description: Divider clock is running. value: 0 - - name: HALT + - name: Halt description: Divider clock is stopped. value: 1 -enum/SLOWCLKDIV_RESET: +enum/SlowclkdivReset: bit_size: 1 variants: - - name: RELEASED + - name: Released description: Divider is not reset. value: 0 - - name: ASSERTED + - name: Asserted description: Divider is reset. value: 1 -enum/SLOWCLKDIV_UNSTAB: +enum/SlowclkdivUnstab: bit_size: 1 variants: - - name: STABLE + - name: Stable description: Divider clock is stable. value: 0 - - name: ONGOING + - name: Ongoing description: Clock frequency is not stable. value: 1 -enum/SmartDMA_D: +enum/SmartDmaD: bit_size: 2 variants: - - name: DISABLE + - name: SmartDmaD0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: SmartDmaD1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/SmartDMA_I: +enum/SmartDmaI: bit_size: 2 variants: - - name: DISABLE + - name: SmartDmaI0 description: 'RAMX0: alias space is disabled.' value: 0 - - name: ENABLE + - name: SmartDmaI1 description: 'RAMX0: same alias space as CPU0_SBUS.' value: 1 -enum/UNLOCK: +enum/Unlock: bit_size: 1 variants: - - name: ENABLE + - name: Enable description: Updates are allowed to all clock configuration registers. value: 0 - - name: FREEZE + - name: Freeze description: Freezes all clock configuration registers update. value: 1 diff --git a/data/metadata/peripherals/mcxa/TRNG.yaml b/data/metadata/peripherals/mcxa/TRNG.yaml index 6c87fda..47b3a5c 100644 --- a/data/metadata/peripherals/mcxa/TRNG.yaml +++ b/data/metadata/peripherals/mcxa/TRNG.yaml @@ -1,5 +1,5 @@ block/Trng: - description: TRNG. + description: pd_main.trng0. items: - name: mctl description: Miscellaneous Control Register. @@ -122,12 +122,11 @@ block/Trng: access: Read fieldset: Status - name: ent - description: Entropy Read Register. + description: Entropy Read Register array: len: 8 stride: 4 byte_offset: 64 - access: Read fieldset: Ent - name: pkrcnt10 description: Statistical Check Poker Count 1 and 0 Register. @@ -186,16 +185,6 @@ block/Trng: byte_offset: 172 access: Read fieldset: IntStatus - - name: cser - description: Common Security Error Register. - byte_offset: 176 - access: Read - fieldset: Cser - - name: csclr - description: Common Security Clear Register. - byte_offset: 180 - access: Write - fieldset: Csclr - name: osc2_ctl description: TRNG Oscillator 2 Control Register. byte_offset: 236 @@ -210,52 +199,11 @@ block/Trng: byte_offset: 244 access: Read fieldset: Vid2 -fieldset/Csclr: - description: Common Security Clear Register. - fields: - - name: red_sigs_clr - description: Redundant Signals error/fault Detected. - bit_offset: 0 - bit_size: 1 - enum: RedSigsClr - - name: red_fsm_clr - description: 'Read only: Redundant FSM error/fault detected.' - bit_offset: 1 - bit_size: 1 - enum: RedFsmClr - - name: local_edc_clr - description: 'Read only: Local-EDC error/fault detected.' - bit_offset: 2 - bit_size: 1 - enum: LocalEdcClr - - name: bus_edc_clr - description: 'Read only: Bus-EDC error/fault detected.' - bit_offset: 3 - bit_size: 1 - enum: BusEdcClr -fieldset/Cser: - description: Common Security Error Register. - fields: - - name: red_sigs - description: Redundant Signals error/fault Detected. - bit_offset: 0 - bit_size: 1 - enum: RedSigs - - name: red_fsm - description: Redundant FSM error/fault detected. - bit_offset: 1 - bit_size: 1 - enum: RedFsm - - name: local_edc - description: Local-EDC error/fault detected. - bit_offset: 2 - bit_size: 1 - enum: LocalEdc - - name: bus_edc - description: Bus-EDC error/fault detected. - bit_offset: 3 - bit_size: 1 - enum: BusEdc + - name: osc_inv_chain_len + description: Oscillator Inverter Chain Length Register. + byte_offset: 248 + access: Read + fieldset: OscInvChainLen fieldset/Ent: description: Entropy Read Register. fields: @@ -300,7 +248,7 @@ fieldset/IntCtrl: bit_offset: 2 bit_size: 1 - name: intg_flt - description: Clear the INTG_FLT interrupt. + description: Clear the INTG_FLT interrupt bit_offset: 3 bit_size: 1 fieldset/IntMask: @@ -319,7 +267,7 @@ fieldset/IntMask: bit_offset: 2 bit_size: 1 - name: intg_flt - description: Mask the INTG_FLT interrupt. + description: Mask the INTG_FLT interrupt bit_offset: 3 bit_size: 1 fieldset/IntStatus: @@ -333,7 +281,6 @@ fieldset/IntStatus: description: Entropy Valid. bit_offset: 1 bit_size: 1 - enum: IntStatusEntVal - name: frq_ct_fail description: Frequency Count Fail. bit_offset: 2 @@ -345,6 +292,11 @@ fieldset/IntStatus: fieldset/Mctl: description: Miscellaneous Control Register. fields: + - name: samp_mode + description: Sample Mode. + bit_offset: 0 + bit_size: 2 + enum: SampMode - name: osc_div description: Oscillator1 Divide. bit_offset: 2 @@ -362,6 +314,10 @@ fieldset/Mctl: description: Reset Defaults. bit_offset: 6 bit_size: 1 + - name: for_sclk + description: Force System Clock. + bit_offset: 7 + bit_size: 1 - name: fct_fail description: Frequency Count Fail. bit_offset: 8 @@ -390,10 +346,6 @@ fieldset/Mctl: description: Program Mode. bit_offset: 16 bit_size: 1 - - name: intg_err - description: Integrity Error. - bit_offset: 31 - bit_size: 1 fieldset/Osc2Ctl: description: TRNG Oscillator 2 Control Register. fields: @@ -432,6 +384,19 @@ fieldset/Osc2Frqcnt: description: Frequency Count. bit_offset: 0 bit_size: 22 +fieldset/OscInvChainLen: + description: Oscillator Inverter Chain Length Register. + fields: + - name: osc1_inv_chain_len + description: Shows the even number of inverters set/chosen for the oscillator 1. + bit_offset: 0 + bit_size: 8 + enum: Osc1InvChainLen + - name: osc2_inv_chain_len + description: Shows the even number of inverters set/chosen for the oscillator 2. + bit_offset: 8 + bit_size: 8 + enum: Osc2InvChainLen fieldset/Pkrcnt10: description: Statistical Check Poker Count 1 and 0 Register. fields: @@ -724,7 +689,7 @@ fieldset/SecCfg: description: Security Configuration Register. fields: - name: no_prgm - description: 'If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control [1:0] Oscillator 2 Divider [3:2] Oscillator Fail Safe Limit [13:12] Oscillator Fail Safe Test [14] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode [1:0] Oscillator Divider [3:2] Reset Defaults [6] Force System Clock [7] Long Runs Continuation Mode [14] After this bit has been written to a 1, it cannot be changed.' + description: 'If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control [1:0] Oscillator 2 Divider [3:2] Oscillator Fail Safe Limit [13:12] Oscillator Fail Safe Test [14] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Poker Range Register (PKRRNG) TRNG Poker Maximum Limit Register (PKRMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Statistical Check Run Length 4 Limit Register (SCR4L) TRNG Statistical Check Run Length 5 Limit Register (SCR5L) TRNG Statistical Check Run Length 6 Limit Register (SCR6PL) TRNG Sparse Bit Limit Register (SBLIM) TRNG Miscellaneous Control Register (MCTL): Sample Mode [1:0] Oscillator Divider [3:2] Reset Defaults [6] Force System Clock [7] Long Runs Continuation Mode [14] After this bit has been written to a 1, it cannot be changed.' bit_offset: 1 bit_size: 1 fieldset/Status: @@ -837,7 +802,7 @@ fieldset/Vid2: bit_size: 8 enum: EcoRev - name: intg_opt - description: Shows the integration options for the TRNG. + description: Shows the integration options for the TRNG. (For 2019 or newer SoCs). bit_offset: 16 bit_size: 8 enum: IntgOpt @@ -846,195 +811,141 @@ fieldset/Vid2: bit_offset: 24 bit_size: 8 enum: Era -enum/BusEdc: - bit_size: 1 - variants: - - name: BUS_EDC_NOERR - description: No Bus-EDC error/fault detected. - value: 0 - - name: bus_edc_err - description: Bus-EDC error/fault detected. - value: 1 -enum/BusEdcClr: - bit_size: 1 - variants: - - name: BUS_EDC_NOEFFECT - description: No effect, ignored. - value: 0 - - name: BUS_EDC_CLEAR - description: Clears the CSER[BUS_EDC] bit. - value: 1 enum/ConfigOpt: bit_size: 8 variants: - - name: CONFIG_OPT_VAL + - name: ConfigOptVal description: TRNG_CONFIG_OPT for TRNG. value: 0 enum/EcoRev: bit_size: 8 variants: - - name: ECO_REV_VAL + - name: EcoRevVal description: TRNG_ECO_REV for TRNG. value: 0 enum/Era: bit_size: 8 variants: - - name: ERA_VAL + - name: EraVal description: ERA of the TRNG. value: 12 enum/IntgOpt: bit_size: 8 variants: - - name: INTG_OPT_VAL + - name: IntgOptVal description: INTG_OPT for TRNG. value: 10 -enum/IntStatusEntVal: - bit_size: 1 - variants: - - name: ENT_VAL_INVALID - description: Busy generating entropy. Any value read from the Entropy registers is invalid. - value: 0 - - name: ENT_VAL_VALID - description: Values read from the Entropy registers are valid. - value: 1 enum/IpId: bit_size: 16 variants: - - name: IP_ID_VAL + - name: IpIdVal description: ID for TRNG. value: 48 -enum/LocalEdc: - bit_size: 1 - variants: - - name: LOCAL_EDC_NOERR - description: No Local-EDC error/fault detected. - value: 0 - - name: LOCAL_EDC_ERR - description: Local-EDC error/fault detected. - value: 1 -enum/LocalEdcClr: - bit_size: 1 - variants: - - name: LOCAL_EDC_NOEFFECT - description: No effect, ignored. - value: 0 - - name: LOCAL_EDC_CLEAR - description: Clears the CSER[LOCAL_EDC] bit. - value: 1 enum/MajRev: bit_size: 8 variants: - - name: MAJ_REV_VAL + - name: MajRevVal description: Major revision number for TRNG. - value: 20 + value: 17 enum/MinRev: bit_size: 8 variants: - - name: MIN_REV_VAL + - name: MinRevVal description: Minor revision number for TRNG. value: 12 +enum/Osc1InvChainLen: + bit_size: 8 + variants: + - name: Osc1InvLen + description: Adding 1 to this count are the total number of inversions occurring in ring oscillator 1. + value: 40 enum/Osc2Div: bit_size: 2 variants: - - name: OSC2_DIV_DIV1 + - name: Osc2DivDiv1 description: Use ring oscillator 2 with no divide. value: 0 - - name: OSC2_DIV_DIV2 + - name: Osc2DivDiv2 description: Use ring oscillator 2 divided-by-2. value: 1 - - name: OSC2_DIV_DIV4 + - name: Osc2DivDiv4 description: Use ring oscillator 2 divided-by-4. value: 2 - - name: OSC2_DIV_DIV8 + - name: Osc2DivDiv8 description: Use ring oscillator 2 divided-by-8. value: 3 +enum/Osc2InvChainLen: + bit_size: 8 + variants: + - name: Osc2InvLen + description: Adding 1 to this count are the total number of inversions occurring in ring oscillator 2. + value: 54 enum/Osc2OutEn: bit_size: 1 variants: - - name: OSC2_OUT_EN_0 + - name: Osc2OutEn0 description: Ring oscillator 2 output is gated to an output pad. value: 0 - - name: OSC2_OUT_EN_1 + - name: Osc2OutEn1 description: Allows external viewing of divided-by-2 ring oscillator 2 if MCTL[PRGM] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad. value: 1 enum/OscDiv: bit_size: 2 variants: - - name: OSC_DIV_DIV1 + - name: OscDivDiv1 description: use ring oscillator with no divide. value: 0 - - name: OSC_DIV_DIV2 + - name: OscDivDiv2 description: use ring oscillator divided-by-2. value: 1 - - name: OSC_DIV_DIV4 + - name: OscDivDiv4 description: use ring oscillator divided-by-4. value: 2 - - name: OSC_DIV_DIV8 + - name: OscDivDiv8 description: use ring oscillator divided-by-8. value: 3 enum/OscFailsafeLmt: bit_size: 2 variants: - - name: OSC_FAILSAFE_LMT_4K + - name: OscFailsafeLmt4k description: The limit N is 4096 (2^12) system clocks. value: 0 - - name: OSC_FAILSAFE_LMT_64K + - name: OscFailsafeLmt64k description: The limit N is 65536 (2^16) system clocks. (default). value: 1 - - name: OSC_FAILSAFE_LMT_1M + - name: OscFailsafeLmt1m description: N is 2^20 system clocks. value: 2 - - name: OSC_FAILSAFE_LMT_4M + - name: OscFailsafeLmt4m description: N is 2^22 system clocks (full range of the counter being used). value: 3 -enum/RedFsm: - bit_size: 1 - variants: - - name: RED_FSM_NOERR - description: No redundant FSM error/fault. - value: 0 - - name: RED_FSM_ERR - description: Redundant FSM error/fault detected. - value: 1 -enum/RedFsmClr: - bit_size: 1 - variants: - - name: RED_FSM_NOEFFECT - description: No effect, ignored. - value: 0 - - name: RED_FSM_CLEAR - description: Clears the CSER[RED_FSM] bit. - value: 1 -enum/RedSigs: - bit_size: 1 - variants: - - name: RED_SIGS_NOERR - description: No redundant signal error/fault. - value: 0 - - name: RED_SIGS_ERR - description: Redundant signal error/fault detected. - value: 1 -enum/RedSigsClr: - bit_size: 1 +enum/SampMode: + bit_size: 2 variants: - - name: RED_SIGS_NOEFFECT - description: No effect, ignored. + - name: SampModeVonBoth + description: undefined/reserved. value: 0 - - name: RED_SIGS_CLEAR - description: Clears the CSER[RED_SIGS] bit. + - name: SampModeRawBoth + description: use raw data into both Entropy shifter and Statistical Checker. value: 1 + - name: SampModeVonEnt + description: undefined/reserved. + value: 2 + - name: SampModeUndef + description: undefined/reserved. + value: 3 enum/TrngEntCtl: bit_size: 2 variants: - - name: TRNG_ENT_CTL_SINGLE_OSC1 + - name: TrngEntCtlSingleOsc1 description: Single oscillator mode, using OSC1 (default). value: 0 - - name: TRNG_ENT_CTL_DUAL_OSCS + - name: TrngEntCtlDualOscs description: Dual oscillator mode. value: 1 - - name: TRNG_ENT_CTL_SINGLE_OSC2 + - name: TrngEntCtlSingleOsc2 description: Single oscillator mode, using OSC2. value: 2 - - name: OSC2_DIV_DIV8 + - name: Osc2DivDiv8 description: Unused, (bit field cannot be written to this value). value: 3 diff --git a/data/metadata/peripherals/mcxa/VBAT.yaml b/data/metadata/peripherals/mcxa/VBAT.yaml index e05996a..ba6e552 100644 --- a/data/metadata/peripherals/mcxa/VBAT.yaml +++ b/data/metadata/peripherals/mcxa/VBAT.yaml @@ -1,1108 +1,868 @@ -block/VBAT: +block/Vbat: description: VBAT. items: - - name: VERID + - name: verid description: Version ID. byte_offset: 0 access: Read - fieldset: VERID - - name: STATUSA + fieldset: Verid + - name: statusa description: Status A. byte_offset: 16 - fieldset: STATUSA - - name: IRQENA + fieldset: Statusa + - name: irqena description: Interrupt Enable A. byte_offset: 24 - fieldset: IRQENA - - name: WAKENA + fieldset: Irqena + - name: wakena description: Wake-up Enable A. byte_offset: 32 - fieldset: WAKENA - - name: WAKECFG + fieldset: Wakena + - name: wakecfg description: Wake-up Configuration. byte_offset: 56 - fieldset: WAKECFG - - name: OSCCTLA + fieldset: Wakecfg + - name: oscctla description: Oscillator Control A. byte_offset: 256 - fieldset: OSCCTLA - - name: OSCCFGA + fieldset: Oscctla + - name: osccfga description: Oscillator Configuration A. byte_offset: 264 - fieldset: OSCCFGA - - name: OSCTSTA + fieldset: Osccfga + - name: osctsta description: Oscillator Test A. byte_offset: 272 - fieldset: OSCTSTA - - name: OSCLCKA + fieldset: Osctsta + - name: osclcka description: Oscillator Lock A. byte_offset: 280 - fieldset: OSCLCKA - - name: OSCCLKE + fieldset: Osclcka + - name: oscclke description: Oscillator Clock Enable. byte_offset: 288 - fieldset: OSCCLKE - - name: FROCTLA + fieldset: Oscclke + - name: froctla description: FRO16K Control A. byte_offset: 512 - fieldset: FROCTLA - - name: FROCFGA + fieldset: Froctla + - name: frocfga description: FRO16K Configuration A. byte_offset: 520 - fieldset: FROCFGA - - name: FROTSTA + fieldset: Frocfga + - name: frotsta description: FRO16K Test A. byte_offset: 528 - fieldset: FROTSTA - - name: FROLCKA + fieldset: Frotsta + - name: frolcka description: FRO16K Lock A. byte_offset: 536 - fieldset: FROLCKA - - name: FROCLKE + fieldset: Frolcka + - name: froclke description: FRO16K Clock Enable. byte_offset: 544 - fieldset: FROCLKE - - name: LDOCTLA + fieldset: Froclke + - name: ldoctla description: LDO_RAM Control A. byte_offset: 768 - fieldset: LDOCTLA - - name: LDOCFGA + fieldset: Ldoctla + - name: ldocfga description: LDO_RAM Configuration A. byte_offset: 776 - fieldset: LDOCFGA - - name: LDOTSTA + fieldset: Ldocfga + - name: ldotsta description: LDO_RAM Test A. byte_offset: 784 - fieldset: LDOTSTA - - name: LDOLCKA + fieldset: Ldotsta + - name: ldolcka description: LDO_RAM Lock A. byte_offset: 792 - fieldset: LDOLCKA - - name: LDORAMC + fieldset: Ldolcka + - name: ldoramc description: RAM Control. byte_offset: 800 - fieldset: LDORAMC - - name: LDOTIMER0 + fieldset: Ldoramc + - name: ldotimer0 description: Bandgap Timer 0. byte_offset: 816 - fieldset: LDOTIMER0 - - name: LDOTIMER1 + fieldset: Ldotimer0 + - name: ldotimer1 description: Bandgap Timer 1. byte_offset: 824 - fieldset: LDOTIMER1 - - name: SWICTLA + fieldset: Ldotimer1 + - name: swictla description: Switch Control A. byte_offset: 1536 - fieldset: SWICTLA - - name: SWILCKA + fieldset: Swictla + - name: swilcka description: Switch Lock A. byte_offset: 1560 - fieldset: SWILCKA - - name: WAKEUP + fieldset: Swilcka + - name: wakeup description: 'Array of registers: WAKEUPA.' array: len: 2 stride: 8 byte_offset: 1792 - block: WAKEUP - - name: WAKLCKA + block: Wakeup + - name: waklcka description: Wakeup Lock A. byte_offset: 2040 - fieldset: WAKLCKA -block/WAKEUP: + fieldset: Waklcka +block/Wakeup: description: 'Array of registers: WAKEUPA.' items: - - name: WAKEUPA + - name: wakeupa description: Wakeup 0 Register A. byte_offset: 0 - fieldset: WAKEUPA -fieldset/FROCFGA: + fieldset: Wakeupa +fieldset/Frocfga: description: FRO16K Configuration A. fields: - - name: FREQ_TRIM + - name: freq_trim description: Frequency Trim. bit_offset: 0 bit_size: 8 - - name: TEMP_TRIM + - name: temp_trim description: Temperature Trim. bit_offset: 8 bit_size: 4 -fieldset/FROCLKE: +fieldset/Froclke: description: FRO16K Clock Enable. fields: - - name: CLKE + - name: clke description: Clock Enable. bit_offset: 0 bit_size: 3 -fieldset/FROCTLA: +fieldset/Froctla: description: FRO16K Control A. fields: - - name: FRO_EN + - name: fro_en description: FRO16K Enable. bit_offset: 0 bit_size: 1 -fieldset/FROLCKA: +fieldset/Frolcka: description: FRO16K Lock A. fields: - - name: LOCK + - name: lock description: Lock. bit_offset: 0 bit_size: 1 -fieldset/FROTSTA: +fieldset/Frotsta: description: FRO16K Test A. fields: - - name: TSTMODE + - name: tstmode description: Test Mode. bit_offset: 0 bit_size: 1 -fieldset/IRQENA: +fieldset/Irqena: description: Interrupt Enable A. fields: - - name: POR_DET + - name: por_det description: POR Detect. bit_offset: 0 bit_size: 1 - enum: IRQENA_POR_DET - - name: WAKEUP_FLAG + - name: wakeup_flag description: Wakeup Pin Flag. bit_offset: 1 bit_size: 1 - enum: IRQENA_WAKEUP_FLAG - - name: TIMER0_FLAG + enum: IrqenaWakeupFlag + - name: timer0_flag description: Bandgap Timer 0. bit_offset: 2 bit_size: 1 - enum: IRQENA_TIMER0_FLAG - - name: TIMER1_FLAG + - name: timer1_flag description: Bandgap Timer 2. bit_offset: 3 bit_size: 1 - enum: IRQENA_TIMER1_FLAG - - name: LDO_RDY + - name: ldo_rdy description: LDO Ready. bit_offset: 4 bit_size: 1 - enum: IRQENA_LDO_RDY - - name: OSC_RDY + - name: osc_rdy description: OSC32k Ready. bit_offset: 5 bit_size: 1 - enum: IRQENA_OSC_RDY -fieldset/LDOCFGA: +fieldset/Ldocfga: description: LDO_RAM Configuration A. fields: - - name: LDO_TRIM + - name: ldo_trim description: LDO Voltage Trim. bit_offset: 0 bit_size: 5 - - name: BG_2X2_TRIM + - name: bg_2x2_trim description: Bandgap Trim. bit_offset: 5 bit_size: 3 - - name: BG_5X5_TRIM + - name: bg_5x5_trim description: Bandgap Trim. bit_offset: 8 bit_size: 2 - - name: REFRESH_TRIM + - name: refresh_trim description: Refresh Trim. bit_offset: 10 bit_size: 2 - enum: REFRESH_TRIM -fieldset/LDOCTLA: + enum: RefreshTrim +fieldset/Ldoctla: description: LDO_RAM Control A. fields: - - name: BG_EN + - name: bg_en description: Bandgap Enable. bit_offset: 0 bit_size: 1 - - name: LDO_EN + - name: ldo_en description: LDO Enable. bit_offset: 1 bit_size: 1 - - name: REFRESH_EN + - name: refresh_en description: Refresh Enable. bit_offset: 2 bit_size: 1 -fieldset/LDOLCKA: +fieldset/Ldolcka: description: LDO_RAM Lock A. fields: - - name: LOCK + - name: lock description: Lock. bit_offset: 0 bit_size: 1 -fieldset/LDORAMC: +fieldset/Ldoramc: description: RAM Control. fields: - - name: ISO + - name: iso description: Isolate SRAM. bit_offset: 0 bit_size: 1 - enum: ISO - - name: SWI + - name: swi description: Switch SRAM. bit_offset: 1 bit_size: 1 - enum: SWI - - name: RET0 + - name: ret0 description: Retention. bit_offset: 8 bit_size: 1 - enum: RET0 - - name: RET1 + - name: ret1 description: Retention. bit_offset: 9 bit_size: 1 - enum: RET1 - - name: RET2 + - name: ret2 description: Retention. bit_offset: 10 bit_size: 1 - enum: RET2 - - name: RET3 + - name: ret3 description: Retention. bit_offset: 11 bit_size: 1 - enum: RET3 -fieldset/LDOTIMER0: +fieldset/Ldotimer0: description: Bandgap Timer 0. fields: - - name: TIMCFG + - name: timcfg description: Timeout Configuration. bit_offset: 0 bit_size: 3 - enum: TIMCFG - - name: TIMEN + enum: Timcfg + - name: timen description: Bandgap Timeout Period Enable. bit_offset: 31 bit_size: 1 - enum: LDOTIMER0_TIMEN -fieldset/LDOTIMER1: +fieldset/Ldotimer1: description: Bandgap Timer 1. fields: - - name: TIMCFG + - name: timcfg description: Timeout Configuration. bit_offset: 0 bit_size: 24 - - name: TIMEN + - name: timen description: Bandgap Timeout Period Enable. bit_offset: 31 bit_size: 1 - enum: LDOTIMER1_TIMEN -fieldset/LDOTSTA: +fieldset/Ldotsta: description: LDO_RAM Test A. fields: - - name: TSTMODE + - name: tstmode description: Test Mode. bit_offset: 0 bit_size: 2 - - name: CONTROL + - name: control description: Spare Control. bit_offset: 2 bit_size: 4 - - name: DISCHG + - name: dischg description: Discharge Switch. bit_offset: 6 bit_size: 1 - - name: STATUS + - name: status description: Spare Status. bit_offset: 28 bit_size: 4 -fieldset/OSCCFGA: +fieldset/Osccfga: description: Oscillator Configuration A. fields: - - name: CMP_TRIM + - name: cmp_trim description: Comparator Trim. bit_offset: 0 bit_size: 2 - enum: CMP_TRIM - - name: CAP2_TRIM + enum: CmpTrim + - name: cap2_trim description: CAP2_TRIM. bit_offset: 2 bit_size: 1 - - name: DLY_TRIM + - name: dly_trim description: Delay Trim. bit_offset: 3 bit_size: 4 - enum: DLY_TRIM - - name: CAP_TRIM + enum: DlyTrim + - name: cap_trim description: Capacitor Trim. bit_offset: 7 bit_size: 2 - enum: CAP_TRIM - - name: INIT_TRIM + enum: CapTrim + - name: init_trim description: Initialization Trim. bit_offset: 9 bit_size: 3 - enum: INIT_TRIM -fieldset/OSCCLKE: + enum: InitTrim +fieldset/Oscclke: description: Oscillator Clock Enable. fields: - - name: CLKE + - name: clke description: Clock Enable. bit_offset: 0 bit_size: 3 -fieldset/OSCCTLA: +fieldset/Oscctla: description: Oscillator Control A. fields: - - name: OSC_EN + - name: osc_en description: Crystal Oscillator Enable. bit_offset: 0 bit_size: 1 - - name: OSC_BYP_EN + - name: osc_byp_en description: Crystal Oscillator Bypass Enable. bit_offset: 1 bit_size: 1 - enum: OSC_BYP_EN - - name: COARSE_AMP_GAIN + - name: coarse_amp_gain description: Amplifier Gain Coarse Adjustment. bit_offset: 2 bit_size: 2 - enum: COARSE_AMP_GAIN - - name: FINE_AMP_GAIN + enum: CoarseAmpGain + - name: fine_amp_gain description: Amplifier Gain Fine Adjustment. bit_offset: 4 bit_size: 2 - enum: FINE_AMP_GAIN - - name: HYST_SEL + enum: FineAmpGain + - name: hyst_sel description: Output Hysteresis Select. bit_offset: 6 bit_size: 1 - enum: HYST_SEL - - name: CAP_SEL_EN + - name: cap_sel_en description: Crystal Load Capacitance Selection Enable. bit_offset: 7 bit_size: 1 - - name: EXTAL_CAP_SEL + - name: extal_cap_sel description: Crystal Load Capacitance Selection. bit_offset: 8 bit_size: 4 - enum: EXTAL_CAP_SEL - - name: XTAL_CAP_SEL + enum: ExtalCapSel + - name: xtal_cap_sel description: Crystal Load Capacitance Selection. bit_offset: 12 bit_size: 4 - enum: XTAL_CAP_SEL - - name: MODE_EN + enum: XtalCapSel + - name: mode_en description: Mode Enable. bit_offset: 16 bit_size: 2 - enum: MODE_EN - - name: SUPPLY_DET + enum: ModeEn + - name: supply_det description: Supply Detector Trim. bit_offset: 18 bit_size: 2 - enum: SUPPLY_DET -fieldset/OSCLCKA: + enum: SupplyDet +fieldset/Osclcka: description: Oscillator Lock A. fields: - - name: LOCK + - name: lock description: Lock. bit_offset: 0 bit_size: 1 -fieldset/OSCTSTA: +fieldset/Osctsta: description: Oscillator Test A. fields: - - name: TSTMODE + - name: tstmode description: Test Mode. bit_offset: 0 bit_size: 5 - - name: SPARE + - name: spare description: Spare Control. bit_offset: 5 bit_size: 8 - - name: TSTOUT + - name: tstout description: Test Output. bit_offset: 31 bit_size: 1 -fieldset/STATUSA: +fieldset/Statusa: description: Status A. fields: - - name: POR_DET + - name: por_det description: POR Detect Flag. bit_offset: 0 bit_size: 1 - enum: STATUSA_POR_DET - - name: WAKEUP_FLAG + enum: StatusaPorDet + - name: wakeup_flag description: Wakeup Pin Flag. bit_offset: 1 bit_size: 1 - enum: STATUSA_WAKEUP_FLAG - - name: TIMER0_FLAG + enum: StatusaWakeupFlag + - name: timer0_flag description: Bandgap Timer 0 Flag. bit_offset: 2 bit_size: 1 - enum: STATUSA_TIMER0_FLAG - - name: TIMER1_FLAG + enum: StatusaTimer0Flag + - name: timer1_flag description: Bandgap Timer 1 Flag. bit_offset: 3 bit_size: 1 - enum: STATUSA_TIMER1_FLAG - - name: LDO_RDY + enum: StatusaTimer1Flag + - name: ldo_rdy description: LDO Ready. bit_offset: 4 bit_size: 1 - enum: STATUSA_LDO_RDY - - name: OSC_RDY + enum: StatusaLdoRdy + - name: osc_rdy description: OSC32k Ready. bit_offset: 5 bit_size: 1 - enum: STATUSA_OSC_RDY -fieldset/SWICTLA: + enum: StatusaOscRdy +fieldset/Swictla: description: Switch Control A. fields: - - name: SWI_EN + - name: swi_en description: Switch Enable. bit_offset: 0 bit_size: 1 - enum: SWI_EN - - name: LP_EN + - name: lp_en description: Low Power Enable. bit_offset: 1 bit_size: 1 - enum: LP_EN -fieldset/SWILCKA: +fieldset/Swilcka: description: Switch Lock A. fields: - - name: LOCK + - name: lock description: Lock. bit_offset: 0 bit_size: 1 - enum: SWILCKA_LOCK -fieldset/VERID: +fieldset/Verid: description: Version ID. fields: - - name: FEATURE + - name: feature description: Feature Specification Number. bit_offset: 0 bit_size: 16 - - name: MINOR + - name: minor description: Minor Version Number. bit_offset: 16 bit_size: 8 - - name: MAJOR + - name: major description: Major Version Number. bit_offset: 24 bit_size: 8 -fieldset/WAKECFG: +fieldset/Wakecfg: description: Wake-up Configuration. fields: - - name: OUT + - name: out description: Output. bit_offset: 0 bit_size: 1 - enum: OUT -fieldset/WAKENA: + enum: Out +fieldset/Wakena: description: Wake-up Enable A. fields: - - name: POR_DET + - name: por_det description: POR Detect. bit_offset: 0 bit_size: 1 - enum: WAKENA_POR_DET - - name: WAKEUP_FLAG + - name: wakeup_flag description: Wake-up Pin Flag. bit_offset: 1 bit_size: 1 - enum: WAKENA_WAKEUP_FLAG - - name: TIMER0_FLAG + enum: WakenaWakeupFlag + - name: timer0_flag description: Bandgap Timer 0. bit_offset: 2 bit_size: 1 - enum: WAKENA_TIMER0_FLAG - - name: TIMER1_FLAG + - name: timer1_flag description: Bandgap Timer 2. bit_offset: 3 bit_size: 1 - enum: WAKENA_TIMER1_FLAG - - name: LDO_RDY + - name: ldo_rdy description: LDO Ready. bit_offset: 4 bit_size: 1 - enum: WAKENA_LDO_RDY - - name: OSC_RDY + - name: osc_rdy description: OSC32K Ready. bit_offset: 5 bit_size: 1 - enum: WAKENA_OSC_RDY -fieldset/WAKEUPA: +fieldset/Wakeupa: description: Wakeup 0 Register A. fields: - - name: REG + - name: reg description: Register. bit_offset: 0 bit_size: 32 -fieldset/WAKLCKA: +fieldset/Waklcka: description: Wakeup Lock A. fields: - - name: LOCK + - name: lock description: Lock. bit_offset: 0 bit_size: 1 - enum: WAKLCKA_LOCK -enum/CAP_TRIM: +enum/CapTrim: bit_size: 2 variants: - - name: VAL0 + - name: Val0 description: Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ). value: 0 - - name: VAL1 + - name: Val1 description: -1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01). value: 1 - - name: VAL2 + - name: Val2 description: -2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10). value: 2 - - name: VAL3 + - name: Val3 description: -2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11). value: 3 -enum/CMP_TRIM: +enum/CmpTrim: bit_size: 2 variants: - - name: CMP_760 + - name: Cmp760 description: 760 mV. value: 0 - - name: CMP_770 + - name: Cmp770 description: 770 mV. value: 1 - - name: CMP_740 + - name: Cmp740 description: 740 mV. value: 3 -enum/COARSE_AMP_GAIN: +enum/CoarseAmpGain: bit_size: 2 variants: - - name: GAIN05 + - name: Gain05 description: ESR Range 0. value: 0 - - name: GAIN10 + - name: Gain10 description: ESR Range 1. value: 1 - - name: GAIN18 + - name: Gain18 description: ESR Range 2. value: 2 - - name: GAIN33 + - name: Gain33 description: ESR Range 3. value: 3 -enum/DLY_TRIM: +enum/DlyTrim: bit_size: 4 variants: - - name: DLY_9_6 + - name: Dly96 description: P current 9(nA) and N Current 6(nA). value: 0 - - name: DLY_13_6 + - name: Dly136 description: P current 13(nA) and N Current 6(nA). value: 1 - - name: DLY_4_6 + - name: Dly46 description: P current 4(nA) and N Current 6(nA). value: 3 - - name: DLY_9_4 + - name: Dly94 description: P current 9(nA) and N Current 4(nA). value: 4 - - name: DLY_13_4 + - name: Dly134 description: P current 13(nA) and N Current 4(nA). value: 5 - - name: DLY_4_4 + - name: Dly44 description: P current 4(nA) and N Current 4(nA). value: 7 - - name: DLY_9_2 + - name: Dly92 description: P current 9(nA) and N Current 2(nA). value: 8 - - name: DLY_13_2 + - name: Dly132 description: P current 13(nA) and N Current 2(nA). value: 9 - - name: DLY_4_2 + - name: Dly42 description: P current 4(nA) and N Current 2(nA). value: 11 -enum/EXTAL_CAP_SEL: +enum/ExtalCapSel: bit_size: 4 variants: - - name: SEL0 + - name: Sel0 description: 0 pF. value: 0 - - name: SEL2 + - name: Sel2 description: 2 pF. value: 1 - - name: SEL4 + - name: Sel4 description: 4 pF. value: 2 - - name: SEL6 + - name: Sel6 description: 6 pF. value: 3 - - name: SEL8 + - name: Sel8 description: 8 pF. value: 4 - - name: SEL10 + - name: Sel10 description: 10 pF. value: 5 - - name: SEL12 + - name: Sel12 description: 12 pF. value: 6 - - name: SEL14 + - name: Sel14 description: 14 pF. value: 7 - - name: SEL16 + - name: Sel16 description: 16 pF. value: 8 - - name: SEL18 + - name: Sel18 description: 18 pF. value: 9 - - name: SEL20 + - name: Sel20 description: 20 pF. value: 10 - - name: SEL22 + - name: Sel22 description: 22 pF. value: 11 - - name: SEL24 + - name: Sel24 description: 24 pF. value: 12 - - name: SEL26 + - name: Sel26 description: 26 pF. value: 13 - - name: SEL28 + - name: Sel28 description: 28 pF. value: 14 - - name: SEL30 + - name: Sel30 description: 30 pF. value: 15 -enum/FINE_AMP_GAIN: +enum/FineAmpGain: bit_size: 2 variants: - - name: AGC200 + - name: Agc200 description: 200 mV. value: 0 -enum/HYST_SEL: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/INIT_TRIM: +enum/InitTrim: bit_size: 3 variants: - - name: SEL0 + - name: Sel0 description: 8 s. value: 0 - - name: SEL1 + - name: Sel1 description: 4 s. value: 1 - - name: SEL2 + - name: Sel2 description: 2 s. value: 2 - - name: SEL3 + - name: Sel3 description: 1 s. value: 3 - - name: SEL4 + - name: Sel4 description: 0.5 s. value: 4 - - name: SEL5 + - name: Sel5 description: 0.25 s. value: 5 - - name: SEL6 + - name: Sel6 description: 0.125 s. value: 6 - - name: SEL7 + - name: Sel7 description: 0.5 ms. value: 7 -enum/IRQENA_LDO_RDY: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/IRQENA_OSC_RDY: +enum/IrqenaWakeupFlag: bit_size: 1 variants: - - name: DISABLE + - name: Clr description: Disable. value: 0 - - name: ENABLE + - name: Set description: Enable. value: 1 -enum/IRQENA_POR_DET: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/IRQENA_TIMER0_FLAG: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/IRQENA_TIMER1_FLAG: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/IRQENA_WAKEUP_FLAG: - bit_size: 1 - variants: - - name: CLR - description: Disable. - value: 0 - - name: SET - description: Enable. - value: 1 -enum/ISO: - bit_size: 1 - variants: - - name: DISABLE - description: State follows the chip power modes. - value: 0 - - name: ENABLE - description: Isolates SRAM and places it in Low-Power Retention mode. - value: 1 -enum/LDOTIMER0_TIMEN: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/LDOTIMER1_TIMEN: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/LP_EN: - bit_size: 1 - variants: - - name: DISABLE - description: VDD_BAT always supplies VBAT modules in low-power modes. - value: 0 - - name: ENABLE - description: VDD_SYS always supplies VBAT modules if SWI_EN is also 1. - value: 1 -enum/MODE_EN: +enum/ModeEn: bit_size: 2 variants: - - name: HP + - name: Hp description: Normal mode. value: 0 - - name: LP + - name: Lp description: Startup mode. value: 1 - - name: SW + - name: Sw description: Low power mode. value: 3 -enum/OSC_BYP_EN: +enum/Out: bit_size: 1 variants: - - name: DISABLE - description: Does not bypass. - value: 0 - - name: ENABLE - description: Bypass. - value: 1 -enum/OUT: - bit_size: 1 - variants: - - name: ON + - name: On description: Logic zero (asserted). value: 0 - - name: OFF + - name: Off description: Logic one. value: 1 -enum/REFRESH_TRIM: +enum/RefreshTrim: bit_size: 2 variants: - - name: SEL7 + - name: Sel7 description: Refresh every 7.8125 ms. value: 0 - - name: SEL15 + - name: Sel15 description: Refresh every 15.625 ms. value: 1 - - name: SEL31 + - name: Sel31 description: Refresh every 31.25 ms. value: 2 - - name: SEL62 + - name: Sel62 description: Refresh every 62.5 ms. value: 3 -enum/RET0: - bit_size: 1 - variants: - - name: DISABLE - description: Corresponding SRAM array is retained in low-power modes. - value: 0 - - name: ENABLE - description: Corresponding SRAM array is not retained in low-power modes. - value: 1 -enum/RET1: - bit_size: 1 - variants: - - name: DISABLE - description: Corresponding SRAM array is retained in low-power modes. - value: 0 - - name: ENABLE - description: Corresponding SRAM array is not retained in low-power modes. - value: 1 -enum/RET2: - bit_size: 1 - variants: - - name: DISABLE - description: Corresponding SRAM array is retained in low-power modes. - value: 0 - - name: ENABLE - description: Corresponding SRAM array is not retained in low-power modes. - value: 1 -enum/RET3: - bit_size: 1 - variants: - - name: DISABLE - description: Corresponding SRAM array is retained in low-power modes. - value: 0 - - name: ENABLE - description: Corresponding SRAM array is not retained in low-power modes. - value: 1 -enum/STATUSA_LDO_RDY: +enum/StatusaLdoRdy: bit_size: 1 variants: - - name: CLR + - name: Clr description: Disabled (not ready). value: 0 - - name: SET + - name: Set description: Enabled (ready). value: 1 -enum/STATUSA_OSC_RDY: +enum/StatusaOscRdy: bit_size: 1 variants: - - name: CLR + - name: Clr description: Disabled (clock not ready). value: 0 - - name: SET + - name: Set description: Enabled (clock ready). value: 1 -enum/STATUSA_POR_DET: +enum/StatusaPorDet: bit_size: 1 variants: - - name: CLR + - name: Clr description: Not reset. value: 0 - - name: SET + - name: Set description: Reset. value: 1 -enum/STATUSA_TIMER0_FLAG: +enum/StatusaTimer0Flag: bit_size: 1 variants: - - name: CLR + - name: Clr description: Not reached. value: 0 - - name: SET + - name: Set description: Reached. value: 1 -enum/STATUSA_TIMER1_FLAG: +enum/StatusaTimer1Flag: bit_size: 1 variants: - - name: CLR + - name: Clr description: Not reached. value: 0 - - name: SET + - name: Set description: Reached. value: 1 -enum/STATUSA_WAKEUP_FLAG: +enum/StatusaWakeupFlag: bit_size: 1 variants: - - name: CLR + - name: Clr description: Not asserted. value: 0 - - name: SET + - name: Set description: Asserted. value: 1 -enum/SUPPLY_DET: +enum/SupplyDet: bit_size: 2 variants: - - name: L3VSUPPLY + - name: L3vsupply description: VBAT supply is less than 3V. value: 0 - - name: G3VSUPPLY + - name: G3vsupply description: VBAT supply is greater than 3V. value: 1 -enum/SWI: - bit_size: 1 - variants: - - name: DISABLE - description: Supply follows the chip power modes. - value: 0 - - name: ENABLE - description: LDO_RAM powers the array. - value: 1 -enum/SWILCKA_LOCK: - bit_size: 1 - variants: - - name: DISABLE - description: Do not block. - value: 0 - - name: ENABLE - description: Block. - value: 1 -enum/SWI_EN: - bit_size: 1 - variants: - - name: DISABLE - description: VDD_BAT. - value: 0 - - name: ENABLE - description: VDD_SYS. - value: 1 -enum/TIMCFG: +enum/Timcfg: bit_size: 3 variants: - - name: CFG1000 + - name: Cfg1000 description: 1 s. value: 0 - - name: CFG500 + - name: Cfg500 description: 500 ms. value: 1 - - name: CFG250 + - name: Cfg250 description: 250 ms. value: 2 - - name: CFG125 + - name: Cfg125 description: 125 ms. value: 3 - - name: CFG62 + - name: Cfg62 description: 62.5 ms. value: 4 - - name: CFG31 + - name: Cfg31 description: 31.25 ms. value: 5 - - name: CFG15 + - name: Cfg15 description: 15.625 ms. value: 6 - - name: CFG7 + - name: Cfg7 description: 7.8125 ms. value: 7 -enum/WAKENA_LDO_RDY: +enum/WakenaWakeupFlag: bit_size: 1 variants: - - name: DISABLE + - name: Clr description: Disable. value: 0 - - name: ENABLE + - name: Set description: Enable. value: 1 -enum/WAKENA_OSC_RDY: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/WAKENA_POR_DET: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/WAKENA_TIMER0_FLAG: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/WAKENA_TIMER1_FLAG: - bit_size: 1 - variants: - - name: DISABLE - description: Disable. - value: 0 - - name: ENABLE - description: Enable. - value: 1 -enum/WAKENA_WAKEUP_FLAG: - bit_size: 1 - variants: - - name: CLR - description: Disable. - value: 0 - - name: SET - description: Enable. - value: 1 -enum/WAKLCKA_LOCK: - bit_size: 1 - variants: - - name: DISABLE - description: Lock is disabled. - value: 0 - - name: ENABLE - description: Lock is enabled. - value: 1 -enum/XTAL_CAP_SEL: +enum/XtalCapSel: bit_size: 4 variants: - - name: SEL0 + - name: Sel0 description: 0 pF. value: 0 - - name: SEL2 + - name: Sel2 description: 2 pF. value: 1 - - name: SEL4 + - name: Sel4 description: 4 pF. value: 2 - - name: SEL6 + - name: Sel6 description: 6 pF. value: 3 - - name: SEL8 + - name: Sel8 description: 8 pF. value: 4 - - name: SEL10 + - name: Sel10 description: 10 pF. value: 5 - - name: SEL12 + - name: Sel12 description: 12 pF. value: 6 - - name: SEL14 + - name: Sel14 description: 14 pF. value: 7 - - name: SEL16 + - name: Sel16 description: 16 pF. value: 8 - - name: SEL18 + - name: Sel18 description: 18 pF. value: 9 - - name: SEL20 + - name: Sel20 description: 20 pF. value: 10 - - name: SEL22 + - name: Sel22 description: 22 pF. value: 11 - - name: SEL24 + - name: Sel24 description: 24 pF. value: 12 - - name: SEL26 + - name: Sel26 description: 26 pF. value: 13 - - name: SEL28 + - name: Sel28 description: 28 pF. value: 14 - - name: SEL30 + - name: Sel30 description: 30 pF. value: 15 diff --git a/data/metadata/peripherals/mcxa/WWDT.yaml b/data/metadata/peripherals/mcxa/WWDT.yaml index 17935af..f40b885 100644 --- a/data/metadata/peripherals/mcxa/WWDT.yaml +++ b/data/metadata/peripherals/mcxa/WWDT.yaml @@ -64,6 +64,10 @@ fieldset/Mod: description: Lock. bit_offset: 5 bit_size: 1 + - name: debug_en + description: Debug Enable. + bit_offset: 6 + bit_size: 1 fieldset/Tc: description: Timer Constant. fields: @@ -95,27 +99,27 @@ fieldset/Window: enum/Wden: bit_size: 1 variants: - - name: STOP + - name: Stop description: Timer stopped. value: 0 - - name: RUN + - name: Run description: Timer running. value: 1 enum/Wdprotect: bit_size: 1 variants: - - name: FLEXIBLE + - name: Flexible description: Flexible. value: 0 - - name: THRESHOLD + - name: Threshold description: Threshold. value: 1 enum/Wdreset: bit_size: 1 variants: - - name: INTERRUPT + - name: Interrupt description: Interrupt. value: 0 - - name: RESET + - name: Reset description: Reset. value: 1 diff --git a/data/metadata/peripherals/update.sh b/data/metadata/peripherals/update.sh new file mode 100755 index 0000000..524d29f --- /dev/null +++ b/data/metadata/peripherals/update.sh @@ -0,0 +1,57 @@ +#!/bin/bash + +set -euxo pipefail + +# This script updates all the peripheral files from source SVDs, +# after applying the relevant transforms. + +# The peripheral description files should still be considered the 'source-of-truth', +# but this script allows for easy updating / checking if anything relevant has changed +# when updating the SVDs. + +CURRENT_DIR="$( dirname -- "${BASH_SOURCE[0]}" )" + +pushd $CURRENT_DIR/../../../ +cargo run -p generator -- extract MCXA256 +cargo run -p generator -- extract MCXA577 +popd + +pushd $CURRENT_DIR + +# Manually curated, do not change +# cp raw/MCXA577/DMA.yaml mcxa/DMA.yaml +# cp raw/MCXA577/EDMA_TCD.yaml mcxa/EDMA_TCD.yaml + +cp raw/MCXA256/FLEXPWM.yaml mcxa/FLEXPWM.yaml +cp raw/MCXA256/SPC.yaml mcxa/SPC.yaml + +cp raw/MCXA577/ADC.yaml mcxa/ADC.yaml +cp raw/MCXA577/AHBSC.yaml mcxa/AHBSC.yaml +cp raw/MCXA577/CDOG.yaml mcxa/CDOG.yaml +cp raw/MCXA577/CMC.yaml mcxa/CMC.yaml +cp raw/MCXA577/CRC.yaml mcxa/CRC.yaml +cp raw/MCXA577/CTIMER.yaml mcxa/CTIMER.yaml +cp raw/MCXA577/FMU.yaml mcxa/FMU.yaml +cp raw/MCXA577/GPIO.yaml mcxa/GPIO.yaml +cp raw/MCXA577/I3C.yaml mcxa/I3C.yaml +cp raw/MCXA577/INPUTMUX.yaml mcxa/INPUTMUX.yaml +cp raw/MCXA577/LPI2C.yaml mcxa/LPI2C.yaml +cp raw/MCXA577/LPSPI.yaml mcxa/LPSPI.yaml +cp raw/MCXA577/LPUART.yaml mcxa/LPUART.yaml +cp raw/MCXA577/MBC.yaml mcxa/MBC.yaml +cp raw/MCXA577/OSTIMER.yaml mcxa/OSTIMER.yaml +cp raw/MCXA577/PORT.yaml mcxa/PORT.yaml +cp raw/MCXA577/SCG.yaml mcxa/SCG.yaml +cp raw/MCXA577/SGI.yaml mcxa/SGI.yaml +cp raw/MCXA577/TRNG.yaml mcxa/TRNG.yaml +cp raw/MCXA577/VBAT.yaml mcxa/VBAT.yaml +cp raw/MCXA577/WWDT.yaml mcxa/WWDT.yaml + +cp raw/MCXA256/RTC.yaml mcxa/RTC2xx.yaml +cp raw/MCXA577/RTC.yaml mcxa/RTC5xx.yaml + +cp raw/MCXA256/MRCC.yaml mcxa/MRCC2xx.yaml +cp raw/MCXA577/MRCC.yaml mcxa/MRCC5xx.yaml + +cp raw/MCXA256/SYSCON.yaml mcxa/SYSCON2xx.yaml +cp raw/MCXA577/SYSCON.yaml mcxa/SYSCON5xx.yaml diff --git a/data/transforms/mcxa/cmc.yaml b/data/transforms/mcxa/cmc.yaml new file mode 100644 index 0000000..b3789a0 --- /dev/null +++ b/data/transforms/mcxa/cmc.yaml @@ -0,0 +1,14 @@ +transforms: + - !MakeFieldArray + fieldsets: cmc::Sramdis0 + from: dis\d+ + to: dis + + - !MakeFieldArray + fieldsets: cmc::Sramret0 + from: ret\d+ + to: ret + + - !MergeEnums + from: cmc::.+Ckmode + to: cmc::Ckmode diff --git a/data/transforms/mcxa/ctimer.yaml b/data/transforms/mcxa/ctimer.yaml index 6da779c..8cdef20 100644 --- a/data/transforms/mcxa/ctimer.yaml +++ b/data/transforms/mcxa/ctimer.yaml @@ -1,49 +1,29 @@ transforms: + # Fix badly OCR'd typo - !RenameEnumVariants - enum: ctimer::([A-Za-z]+)(\d+)(.+) - from: ([A-Z]+)[0-9O]([A-Z]+)_([0-9]) - to: $1$2$3 + enum: ctimer::Mr[0-9](.+) + from: Mris([0-9]) + to: Mr1S$1 - !RenameEnumVariants - enum: ctimer::Mr[0-9]s - from: ([A-Z_]+)([0-9]) - to: MRS$2 + enum: ctimer::Mr[0-9](.+) + from: Mr[0-9]([A-Za-z_]+[0-9]) + to: Mr$1 - - !MergeEnums - from: ctimer::Cap(\d+)(.+) - to: ctimer::Cap$2 - skip_unmergeable: false + - !DeleteEnums + from: ctimer::Cap\d+(.+) - - !MergeEnums - from: ctimer::Em(\d+) - to: ctimer::Em - skip_unmergeable: false + - !DeleteEnums + from: ctimer::Mr.+ + + - !DeleteEnums + from: ctimer::Em\d+ - !MergeEnums from: ctimer::Emc(\d+) to: ctimer::Emc skip_unmergeable: false - - !MergeEnums - from: ctimer::Mr(\d+)i - to: ctimer::Mri - skip_unmergeable: false - - - !MergeEnums - from: ctimer::Mr(\d+)r - to: ctimer::Mrr - skip_unmergeable: false - - - !MergeEnums - from: ctimer::Mr(\d+)rl - to: ctimer::Mrrl - skip_unmergeable: false - - - !MergeEnums - from: ctimer::Mr(\d+)s - to: ctimer::Mrs - skip_unmergeable: false - - !MergeEnums from: ctimer::Pwmen(\d+) to: ctimer::Pwmen diff --git a/data/transforms/mcxa/dma.yaml b/data/transforms/mcxa/dma.yaml index 41591c8..b6af527 100644 --- a/data/transforms/mcxa/dma.yaml +++ b/data/transforms/mcxa/dma.yaml @@ -1,3 +1,5 @@ +# Note: MCXA5xx DMA instances differ quite a bit. + transforms: - !RenamePeripherals from: EDMA0_TCD0 diff --git a/data/transforms/mcxa/flexpwm.yaml b/data/transforms/mcxa/flexpwm.yaml index bcd95a5..059a7c8 100644 --- a/data/transforms/mcxa/flexpwm.yaml +++ b/data/transforms/mcxa/flexpwm.yaml @@ -2,13 +2,13 @@ transforms: # Fix names of sm*sel(23|45) enum variants such that they overlap - !RenameEnumVariants enum: flexpwm::Sm\d+sel\d+ - from: (.*)SM\d+(PWM|OUT)\d+ + from: (.*)Sm\d+(pwm|out)\d+ to: $1$2 - !RenameEnumVariants enum: flexpwm::Sm\d+sel\d+ - from: PWM\d+_EXTA - to: PWM_EXTA + from: Pwm\d+Exta + to: PwmExta - !MergeEnums from: flexpwm::Sm\d(.+) diff --git a/data/transforms/mcxa/gpio.yaml b/data/transforms/mcxa/gpio.yaml index cde55e7..310a70d 100644 --- a/data/transforms/mcxa/gpio.yaml +++ b/data/transforms/mcxa/gpio.yaml @@ -11,7 +11,10 @@ transforms: type: All - !DeleteEnums - from: gpio::(Ptto|Pdi|Pdo)(\d+) + from: gpio::(Ptto|Pdi|Pdo|Giwe|Isf)(\d+) + + - !DeleteEnums + from: gpio::(Feature|Icnp|Icns|Pcnp|Pcns) - !MergeEnums from: gpio::(Pdd|Pid|Ptso|Ptco)(\d+) @@ -60,3 +63,18 @@ transforms: - !MergeFieldsets from: gpio::Isfr\d to: gpio::Isfr + + - !MakeFieldArray + fieldsets: gpio::Pcnp + from: npe(\d+) + to: npe + + - !MakeFieldArray + fieldsets: gpio::Pcns + from: nse(\d+) + to: nse + + - !MakeFieldArray + fieldsets: gpio::Gic(h|l)r + from: giwe(\d+) + to: giwe diff --git a/data/transforms/mcxa/i3c.yaml b/data/transforms/mcxa/i3c.yaml index 606cd6f..7b80484 100644 --- a/data/transforms/mcxa/i3c.yaml +++ b/data/transforms/mcxa/i3c.yaml @@ -1,9 +1,17 @@ transforms: + # Merge any i3c peripherals, and allow overlapping registers + - !MergeBlocks + from: i3c\d+::I3c\d+ + to: i3c::I3c + main: i3c::I3c + check: NoCheck + + # Delete enums that could be bools. - !DeleteEnums - from: i3c0::Mintclr(.+) + from: i3c\d*::Mintclr(.+) - !DeleteEnums - from: i3c0::(.+)Flush(f|t)b + from: i3c\d*::(.+)Flush(f|t)b - !DeleteEnums - from: i3c0::Mstatus(Txnotfull|Rxpend) + from: i3c\d*::Mstatus(Txnotfull|Rxpend) diff --git a/data/transforms/mcxa/inputmux.yaml b/data/transforms/mcxa/inputmux.yaml index d6d102b..01bb168 100644 --- a/data/transforms/mcxa/inputmux.yaml +++ b/data/transforms/mcxa/inputmux.yaml @@ -1,7 +1,8 @@ transforms: - !MergeEnums - from: inputmux0::(.+)(\d+)(TrigTrigin|InputInp|TrigInp|Inp)$ + from: inputmux0::(.+)(\d+)(TrigTrigin|TrigInp|trigInp|InputInp|Inp) to: inputmux0::$1$3 + skip_unmergeable: true - !MergeEnums from: inputmux0::TrigIn(\d+)Val @@ -16,7 +17,7 @@ transforms: to: inputmux0::Qdc${2}Inp - !MergeFieldsets - from: inputmux0::([^\d]+|Lpi2c)(\d+)(Trig|Input|)$ + from: inputmux0::(Lpi2c|Lpuart|Lpspi|Cmp|Adc|Dac)(\d*)(Trig|Input|)$ to: inputmux0::$1$3 - !MergeFieldsets diff --git a/data/transforms/mcxa/mbc.yaml b/data/transforms/mcxa/mbc.yaml index eb480b7..0e3adbf 100644 --- a/data/transforms/mcxa/mbc.yaml +++ b/data/transforms/mcxa/mbc.yaml @@ -16,7 +16,7 @@ transforms: to: mbc0::$1 - !MergeFieldsets - from: mbc0::Dom0Mem(\d+)BlkCfgW(\d+) + from: mbc0::Mem(\d+)BlkCfgW(\d+) to: mbc0::MemnBlkCfgW - !MakeRegisterArray diff --git a/data/transforms/mcxa/mcxa5/ahbsc.yaml b/data/transforms/mcxa/mcxa5/ahbsc.yaml index 64881b6..c8c7858 100644 --- a/data/transforms/mcxa/mcxa5/ahbsc.yaml +++ b/data/transforms/mcxa/mcxa5/ahbsc.yaml @@ -1,4 +1,12 @@ transforms: + - !Rename + from: secure_ahb_ctrl::(.+) + to: ahbsc::$1 + + - !Rename + from: ahbsc::SecureAhbCtrl + to: ahbsc::Ahbsc + # Temporarily move everything that is not a Rule someplace else - !Rename from: ahbsc::(Lock.+|Master.+|MiscCtrl.+|SecVio.+) @@ -26,7 +34,7 @@ transforms: to: ahbsc::MiscCtrlEnable - !MakeFieldArray - fieldsets: ahbsc::(.+MemRule|AhbSecureCtrlMemRule0) + fieldsets: ahbsc::(.+MemRule|AhbSecureCtrlMemRule0|AhbSecureCtrlPeripheralRule0|AhbSlavePortP\d+SlaveRule|AonDomainSramMemRule0|Flash\d+MemRule0|RamxMemRule0) from: rule(\d+) to: rule @@ -39,10 +47,28 @@ transforms: from: dma[01]_ipd_req_\d+ to: dma_ipd_req + # sec_gp_reg8 is wrong; and 9 is missing from SVD + - !DeleteRegisters + block: ahbsc::Ahbsc + from: sec_gp_reg8 + + - !DeleteFieldsets + from: ahbsc::SecGpReg8 + - !MergeFieldsets from: ahbsc::SecGpReg\d+ to: ahbsc::SecGpReg + - !AddRegisters + block: ahbsc::Ahbsc + registers: + - name: sec_gp_reg8 + byte_offset: 0xfa0 + fieldset: ahbsc::SecGpReg + - name: sec_gp_reg9 + byte_offset: 0xfa4 + fieldset: ahbsc::SecGpReg + - !MakeRegisterArray blocks: ahbsc::Ahbsc from: sec_gp_reg\d+ diff --git a/data/transforms/mcxa/mcxa5/i3c.yaml b/data/transforms/mcxa/mcxa5/i3c.yaml index 31a013e..fab4f8c 100644 --- a/data/transforms/mcxa/mcxa5/i3c.yaml +++ b/data/transforms/mcxa/mcxa5/i3c.yaml @@ -1,14 +1,20 @@ transforms: - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mconfig - fieldset: i3c::Mconfig + # Pick I3C Type variant (I3C1 has extra Variant:3 BT) + - !ModifyFieldsEnum + fieldset: i3c1::Mctrl + field: type_ + enum: i3c::Type - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mconfig_ext - fieldset: i3c::MconfigExt + # Delete unused Type enum + - !Delete + from: i3c1::Type + type: Enum + - !MergeEnums + from: i3c1?::(.*) + to: i3c::$1 + + # Select (less capable) I3C (without 1) variants - !ModifyRegisters blocks: i3c1::I3c1 registers: sconfig @@ -16,78 +22,8 @@ transforms: - !ModifyRegisters blocks: i3c1::I3c1 - registers: sstatus - fieldset: i3c::Sstatus - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sctrl - fieldset: i3c::Sctrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sintset - fieldset: i3c::Sintset - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sintclr - fieldset: i3c::Sintclr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sintmasked - fieldset: i3c::Sintmasked - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: serrwarn - fieldset: i3c::Serrwarn - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sdmactrl - fieldset: i3c::Sdmactrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sdatactrl - fieldset: i3c::Sdatactrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: swdatab - fieldset: i3c::Swdatab - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: swdatabe - fieldset: i3c::Swdatabe - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: swdatah - fieldset: i3c::Swdatah - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: swdatahe - fieldset: i3c::Swdatahe - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: srdatab - fieldset: i3c::Srdatab - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: srdatah - fieldset: i3c::Srdatah - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: swdatab1 - fieldset: i3c::Swdatab1 + registers: merrwarn + fieldset: i3c::Merrwarn - !ModifyRegisters blocks: i3c1::I3c1 @@ -101,193 +37,13 @@ transforms: - !ModifyRegisters blocks: i3c1::I3c1 - registers: smaxlimits - fieldset: i3c::Smaxlimits - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sidpartno - fieldset: i3c::Sidpartno - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sidext - fieldset: i3c::Sidext - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: svendorid - fieldset: i3c::Svendorid - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: stcclock - fieldset: i3c::Stcclock - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: smsgmapaddr - fieldset: i3c::Smsgmapaddr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mctrl - fieldset: i3c::Mctrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mstatus - fieldset: i3c::Mstatus - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mibirules - fieldset: i3c::Mibirules - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mintset - fieldset: i3c::Mintset - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mintclr - fieldset: i3c::Mintclr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mintmasked - fieldset: i3c::Mintmasked - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: merrwarn - fieldset: i3c::Merrwarn - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mdmactrl - fieldset: i3c::Mdmactrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwdatab - fieldset: i3c::Mwdatab - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwdatabe - fieldset: i3c::Mwdatabe - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwdatah - fieldset: i3c::Mwdatah - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwdatahe - fieldset: i3c::Mwdatahe - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mrdatab - fieldset: i3c::Mrdatab - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mrdatah - fieldset: i3c::Mrdatah - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwdatab1 - fieldset: i3c::Mwdatab1 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mdatactrl - fieldset: i3c::Mdatactrl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwmsg_sdr_control - fieldset: i3c::MwmsgSdrControl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwmsg_sdr_data - fieldset: i3c::MwmsgSdrData - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mrmsg_sdr - fieldset: i3c::MrmsgSdr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mrmsg_ddr - fieldset: i3c::MrmsgDdr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwmsg_ddr_control - fieldset: i3c::MwmsgDdrControl - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwmsg_ddr_control2 - fieldset: i3c::MwmsgDdrControl2 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mwmsg_ddr_data - fieldset: i3c::MwmsgDdrData - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: mdynaddr - fieldset: i3c::Mdynaddr - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: smapctrl0 - fieldset: i3c::Smapctrl0 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: smapctrl1 - fieldset: i3c::Smapctrl1 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: ibiext1 - fieldset: i3c::Ibiext1 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: ibiext2 - fieldset: i3c::Ibiext2 - - - !ModifyRegisters - blocks: i3c1::I3c1 - registers: sid - fieldset: i3c::Sid - - - !MergeBlocks - from: i3c1::I3c1 - to: i3c::I3c - main: i3c::I3c + registers: serrwarn + fieldset: i3c::Serrwarn - !Delete - from: i3c1::(.+) - type: All - - - !DeleteEnums - from: i3c::Mintclr(.+) + from: i3c1::(Merrwarn|Sconfig|Scapabilities|Scapabilities2|Serrwarn) - - !DeleteEnums - from: i3c::(.+)Flush(f|t)b + - !MergeFieldsets + from: i3c1?::(.*) + to: i3c::$1 - - !DeleteEnums - from: i3c::Mstatus(Txnotfull|Rxpend) diff --git a/data/transforms/mcxa/mcxa5/scg.yaml b/data/transforms/mcxa/mcxa5/scg.yaml new file mode 100644 index 0000000..aaf4185 --- /dev/null +++ b/data/transforms/mcxa/mcxa5/scg.yaml @@ -0,0 +1,36 @@ +transforms: + - !RenameFields + fieldset: scg0::Firccfg + from: range + to: freq_sel + + - !Rename + from: scg0::SosccfgRange + to: scg0::Range + type: Enum + + - !Rename + from: scg0::SpllctrlSource + to: scg0::Source + type: Enum + + - !Rename + from: scg0::FirccfgRange + to: scg0::FreqSel + type: Enum + + - !DeleteEnumVariants + enum: scg0::Source + from: .* + + - !AddEnumVariants + enum: scg0::Source + variants: + - { name: Sosc, value: 0, description: "SOSC" } + - { + name: Firc, + value: 1, + description: "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock.", + } + - { name: Rosc, value: 2, description: "ROSC" } + - { name: Sirc, value: 3, description: "SIRC 12 MHz clock" } diff --git a/data/transforms/mcxa/mcxa5/trng.yaml b/data/transforms/mcxa/mcxa5/trng.yaml new file mode 100644 index 0000000..e9179c5 --- /dev/null +++ b/data/transforms/mcxa/mcxa5/trng.yaml @@ -0,0 +1,24 @@ +transforms: + - !AddFields + fieldset: trng0::IntMask + fields: + - name: intg_flt + description: Mask the INTG_FLT interrupt + bit_offset: 3 + bit_size: 1 + + - !AddFields + fieldset: trng0::IntCtrl + fields: + - name: intg_flt + description: Clear the INTG_FLT interrupt + bit_offset: 3 + bit_size: 1 + + - !AddFields + fieldset: trng0::IntStatus + fields: + - name: intg_flt + description: Integrity Fault. An internal fault has occurred. + bit_offset: 3 + bit_size: 1 diff --git a/data/transforms/mcxa/mrcc.yaml b/data/transforms/mcxa/mrcc.yaml index fb6f376..dffb4c1 100644 --- a/data/transforms/mcxa/mrcc.yaml +++ b/data/transforms/mcxa/mrcc.yaml @@ -1,4 +1,8 @@ transforms: + - !Rename + from: mrcc0::Mrcc0 + to: mrcc0::Mrcc + - !MergeEnums from: mrcc0::Mrcc(.+)(\d+)(.+) to: mrcc0::Mrcc$3 @@ -9,14 +13,18 @@ transforms: from: mrcc0::Mrcc(.+)(\d+)(.+) to: mrcc0::Mrcc$1$3 - - !MergeEnums - from: mrcc0::Mrcc(.*)(\d*)(ClkdivReset|ClkdivHalt|ClkdivUnstab) - to: mrcc0::Mrcc$3 + - !MergeFieldsets + from: mrcc0::Mrcc(.+)(\d+)(.+) + to: mrcc0::Mrcc$1$3 + - !MergeEnums + from: mrcc0::Mrcc(.*)Clkdiv(Reset|Halt|Unstab)? + to: mrcc0::MrccClkdiv$2 + + - !MergeFieldsets + from: mrcc0::Mrcc.+Clkdiv + to: mrcc0::MrccClkdiv + - !Rename from: mrcc0::Mrcc(.+) to: mrcc0::$1 - - - !MergeFieldsets - from: mrcc0::Mrcc(.+)(\d+)(.+) - to: mrcc0::$1$3 diff --git a/data/transforms/mcxa/port.yaml b/data/transforms/mcxa/port.yaml index 85c958c..3bad428 100644 --- a/data/transforms/mcxa/port.yaml +++ b/data/transforms/mcxa/port.yaml @@ -6,13 +6,63 @@ transforms: to: port::Pcr - !ModifyRegisters - blocks: port\d+::Port(\d+) + blocks: port\d+::Port\d* registers: pcr\d+ fieldset: port::Pcr - !DeleteFieldsets from: port\d+::Pcr\d+ + # Merge all Mux into the most capable variant of it with bitsize = 4. + # In the HAL we will enforce this constraint, but for the PAC this only makes the types more complex. + - !DeleteEnums + from: port\d+::Pcr(\d+)Mux + bit_size: 1 + - !DeleteEnums + from: port\d+::Pcr(\d+)Mux + bit_size: 2 + - !DeleteEnums + from: port\d+::Pcr(\d+)Mux + bit_size: 3 + - !MergeEnums + from: port\d+::Pcr(\d+)Mux + to: port::Mux + + - !DeleteEnumVariants + enum: port::Mux + from: .* + + - !AddEnumVariants + enum: port::Mux + variants: + - { name: Mux0, value: 0 } + - { name: Mux1, value: 1 } + - { name: Mux2, value: 2 } + - { name: Mux3, value: 3 } + - { name: Mux4, value: 4 } + - { name: Mux5, value: 5 } + - { name: Mux6, value: 6 } + - { name: Mux7, value: 7 } + - { name: Mux8, value: 8 } + - { name: Mux9, value: 9 } + - { name: Mux10, value: 10 } + - { name: Mux11, value: 11 } + - { name: Mux12, value: 12 } + - { name: Mux13, value: 13 } + + - !MergeEnums + from: port\d+::(.+) + to: port::$1 + + - !MergeFieldsets + from: port\d+::(.+) + to: port::$1 + + # For now, delete half-supported drive-strength + - !DeleteRegisters + block: port\d+::Port\d* + from: calib\d+ + # Roughly merge all port blocks together. - !MergeBlocks from: port\d*::Port\d* @@ -30,38 +80,6 @@ transforms: to: port::Port type: Block - # Merge all Mux into the most capable variant of it with bitsize = 4. - # Pcr 0, 1 and 7 have a smaller Mux set for ports 0 and 4. - # In the HAL we will enforce this constraint, but for the PAC this only makes the types more complex. - - !DeleteEnums - from: port::Pcr(\d+)Mux - bit_size: 3 - - !MergeEnums - from: port::Pcr(\d+)Mux - to: port::Mux - - - !DeleteEnumVariants - enum: port::Mux - from: .* - - - !AddEnumVariants - enum: port::Mux - variants: - - { name: MUX0, value: 0 } - - { name: MUX1, value: 1 } - - { name: MUX2, value: 2 } - - { name: MUX3, value: 3 } - - { name: MUX4, value: 4 } - - { name: MUX5, value: 5 } - - { name: MUX6, value: 6 } - - { name: MUX7, value: 7 } - - { name: MUX8, value: 8 } - - { name: MUX9, value: 9 } - - { name: MUX10, value: 10 } - - { name: MUX11, value: 11 } - - { name: MUX12, value: 12 } - - { name: MUX13, value: 13 } - - !MergeEnums from: port::Gpwe\d+ to: port::Gpwe @@ -81,10 +99,6 @@ transforms: from: port::Pcr(\d+)(.+) to: port::$2 - - !MergeFieldsets - from: port::Pcr(\d+) - to: port::Pcr - - !MakeRegisterArray blocks: port::Port from: pcr(\d+) diff --git a/data/transforms/mcxa/rtc.yaml b/data/transforms/mcxa/rtc.yaml index 809ae87..9359ff8 100644 --- a/data/transforms/mcxa/rtc.yaml +++ b/data/transforms/mcxa/rtc.yaml @@ -1,3 +1,3 @@ transforms: - !DeleteEnums - from: rtc0::(Tce|Tiie|Toie|Taie|Tsie|Taf|Tif|Tof) + from: rtc0::(Tce|Tiie|Toie|Taie|Tsie|Taf|Tif|Tof|Tcr) diff --git a/data/transforms/mcxa/scg.yaml b/data/transforms/mcxa/scg.yaml index dd173d8..2b99208 100644 --- a/data/transforms/mcxa/scg.yaml +++ b/data/transforms/mcxa/scg.yaml @@ -2,3 +2,23 @@ transforms: - !MergeEnums from: scg0::(Rccr|Csr)Scs to: scg0::Scs + + # MCXA256 uses different ranges than MCXA577 + # Furthermore, MCXA577 SVD does not match data sheet + # For now, fill variants with both frequency sets + # TODO: use metapac clock tree to generate this + - !DeleteEnumVariants + enum: scg0::FreqSel + from: .* + + - !ResizeEnums + enum: scg0::FreqSel + bit_size: 4 + + - !AddEnumVariants + enum: scg0::FreqSel + variants: + - { name: Firc45_48mhz, value: 1 } + - { name: Firc60_64mhz, value: 3 } + - { name: Firc90_96mhz, value: 5 } + - { name: Firc180_192mhz, value: 7 } diff --git a/data/transforms/mcxa/spc.yaml b/data/transforms/mcxa/spc.yaml index fc8f2e5..f2cf61e 100644 --- a/data/transforms/mcxa/spc.yaml +++ b/data/transforms/mcxa/spc.yaml @@ -9,5 +9,6 @@ transforms: - !AddEnumVariants enum: spc0::Vsm variants: - - { name: SRAM1V0, value: 1, description: "SRAM configured for 1.0V" } - - { name: SRAM1V2, value: 3, description: "SRAM configured for 1.2V" } + - { name: Sram1v0, value: 1, description: "SRAM configured for 1.0V" } + - { name: Sram1v1, value: 2, description: "SRAM configured for 1.1V" } + - { name: Sram1v2, value: 3, description: "SRAM configured for 1.2V" } diff --git a/data/transforms/mcxa/trng.yaml b/data/transforms/mcxa/trng.yaml index 1074e2a..1f28329 100644 --- a/data/transforms/mcxa/trng.yaml +++ b/data/transforms/mcxa/trng.yaml @@ -8,5 +8,16 @@ transforms: to: trng0::Ent type: Fieldset + - !AddRegisters + block: trng0::Trng0 + registers: + - name: ent + description: Entropy Read Register + byte_offset: 64 + fieldset: trng0::Ent + array: + len: 8 + stride: 4 + - !DeleteEnums - from: trng0::(IntMaskHwErr|IntMaskIntgFlt|IntStatusFrqCtFail|IntStatusHwErr|IntStatusIntgFlt|LocalEdc|LocalEdcClr|NoPrgm|RedFsm|RedFsmClr|RedSigs|RedSigsClr|IntMaskFrqCtFail|IntMaskEntVal|IntCtrlIntgFlt|IntCtrlHwErr|IntCtrlFrqCtFail|IntCtrlEntVal|BusEdcClr|BusEdc) + from: trng0::(IntMaskHwErr|IntMaskIntgFlt|IntStatusFrqCtFail|IntStatusHwErr|IntStatusIntgFlt|LocalEdc|LocalEdcClr|NoPrgm|RedFsm|RedFsmClr|RedSigs|RedSigsClr|IntMaskFrqCtFail|IntMaskEntVal|IntCtrlIntgFlt|IntCtrlHwErr|IntCtrlFrqCtFail|IntCtrlEntVal|BusEdcClr|BusEdc|IntStatusEntVal) diff --git a/data/transforms/mcxa256.yaml b/data/transforms/mcxa256.yaml index d10c8a3..b65a904 100644 --- a/data/transforms/mcxa256.yaml +++ b/data/transforms/mcxa256.yaml @@ -7,6 +7,7 @@ includes: - mcxa/adc.yaml - mcxa/can.yaml - mcxa/cdog.yaml + - mcxa/cmc.yaml - mcxa/crc.yaml - mcxa/ctimer.yaml - mcxa/dma.yaml diff --git a/data/transforms/mcxa577.yaml b/data/transforms/mcxa577.yaml index 79ed732..21cbab7 100644 --- a/data/transforms/mcxa577.yaml +++ b/data/transforms/mcxa577.yaml @@ -9,10 +9,13 @@ includes: - mcxa/mcxa5/port.yaml - mcxa/mcxa5/rtc.yaml - mcxa/mcxa5/ahbsc.yaml + - mcxa/mcxa5/scg.yaml + - mcxa/mcxa5/trng.yaml - mcxa/adc.yaml - mcxa/can.yaml - mcxa/cdog.yaml + - mcxa/cmc.yaml - mcxa/crc.yaml - mcxa/ctimer.yaml - mcxa/dma.yaml @@ -35,4 +38,3 @@ includes: - remove-suffix.yaml transforms: - !Sort - diff --git a/generator/Cargo.toml b/generator/Cargo.toml index 9e9d68a..25c9deb 100644 --- a/generator/Cargo.toml +++ b/generator/Cargo.toml @@ -26,4 +26,4 @@ inflections = "1.1" itertools = "0.14" regex = "1.12" -chiptool = { git = "https://github.com/embassy-rs/chiptool.git", rev = "be1bff3e9e1b27b090e69bd9ac753c66fdcce678" } +chiptool = { git = "https://github.com/embassy-rs/chiptool.git", rev = "859f02b7c3408f52c37065de6f1ad1b1bcb0c94a" } diff --git a/nxp-pac/src/meta_peripherals/mcxa/ADC.rs b/nxp-pac/src/meta_peripherals/mcxa/ADC.rs index d9d5fe9..6091efc 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/ADC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/ADC.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "ADC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Adc { @@ -135,7 +136,7 @@ impl Adc { self, n: usize, ) -> crate::pac::common::Reg { - assert!(n < 34usize); + assert!(n < 33usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0400usize + n * 4usize) as _) } @@ -145,6 +146,11 @@ impl Adc { pub const fn cfg2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0ff8usize) as _) } } + #[doc = "ADC Test Register."] + #[inline(always)] + pub const fn tst(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0ffcusize) as _) } + } } #[doc = "Calibration General A-Side Registers."] #[repr(transparent)] @@ -327,6 +333,42 @@ impl defmt::Format for Cfg { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Cfg2(pub u32); impl Cfg2 { + #[doc = "Async SAR settling delay."] + #[must_use] + #[inline(always)] + pub const fn as_settle(&self) -> AsSettle { + let val = (self.0 >> 0usize) & 0x03; + AsSettle::from_bits(val as u8) + } + #[doc = "Async SAR settling delay."] + #[inline(always)] + pub const fn set_as_settle(&mut self, val: AsSettle) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Async SAR latch time out delay."] + #[must_use] + #[inline(always)] + pub const fn as_lto(&self) -> AsLto { + let val = (self.0 >> 2usize) & 0x03; + AsLto::from_bits(val as u8) + } + #[doc = "Async SAR latch time out delay."] + #[inline(always)] + pub const fn set_as_lto(&mut self, val: AsLto) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); + } + #[doc = "Noise cancellation delay selection."] + #[must_use] + #[inline(always)] + pub const fn noise_cancel(&self) -> NoiseCancel { + let val = (self.0 >> 4usize) & 0x03; + NoiseCancel::from_bits(val as u8) + } + #[doc = "Noise cancellation delay selection."] + #[inline(always)] + pub const fn set_noise_cancel(&mut self, val: NoiseCancel) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + } #[doc = "Justified Left Enable register."] #[must_use] #[inline(always)] @@ -385,6 +427,9 @@ impl Default for Cfg2 { impl core::fmt::Debug for Cfg2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Cfg2") + .field("as_settle", &self.as_settle()) + .field("as_lto", &self.as_lto()) + .field("noise_cancel", &self.noise_cancel()) .field("jleft", &self.jleft()) .field("hs", &self.hs()) .field("hsextra", &self.hsextra()) @@ -397,7 +442,10 @@ impl defmt::Format for Cfg2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Cfg2 {{ jleft: {=bool:?}, hs: {=bool:?}, hsextra: {:?}, tune: {=u8:?} }}", + "Cfg2 {{ as_settle: {:?}, as_lto: {:?}, noise_cancel: {:?}, jleft: {=bool:?}, hs: {=bool:?}, hsextra: {:?}, tune: {=u8:?} }}", + self.as_settle(), + self.as_lto(), + self.noise_cancel(), self.jleft(), self.hs(), self.hsextra(), @@ -571,6 +619,30 @@ impl Cmdl { pub const fn set_mode(&mut self, val: Mode) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); } + #[doc = "Alternate Channel B Input Channel Select."] + #[must_use] + #[inline(always)] + pub const fn altb_adch(&self) -> AltbAdch { + let val = (self.0 >> 16usize) & 0x1f; + AltbAdch::from_bits(val as u8) + } + #[doc = "Alternate Channel B Input Channel Select."] + #[inline(always)] + pub const fn set_altb_adch(&mut self, val: AltbAdch) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val.to_bits() as u32) & 0x1f) << 16usize); + } + #[doc = "Alternate Channel B Select Enable."] + #[must_use] + #[inline(always)] + pub const fn altben(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "Alternate Channel B Select Enable."] + #[inline(always)] + pub const fn set_altben(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } } impl Default for Cmdl { #[inline(always)] @@ -584,6 +656,8 @@ impl core::fmt::Debug for Cmdl { .field("adch", &self.adch()) .field("ctype", &self.ctype()) .field("mode", &self.mode()) + .field("altb_adch", &self.altb_adch()) + .field("altben", &self.altben()) .finish() } } @@ -592,10 +666,12 @@ impl defmt::Format for Cmdl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Cmdl {{ adch: {=u8:?}, ctype: {:?}, mode: {:?} }}", + "Cmdl {{ adch: {=u8:?}, ctype: {:?}, mode: {:?}, altb_adch: {:?}, altben: {=bool:?} }}", self.adch(), self.ctype(), - self.mode() + self.mode(), + self.altb_adch(), + self.altben() ) } } @@ -905,13 +981,13 @@ impl Gcc0 { #[doc = "Gain Calibration Value Valid."] #[must_use] #[inline(always)] - pub const fn rdy(&self) -> Gcc0rdy { + pub const fn rdy(&self) -> Gcc0Rdy { let val = (self.0 >> 24usize) & 0x01; - Gcc0rdy::from_bits(val as u8) + Gcc0Rdy::from_bits(val as u8) } #[doc = "Gain Calibration Value Valid."] #[inline(always)] - pub const fn set_rdy(&mut self, val: Gcc0rdy) { + pub const fn set_rdy(&mut self, val: Gcc0Rdy) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); } } @@ -1688,6 +1764,103 @@ impl defmt::Format for Tctrl { ) } } +#[doc = "ADC Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Tst(pub u32); +impl Tst { + #[doc = "Calibration Sample Time Long."] + #[must_use] + #[inline(always)] + pub const fn cst_long(&self) -> CstLong { + let val = (self.0 >> 0usize) & 0x01; + CstLong::from_bits(val as u8) + } + #[doc = "Calibration Sample Time Long."] + #[inline(always)] + pub const fn set_cst_long(&mut self, val: CstLong) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Force P-side positive offset."] + #[must_use] + #[inline(always)] + pub const fn foffp(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Force P-side positive offset."] + #[inline(always)] + pub const fn set_foffp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Force P-side negative offset."] + #[must_use] + #[inline(always)] + pub const fn foffp2(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Force P-side negative offset."] + #[inline(always)] + pub const fn set_foffp2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enable FIFO Data out to Pin."] + #[must_use] + #[inline(always)] + pub const fn ipp_do_en(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Enable FIFO Data out to Pin."] + #[inline(always)] + pub const fn set_ipp_do_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Enable test configuration."] + #[must_use] + #[inline(always)] + pub const fn testen(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Enable test configuration."] + #[inline(always)] + pub const fn set_testen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } +} +impl Default for Tst { + #[inline(always)] + fn default() -> Tst { + Tst(0) + } +} +impl core::fmt::Debug for Tst { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tst") + .field("cst_long", &self.cst_long()) + .field("foffp", &self.foffp()) + .field("foffp2", &self.foffp2()) + .field("ipp_do_en", &self.ipp_do_en()) + .field("testen", &self.testen()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Tst { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Tst {{ cst_long: {:?}, foffp: {=bool:?}, foffp2: {=bool:?}, ipp_do_en: {=bool:?}, testen: {=bool:?} }}", + self.cst_long(), + self.foffp(), + self.foffp2(), + self.ipp_do_en(), + self.testen() + ) + } +} #[doc = "Trigger Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1929,9 +2102,9 @@ impl defmt::Format for Verid { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AdcActive { #[doc = "The ADC is IDLE. There are no pending triggers to service and no active commands are being processed."] - NOT_ACTIVE = 0x0, + NotActive = 0x0, #[doc = "The ADC is processing a conversion, running through the power up delay, or servicing a trigger."] - BUSY = 0x01, + Busy = 0x01, } impl AdcActive { #[inline(always)] @@ -1958,29 +2131,170 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AltbAdch { + #[doc = "Select CH0B."] + SelectCh0b = 0x0, + #[doc = "Select CH1B."] + SelectCh1b = 0x01, + #[doc = "Select CH2B."] + SelectCh2b = 0x02, + #[doc = "Select CH3B."] + SelectCh3b = 0x03, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB4 = 0x04, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB5 = 0x05, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB6 = 0x06, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB7 = 0x07, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB8 = 0x08, + #[doc = "Select corresponding channel CHnB."] + SelectCorrespondingCHnB9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + _RESERVED_10 = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + _RESERVED_19 = 0x19, + _RESERVED_1a = 0x1a, + _RESERVED_1b = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + #[doc = "Select CH30B."] + SelectCh30b = 0x1e, + #[doc = "Select CH31B."] + SelectCh31b = 0x1f, +} +impl AltbAdch { + #[inline(always)] + pub const fn from_bits(val: u8) -> AltbAdch { + unsafe { core::mem::transmute(val & 0x1f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for AltbAdch { + #[inline(always)] + fn from(val: u8) -> AltbAdch { + AltbAdch::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: AltbAdch) -> u8 { + AltbAdch::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AsLto { + #[doc = "Shortest delay."] + ShortestDelay = 0x0, + #[doc = "Mid 1 delay."] + Mid1Delay = 0x01, + #[doc = "Mid 2 delay."] + Mid2Delay = 0x02, + #[doc = "Longest delay."] + LongestDelay = 0x03, +} +impl AsLto { + #[inline(always)] + pub const fn from_bits(val: u8) -> AsLto { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for AsLto { + #[inline(always)] + fn from(val: u8) -> AsLto { + AsLto::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: AsLto) -> u8 { + AsLto::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AsSettle { + #[doc = "Shortest delay."] + ShortestDelay = 0x0, + #[doc = "Mid 1 delay."] + Mid1Delay = 0x01, + #[doc = "Mid 2 delay."] + Mid2Delay = 0x02, + #[doc = "Longest delay."] + LongestDelay = 0x03, +} +impl AsSettle { + #[inline(always)] + pub const fn from_bits(val: u8) -> AsSettle { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for AsSettle { + #[inline(always)] + fn from(val: u8) -> AsSettle { + AsSettle::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: AsSettle) -> u8 { + AsSettle::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Avgs { #[doc = "Single conversion."] - NO_AVERAGE = 0x0, + NoAverage = 0x0, #[doc = "2 conversions averaged."] - AVERAGE_2 = 0x01, + Average2 = 0x01, #[doc = "4 conversions averaged."] - AVERAGE_4 = 0x02, + Average4 = 0x02, #[doc = "8 conversions averaged."] - AVERAGE_8 = 0x03, + Average8 = 0x03, #[doc = "16 conversions averaged."] - AVERAGE_16 = 0x04, + Average16 = 0x04, #[doc = "32 conversions averaged."] - AVERAGE_32 = 0x05, + Average32 = 0x05, #[doc = "64 conversions averaged."] - AVERAGE_64 = 0x06, + Average64 = 0x06, #[doc = "128 conversions averaged."] - AVERAGE_128 = 0x07, + Average128 = 0x07, #[doc = "256 conversions averaged."] - AVERAGE_256 = 0x08, + Average256 = 0x08, #[doc = "512 conversions averaged."] - AVERAGE_512 = 0x09, + Average512 = 0x09, #[doc = "1024 conversions averaged."] - AVERAGE_1024 = 0x0a, + Average1024 = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, @@ -2014,27 +2328,27 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CalAvgs { #[doc = "Single conversion."] - NO_AVERAGE = 0x0, + NoAverage = 0x0, #[doc = "2 conversions averaged."] - AVERAGE_2 = 0x01, + Average2 = 0x01, #[doc = "4 conversions averaged."] - AVERAGE_4 = 0x02, + Average4 = 0x02, #[doc = "8 conversions averaged."] - AVERAGE_8 = 0x03, + Average8 = 0x03, #[doc = "16 conversions averaged."] - AVERAGE_16 = 0x04, + Average16 = 0x04, #[doc = "32 conversions averaged."] - AVERAGE_32 = 0x05, + Average32 = 0x05, #[doc = "64 conversions averaged."] - AVERAGE_64 = 0x06, + Average64 = 0x06, #[doc = "128 conversions averaged."] - AVERAGE_128 = 0x07, + Average128 = 0x07, #[doc = "256 conversions averaged."] - AVERAGE_256 = 0x08, + Average256 = 0x08, #[doc = "512 conversions averaged."] - AVERAGE_512 = 0x09, + Average512 = 0x09, #[doc = "1024 conversions averaged."] - AVERAGE_1024 = 0x0a, + Average1024 = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, @@ -2068,9 +2382,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CalRdy { #[doc = "Calibration is incomplete or hasn't been ran."] - NOT_SET = 0x0, + NotSet = 0x0, #[doc = "The ADC is calibrated."] - HARDWARE_CAL_STEP_COMPLETED = 0x01, + HardwareCalStepCompleted = 0x01, } impl CalRdy { #[inline(always)] @@ -2099,9 +2413,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CalReq { #[doc = "No request for hardware calibration has been made."] - NO_CALIBRATION_REQUEST = 0x0, + NoCalibrationRequest = 0x0, #[doc = "A request for hardware calibration has been made."] - CALIBRATION_REQUEST_PENDING = 0x01, + CalibrationRequestPending = 0x01, } impl CalReq { #[inline(always)] @@ -2130,9 +2444,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Calhs { #[doc = "No request for high speed mode trim has been made."] - NO_ACTIVE_HS_TRIM_REQUEST = 0x0, + NoActiveHsTrimRequest = 0x0, #[doc = "Request for high speed mode trim has been made."] - HS_TRIM_REQUEST_PENDING = 0x01, + HsTrimRequestPending = 0x01, } impl Calhs { #[inline(always)] @@ -2161,9 +2475,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Calofs { #[doc = "No request for offset calibration has been made."] - NO_ACTIVE_OFFSET_CALIBRATION_REQUEST = 0x0, + NoActiveOffsetCalibrationRequest = 0x0, #[doc = "Request for offset calibration function."] - OFFSET_CALIBRATION_REQUEST_PENDING = 0x01, + OffsetCalibrationRequestPending = 0x01, } impl Calofs { #[inline(always)] @@ -2192,9 +2506,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Calofsi { #[doc = "Calibration Not Implemented."] - CAL_FUNCTION_NOT_AVAILABLE = 0x0, + CalFunctionNotAvailable = 0x0, #[doc = "Calibration Implemented."] - CAL_FUNCTION_AVAILABLE = 0x01, + CalFunctionAvailable = 0x01, } impl Calofsi { #[inline(always)] @@ -2223,21 +2537,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmdact { #[doc = "No command is currently in progress."] - NO_COMMAND_ACTIVE = 0x0, + NoCommandActive = 0x0, #[doc = "Command 1 currently being executed."] - COMMAND_1 = 0x01, + Command1 = 0x01, #[doc = "Command 2 currently being executed."] - COMMAND_2 = 0x02, + Command2 = 0x02, #[doc = "Associated command number is currently being executed."] - COMMAND_X_3 = 0x03, + CommandX3 = 0x03, #[doc = "Associated command number is currently being executed."] - COMMAND_X_4 = 0x04, + CommandX4 = 0x04, #[doc = "Associated command number is currently being executed."] - COMMAND_X_5 = 0x05, + CommandX5 = 0x05, #[doc = "Associated command number is currently being executed."] - COMMAND_X_6 = 0x06, + CommandX6 = 0x06, #[doc = "Associated command number is currently being executed."] - COMMAND_X_7 = 0x07, + CommandX7 = 0x07, } impl Cmdact { #[inline(always)] @@ -2266,21 +2580,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmdsrc { #[doc = "Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer."] - NOT_VALID = 0x0, + NotValid = 0x0, #[doc = "CMD1 buffer used as control settings for this conversion."] - CMD1 = 0x01, + Cmd1 = 0x01, #[doc = "Corresponding command buffer used as control settings for this conversion."] - CORRESPONDING_CMD_2 = 0x02, + CorrespondingCmd2 = 0x02, #[doc = "Corresponding command buffer used as control settings for this conversion."] - CORRESPONDING_CMD_3 = 0x03, + CorrespondingCmd3 = 0x03, #[doc = "Corresponding command buffer used as control settings for this conversion."] - CORRESPONDING_CMD_4 = 0x04, + CorrespondingCmd4 = 0x04, #[doc = "Corresponding command buffer used as control settings for this conversion."] - CORRESPONDING_CMD_5 = 0x05, + CorrespondingCmd5 = 0x05, #[doc = "Corresponding command buffer used as control settings for this conversion."] - CORRESPONDING_CMD_6 = 0x06, + CorrespondingCmd6 = 0x06, #[doc = "CMD7 buffer used as control settings for this conversion."] - CMD7 = 0x07, + Cmd7 = 0x07, } impl Cmdsrc { #[inline(always)] @@ -2309,12 +2623,12 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmpen { #[doc = "Compare disabled."] - DISABLED_ALWAYS_STORE_RESULT = 0x0, + DisabledAlwaysStoreResult = 0x0, _RESERVED_1 = 0x01, #[doc = "Compare enabled. Store on true."] - COMPARE_RESULT_STORE_IF_TRUE = 0x02, + CompareResultStoreIfTrue = 0x02, #[doc = "Compare enabled. Repeat channel acquisition (sample/convert/compare) until true."] - COMPARE_RESULT_KEEP_CONVERTING_UNTIL_TRUE_STORE_IF_TRUE = 0x03, + CompareResultKeepConvertingUntilTrueStoreIfTrue = 0x03, } impl Cmpen { #[inline(always)] @@ -2341,17 +2655,48 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CstLong { + #[doc = "Normal sample time. Minimum sample time of 3.5 ADCK cycles."] + Sample3p5 = 0x0, + #[doc = "Increased sample time. 67.5 ADCK cycles total sample time."] + Sample67p5 = 0x01, +} +impl CstLong { + #[inline(always)] + pub const fn from_bits(val: u8) -> CstLong { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CstLong { + #[inline(always)] + fn from(val: u8) -> CstLong { + CstLong::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CstLong) -> u8 { + CstLong::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Csw { #[doc = "Channel scaling not supported."] - CSCALE_NOT_SUPPORTED = 0x0, + CscaleNotSupported = 0x0, #[doc = "Channel scaling supported. 1-bit CSCALE control field."] - BIT_WIDTH_1 = 0x01, + BitWidth1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, #[doc = "Channel scaling supported. 6-bit CSCALE control field."] - BIT_WIDTH_6 = 0x06, + BitWidth6 = 0x06, _RESERVED_7 = 0x07, } impl Csw { @@ -2381,7 +2726,7 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ctype { #[doc = "Single-Ended Mode. Only A side channel is converted."] - SINGLE_ENDED_A_SIDE_CHANNEL = 0x0, + SingleEndedASideChannel = 0x0, _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, @@ -2413,9 +2758,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Diffen { #[doc = "Differential operation not supported."] - DIFFERENTIAL_NOT_SUPPORTED = 0x0, + DifferentialNotSupported = 0x0, #[doc = "Differential operation supported."] - DIFFERENTIAL_SUPPORTED = 0x01, + DifferentialSupported = 0x01, } impl Diffen { #[inline(always)] @@ -2444,9 +2789,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dozen { #[doc = "ADC is enabled in low power mode."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "ADC is disabled in low power mode."] - DISABLED = 0x01, + Disabled = 0x01, } impl Dozen { #[inline(always)] @@ -2475,17 +2820,17 @@ impl From for u8 { pub struct Fifosize(u8); impl Fifosize { #[doc = "Result FIFO depth = 2 dataword."] - pub const ENTRIES_2: Self = Self(0x01); + pub const Entries2: Self = Self(0x01); #[doc = "Result FIFO depth = 4 datawords."] - pub const ENTRIES_4: Self = Self(0x04); + pub const Entries4: Self = Self(0x04); #[doc = "Result FIFO depth = 8 datawords."] - pub const ENTRIES_8: Self = Self(0x08); + pub const Entries8: Self = Self(0x08); #[doc = "Result FIFO depth = 16 datawords."] - pub const ENTRIES_16: Self = Self(0x10); + pub const Entries16: Self = Self(0x10); #[doc = "Result FIFO depth = 32 datawords."] - pub const ENTRIES_32: Self = Self(0x20); + pub const Entries32: Self = Self(0x20); #[doc = "Result FIFO depth = 64 datawords."] - pub const ENTRIES_64: Self = Self(0x40); + pub const Entries64: Self = Self(0x40); } impl Fifosize { pub const fn from_bits(val: u8) -> Fifosize { @@ -2498,12 +2843,12 @@ impl Fifosize { impl core::fmt::Debug for Fifosize { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x01 => f.write_str("ENTRIES_2"), - 0x04 => f.write_str("ENTRIES_4"), - 0x08 => f.write_str("ENTRIES_8"), - 0x10 => f.write_str("ENTRIES_16"), - 0x20 => f.write_str("ENTRIES_32"), - 0x40 => f.write_str("ENTRIES_64"), + 0x01 => f.write_str("Entries2"), + 0x04 => f.write_str("Entries4"), + 0x08 => f.write_str("Entries8"), + 0x10 => f.write_str("Entries16"), + 0x20 => f.write_str("Entries32"), + 0x40 => f.write_str("Entries64"), other => core::write!(f, "0x{:02X}", other), } } @@ -2512,12 +2857,12 @@ impl core::fmt::Debug for Fifosize { impl defmt::Format for Fifosize { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x01 => defmt::write!(f, "ENTRIES_2"), - 0x04 => defmt::write!(f, "ENTRIES_4"), - 0x08 => defmt::write!(f, "ENTRIES_8"), - 0x10 => defmt::write!(f, "ENTRIES_16"), - 0x20 => defmt::write!(f, "ENTRIES_32"), - 0x40 => defmt::write!(f, "ENTRIES_64"), + 0x01 => defmt::write!(f, "Entries2"), + 0x04 => defmt::write!(f, "Entries4"), + 0x08 => defmt::write!(f, "Entries8"), + 0x10 => defmt::write!(f, "Entries16"), + 0x20 => defmt::write!(f, "Entries32"), + 0x40 => defmt::write!(f, "Entries64"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -2539,9 +2884,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fof0 { #[doc = "No result FIFO 0 overflow has occurred since the last time the flag was cleared."] - NO_OVERFLOW = 0x0, + NoOverflow = 0x0, #[doc = "At least one result FIFO 0 overflow has occurred since the last time the flag was cleared."] - OVERFLOW_DETECTED = 0x01, + OverflowDetected = 0x01, } impl Fof0 { #[inline(always)] @@ -2568,15 +2913,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Gcc0rdy { +pub enum Gcc0Rdy { #[doc = "The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set."] - GAIN_CAL_NOT_VALID = 0x0, + GainCalNotValid = 0x0, #[doc = "The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa\\[GCALR\\]."] - HARDWARE_CAL_ROUTINE_COMPLETED = 0x01, + HardwareCalRoutineCompleted = 0x01, } -impl Gcc0rdy { +impl Gcc0Rdy { #[inline(always)] - pub const fn from_bits(val: u8) -> Gcc0rdy { + pub const fn from_bits(val: u8) -> Gcc0Rdy { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2584,16 +2929,16 @@ impl Gcc0rdy { unsafe { core::mem::transmute(self) } } } -impl From for Gcc0rdy { +impl From for Gcc0Rdy { #[inline(always)] - fn from(val: u8) -> Gcc0rdy { - Gcc0rdy::from_bits(val) + fn from(val: u8) -> Gcc0Rdy { + Gcc0Rdy::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Gcc0rdy) -> u8 { - Gcc0rdy::to_bits(val) + fn from(val: Gcc0Rdy) -> u8 { + Gcc0Rdy::to_bits(val) } } #[repr(u8)] @@ -2601,9 +2946,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum HptExdi { #[doc = "High priority trigger exceptions are enabled."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "High priority trigger exceptions are disabled."] - DISABLED = 0x01, + Disabled = 0x01, } impl HptExdi { #[inline(always)] @@ -2631,10 +2976,10 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hsextra { - #[doc = "No extra cycle added."] - HSEXTRA_0 = 0x0, - #[doc = "Extra cycle added."] - HSEXTRA_1 = 0x01, + #[doc = "No extra cycle added. Allow 2 ADCK cycles for async SAR operation."] + Hsextra0 = 0x0, + #[doc = "Extra cycle added. Allow 3 ADCK cycles for async SAR operation."] + Hsextra1 = 0x01, } impl Hsextra { #[inline(always)] @@ -2663,9 +3008,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Iadcki { #[doc = "Internal clock source not implemented."] - INTERNAL_CLK_NOT_AVAILABLE = 0x0, + InternalClkNotAvailable = 0x0, #[doc = "Internal clock source (and CFG\\[ADCKEN\\]) implemented."] - INTERNAL_CLK_AVAILABLE = 0x01, + InternalClkAvailable = 0x01, } impl Iadcki { #[inline(always)] @@ -2694,32 +3039,32 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Loop { #[doc = "Looping not enabled. Command executes 1 time."] - CMD_EXEC_1X = 0x0, + CmdExec1x = 0x0, #[doc = "Loop 1 time. Command executes 2 times."] - CMD_EXEC_2X = 0x01, + CmdExec2x = 0x01, #[doc = "Loop 2 times. Command executes 3 times."] - CMD_EXEC_3X = 0x02, + CmdExec3x = 0x02, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_3 = 0x03, + CmdExecutesCorrespondingTimes3 = 0x03, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_4 = 0x04, + CmdExecutesCorrespondingTimes4 = 0x04, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_5 = 0x05, + CmdExecutesCorrespondingTimes5 = 0x05, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_6 = 0x06, + CmdExecutesCorrespondingTimes6 = 0x06, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_7 = 0x07, + CmdExecutesCorrespondingTimes7 = 0x07, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_8 = 0x08, + CmdExecutesCorrespondingTimes8 = 0x08, #[doc = "Loop corresponding number of times. Command executes LOOP+1 times."] - CMD_EXECUTES_CORRESPONDING_TIMES_9 = 0x09, + CmdExecutesCorrespondingTimes9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Loop 15 times. Command executes 16 times."] - CMD_EXEC_15X = 0x0f, + CmdExec15x = 0x0f, } impl Loop { #[inline(always)] @@ -2748,32 +3093,32 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Loopcnt { #[doc = "Result is from initial conversion in command."] - RESULT_1 = 0x0, + Result1 = 0x0, #[doc = "Result is from second conversion in command."] - RESULT_2 = 0x01, + Result2 = 0x01, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_2 = 0x02, + CorrespondingResult2 = 0x02, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_3 = 0x03, + CorrespondingResult3 = 0x03, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_4 = 0x04, + CorrespondingResult4 = 0x04, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_5 = 0x05, + CorrespondingResult5 = 0x05, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_6 = 0x06, + CorrespondingResult6 = 0x06, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_7 = 0x07, + CorrespondingResult7 = 0x07, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_8 = 0x08, + CorrespondingResult8 = 0x08, #[doc = "Result is from LOOPCNT+1 conversion in command."] - CORRESPONDING_RESULT_9 = 0x09, + CorrespondingResult9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Result is from 16th conversion in command."] - RESULT_16 = 0x0f, + Result16 = 0x0f, } impl Loopcnt { #[inline(always)] @@ -2802,9 +3147,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mode { #[doc = "Standard resolution. Single-ended 12-bit conversion."] - DATA_12_BITS = 0x0, + Data12Bits = 0x0, #[doc = "High resolution. Single-ended 16-bit conversion."] - DATA_16_BITS = 0x01, + Data16Bits = 0x01, } impl Mode { #[inline(always)] @@ -2833,9 +3178,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mvi { #[doc = "Single voltage reference high (VREFH) input supported."] - MULTIPLE_REF_NOT_SUPPORTED = 0x0, + MultipleRefNotSupported = 0x0, #[doc = "Multiple voltage reference high (VREFH) inputs supported."] - MULTIPLE_REF_SUPPORTED = 0x01, + MultipleRefSupported = 0x01, } impl Mvi { #[inline(always)] @@ -2864,21 +3209,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Next { #[doc = "No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger."] - NO_NEXT_CMD_TERMINATE_ON_FINISH = 0x0, + NoNextCmdTerminateOnFinish = 0x0, #[doc = "Select CMD1 command buffer register as next command."] - DO_CMD1_NEXT = 0x01, + DoCmd1Next = 0x01, #[doc = "Select corresponding CMD command buffer register as next command."] - DO_CORRESPONDING_CMD_NEXT_2 = 0x02, + DoCorrespondingCmdNext2 = 0x02, #[doc = "Select corresponding CMD command buffer register as next command."] - DO_CORRESPONDING_CMD_NEXT_3 = 0x03, + DoCorrespondingCmdNext3 = 0x03, #[doc = "Select corresponding CMD command buffer register as next command."] - DO_CORRESPONDING_CMD_NEXT_4 = 0x04, + DoCorrespondingCmdNext4 = 0x04, #[doc = "Select corresponding CMD command buffer register as next command."] - DO_CORRESPONDING_CMD_NEXT_5 = 0x05, + DoCorrespondingCmdNext5 = 0x05, #[doc = "Select corresponding CMD command buffer register as next command."] - DO_CORRESPONDING_CMD_NEXT_6 = 0x06, + DoCorrespondingCmdNext6 = 0x06, #[doc = "Select CMD7 command buffer register as next command."] - DO_CMD7_NEXT = 0x07, + DoCmd7Next = 0x07, } impl Next { #[inline(always)] @@ -2905,17 +3250,52 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum NoiseCancel { + #[doc = "Noise cancelling disabled."] + Disabled = 0x0, + #[doc = "Shortest delay."] + ShortDelay = 0x01, + #[doc = "Mid delay."] + MidDelay = 0x02, + #[doc = "Longest delay."] + LongestDelay = 0x03, +} +impl NoiseCancel { + #[inline(always)] + pub const fn from_bits(val: u8) -> NoiseCancel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for NoiseCancel { + #[inline(always)] + fn from(val: u8) -> NoiseCancel { + NoiseCancel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: NoiseCancel) -> u8 { + NoiseCancel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum NumFifo { #[doc = "N/A."] - NO_FIFO_IMPLEMENTED = 0x0, + NoFifoImplemented = 0x0, #[doc = "This design supports one result FIFO."] - CNT_1 = 0x01, + Cnt1 = 0x01, #[doc = "This design supports two result FIFOs."] - CNT_2 = 0x02, + Cnt2 = 0x02, #[doc = "This design supports three result FIFOs."] - CNT_3 = 0x03, + Cnt3 = 0x03, #[doc = "This design supports four result FIFOs."] - CNT_4 = 0x04, + Cnt4 = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, @@ -2947,9 +3327,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum NumSec { #[doc = "This design supports one single ended conversion at a time."] - SINGLE_CONVERTOR = 0x0, + SingleConvertor = 0x0, #[doc = "This design supports two simultaneous single ended conversions."] - DUAL_CONVERTOR = 0x01, + DualConvertor = 0x01, } impl NumSec { #[inline(always)] @@ -2978,9 +3358,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pwrsel { #[doc = "Low power."] - LOWEST = 0x0, + Lowest = 0x0, #[doc = "High power."] - HIGHEST = 0x01, + Highest = 0x01, } impl Pwrsel { #[inline(always)] @@ -3009,9 +3389,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rdy0 { #[doc = "Result FIFO 0 data level not above watermark level."] - BELOW_THRESHOLD = 0x0, + BelowThreshold = 0x0, #[doc = "Result FIFO 0 holding data above watermark level."] - ABOVE_THRESHOLD = 0x01, + AboveThreshold = 0x01, } impl Rdy0 { #[inline(always)] @@ -3040,11 +3420,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Refsel { #[doc = "(Default) Option 1 setting."] - OPTION_1 = 0x0, + Option1 = 0x0, #[doc = "Option 2 setting."] - OPTION_2 = 0x01, + Option2 = 0x01, #[doc = "Option 3 setting."] - OPTION_3 = 0x02, + Option3 = 0x02, _RESERVED_3 = 0x03, } impl Refsel { @@ -3074,9 +3454,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Res { #[doc = "Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - MAX_13_BIT = 0x0, + Max13Bit = 0x0, #[doc = "Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."] - MAX_16_BIT = 0x01, + Max16Bit = 0x01, } impl Res { #[inline(always)] @@ -3105,9 +3485,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rst { #[doc = "ADC logic is not reset."] - RELEASED_FROM_RESET = 0x0, + ReleasedFromReset = 0x0, #[doc = "ADC logic is reset."] - HELD_IN_RESET = 0x01, + HeldInReset = 0x01, } impl Rst { #[inline(always)] @@ -3136,9 +3516,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rstfifo0 { #[doc = "No effect."] - NO_ACTION = 0x0, + NoAction = 0x0, #[doc = "FIFO 0 is reset."] - TRIGGER_RESET = 0x01, + TriggerReset = 0x01, } impl Rstfifo0 { #[inline(always)] @@ -3167,21 +3547,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sts { #[doc = "Minimum sample time of 3.5 ADCK cycles."] - SAMPLE_3P5 = 0x0, + Sample3p5 = 0x0, #[doc = "3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time."] - SAMPLE_5P5 = 0x01, + Sample5p5 = 0x01, #[doc = "3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time."] - SAMPLE_7P5 = 0x02, + Sample7p5 = 0x02, #[doc = "3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time."] - SAMPLE_11P5 = 0x03, + Sample11p5 = 0x03, #[doc = "3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time."] - SAMPLE_19P5 = 0x04, + Sample19p5 = 0x04, #[doc = "3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time."] - SAMPLE_35P5 = 0x05, + Sample35p5 = 0x05, #[doc = "3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time."] - SAMPLE_67P5 = 0x06, + Sample67p5 = 0x06, #[doc = "3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time."] - SAMPLE_131P5 = 0x07, + Sample131p5 = 0x07, } impl Sts { #[inline(always)] @@ -3210,21 +3590,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tcmd { #[doc = "Not a valid selection from the command buffer. Trigger event is ignored."] - NOT_VALID = 0x0, + NotValid = 0x0, #[doc = "CMD1 is executed."] - EXECUTE_CMD1 = 0x01, + ExecuteCmd1 = 0x01, #[doc = "Corresponding CMD is executed."] - EXECUTE_CORRESPONDING_CMD_2 = 0x02, + ExecuteCorrespondingCmd2 = 0x02, #[doc = "Corresponding CMD is executed."] - EXECUTE_CORRESPONDING_CMD_3 = 0x03, + ExecuteCorrespondingCmd3 = 0x03, #[doc = "Corresponding CMD is executed."] - EXECUTE_CORRESPONDING_CMD_4 = 0x04, + ExecuteCorrespondingCmd4 = 0x04, #[doc = "Corresponding CMD is executed."] - EXECUTE_CORRESPONDING_CMD_5 = 0x05, + ExecuteCorrespondingCmd5 = 0x05, #[doc = "Corresponding CMD is executed."] - EXECUTE_CORRESPONDING_CMD_6 = 0x06, + ExecuteCorrespondingCmd6 = 0x06, #[doc = "CMD7 is executed."] - EXECUTE_CMD7 = 0x07, + ExecuteCmd7 = 0x07, } impl Tcmd { #[inline(always)] @@ -3253,32 +3633,32 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcompFlag { #[doc = "No triggers have been completed. Trigger completion interrupts are disabled."] - NO_TRIGGER = 0x0, + NoTrigger = 0x0, #[doc = "Trigger 0 has been completed and trigger 0 has enabled completion interrupts."] - BIT0_MEANS_TRIGGER_0_COMPLETED = 0x01, + Bit0MeansTrigger0Completed = 0x01, #[doc = "Trigger 1 has been completed and trigger 1 has enabled completion interrupts."] - BIT1_MEANS_TRIGGER_1_COMPLETED = 0x02, + Bit1MeansTrigger1Completed = 0x02, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_3 = 0x03, + SetBitsIndicateTriggerXCompleted3 = 0x03, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_4 = 0x04, + SetBitsIndicateTriggerXCompleted4 = 0x04, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_5 = 0x05, + SetBitsIndicateTriggerXCompleted5 = 0x05, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_6 = 0x06, + SetBitsIndicateTriggerXCompleted6 = 0x06, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_7 = 0x07, + SetBitsIndicateTriggerXCompleted7 = 0x07, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_8 = 0x08, + SetBitsIndicateTriggerXCompleted8 = 0x08, #[doc = "Associated trigger sequence has completed and has enabled completion interrupts."] - SET_BITS_INDICATE_TRIGGER_X_COMPLETED_9 = 0x09, + SetBitsIndicateTriggerXCompleted9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Every trigger sequence has been completed and every trigger has enabled completion interrupts."] - ALL_BITS_SET_INDICATE_ALL_TRIGGERS_COMPLETED = 0x0f, + AllBitsSetIndicateAllTriggersCompleted = 0x0f, } impl TcompFlag { #[inline(always)] @@ -3307,32 +3687,32 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcompIe { #[doc = "Trigger completion interrupts are disabled."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Trigger completion interrupts are enabled for trigger source 0 only."] - TRIGGER_0_COMPLETE_ENABLED = 0x01, + Trigger0CompleteEnabled = 0x01, #[doc = "Trigger completion interrupts are enabled for trigger source 1 only."] - TRIGGER_1_COMPLETE_ENABLED = 0x02, + Trigger1CompleteEnabled = 0x02, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_3 = 0x03, + TriggerXCompleteEnabled3 = 0x03, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_4 = 0x04, + TriggerXCompleteEnabled4 = 0x04, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_5 = 0x05, + TriggerXCompleteEnabled5 = 0x05, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_6 = 0x06, + TriggerXCompleteEnabled6 = 0x06, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_7 = 0x07, + TriggerXCompleteEnabled7 = 0x07, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_8 = 0x08, + TriggerXCompleteEnabled8 = 0x08, #[doc = "Associated trigger completion interrupts are enabled."] - TRIGGER_X_COMPLETE_ENABLED_9 = 0x09, + TriggerXCompleteEnabled9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Trigger completion interrupts are enabled for every trigger source."] - ALL_TRIGGER_COMPLETES_ENABLED = 0x0f, + AllTriggerCompletesEnabled = 0x0f, } impl TcompIe { #[inline(always)] @@ -3361,9 +3741,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcompInt { #[doc = "Either IE\\[TCOMP_IE\\] is set to 0, or no trigger sequences have run to completion."] - FLAG_CLEAR = 0x0, + FlagClear = 0x0, #[doc = "Trigger sequence has been completed and all data is stored in the associated FIFO."] - COMPLETION_DETECTED = 0x01, + CompletionDetected = 0x01, } impl TcompInt { #[inline(always)] @@ -3392,9 +3772,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TexcInt { #[doc = "No trigger exceptions have occurred."] - NO_EXCEPTION = 0x0, + NoException = 0x0, #[doc = "A trigger exception has occurred and is pending acknowledgement."] - EXCEPTION_DETECTED = 0x01, + ExceptionDetected = 0x01, } impl TexcInt { #[inline(always)] @@ -3423,32 +3803,32 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TexcNum { #[doc = "No triggers have been interrupted by a high priority exception. Or CFG\\[TRES\\] = 1."] - NO_EXCEPTIONS = 0x0, + NoExceptions = 0x0, #[doc = "Trigger 0 has been interrupted by a high priority exception."] - BIT0_MEANS_TRIGGER_0_INTERRUPTED = 0x01, + Bit0MeansTrigger0Interrupted = 0x01, #[doc = "Trigger 1 has been interrupted by a high priority exception."] - BIT1_MEANS_TRIGGER_1_INTERRUPTED = 0x02, + Bit1MeansTrigger1Interrupted = 0x02, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_3 = 0x03, + SetBitsIndicateTriggerXInterrupted3 = 0x03, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_4 = 0x04, + SetBitsIndicateTriggerXInterrupted4 = 0x04, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_5 = 0x05, + SetBitsIndicateTriggerXInterrupted5 = 0x05, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_6 = 0x06, + SetBitsIndicateTriggerXInterrupted6 = 0x06, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_7 = 0x07, + SetBitsIndicateTriggerXInterrupted7 = 0x07, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_8 = 0x08, + SetBitsIndicateTriggerXInterrupted8 = 0x08, #[doc = "Associated trigger sequence has interrupted by a high priority exception."] - SET_BITS_INDICATE_TRIGGER_X_INTERRUPTED_9 = 0x09, + SetBitsIndicateTriggerXInterrupted9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Every trigger sequence has been interrupted by a high priority exception."] - ALL_BITS_SET_INDICATE_ALL_TRIGGERS_INTERRUPTED = 0x0f, + AllBitsSetIndicateAllTriggersInterrupted = 0x0f, } impl TexcNum { #[inline(always)] @@ -3477,13 +3857,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tpri { #[doc = "Set to highest priority, Level 1."] - HIGHEST_PRIORITY = 0x0, + HighestPriority = 0x0, #[doc = "Set to corresponding priority level."] - CORRESPONDING_LOWER_PRIORITY_1 = 0x01, + CorrespondingLowerPriority1 = 0x01, #[doc = "Set to corresponding priority level."] - CORRESPONDING_LOWER_PRIORITY_2 = 0x02, + CorrespondingLowerPriority2 = 0x02, #[doc = "Set to lowest priority, Level 4."] - LOWEST_PRIORITY = 0x03, + LowestPriority = 0x03, } impl Tpri { #[inline(always)] @@ -3512,11 +3892,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tprictrl { #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."] - ABORT_CURRENT_ON_PRIORITY = 0x0, + AbortCurrentOnPriority = 0x0, #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."] - FINISH_CURRENT_ON_PRIORITY = 0x01, + FinishCurrentOnPriority = 0x01, #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."] - FINISH_SEQUENCE_ON_PRIORITY = 0x02, + FinishSequenceOnPriority = 0x02, _RESERVED_3 = 0x03, } impl Tprictrl { @@ -3546,13 +3926,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Trgact { #[doc = "Command (sequence) associated with Trigger 0 currently being executed."] - TRIG_0 = 0x0, + Trig0 = 0x0, #[doc = "Command (sequence) associated with Trigger 1 currently being executed."] - TRIG_1 = 0x01, + Trig1 = 0x01, #[doc = "Command (sequence) associated with Trigger 2 currently being executed."] - TRIG_2 = 0x02, + Trig2 = 0x02, #[doc = "Command (sequence) associated with Trigger 3 currently being executed."] - TRIG_3 = 0x03, + Trig3 = 0x03, } impl Trgact { #[inline(always)] @@ -3581,13 +3961,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tsrc { #[doc = "Trigger source 0 initiated this conversion."] - TRIGGER_0 = 0x0, + Trigger0 = 0x0, #[doc = "Trigger source 1 initiated this conversion."] - TRIGGER_1 = 0x01, + Trigger1 = 0x01, #[doc = "Trigger source 2 initiated this conversion."] - TRIGGER_2 = 0x02, + Trigger2 = 0x02, #[doc = "Trigger source 3 initiated this conversion."] - TRIGGER_3 = 0x03, + Trigger3 = 0x03, } impl Tsrc { #[inline(always)] @@ -3616,9 +3996,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Vr1rngi { #[doc = "Range control not required. CFG\\[VREF1RNG\\] is not implemented."] - REF1_FIXED_VOLTAGE_RANGE = 0x0, + Ref1FixedVoltageRange = 0x0, #[doc = "Range control required. CFG\\[VREF1RNG\\] is implemented."] - REF1_SELECTABLE_VOLTAGE_RANGE = 0x01, + Ref1SelectableVoltageRange = 0x01, } impl Vr1rngi { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/AHBSC.rs b/nxp-pac/src/meta_peripherals/mcxa/AHBSC.rs index b4e305a..3b25edc 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/AHBSC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/AHBSC.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "AHBSC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ahbsc { @@ -17,41 +18,52 @@ impl Ahbsc { pub const fn as_ptr(&self) -> *mut () { self.ptr as _ } - #[doc = "Flash Memory Rule."] + #[doc = "AHB Slave Port 0 Rule."] #[inline(always)] - pub const fn flash00_mem_rule( + pub const fn ahb_slave_port_p0_slave_rule( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 4usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize + n * 4usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize + n * 4usize) as _) } } #[doc = "Flash Memory Rule."] #[inline(always)] - pub const fn flash01_mem_rule( + pub const fn flash00_mem_rule( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 4usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize + n * 4usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize + n * 4usize) as _) } } - #[doc = "Flash IFR0 Rule register."] + #[doc = "Flash Memory Rule."] #[inline(always)] - pub const fn flash02_mem_rule( + pub const fn flash01_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x30usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } } #[doc = "Flash Memory Rule."] #[inline(always)] - pub const fn flash03_mem_rule( + pub const fn flash02_mem_rule0( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x30usize) as _) } + } + #[doc = "AHB Slave Port 1 Rule."] + #[inline(always)] + pub const fn ahb_slave_port_p1_slave_rule( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize) as _) } + n: usize, + ) -> crate::pac::common::Reg { + assert!(n < 4usize); + unsafe { + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize + n * 4usize) as _) + } } #[doc = "ROM Memory Rule."] #[inline(always)] @@ -59,6 +71,17 @@ impl Ahbsc { self, n: usize, ) -> crate::pac::common::Reg { + assert!(n < 4usize); + unsafe { + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x50usize + n * 4usize) as _) + } + } + #[doc = "AHB Slave Port 2 Rule."] + #[inline(always)] + pub const fn ahb_slave_port_p2_slave_rule( + self, + n: usize, + ) -> crate::pac::common::Reg { assert!(n < 4usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x60usize + n * 4usize) as _) @@ -66,244 +89,244 @@ impl Ahbsc { } #[doc = "RAMX Memory Rule."] #[inline(always)] - pub const fn ramx_mem_rule( + pub const fn ramx_mem_rule0( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x70usize) as _) } + } + #[doc = "AHB Slave Port 3 Rule."] + #[inline(always)] + pub const fn ahb_slave_port_p3_slave_rule( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 4usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x80usize + n * 4usize) as _) } } - #[doc = "RAMA Memory Rule 0."] + #[doc = "RAMA Memory Rule."] #[inline(always)] pub const fn rama_mem_rule( self, n: usize, ) -> crate::pac::common::Reg { - assert!(n < 8usize); + assert!(n < 4usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa0usize + n * 4usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x90usize + n * 4usize) as _) } } - #[doc = "RAMB Memory Rule 0."] + #[doc = "AHB Slave Port 4 Rule."] #[inline(always)] - pub const fn ramb_mem_rule( + pub const fn ahb_slave_port_p4_slave_rule( self, n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 8usize); + ) -> crate::pac::common::Reg { + assert!(n < 4usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd0usize + n * 4usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa0usize + n * 4usize) as _) } } - #[doc = "AHB Slave Port 5 Rule Register."] - #[inline(always)] - pub const fn ahb_slave_port_p5_slave_rule0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf0usize) as _) } - } - #[doc = "APB Bridge Group 0 Memory Rule Register 0."] - #[inline(always)] - pub const fn apb_peripheral_group0_mem_rule0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0100usize) as _) } - } - #[doc = "APB Bridge Group 0 Memory Rule Register 1."] + #[doc = "RAMB Memory Rule."] #[inline(always)] - pub const fn apb_peripheral_group0_mem_rule1( + pub const fn ramb_mem_rule( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0104usize) as _) } + n: usize, + ) -> crate::pac::common::Reg { + assert!(n < 4usize); + unsafe { + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xb0usize + n * 4usize) as _) + } } - #[doc = "AIPS Bridge Group 0 Memory Rule 0."] + #[doc = "AHB Peripheral Slave Port 5 Slave Rule 0."] #[inline(always)] - pub const fn aips_bridge_group0_mem_rule0( + pub const fn ahb_peripheral_slave_port_p5_slave_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0110usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc0usize) as _) } } - #[doc = "AIPS Bridge Group 0 Memory Rule 1."] + #[doc = "AHB Peripheral Slave Port 5 Slave Rule 1."] #[inline(always)] - pub const fn aips_bridge_group0_mem_rule1( + pub const fn ahb_peripheral_slave_port_p5_slave_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0114usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc4usize) as _) } } - #[doc = "AIPS Bridge Group 1 Memory Rule 0."] + #[doc = "APB Bridge Group 0 Memory Rule 0."] #[inline(always)] - pub const fn aips_bridge_group1_mem_rule0( + pub const fn apb_peripheral_group0_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd0usize) as _) } } - #[doc = "AIPS Bridge Group 1 Memory Rule 1."] + #[doc = "APB Bridge Group 0 Memory Rule 1."] #[inline(always)] - pub const fn aips_bridge_group1_mem_rule1( + pub const fn apb_peripheral_group0_mem_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0124usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd4usize) as _) } } - #[doc = "AHB Secure Control Peripheral Rule."] + #[doc = "APB Bridge Group 0 Rule 2."] #[inline(always)] - pub const fn ahb_secure_ctrl_mem_rule0( + pub const fn apb_peripheral_group0_mem_rule2( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0130usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd8usize) as _) } } - #[doc = "AHB Peripheral 0 Memory Rule 1."] + #[doc = "APB Bridge Group 0 Memory Rule 3."] #[inline(always)] - pub const fn ahb_peripheral0_mem_rule1( + pub const fn apb_peripheral_group0_mem_rule3( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0140usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xdcusize) as _) } } - #[doc = "AHB Peripheral 0 Memory Rule 2."] + #[doc = "AIPS Bridge Group 0 Memory Rule 0."] #[inline(always)] - pub const fn ahb_peripheral0_mem_rule2( + pub const fn aips_bridge_group0_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0150usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe0usize) as _) } } - #[doc = "AHB Peripheral 0 Memory Rule 3."] + #[doc = "AIPS Bridge Group 0 Memory Rule 1."] #[inline(always)] - pub const fn ahb_peripheral0_mem_rule3( + pub const fn aips_bridge_group0_mem_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0160usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe4usize) as _) } } - #[doc = "AHB Peripheral 0 Memory Rule 4."] + #[doc = "AIPS Bridge Group 0 Memory Rule 2."] #[inline(always)] - pub const fn ahb_peripheral0_mem_rule4( + pub const fn aips_bridge_group0_mem_rule2( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0170usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe8usize) as _) } } - #[doc = "AHB Peripheral 0 Memory Rule 5."] + #[doc = "AIPS Bridge Group 0 Memory Rule 3."] #[inline(always)] - pub const fn ahb_peripheral0_mem_rule5( + pub const fn aips_bridge_group0_mem_rule3( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0180usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xecusize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 0."] + #[doc = "AIPS Bridge Group 2 Memory Rule 0."] #[inline(always)] pub const fn aips_bridge_group2_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a0usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf0usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 1."] + #[doc = "AIPS Bridge Group 2 Memory Rule 1."] #[inline(always)] pub const fn aips_bridge_group2_mem_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a4usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf4usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 2."] + #[doc = "AIPS Bridge Group 2 Memory Rule 2."] #[inline(always)] pub const fn aips_bridge_group2_mem_rule2( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a8usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf8usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 3."] + #[doc = "AIPS Bridge Group 2 Memory Rule 3."] #[inline(always)] pub const fn aips_bridge_group2_mem_rule3( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01acusize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xfcusize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 4."] + #[doc = "AIPS Bridge Group 3 Rule 0."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule4( + pub const fn aips_bridge_group3_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b0usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0100usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 5."] + #[doc = "AIPS Bridge Group 3 Memory Rule 1."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule5( + pub const fn aips_bridge_group3_mem_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b4usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0104usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 6."] + #[doc = "AIPS Bridge Group 3 Rule 2."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule6( + pub const fn aips_bridge_group3_mem_rule2( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b8usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0108usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 7."] + #[doc = "AIPS Bridge Group 3 Rule 3."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule7( + pub const fn aips_bridge_group3_mem_rule3( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01bcusize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x010cusize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 8."] + #[doc = "AHB Secure Control Peripheral Rule 0."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule8( + pub const fn ahb_secure_ctrl_peripheral_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01c0usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0110usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 9."] + #[doc = "AHB Slave Port 6 Rule."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule9( + pub const fn ahb_slave_port_p6_slave_rule( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01c4usize) as _) } + n: usize, + ) -> crate::pac::common::Reg { + assert!(n < 4usize); + unsafe { + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize + n * 4usize) as _) + } } - #[doc = "AIPS Bridge Group 2 Rule 10."] + #[doc = "AON Domain Peripheral Rule 0."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule10( + pub const fn aon_domain_peripheral_mem_rule0( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01c8usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0130usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 11."] + #[doc = "AON Domain Peripheral Rule 1."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule11( + pub const fn aon_domain_peripheral_mem_rule1( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01ccusize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0134usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 12."] + #[doc = "AON Domain Peripheral Rule 2."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule12( + pub const fn aon_domain_peripheral_mem_rule2( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01d0usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0138usize) as _) } } - #[doc = "AIPS Bridge Group 2 Rule 13."] + #[doc = "AON Domain Peripheral Rule 3."] #[inline(always)] - pub const fn aips_bridge_group2_mem_rule13( + pub const fn aon_domain_peripheral_mem_rule3( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01d4usize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x013cusize) as _) } } - #[doc = "FLEXSPI0 Region 0 Memory Rule."] + #[doc = "AHB Slave Port 6 Rule."] #[inline(always)] - pub const fn flexspi0_region0_mem_rule( + pub const fn ahb_slave_port_p7_slave_rule( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 4usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01f0usize + n * 4usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0140usize + n * 4usize) as _) } } - #[doc = "Array of registers: FLEXSPI0_REGION_MEM_RULE."] + #[doc = "AON Domain SRAM Memory Rule."] #[inline(always)] - pub const fn flexspi0_region1_6_mem_rule(self, n: usize) -> Flexspi0region16memRule { - assert!(n < 6usize); - unsafe { - Flexspi0region16memRule::from_ptr(self.ptr.wrapping_add(0x0200usize + n * 16usize) as _) - } + pub const fn aon_domain_sram_mem_rule0( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0150usize) as _) } } #[doc = "Security Violation Address."] #[inline(always)] @@ -363,7 +386,7 @@ impl Ahbsc { #[inline(always)] pub const fn cpu0_lock_reg( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0fecusize) as _) } } #[doc = "Secure Control Duplicate."] @@ -381,145 +404,94 @@ impl Ahbsc { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0ffcusize) as _) } } } -#[doc = "Array of registers: FLEXSPI0_REGION_MEM_RULE."] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flexspi0region16memRule { - ptr: *mut u8, -} -unsafe impl Send for Flexspi0region16memRule {} -unsafe impl Sync for Flexspi0region16memRule {} -impl Flexspi0region16memRule { - #[inline(always)] - pub const unsafe fn from_ptr(ptr: *mut ()) -> Self { - Self { ptr: ptr as _ } - } - #[inline(always)] - pub const fn as_ptr(&self) -> *mut () { - self.ptr as _ - } - #[doc = "FLEXSPI0 Region index Memory Rule."] - #[inline(always)] - pub const fn flexspi0_region_mem_rule( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize) as _) } - } -} -#[doc = "AHB Peripheral 0 Memory Rule 1."] +#[doc = "AHB Peripheral Slave Port 5 Slave Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbPeripheral0memRule1(pub u32); -impl AhbPeripheral0memRule1 { - #[doc = "GPIO0."] +pub struct AhbPeripheralSlavePortP5SlaveRule0(pub u32); +impl AhbPeripheralSlavePortP5SlaveRule0 { + #[doc = "AIPS4 slaves."] #[must_use] #[inline(always)] - pub const fn gpio0(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; + pub const fn aips4_slaves(&self) -> Rule { + let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO0."] + #[doc = "AIPS4 slaves."] #[inline(always)] - pub const fn set_gpio0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_aips4_slaves(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "GPIO0 ALIAS."] + #[doc = "CDOG0."] #[must_use] #[inline(always)] - pub const fn gpio0_alias(&self) -> Rule { - let val = (self.0 >> 4usize) & 0x03; + pub const fn cdog0(&self) -> Rule { + let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO0 ALIAS."] + #[doc = "CDOG0."] #[inline(always)] - pub const fn set_gpio0_alias(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + pub const fn set_cdog0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } -} -impl Default for AhbPeripheral0memRule1 { + #[doc = "DEBUG_MAILBOX."] + #[must_use] #[inline(always)] - fn default() -> AhbPeripheral0memRule1 { - AhbPeripheral0memRule1(0) - } -} -impl core::fmt::Debug for AhbPeripheral0memRule1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbPeripheral0memRule1") - .field("gpio0", &self.gpio0()) - .field("gpio0_alias", &self.gpio0_alias()) - .finish() + pub const fn debug_mailbox(&self) -> Rule { + let val = (self.0 >> 24usize) & 0x03; + Rule::from_bits(val as u8) } -} -#[cfg(feature = "defmt")] -impl defmt::Format for AhbPeripheral0memRule1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "AhbPeripheral0memRule1 {{ gpio0: {:?}, gpio0_alias: {:?} }}", - self.gpio0(), - self.gpio0_alias() - ) + #[doc = "DEBUG_MAILBOX."] + #[inline(always)] + pub const fn set_debug_mailbox(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } -} -#[doc = "AHB Peripheral 0 Memory Rule 2."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbPeripheral0memRule2(pub u32); -impl AhbPeripheral0memRule2 { #[doc = "GPIO1."] #[must_use] #[inline(always)] pub const fn gpio1(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; + let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } #[doc = "GPIO1."] #[inline(always)] pub const fn set_gpio1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "GPIO1 ALIAS."] - #[must_use] - #[inline(always)] - pub const fn gpio1_alias(&self) -> Rule { - let val = (self.0 >> 4usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "GPIO1 ALIAS."] - #[inline(always)] - pub const fn set_gpio1_alias(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AhbPeripheral0memRule2 { +impl Default for AhbPeripheralSlavePortP5SlaveRule0 { #[inline(always)] - fn default() -> AhbPeripheral0memRule2 { - AhbPeripheral0memRule2(0) + fn default() -> AhbPeripheralSlavePortP5SlaveRule0 { + AhbPeripheralSlavePortP5SlaveRule0(0) } } -impl core::fmt::Debug for AhbPeripheral0memRule2 { +impl core::fmt::Debug for AhbPeripheralSlavePortP5SlaveRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbPeripheral0memRule2") + f.debug_struct("AhbPeripheralSlavePortP5SlaveRule0") + .field("aips4_slaves", &self.aips4_slaves()) + .field("cdog0", &self.cdog0()) + .field("debug_mailbox", &self.debug_mailbox()) .field("gpio1", &self.gpio1()) - .field("gpio1_alias", &self.gpio1_alias()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbPeripheral0memRule2 { +impl defmt::Format for AhbPeripheralSlavePortP5SlaveRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbPeripheral0memRule2 {{ gpio1: {:?}, gpio1_alias: {:?} }}", - self.gpio1(), - self.gpio1_alias() + "AhbPeripheralSlavePortP5SlaveRule0 {{ aips4_slaves: {:?}, cdog0: {:?}, debug_mailbox: {:?}, gpio1: {:?} }}", + self.aips4_slaves(), + self.cdog0(), + self.debug_mailbox(), + self.gpio1() ) } } -#[doc = "AHB Peripheral 0 Memory Rule 3."] +#[doc = "AHB Peripheral Slave Port 5 Slave Rule 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbPeripheral0memRule3(pub u32); -impl AhbPeripheral0memRule3 { +pub struct AhbPeripheralSlavePortP5SlaveRule1(pub u32); +impl AhbPeripheralSlavePortP5SlaveRule1 { #[doc = "GPIO2."] #[must_use] #[inline(always)] @@ -532,2173 +504,2375 @@ impl AhbPeripheral0memRule3 { pub const fn set_gpio2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "GPIO2 ALIAS."] + #[doc = "GPIO3."] #[must_use] #[inline(always)] - pub const fn gpio2_alias(&self) -> Rule { + pub const fn gpio3(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO2 ALIAS."] + #[doc = "GPIO3."] #[inline(always)] - pub const fn set_gpio2_alias(&mut self, val: Rule) { + pub const fn set_gpio3(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } + #[doc = "CDOG1."] + #[must_use] + #[inline(always)] + pub const fn cdog1(&self) -> Rule { + let val = (self.0 >> 8usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "CDOG1."] + #[inline(always)] + pub const fn set_cdog1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } } -impl Default for AhbPeripheral0memRule3 { +impl Default for AhbPeripheralSlavePortP5SlaveRule1 { #[inline(always)] - fn default() -> AhbPeripheral0memRule3 { - AhbPeripheral0memRule3(0) + fn default() -> AhbPeripheralSlavePortP5SlaveRule1 { + AhbPeripheralSlavePortP5SlaveRule1(0) } } -impl core::fmt::Debug for AhbPeripheral0memRule3 { +impl core::fmt::Debug for AhbPeripheralSlavePortP5SlaveRule1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbPeripheral0memRule3") + f.debug_struct("AhbPeripheralSlavePortP5SlaveRule1") .field("gpio2", &self.gpio2()) - .field("gpio2_alias", &self.gpio2_alias()) + .field("gpio3", &self.gpio3()) + .field("cdog1", &self.cdog1()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbPeripheral0memRule3 { +impl defmt::Format for AhbPeripheralSlavePortP5SlaveRule1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbPeripheral0memRule3 {{ gpio2: {:?}, gpio2_alias: {:?} }}", + "AhbPeripheralSlavePortP5SlaveRule1 {{ gpio2: {:?}, gpio3: {:?}, cdog1: {:?} }}", self.gpio2(), - self.gpio2_alias() + self.gpio3(), + self.cdog1() ) } } -#[doc = "AHB Peripheral 0 Memory Rule 4."] +#[doc = "AHB Secure Control Peripheral Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbPeripheral0memRule4(pub u32); -impl AhbPeripheral0memRule4 { - #[doc = "GPIO3."] - #[must_use] - #[inline(always)] - pub const fn gpio3(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "GPIO3."] - #[inline(always)] - pub const fn set_gpio3(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "GPIO3 ALIAS."] +pub struct AhbSecureCtrlPeripheralRule0(pub u32); +impl AhbSecureCtrlPeripheralRule0 { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn gpio3_alias(&self) -> Rule { - let val = (self.0 >> 4usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO3 ALIAS."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_gpio3_alias(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for AhbPeripheral0memRule4 { +impl Default for AhbSecureCtrlPeripheralRule0 { #[inline(always)] - fn default() -> AhbPeripheral0memRule4 { - AhbPeripheral0memRule4(0) + fn default() -> AhbSecureCtrlPeripheralRule0 { + AhbSecureCtrlPeripheralRule0(0) } } -impl core::fmt::Debug for AhbPeripheral0memRule4 { +impl core::fmt::Debug for AhbSecureCtrlPeripheralRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbPeripheral0memRule4") - .field("gpio3", &self.gpio3()) - .field("gpio3_alias", &self.gpio3_alias()) + f.debug_struct("AhbSecureCtrlPeripheralRule0") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbPeripheral0memRule4 { +impl defmt::Format for AhbSecureCtrlPeripheralRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbPeripheral0memRule4 {{ gpio3: {:?}, gpio3_alias: {:?} }}", - self.gpio3(), - self.gpio3_alias() + "AhbSecureCtrlPeripheralRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize) ) } } -#[doc = "AHB Peripheral 0 Memory Rule 5."] +#[doc = "AHB Slave Port 0 Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbPeripheral0memRule5(pub u32); -impl AhbPeripheral0memRule5 { - #[doc = "GPIO4."] - #[must_use] - #[inline(always)] - pub const fn gpio4(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "GPIO4."] - #[inline(always)] - pub const fn set_gpio4(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "GPIO4 ALIAS."] +pub struct AhbSlavePortP0SlaveRule(pub u32); +impl AhbSlavePortP0SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn gpio4_alias(&self) -> Rule { - let val = (self.0 >> 4usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO4 ALIAS."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_gpio4_alias(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for AhbPeripheral0memRule5 { +impl Default for AhbSlavePortP0SlaveRule { #[inline(always)] - fn default() -> AhbPeripheral0memRule5 { - AhbPeripheral0memRule5(0) + fn default() -> AhbSlavePortP0SlaveRule { + AhbSlavePortP0SlaveRule(0) } } -impl core::fmt::Debug for AhbPeripheral0memRule5 { +impl core::fmt::Debug for AhbSlavePortP0SlaveRule { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbPeripheral0memRule5") - .field("gpio4", &self.gpio4()) - .field("gpio4_alias", &self.gpio4_alias()) + f.debug_struct("AhbSlavePortP0SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbPeripheral0memRule5 { +impl defmt::Format for AhbSlavePortP0SlaveRule { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbPeripheral0memRule5 {{ gpio4: {:?}, gpio4_alias: {:?} }}", - self.gpio4(), - self.gpio4_alias() + "AhbSlavePortP0SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) ) } } -#[doc = "AHB Secure Control Peripheral Rule."] +#[doc = "AHB Slave Port 1 Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbSecureCtrlMemRule0(pub u32); -impl AhbSecureCtrlMemRule0 { - #[doc = "AHBSC."] +pub struct AhbSlavePortP1SlaveRule(pub u32); +impl AhbSlavePortP1SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 4usize); + assert!(n < 8usize); let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "AHBSC."] + #[doc = "Rule 0."] #[inline(always)] pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 4usize); + assert!(n < 8usize); let offs = 0usize + n * 4usize; self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for AhbSecureCtrlMemRule0 { +impl Default for AhbSlavePortP1SlaveRule { #[inline(always)] - fn default() -> AhbSecureCtrlMemRule0 { - AhbSecureCtrlMemRule0(0) + fn default() -> AhbSlavePortP1SlaveRule { + AhbSlavePortP1SlaveRule(0) } } -impl core::fmt::Debug for AhbSecureCtrlMemRule0 { +impl core::fmt::Debug for AhbSlavePortP1SlaveRule { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbSecureCtrlMemRule0") + f.debug_struct("AhbSlavePortP1SlaveRule") .field("rule[0]", &self.rule(0usize)) .field("rule[1]", &self.rule(1usize)) .field("rule[2]", &self.rule(2usize)) .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbSecureCtrlMemRule0 { +impl defmt::Format for AhbSlavePortP1SlaveRule { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbSecureCtrlMemRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", + "AhbSlavePortP1SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", self.rule(0usize), self.rule(1usize), self.rule(2usize), - self.rule(3usize) + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) ) } } -#[doc = "AHB Slave Port 5 Rule Register."] +#[doc = "AHB Slave Port 2 Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AhbSlavePortP5slaveRule0(pub u32); -impl AhbSlavePortP5slaveRule0 { - #[doc = "CDOG0."] +pub struct AhbSlavePortP2SlaveRule(pub u32); +impl AhbSlavePortP2SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn cdog0(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CDOG0."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_cdog0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } - #[doc = "CDOG1."] +} +impl Default for AhbSlavePortP2SlaveRule { + #[inline(always)] + fn default() -> AhbSlavePortP2SlaveRule { + AhbSlavePortP2SlaveRule(0) + } +} +impl core::fmt::Debug for AhbSlavePortP2SlaveRule { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AhbSlavePortP2SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for AhbSlavePortP2SlaveRule { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AhbSlavePortP2SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) + ) + } +} +#[doc = "AHB Slave Port 3 Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AhbSlavePortP3SlaveRule(pub u32); +impl AhbSlavePortP3SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn cdog1(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CDOG1."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_cdog1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } - #[doc = "DEBUG_MAILBOX."] +} +impl Default for AhbSlavePortP3SlaveRule { + #[inline(always)] + fn default() -> AhbSlavePortP3SlaveRule { + AhbSlavePortP3SlaveRule(0) + } +} +impl core::fmt::Debug for AhbSlavePortP3SlaveRule { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AhbSlavePortP3SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for AhbSlavePortP3SlaveRule { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AhbSlavePortP3SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) + ) + } +} +#[doc = "AHB Slave Port 4 Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AhbSlavePortP4SlaveRule(pub u32); +impl AhbSlavePortP4SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn debug_mailbox(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DEBUG_MAILBOX."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_debug_mailbox(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); + } +} +impl Default for AhbSlavePortP4SlaveRule { + #[inline(always)] + fn default() -> AhbSlavePortP4SlaveRule { + AhbSlavePortP4SlaveRule(0) + } +} +impl core::fmt::Debug for AhbSlavePortP4SlaveRule { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AhbSlavePortP4SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for AhbSlavePortP4SlaveRule { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AhbSlavePortP4SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) + ) } - #[doc = "Rule 6."] +} +#[doc = "AHB Slave Port 6 Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AhbSlavePortP6SlaveRule(pub u32); +impl AhbSlavePortP6SlaveRule { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn mau0(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "Rule 6."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_mau0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for AhbSlavePortP5slaveRule0 { +impl Default for AhbSlavePortP6SlaveRule { #[inline(always)] - fn default() -> AhbSlavePortP5slaveRule0 { - AhbSlavePortP5slaveRule0(0) + fn default() -> AhbSlavePortP6SlaveRule { + AhbSlavePortP6SlaveRule(0) } } -impl core::fmt::Debug for AhbSlavePortP5slaveRule0 { +impl core::fmt::Debug for AhbSlavePortP6SlaveRule { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AhbSlavePortP5slaveRule0") - .field("cdog0", &self.cdog0()) - .field("cdog1", &self.cdog1()) - .field("debug_mailbox", &self.debug_mailbox()) - .field("mau0", &self.mau0()) + f.debug_struct("AhbSlavePortP6SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AhbSlavePortP5slaveRule0 { +impl defmt::Format for AhbSlavePortP6SlaveRule { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AhbSlavePortP5slaveRule0 {{ cdog0: {:?}, cdog1: {:?}, debug_mailbox: {:?}, mau0: {:?} }}", - self.cdog0(), - self.cdog1(), - self.debug_mailbox(), - self.mau0() + "AhbSlavePortP6SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) + ) + } +} +#[doc = "AHB Slave Port 6 Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AhbSlavePortP7SlaveRule(pub u32); +impl AhbSlavePortP7SlaveRule { + #[doc = "Rule 0."] + #[must_use] + #[inline(always)] + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "Rule 0."] + #[inline(always)] + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); + } +} +impl Default for AhbSlavePortP7SlaveRule { + #[inline(always)] + fn default() -> AhbSlavePortP7SlaveRule { + AhbSlavePortP7SlaveRule(0) + } +} +impl core::fmt::Debug for AhbSlavePortP7SlaveRule { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AhbSlavePortP7SlaveRule") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for AhbSlavePortP7SlaveRule { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AhbSlavePortP7SlaveRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) ) } } #[doc = "AIPS Bridge Group 0 Memory Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup0memRule0(pub u32); -impl AipsBridgeGroup0memRule0 { - #[doc = "EWM0."] +pub struct AipsBridgeGroup0MemRule0(pub u32); +impl AipsBridgeGroup0MemRule0 { + #[doc = "eDMA_0_MP."] #[must_use] #[inline(always)] - pub const fn ewm0(&self) -> Rule { + pub const fn e_dma_0_mp(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "EWM0."] + #[doc = "eDMA_0_MP."] #[inline(always)] - pub const fn set_ewm0(&mut self, val: Rule) { + pub const fn set_e_dma_0_mp(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "ROMCP."] + #[doc = "eDMA_0_TCD0."] #[must_use] #[inline(always)] - pub const fn romcp(&self) -> Rule { + pub const fn e_dma_0_tcd0(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "ROMCP."] + #[doc = "eDMA_0_TCD0."] #[inline(always)] - pub const fn set_romcp(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "PKC0."] + #[doc = "eDMA_0_TCD1."] #[must_use] #[inline(always)] - pub const fn pkc0(&self) -> Rule { + pub const fn e_dma_0_tcd1(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PKC0."] + #[doc = "eDMA_0_TCD1."] #[inline(always)] - pub const fn set_pkc0(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "DMA_1_MP."] + #[doc = "eDMA_0_TCD2."] #[must_use] #[inline(always)] - pub const fn dma_1_mp(&self) -> Rule { + pub const fn e_dma_0_tcd2(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_1_MP."] + #[doc = "eDMA_0_TCD2."] #[inline(always)] - pub const fn set_dma_1_mp(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "DMA_1_CH0."] + #[doc = "FLEXSPI0 Registers."] #[must_use] #[inline(always)] - pub const fn dma_1_ch0(&self) -> Rule { + pub const fn e_dma_0_tcd3(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_1_CH0."] + #[doc = "FLEXSPI0 Registers."] #[inline(always)] - pub const fn set_dma_1_ch0(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd3(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "DMA_1_CH1."] + #[doc = "eDMA_0_TCD4 (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_1_ch1(&self) -> Rule { + pub const fn e_dma_0_tcd4(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_1_CH1."] + #[doc = "eDMA_0_TCD4 (Reserved)."] #[inline(always)] - pub const fn set_dma_1_ch1(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd4(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "DMA_1_CH2."] + #[doc = "eDMA_0_TCD5 (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_1_ch2(&self) -> Rule { + pub const fn e_dma_0_tcd5(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_1_CH2."] + #[doc = "eDMA_0_TCD5 (Reserved)."] #[inline(always)] - pub const fn set_dma_1_ch2(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd5(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "DMA_1_CH3."] + #[doc = "eDMA_0_TCD6 (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_1_ch3(&self) -> Rule { + pub const fn e_dma_0_tcd6(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_1_CH3."] + #[doc = "eDMA_0_TCD6 (Reserved)."] #[inline(always)] - pub const fn set_dma_1_ch3(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd6(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup0memRule0 { +impl Default for AipsBridgeGroup0MemRule0 { #[inline(always)] - fn default() -> AipsBridgeGroup0memRule0 { - AipsBridgeGroup0memRule0(0) + fn default() -> AipsBridgeGroup0MemRule0 { + AipsBridgeGroup0MemRule0(0) } } -impl core::fmt::Debug for AipsBridgeGroup0memRule0 { +impl core::fmt::Debug for AipsBridgeGroup0MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup0memRule0") - .field("ewm0", &self.ewm0()) - .field("romcp", &self.romcp()) - .field("pkc0", &self.pkc0()) - .field("dma_1_mp", &self.dma_1_mp()) - .field("dma_1_ch0", &self.dma_1_ch0()) - .field("dma_1_ch1", &self.dma_1_ch1()) - .field("dma_1_ch2", &self.dma_1_ch2()) - .field("dma_1_ch3", &self.dma_1_ch3()) + f.debug_struct("AipsBridgeGroup0MemRule0") + .field("e_dma_0_mp", &self.e_dma_0_mp()) + .field("e_dma_0_tcd0", &self.e_dma_0_tcd0()) + .field("e_dma_0_tcd1", &self.e_dma_0_tcd1()) + .field("e_dma_0_tcd2", &self.e_dma_0_tcd2()) + .field("e_dma_0_tcd3", &self.e_dma_0_tcd3()) + .field("e_dma_0_tcd4", &self.e_dma_0_tcd4()) + .field("e_dma_0_tcd5", &self.e_dma_0_tcd5()) + .field("e_dma_0_tcd6", &self.e_dma_0_tcd6()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup0memRule0 { +impl defmt::Format for AipsBridgeGroup0MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup0memRule0 {{ ewm0: {:?}, romcp: {:?}, pkc0: {:?}, dma_1_mp: {:?}, dma_1_ch0: {:?}, dma_1_ch1: {:?}, dma_1_ch2: {:?}, dma_1_ch3: {:?} }}", - self.ewm0(), - self.romcp(), - self.pkc0(), - self.dma_1_mp(), - self.dma_1_ch0(), - self.dma_1_ch1(), - self.dma_1_ch2(), - self.dma_1_ch3() + "AipsBridgeGroup0MemRule0 {{ e_dma_0_mp: {:?}, e_dma_0_tcd0: {:?}, e_dma_0_tcd1: {:?}, e_dma_0_tcd2: {:?}, e_dma_0_tcd3: {:?}, e_dma_0_tcd4: {:?}, e_dma_0_tcd5: {:?}, e_dma_0_tcd6: {:?} }}", + self.e_dma_0_mp(), + self.e_dma_0_tcd0(), + self.e_dma_0_tcd1(), + self.e_dma_0_tcd2(), + self.e_dma_0_tcd3(), + self.e_dma_0_tcd4(), + self.e_dma_0_tcd5(), + self.e_dma_0_tcd6() ) } } #[doc = "AIPS Bridge Group 0 Memory Rule 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup0memRule1(pub u32); -impl AipsBridgeGroup0memRule1 { - #[doc = "ENET0_0."] - #[must_use] - #[inline(always)] - pub const fn enet0_0(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "ENET0_0."] - #[inline(always)] - pub const fn set_enet0_0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); - } - #[doc = "ENET0_1."] - #[must_use] - #[inline(always)] - pub const fn enet0_1(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "ENET0_1."] - #[inline(always)] - pub const fn set_enet0_1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); - } - #[doc = "eSPI."] - #[must_use] - #[inline(always)] - pub const fn e_spi(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "eSPI."] - #[inline(always)] - pub const fn set_e_spi(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); - } -} -impl Default for AipsBridgeGroup0memRule1 { - #[inline(always)] - fn default() -> AipsBridgeGroup0memRule1 { - AipsBridgeGroup0memRule1(0) - } -} -impl core::fmt::Debug for AipsBridgeGroup0memRule1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup0memRule1") - .field("enet0_0", &self.enet0_0()) - .field("enet0_1", &self.enet0_1()) - .field("e_spi", &self.e_spi()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup0memRule1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "AipsBridgeGroup0memRule1 {{ enet0_0: {:?}, enet0_1: {:?}, e_spi: {:?} }}", - self.enet0_0(), - self.enet0_1(), - self.e_spi() - ) - } -} -#[doc = "AIPS Bridge Group 1 Memory Rule 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup1memRule0(pub u32); -impl AipsBridgeGroup1memRule0 { - #[doc = "FLEXSPI0."] +pub struct AipsBridgeGroup0MemRule1(pub u32); +impl AipsBridgeGroup0MemRule1 { + #[doc = "eDMA_0_TCD7 (Reserved)."] #[must_use] #[inline(always)] - pub const fn flexspi0(&self) -> Rule { + pub const fn e_dma_0_tcd7(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "FLEXSPI0."] + #[doc = "eDMA_0_TCD7 (Reserved)."] #[inline(always)] - pub const fn set_flexspi0(&mut self, val: Rule) { + pub const fn set_e_dma_0_tcd7(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "LPSPI2."] + #[doc = "AOI0."] #[must_use] #[inline(always)] - pub const fn lpspi2(&self) -> Rule { + pub const fn aoi0(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPSPI2."] + #[doc = "AOI0."] #[inline(always)] - pub const fn set_lpspi2(&mut self, val: Rule) { + pub const fn set_aoi0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "LPSPI3."] + #[doc = "CRC0."] #[must_use] #[inline(always)] - pub const fn lpspi3(&self) -> Rule { + pub const fn crc0(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPSPI3."] + #[doc = "CRC0."] #[inline(always)] - pub const fn set_lpspi3(&mut self, val: Rule) { + pub const fn set_crc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "LPSPI4."] + #[doc = "CMC0."] #[must_use] #[inline(always)] - pub const fn lpspi4(&self) -> Rule { + pub const fn cmc0(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPSPI4."] + #[doc = "CMC0."] #[inline(always)] - pub const fn set_lpspi4(&mut self, val: Rule) { + pub const fn set_cmc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "LPSPI5."] - #[must_use] - #[inline(always)] - pub const fn lpspi5(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "LPSPI5."] - #[inline(always)] - pub const fn set_lpspi5(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); - } -} -impl Default for AipsBridgeGroup1memRule0 { - #[inline(always)] - fn default() -> AipsBridgeGroup1memRule0 { - AipsBridgeGroup1memRule0(0) - } -} -impl core::fmt::Debug for AipsBridgeGroup1memRule0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup1memRule0") - .field("flexspi0", &self.flexspi0()) - .field("lpspi2", &self.lpspi2()) - .field("lpspi3", &self.lpspi3()) - .field("lpspi4", &self.lpspi4()) - .field("lpspi5", &self.lpspi5()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup1memRule0 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "AipsBridgeGroup1memRule0 {{ flexspi0: {:?}, lpspi2: {:?}, lpspi3: {:?}, lpspi4: {:?}, lpspi5: {:?} }}", - self.flexspi0(), - self.lpspi2(), - self.lpspi3(), - self.lpspi4(), - self.lpspi5() - ) - } -} -#[doc = "AIPS Bridge Group 1 Memory Rule 1."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup1memRule1(pub u32); -impl AipsBridgeGroup1memRule1 { - #[doc = "SPI_FILETER0."] + #[doc = "ERM0."] #[must_use] #[inline(always)] - pub const fn spi_fileter0(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "SPI_FILETER0."] - #[inline(always)] - pub const fn set_spi_fileter0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); - } - #[doc = "10BASE_T1S0."] - #[must_use] - #[inline(always)] - pub const fn t1s0(&self) -> Rule { + pub const fn erm0(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "10BASE_T1S0."] + #[doc = "ERM0."] #[inline(always)] - pub const fn set_t1s0(&mut self, val: Rule) { + pub const fn set_erm0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "USB1."] + #[doc = "MBC0."] #[must_use] #[inline(always)] - pub const fn usb1(&self) -> Rule { + pub const fn mbc0(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "USB1."] + #[doc = "MBC0."] #[inline(always)] - pub const fn set_usb1(&mut self, val: Rule) { + pub const fn set_mbc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "USB1_PHY."] + #[doc = "SCG0."] #[must_use] #[inline(always)] - pub const fn usb1_phy(&self) -> Rule { + pub const fn scg0(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "USB1_PHY."] + #[doc = "SCG0."] #[inline(always)] - pub const fn set_usb1_phy(&mut self, val: Rule) { + pub const fn set_scg0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup1memRule1 { +impl Default for AipsBridgeGroup0MemRule1 { #[inline(always)] - fn default() -> AipsBridgeGroup1memRule1 { - AipsBridgeGroup1memRule1(0) + fn default() -> AipsBridgeGroup0MemRule1 { + AipsBridgeGroup0MemRule1(0) } } -impl core::fmt::Debug for AipsBridgeGroup1memRule1 { +impl core::fmt::Debug for AipsBridgeGroup0MemRule1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup1memRule1") - .field("spi_fileter0", &self.spi_fileter0()) - .field("t1s0", &self.t1s0()) - .field("usb1", &self.usb1()) - .field("usb1_phy", &self.usb1_phy()) + f.debug_struct("AipsBridgeGroup0MemRule1") + .field("e_dma_0_tcd7", &self.e_dma_0_tcd7()) + .field("aoi0", &self.aoi0()) + .field("crc0", &self.crc0()) + .field("cmc0", &self.cmc0()) + .field("erm0", &self.erm0()) + .field("mbc0", &self.mbc0()) + .field("scg0", &self.scg0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup1memRule1 { +impl defmt::Format for AipsBridgeGroup0MemRule1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup1memRule1 {{ spi_fileter0: {:?}, t1s0: {:?}, usb1: {:?}, usb1_phy: {:?} }}", - self.spi_fileter0(), - self.t1s0(), - self.usb1(), - self.usb1_phy() - ) - } -} -#[doc = "AIPS Bridge Group 2 Rule 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule0(pub u32); -impl AipsBridgeGroup2memRule0 { - #[doc = "DMA_0_MP."] - #[must_use] - #[inline(always)] - pub const fn dma_0_mp(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "DMA_0_MP."] - #[inline(always)] - pub const fn set_dma_0_mp(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + "AipsBridgeGroup0MemRule1 {{ e_dma_0_tcd7: {:?}, aoi0: {:?}, crc0: {:?}, cmc0: {:?}, erm0: {:?}, mbc0: {:?}, scg0: {:?} }}", + self.e_dma_0_tcd7(), + self.aoi0(), + self.crc0(), + self.cmc0(), + self.erm0(), + self.mbc0(), + self.scg0() + ) } - #[doc = "DMA_0_CH0."] +} +#[doc = "AIPS Bridge Group 0 Memory Rule 2."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AipsBridgeGroup0MemRule2(pub u32); +impl AipsBridgeGroup0MemRule2 { + #[doc = "SYSCON."] #[must_use] #[inline(always)] - pub const fn dma_0_ch0(&self) -> Rule { + pub const fn syscon(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH0."] + #[doc = "SYSCON."] #[inline(always)] - pub const fn set_dma_0_ch0(&mut self, val: Rule) { + pub const fn set_syscon(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "DMA_0_CH1."] + #[doc = "WUU0."] #[must_use] #[inline(always)] - pub const fn dma_0_ch1(&self) -> Rule { + pub const fn wuu0(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH1."] + #[doc = "WUU0."] #[inline(always)] - pub const fn set_dma_0_ch1(&mut self, val: Rule) { + pub const fn set_wuu0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "DMA_0_CH2."] - #[must_use] - #[inline(always)] - pub const fn dma_0_ch2(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "DMA_0_CH2."] - #[inline(always)] - pub const fn set_dma_0_ch2(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); - } - #[doc = "DMA_0_CH3."] + #[doc = "FMC0."] #[must_use] #[inline(always)] - pub const fn dma_0_ch3(&self) -> Rule { + pub const fn fmc0(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH3."] + #[doc = "FMC0."] #[inline(always)] - pub const fn set_dma_0_ch3(&mut self, val: Rule) { + pub const fn set_fmc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "DMA_0_CH4."] + #[doc = "FMU0."] #[must_use] #[inline(always)] - pub const fn dma_0_ch4(&self) -> Rule { + pub const fn fmu0(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH4."] + #[doc = "FMU0."] #[inline(always)] - pub const fn set_dma_0_ch4(&mut self, val: Rule) { + pub const fn set_fmu0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "DMA_0_CH5."] + #[doc = "FMU0_TST."] #[must_use] #[inline(always)] - pub const fn dma_0_ch5(&self) -> Rule { + pub const fn fmu0_tst(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH5."] + #[doc = "FMU0_TST."] #[inline(always)] - pub const fn set_dma_0_ch5(&mut self, val: Rule) { + pub const fn set_fmu0_tst(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "DMA_0_CH6."] + #[doc = "BCANXL (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_0_ch6(&self) -> Rule { + pub const fn bcanxl(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH6."] + #[doc = "BCANXL (Reserved)."] #[inline(always)] - pub const fn set_dma_0_ch6(&mut self, val: Rule) { + pub const fn set_bcanxl(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup2memRule0 { +impl Default for AipsBridgeGroup0MemRule2 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule0 { - AipsBridgeGroup2memRule0(0) + fn default() -> AipsBridgeGroup0MemRule2 { + AipsBridgeGroup0MemRule2(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule0 { +impl core::fmt::Debug for AipsBridgeGroup0MemRule2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule0") - .field("dma_0_mp", &self.dma_0_mp()) - .field("dma_0_ch0", &self.dma_0_ch0()) - .field("dma_0_ch1", &self.dma_0_ch1()) - .field("dma_0_ch2", &self.dma_0_ch2()) - .field("dma_0_ch3", &self.dma_0_ch3()) - .field("dma_0_ch4", &self.dma_0_ch4()) - .field("dma_0_ch5", &self.dma_0_ch5()) - .field("dma_0_ch6", &self.dma_0_ch6()) + f.debug_struct("AipsBridgeGroup0MemRule2") + .field("syscon", &self.syscon()) + .field("wuu0", &self.wuu0()) + .field("fmc0", &self.fmc0()) + .field("fmu0", &self.fmu0()) + .field("fmu0_tst", &self.fmu0_tst()) + .field("bcanxl", &self.bcanxl()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule0 { +impl defmt::Format for AipsBridgeGroup0MemRule2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule0 {{ dma_0_mp: {:?}, dma_0_ch0: {:?}, dma_0_ch1: {:?}, dma_0_ch2: {:?}, dma_0_ch3: {:?}, dma_0_ch4: {:?}, dma_0_ch5: {:?}, dma_0_ch6: {:?} }}", - self.dma_0_mp(), - self.dma_0_ch0(), - self.dma_0_ch1(), - self.dma_0_ch2(), - self.dma_0_ch3(), - self.dma_0_ch4(), - self.dma_0_ch5(), - self.dma_0_ch6() + "AipsBridgeGroup0MemRule2 {{ syscon: {:?}, wuu0: {:?}, fmc0: {:?}, fmu0: {:?}, fmu0_tst: {:?}, bcanxl: {:?} }}", + self.syscon(), + self.wuu0(), + self.fmc0(), + self.fmu0(), + self.fmu0_tst(), + self.bcanxl() ) } } -#[doc = "AIPS Bridge Group 2 Rule 1."] +#[doc = "AIPS Bridge Group 0 Memory Rule 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule1(pub u32); -impl AipsBridgeGroup2memRule1 { - #[doc = "DMA_0_CH7."] +pub struct AipsBridgeGroup0MemRule3(pub u32); +impl AipsBridgeGroup0MemRule3 { + #[doc = "CANDMA (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_0_ch7(&self) -> Rule { + pub const fn candma(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH7."] + #[doc = "CANDMA (Reserved)."] #[inline(always)] - pub const fn set_dma_0_ch7(&mut self, val: Rule) { + pub const fn set_candma(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "DMA_0_CH8."] + #[doc = "FLEXIO (Reserved)."] #[must_use] #[inline(always)] - pub const fn dma_0_ch8(&self) -> Rule { + pub const fn flexio(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH8."] + #[doc = "FLEXIO (Reserved)."] #[inline(always)] - pub const fn set_dma_0_ch8(&mut self, val: Rule) { + pub const fn set_flexio(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "DMA_0_CH9."] + #[doc = "LPI2C0."] #[must_use] #[inline(always)] - pub const fn dma_0_ch9(&self) -> Rule { + pub const fn lpi2c0(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH9."] + #[doc = "LPI2C0."] #[inline(always)] - pub const fn set_dma_0_ch9(&mut self, val: Rule) { + pub const fn set_lpi2c0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "DMA_0_CH10."] + #[doc = "LPI2C1."] #[must_use] #[inline(always)] - pub const fn dma_0_ch10(&self) -> Rule { + pub const fn lpi2c1(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH10."] + #[doc = "LPI2C1."] #[inline(always)] - pub const fn set_dma_0_ch10(&mut self, val: Rule) { + pub const fn set_lpi2c1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "DMA_0_CH11."] + #[doc = "LPSPI0."] #[must_use] #[inline(always)] - pub const fn dma_0_ch11(&self) -> Rule { + pub const fn lpspi0(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DMA_0_CH11."] + #[doc = "LPSPI0."] #[inline(always)] - pub const fn set_dma_0_ch11(&mut self, val: Rule) { + pub const fn set_lpspi0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } + #[doc = "LPSPI1."] + #[must_use] + #[inline(always)] + pub const fn lpspi1(&self) -> Rule { + let val = (self.0 >> 20usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "LPSPI1."] + #[inline(always)] + pub const fn set_lpspi1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + } + #[doc = "LPSPI2 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn lpspi2(&self) -> Rule { + let val = (self.0 >> 24usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "LPSPI2 (Reserved)."] + #[inline(always)] + pub const fn set_lpspi2(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + } + #[doc = "LPUART0."] + #[must_use] + #[inline(always)] + pub const fn lpuart0(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "LPUART0."] + #[inline(always)] + pub const fn set_lpuart0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule1 { +impl Default for AipsBridgeGroup0MemRule3 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule1 { - AipsBridgeGroup2memRule1(0) + fn default() -> AipsBridgeGroup0MemRule3 { + AipsBridgeGroup0MemRule3(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule1 { +impl core::fmt::Debug for AipsBridgeGroup0MemRule3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule1") - .field("dma_0_ch7", &self.dma_0_ch7()) - .field("dma_0_ch8", &self.dma_0_ch8()) - .field("dma_0_ch9", &self.dma_0_ch9()) - .field("dma_0_ch10", &self.dma_0_ch10()) - .field("dma_0_ch11", &self.dma_0_ch11()) + f.debug_struct("AipsBridgeGroup0MemRule3") + .field("candma", &self.candma()) + .field("flexio", &self.flexio()) + .field("lpi2c0", &self.lpi2c0()) + .field("lpi2c1", &self.lpi2c1()) + .field("lpspi0", &self.lpspi0()) + .field("lpspi1", &self.lpspi1()) + .field("lpspi2", &self.lpspi2()) + .field("lpuart0", &self.lpuart0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule1 { +impl defmt::Format for AipsBridgeGroup0MemRule3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule1 {{ dma_0_ch7: {:?}, dma_0_ch8: {:?}, dma_0_ch9: {:?}, dma_0_ch10: {:?}, dma_0_ch11: {:?} }}", - self.dma_0_ch7(), - self.dma_0_ch8(), - self.dma_0_ch9(), - self.dma_0_ch10(), - self.dma_0_ch11() + "AipsBridgeGroup0MemRule3 {{ candma: {:?}, flexio: {:?}, lpi2c0: {:?}, lpi2c1: {:?}, lpspi0: {:?}, lpspi1: {:?}, lpspi2: {:?}, lpuart0: {:?} }}", + self.candma(), + self.flexio(), + self.lpi2c0(), + self.lpi2c1(), + self.lpspi0(), + self.lpspi1(), + self.lpspi2(), + self.lpuart0() ) } } -#[doc = "AIPS Bridge Group 2 Rule 10."] +#[doc = "AIPS Bridge Group 2 Memory Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule10(pub u32); -impl AipsBridgeGroup2memRule10 { - #[doc = "CAN1 Region 0."] +pub struct AipsBridgeGroup2MemRule0(pub u32); +impl AipsBridgeGroup2MemRule0 { + #[doc = "LPUART1."] #[must_use] #[inline(always)] - pub const fn can1_region0(&self) -> Rule { + pub const fn lpuart1(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN1 Region 0."] + #[doc = "LPUART1."] #[inline(always)] - pub const fn set_can1_region0(&mut self, val: Rule) { + pub const fn set_lpuart1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "CAN1 Region 1."] + #[doc = "LPUART2 (Reserved)."] #[must_use] #[inline(always)] - pub const fn can1_region1(&self) -> Rule { + pub const fn lpuart2(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN1 Region 1."] + #[doc = "LPUART2 (Reserved)."] #[inline(always)] - pub const fn set_can1_region1(&mut self, val: Rule) { + pub const fn set_lpuart2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "CAN1 Region 2."] + #[doc = "LPUART3 (Reserved)."] #[must_use] #[inline(always)] - pub const fn can1_region2(&self) -> Rule { + pub const fn lpuart3(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN1 Region 2."] + #[doc = "LPUART3 (Reserved)."] #[inline(always)] - pub const fn set_can1_region2(&mut self, val: Rule) { + pub const fn set_lpuart3(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "CAN1 Region 3."] + #[doc = "LPUART4 (Reserved)."] #[must_use] #[inline(always)] - pub const fn can1_region3(&self) -> Rule { + pub const fn lpuart4(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN1 Region 3."] + #[doc = "LPUART4 (Reserved)."] #[inline(always)] - pub const fn set_can1_region3(&mut self, val: Rule) { + pub const fn set_lpuart4(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "LPI2C2."] + #[doc = "USB_FS_OTG (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpi2c2(&self) -> Rule { + pub const fn usb_fs_otg(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPI2C2."] + #[doc = "USB_FS_OTG (Reserved)."] #[inline(always)] - pub const fn set_lpi2c2(&mut self, val: Rule) { + pub const fn set_usb_fs_otg(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "LPI2C3."] + #[doc = "USB_FS_DCD (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpi2c3(&self) -> Rule { + pub const fn usb_fs_dcd(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPI2C3."] + #[doc = "USB_FS_DCD (Reserved)."] #[inline(always)] - pub const fn set_lpi2c3(&mut self, val: Rule) { + pub const fn set_usb_fs_dcd(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "LPI2C4."] + #[doc = "USB_TYPEC_PD (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpi2c4(&self) -> Rule { + pub const fn usb_typec_pd(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPI2C4."] + #[doc = "USB_TYPEC_PD (Reserved)."] #[inline(always)] - pub const fn set_lpi2c4(&mut self, val: Rule) { + pub const fn set_usb_typec_pd(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } + #[doc = "QUAD_DECODER0 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn quad_decoder0(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "QUAD_DECODER0 (Reserved)."] + #[inline(always)] + pub const fn set_quad_decoder0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule10 { +impl Default for AipsBridgeGroup2MemRule0 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule10 { - AipsBridgeGroup2memRule10(0) + fn default() -> AipsBridgeGroup2MemRule0 { + AipsBridgeGroup2MemRule0(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule10 { +impl core::fmt::Debug for AipsBridgeGroup2MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule10") - .field("can1_region0", &self.can1_region0()) - .field("can1_region1", &self.can1_region1()) - .field("can1_region2", &self.can1_region2()) - .field("can1_region3", &self.can1_region3()) - .field("lpi2c2", &self.lpi2c2()) - .field("lpi2c3", &self.lpi2c3()) - .field("lpi2c4", &self.lpi2c4()) + f.debug_struct("AipsBridgeGroup2MemRule0") + .field("lpuart1", &self.lpuart1()) + .field("lpuart2", &self.lpuart2()) + .field("lpuart3", &self.lpuart3()) + .field("lpuart4", &self.lpuart4()) + .field("usb_fs_otg", &self.usb_fs_otg()) + .field("usb_fs_dcd", &self.usb_fs_dcd()) + .field("usb_typec_pd", &self.usb_typec_pd()) + .field("quad_decoder0", &self.quad_decoder0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule10 { +impl defmt::Format for AipsBridgeGroup2MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule10 {{ can1_region0: {:?}, can1_region1: {:?}, can1_region2: {:?}, can1_region3: {:?}, lpi2c2: {:?}, lpi2c3: {:?}, lpi2c4: {:?} }}", - self.can1_region0(), - self.can1_region1(), - self.can1_region2(), - self.can1_region3(), - self.lpi2c2(), - self.lpi2c3(), - self.lpi2c4() + "AipsBridgeGroup2MemRule0 {{ lpuart1: {:?}, lpuart2: {:?}, lpuart3: {:?}, lpuart4: {:?}, usb_fs_otg: {:?}, usb_fs_dcd: {:?}, usb_typec_pd: {:?}, quad_decoder0: {:?} }}", + self.lpuart1(), + self.lpuart2(), + self.lpuart3(), + self.lpuart4(), + self.usb_fs_otg(), + self.usb_fs_dcd(), + self.usb_typec_pd(), + self.quad_decoder0() ) } } -#[doc = "AIPS Bridge Group 2 Rule 11."] +#[doc = "AIPS Bridge Group 2 Memory Rule 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule11(pub u32); -impl AipsBridgeGroup2memRule11 { - #[doc = "LPUART5."] +pub struct AipsBridgeGroup2MemRule1(pub u32); +impl AipsBridgeGroup2MemRule1 { + #[doc = "QUAD_DECODER1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpuart5(&self) -> Rule { - let val = (self.0 >> 8usize) & 0x03; + pub const fn quad_decoder1(&self) -> Rule { + let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPUART5."] + #[doc = "QUAD_DECODER1 (Reserved)."] #[inline(always)] - pub const fn set_lpuart5(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + pub const fn set_quad_decoder1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "I3C3."] + #[doc = "FLEXPWM0."] #[must_use] #[inline(always)] - pub const fn i3c3(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; + pub const fn flexpwm0(&self) -> Rule { + let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "I3C3."] + #[doc = "FLEXPWM0."] #[inline(always)] - pub const fn set_i3c3(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + pub const fn set_flexpwm0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "GPIO5."] + #[doc = "FLEXPWM1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn gpio5(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; + pub const fn flexpwm1(&self) -> Rule { + let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO5."] + #[doc = "FLEXPWM1 (Reserved)."] #[inline(always)] - pub const fn set_gpio5(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + pub const fn set_flexpwm1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } -} -impl Default for AipsBridgeGroup2memRule11 { + #[doc = "LPTMR0 (Reserved)."] + #[must_use] #[inline(always)] - fn default() -> AipsBridgeGroup2memRule11 { - AipsBridgeGroup2memRule11(0) - } -} -impl core::fmt::Debug for AipsBridgeGroup2memRule11 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule11") - .field("lpuart5", &self.lpuart5()) - .field("i3c3", &self.i3c3()) - .field("gpio5", &self.gpio5()) - .finish() + pub const fn lptmr0(&self) -> Rule { + let val = (self.0 >> 12usize) & 0x03; + Rule::from_bits(val as u8) } -} -#[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule11 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "AipsBridgeGroup2memRule11 {{ lpuart5: {:?}, i3c3: {:?}, gpio5: {:?} }}", - self.lpuart5(), - self.i3c3(), - self.gpio5() - ) + #[doc = "LPTMR0 (Reserved)."] + #[inline(always)] + pub const fn set_lptmr0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } -} -#[doc = "AIPS Bridge Group 2 Rule 12."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule12(pub u32); -impl AipsBridgeGroup2memRule12 { - #[doc = "GPIO5_ALIAS."] + #[doc = "LPTMR1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn gpio5_alias(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; + pub const fn lptmr1(&self) -> Rule { + let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GPIO5_ALIAS."] + #[doc = "LPTMR1 (Reserved)."] #[inline(always)] - pub const fn set_gpio5_alias(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_lptmr1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "PORT5."] + #[doc = "OSTIMER0."] #[must_use] #[inline(always)] - pub const fn port5(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; + pub const fn ostimer0(&self) -> Rule { + let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PORT5."] + #[doc = "OSTIMER0."] #[inline(always)] - pub const fn set_port5(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + pub const fn set_ostimer0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "DGDET0."] + #[doc = "WAKE_TIMER (Reserved)."] #[must_use] #[inline(always)] - pub const fn dgdet0(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; + pub const fn wake_timer(&self) -> Rule { + let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DGDET0."] + #[doc = "WAKE_TIMER (Reserved)."] #[inline(always)] - pub const fn set_dgdet0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + pub const fn set_wake_timer(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "ITRC0."] + #[doc = "HSADC0."] #[must_use] #[inline(always)] - pub const fn itrc0(&self) -> Rule { + pub const fn hsadc0(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "ITRC0."] + #[doc = "HSADC0."] #[inline(always)] - pub const fn set_itrc0(&mut self, val: Rule) { + pub const fn set_hsadc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup2memRule12 { +impl Default for AipsBridgeGroup2MemRule1 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule12 { - AipsBridgeGroup2memRule12(0) + fn default() -> AipsBridgeGroup2MemRule1 { + AipsBridgeGroup2MemRule1(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule12 { +impl core::fmt::Debug for AipsBridgeGroup2MemRule1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule12") - .field("gpio5_alias", &self.gpio5_alias()) - .field("port5", &self.port5()) - .field("dgdet0", &self.dgdet0()) - .field("itrc0", &self.itrc0()) + f.debug_struct("AipsBridgeGroup2MemRule1") + .field("quad_decoder1", &self.quad_decoder1()) + .field("flexpwm0", &self.flexpwm0()) + .field("flexpwm1", &self.flexpwm1()) + .field("lptmr0", &self.lptmr0()) + .field("lptmr1", &self.lptmr1()) + .field("ostimer0", &self.ostimer0()) + .field("wake_timer", &self.wake_timer()) + .field("hsadc0", &self.hsadc0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule12 { +impl defmt::Format for AipsBridgeGroup2MemRule1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule12 {{ gpio5_alias: {:?}, port5: {:?}, dgdet0: {:?}, itrc0: {:?} }}", - self.gpio5_alias(), - self.port5(), - self.dgdet0(), - self.itrc0() + "AipsBridgeGroup2MemRule1 {{ quad_decoder1: {:?}, flexpwm0: {:?}, flexpwm1: {:?}, lptmr0: {:?}, lptmr1: {:?}, ostimer0: {:?}, wake_timer: {:?}, hsadc0: {:?} }}", + self.quad_decoder1(), + self.flexpwm0(), + self.flexpwm1(), + self.lptmr0(), + self.lptmr1(), + self.ostimer0(), + self.wake_timer(), + self.hsadc0() ) } } -#[doc = "AIPS Bridge Group 2 Rule 13."] +#[doc = "AIPS Bridge Group 2 Memory Rule 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule13(pub u32); -impl AipsBridgeGroup2memRule13 { - #[doc = "GLIKEY0."] +pub struct AipsBridgeGroup2MemRule2(pub u32); +impl AipsBridgeGroup2MemRule2 { + #[doc = "ADC1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn glikey0(&self) -> Rule { + pub const fn adc1(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "GLIKEY0."] + #[doc = "ADC1 (Reserved)."] #[inline(always)] - pub const fn set_glikey0(&mut self, val: Rule) { + pub const fn set_adc1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "TDET0."] + #[doc = "CMP0."] #[must_use] #[inline(always)] - pub const fn tdet0(&self) -> Rule { + pub const fn cmp0(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "TDET0."] + #[doc = "CMP0."] #[inline(always)] - pub const fn set_tdet0(&mut self, val: Rule) { + pub const fn set_cmp0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "SECCON."] + #[doc = "CMP1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn seccon(&self) -> Rule { + pub const fn cmp1(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "SECCON."] + #[doc = "CMP1 (Reserved)."] #[inline(always)] - pub const fn set_seccon(&mut self, val: Rule) { + pub const fn set_cmp1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "SGI0."] + #[doc = "CMP2 (Reserved)."] #[must_use] #[inline(always)] - pub const fn sgi0(&self) -> Rule { + pub const fn cmp2(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "SGI0."] + #[doc = "CMP2 (Reserved)."] #[inline(always)] - pub const fn set_sgi0(&mut self, val: Rule) { + pub const fn set_cmp2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "TRNG0."] + #[doc = "DAC0 (Reserved)."] #[must_use] #[inline(always)] - pub const fn trng0(&self) -> Rule { + pub const fn dac0(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "TRNG0."] + #[doc = "DAC0 (Reserved)."] #[inline(always)] - pub const fn set_trng0(&mut self, val: Rule) { + pub const fn set_dac0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "UDF0."] + #[doc = "DAC1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn udf0(&self) -> Rule { + pub const fn dac1(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "UDF0."] + #[doc = "DAC1 (Reserved)."] #[inline(always)] - pub const fn set_udf0(&mut self, val: Rule) { + pub const fn set_dac1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "RTC0."] + #[doc = "DAC2 (Reserved)."] #[must_use] #[inline(always)] - pub const fn rtc0(&self) -> Rule { + pub const fn dac2(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "RTC0."] + #[doc = "DAC2 (Reserved)."] #[inline(always)] - pub const fn set_rtc0(&mut self, val: Rule) { + pub const fn set_dac2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } + #[doc = "OPAMP0 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn opamp0(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "OPAMP0 (Reserved)."] + #[inline(always)] + pub const fn set_opamp0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule13 { +impl Default for AipsBridgeGroup2MemRule2 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule13 { - AipsBridgeGroup2memRule13(0) + fn default() -> AipsBridgeGroup2MemRule2 { + AipsBridgeGroup2MemRule2(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule13 { +impl core::fmt::Debug for AipsBridgeGroup2MemRule2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule13") - .field("glikey0", &self.glikey0()) - .field("tdet0", &self.tdet0()) - .field("seccon", &self.seccon()) - .field("sgi0", &self.sgi0()) - .field("trng0", &self.trng0()) - .field("udf0", &self.udf0()) - .field("rtc0", &self.rtc0()) + f.debug_struct("AipsBridgeGroup2MemRule2") + .field("adc1", &self.adc1()) + .field("cmp0", &self.cmp0()) + .field("cmp1", &self.cmp1()) + .field("cmp2", &self.cmp2()) + .field("dac0", &self.dac0()) + .field("dac1", &self.dac1()) + .field("dac2", &self.dac2()) + .field("opamp0", &self.opamp0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule13 { +impl defmt::Format for AipsBridgeGroup2MemRule2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule13 {{ glikey0: {:?}, tdet0: {:?}, seccon: {:?}, sgi0: {:?}, trng0: {:?}, udf0: {:?}, rtc0: {:?} }}", - self.glikey0(), - self.tdet0(), - self.seccon(), - self.sgi0(), - self.trng0(), - self.udf0(), - self.rtc0() + "AipsBridgeGroup2MemRule2 {{ adc1: {:?}, cmp0: {:?}, cmp1: {:?}, cmp2: {:?}, dac0: {:?}, dac1: {:?}, dac2: {:?}, opamp0: {:?} }}", + self.adc1(), + self.cmp0(), + self.cmp1(), + self.cmp2(), + self.dac0(), + self.dac1(), + self.dac2(), + self.opamp0() ) } } -#[doc = "AIPS Bridge Group 2 Rule 2."] +#[doc = "AIPS Bridge Group 2 Memory Rule 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule2(pub u32); -impl AipsBridgeGroup2memRule2 { - #[doc = "SYSCON."] +pub struct AipsBridgeGroup2MemRule3(pub u32); +impl AipsBridgeGroup2MemRule3 { + #[doc = "OPAMP1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn syscon(&self) -> Rule { + pub const fn opamp1(&self) -> Rule { + let val = (self.0 >> 0usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "OPAMP1 (Reserved)."] + #[inline(always)] + pub const fn set_opamp1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "OPAMP2 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn opamp2(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "SYSCON."] + #[doc = "OPAMP2 (Reserved)."] #[inline(always)] - pub const fn set_syscon(&mut self, val: Rule) { + pub const fn set_opamp2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "WUU."] + #[doc = "SD_ADC0 (Reserved)."] #[must_use] #[inline(always)] - pub const fn wuu(&self) -> Rule { + pub const fn sd_adc0(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "WUU."] + #[doc = "SD_ADC0 (Reserved)."] #[inline(always)] - pub const fn set_wuu(&mut self, val: Rule) { + pub const fn set_sd_adc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "VBAT."] + #[doc = "DGO_GPIO1_3 (Reserved)."] #[must_use] #[inline(always)] - pub const fn vbat(&self) -> Rule { + pub const fn dgo_gpio1_3(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "VBAT."] + #[doc = "DGO_GPIO1_3 (Reserved)."] #[inline(always)] - pub const fn set_vbat(&mut self, val: Rule) { + pub const fn set_dgo_gpio1_3(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "FMC."] + #[doc = "PORT1."] #[must_use] #[inline(always)] - pub const fn fmc(&self) -> Rule { + pub const fn port1(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "FMC."] + #[doc = "PORT1."] #[inline(always)] - pub const fn set_fmc(&mut self, val: Rule) { + pub const fn set_port1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "FMU."] + #[doc = "PORT2."] #[must_use] #[inline(always)] - pub const fn fmu(&self) -> Rule { + pub const fn port2(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "FMU."] + #[doc = "PORT2."] #[inline(always)] - pub const fn set_fmu(&mut self, val: Rule) { + pub const fn set_port2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } + #[doc = "PORT3."] + #[must_use] + #[inline(always)] + pub const fn port3(&self) -> Rule { + let val = (self.0 >> 24usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "PORT3."] + #[inline(always)] + pub const fn set_port3(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + } + #[doc = "PORT4 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn port4(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "PORT4 (Reserved)."] + #[inline(always)] + pub const fn set_port4(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule2 { +impl Default for AipsBridgeGroup2MemRule3 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule2 { - AipsBridgeGroup2memRule2(0) + fn default() -> AipsBridgeGroup2MemRule3 { + AipsBridgeGroup2MemRule3(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule2 { +impl core::fmt::Debug for AipsBridgeGroup2MemRule3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule2") - .field("syscon", &self.syscon()) - .field("wuu", &self.wuu()) - .field("vbat", &self.vbat()) - .field("fmc", &self.fmc()) - .field("fmu", &self.fmu()) + f.debug_struct("AipsBridgeGroup2MemRule3") + .field("opamp1", &self.opamp1()) + .field("opamp2", &self.opamp2()) + .field("sd_adc0", &self.sd_adc0()) + .field("dgo_gpio1_3", &self.dgo_gpio1_3()) + .field("port1", &self.port1()) + .field("port2", &self.port2()) + .field("port3", &self.port3()) + .field("port4", &self.port4()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule2 { +impl defmt::Format for AipsBridgeGroup2MemRule3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule2 {{ syscon: {:?}, wuu: {:?}, vbat: {:?}, fmc: {:?}, fmu: {:?} }}", - self.syscon(), - self.wuu(), - self.vbat(), - self.fmc(), - self.fmu() + "AipsBridgeGroup2MemRule3 {{ opamp1: {:?}, opamp2: {:?}, sd_adc0: {:?}, dgo_gpio1_3: {:?}, port1: {:?}, port2: {:?}, port3: {:?}, port4: {:?} }}", + self.opamp1(), + self.opamp2(), + self.sd_adc0(), + self.dgo_gpio1_3(), + self.port1(), + self.port2(), + self.port3(), + self.port4() ) } } -#[doc = "AIPS Bridge Group 2 Rule 3."] +#[doc = "AIPS Bridge Group 3 Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule3(pub u32); -impl AipsBridgeGroup2memRule3 { - #[doc = "FLEXIO."] +pub struct AipsBridgeGroup3MemRule0(pub u32); +impl AipsBridgeGroup3MemRule0 { + #[doc = "PORT5 (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn port5(&self) -> Rule { + let val = (self.0 >> 0usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "PORT5 (Reserved)."] + #[inline(always)] + pub const fn set_port5(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "SAI (Reserved)."] #[must_use] #[inline(always)] - pub const fn flexio(&self) -> Rule { + pub const fn sai(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "FLEXIO."] + #[doc = "SAI (Reserved)."] #[inline(always)] - pub const fn set_flexio(&mut self, val: Rule) { + pub const fn set_sai(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "LPI2C0."] + #[doc = "SEGMENT_LCD (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpi2c0(&self) -> Rule { + pub const fn segment_lcd(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPI2C0."] + #[doc = "SEGMENT_LCD (Reserved)."] #[inline(always)] - pub const fn set_lpi2c0(&mut self, val: Rule) { + pub const fn set_segment_lcd(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "LPI2C1."] + #[doc = "TSI (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpi2c1(&self) -> Rule { + pub const fn tsi(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPI2C1."] + #[doc = "TSI (Reserved)."] #[inline(always)] - pub const fn set_lpi2c1(&mut self, val: Rule) { + pub const fn set_tsi(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "LPSPI0."] + #[doc = "MU0."] #[must_use] #[inline(always)] - pub const fn lpspi0(&self) -> Rule { + pub const fn mu0(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPSPI0."] + #[doc = "MU0."] #[inline(always)] - pub const fn set_lpspi0(&mut self, val: Rule) { + pub const fn set_mu0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "LPSPI1."] + #[doc = "MU1 (Reserved)."] #[must_use] #[inline(always)] - pub const fn lpspi1(&self) -> Rule { + pub const fn mu1(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPSPI1."] + #[doc = "MU1 (Reserved)."] #[inline(always)] - pub const fn set_lpspi1(&mut self, val: Rule) { + pub const fn set_mu1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "I3C2."] - #[must_use] - #[inline(always)] - pub const fn i3c2(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "I3C2."] - #[inline(always)] - pub const fn set_i3c2(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); - } - #[doc = "LPUART0."] - #[must_use] - #[inline(always)] - pub const fn lpuart0(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "LPUART0."] - #[inline(always)] - pub const fn set_lpuart0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); - } } -impl Default for AipsBridgeGroup2memRule3 { +impl Default for AipsBridgeGroup3MemRule0 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule3 { - AipsBridgeGroup2memRule3(0) + fn default() -> AipsBridgeGroup3MemRule0 { + AipsBridgeGroup3MemRule0(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule3 { +impl core::fmt::Debug for AipsBridgeGroup3MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule3") - .field("flexio", &self.flexio()) - .field("lpi2c0", &self.lpi2c0()) - .field("lpi2c1", &self.lpi2c1()) - .field("lpspi0", &self.lpspi0()) - .field("lpspi1", &self.lpspi1()) - .field("i3c2", &self.i3c2()) - .field("lpuart0", &self.lpuart0()) + f.debug_struct("AipsBridgeGroup3MemRule0") + .field("port5", &self.port5()) + .field("sai", &self.sai()) + .field("segment_lcd", &self.segment_lcd()) + .field("tsi", &self.tsi()) + .field("mu0", &self.mu0()) + .field("mu1", &self.mu1()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule3 { +impl defmt::Format for AipsBridgeGroup3MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule3 {{ flexio: {:?}, lpi2c0: {:?}, lpi2c1: {:?}, lpspi0: {:?}, lpspi1: {:?}, i3c2: {:?}, lpuart0: {:?} }}", - self.flexio(), - self.lpi2c0(), - self.lpi2c1(), - self.lpspi0(), - self.lpspi1(), - self.i3c2(), - self.lpuart0() + "AipsBridgeGroup3MemRule0 {{ port5: {:?}, sai: {:?}, segment_lcd: {:?}, tsi: {:?}, mu0: {:?}, mu1: {:?} }}", + self.port5(), + self.sai(), + self.segment_lcd(), + self.tsi(), + self.mu0(), + self.mu1() ) } } -#[doc = "AIPS Bridge Group 2 Rule 4."] +#[doc = "AIPS Bridge Group 3 Rule 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule4(pub u32); -impl AipsBridgeGroup2memRule4 { - #[doc = "LPUART1."] +pub struct AipsBridgeGroup3MemRule2(pub u32); +impl AipsBridgeGroup3MemRule2 { + #[doc = "PKC0."] #[must_use] #[inline(always)] - pub const fn lpuart1(&self) -> Rule { + pub const fn pkc0(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPUART1."] + #[doc = "PKC0."] #[inline(always)] - pub const fn set_lpuart1(&mut self, val: Rule) { + pub const fn set_pkc0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "LPUART2."] + #[doc = "SGI0."] #[must_use] #[inline(always)] - pub const fn lpuart2(&self) -> Rule { + pub const fn sgi0(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPUART2."] + #[doc = "SGI0."] #[inline(always)] - pub const fn set_lpuart2(&mut self, val: Rule) { + pub const fn set_sgi0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "LPUART3."] + #[doc = "TRNG0."] #[must_use] #[inline(always)] - pub const fn lpuart3(&self) -> Rule { + pub const fn trng0(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPUART3."] + #[doc = "TRNG0."] #[inline(always)] - pub const fn set_lpuart3(&mut self, val: Rule) { + pub const fn set_trng0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "LPUART4."] + #[doc = "CAN0 RULE0."] #[must_use] #[inline(always)] - pub const fn lpuart4(&self) -> Rule { + pub const fn udf0(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPUART4."] + #[doc = "CAN0 RULE0."] #[inline(always)] - pub const fn set_lpuart4(&mut self, val: Rule) { + pub const fn set_udf0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } + #[doc = "eDMA_1_MP."] + #[must_use] + #[inline(always)] + pub const fn e_mda_1_mp(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "eDMA_1_MP."] + #[inline(always)] + pub const fn set_e_mda_1_mp(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule4 { +impl Default for AipsBridgeGroup3MemRule2 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule4 { - AipsBridgeGroup2memRule4(0) + fn default() -> AipsBridgeGroup3MemRule2 { + AipsBridgeGroup3MemRule2(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule4 { +impl core::fmt::Debug for AipsBridgeGroup3MemRule2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule4") - .field("lpuart1", &self.lpuart1()) - .field("lpuart2", &self.lpuart2()) - .field("lpuart3", &self.lpuart3()) - .field("lpuart4", &self.lpuart4()) + f.debug_struct("AipsBridgeGroup3MemRule2") + .field("pkc0", &self.pkc0()) + .field("sgi0", &self.sgi0()) + .field("trng0", &self.trng0()) + .field("udf0", &self.udf0()) + .field("e_mda_1_mp", &self.e_mda_1_mp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule4 { +impl defmt::Format for AipsBridgeGroup3MemRule2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule4 {{ lpuart1: {:?}, lpuart2: {:?}, lpuart3: {:?}, lpuart4: {:?} }}", - self.lpuart1(), - self.lpuart2(), - self.lpuart3(), - self.lpuart4() + "AipsBridgeGroup3MemRule2 {{ pkc0: {:?}, sgi0: {:?}, trng0: {:?}, udf0: {:?}, e_mda_1_mp: {:?} }}", + self.pkc0(), + self.sgi0(), + self.trng0(), + self.udf0(), + self.e_mda_1_mp() ) } } -#[doc = "AIPS Bridge Group 2 Rule 5."] +#[doc = "AIPS Bridge Group 3 Rule 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule5(pub u32); -impl AipsBridgeGroup2memRule5 { - #[doc = "LPTMR."] +pub struct AipsBridgeGroup3MemRule3(pub u32); +impl AipsBridgeGroup3MemRule3 { + #[doc = "eDMA_1_TCD0."] #[must_use] #[inline(always)] - pub const fn lptmr(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; + pub const fn e_dma_1_tcd0(&self) -> Rule { + let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "LPTMR."] + #[doc = "eDMA_1_TCD0."] #[inline(always)] - pub const fn set_lptmr(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + pub const fn set_e_dma_1_tcd0(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "OSTIMER."] + #[doc = "eDMA_1_TCD1."] #[must_use] #[inline(always)] - pub const fn ostimer(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; + pub const fn e_dma_1_tcd1(&self) -> Rule { + let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "OSTIMER."] + #[doc = "eDMA_1_TCD1."] #[inline(always)] - pub const fn set_ostimer(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + pub const fn set_e_dma_1_tcd1(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "WAKE_TIMER."] + #[doc = "eDMA_1_TCD2."] #[must_use] #[inline(always)] - pub const fn wake_timer(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; + pub const fn e_dma_1_tcd2(&self) -> Rule { + let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "WAKE_TIMER."] + #[doc = "eDMA_1_TCD2."] #[inline(always)] - pub const fn set_wake_timer(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + pub const fn set_e_dma_1_tcd2(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "ADC0."] + #[doc = "eDMA_1_TCD3."] #[must_use] #[inline(always)] - pub const fn adc0(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; + pub const fn e_dma_1_tcd3(&self) -> Rule { + let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "ADC0."] + #[doc = "eDMA_1_TCD3."] #[inline(always)] - pub const fn set_adc0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + pub const fn set_e_dma_1_tcd3(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } } -impl Default for AipsBridgeGroup2memRule5 { +impl Default for AipsBridgeGroup3MemRule3 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule5 { - AipsBridgeGroup2memRule5(0) + fn default() -> AipsBridgeGroup3MemRule3 { + AipsBridgeGroup3MemRule3(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule5 { +impl core::fmt::Debug for AipsBridgeGroup3MemRule3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule5") - .field("lptmr", &self.lptmr()) - .field("ostimer", &self.ostimer()) - .field("wake_timer", &self.wake_timer()) - .field("adc0", &self.adc0()) + f.debug_struct("AipsBridgeGroup3MemRule3") + .field("e_dma_1_tcd0", &self.e_dma_1_tcd0()) + .field("e_dma_1_tcd1", &self.e_dma_1_tcd1()) + .field("e_dma_1_tcd2", &self.e_dma_1_tcd2()) + .field("e_dma_1_tcd3", &self.e_dma_1_tcd3()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule5 { +impl defmt::Format for AipsBridgeGroup3MemRule3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule5 {{ lptmr: {:?}, ostimer: {:?}, wake_timer: {:?}, adc0: {:?} }}", - self.lptmr(), - self.ostimer(), - self.wake_timer(), - self.adc0() + "AipsBridgeGroup3MemRule3 {{ e_dma_1_tcd0: {:?}, e_dma_1_tcd1: {:?}, e_dma_1_tcd2: {:?}, e_dma_1_tcd3: {:?} }}", + self.e_dma_1_tcd0(), + self.e_dma_1_tcd1(), + self.e_dma_1_tcd2(), + self.e_dma_1_tcd3() ) } } -#[doc = "AIPS Bridge Group 2 Rule 6."] +#[doc = "AON Domain Peripheral Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule6(pub u32); -impl AipsBridgeGroup2memRule6 { - #[doc = "ADC1."] +pub struct AonDomainPeripheralMemRule0(pub u32); +impl AonDomainPeripheralMemRule0 { + #[doc = "LPI2C."] #[must_use] #[inline(always)] - pub const fn adc1(&self) -> Rule { + pub const fn lpi2c(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "ADC1."] + #[doc = "LPI2C."] #[inline(always)] - pub const fn set_adc1(&mut self, val: Rule) { + pub const fn set_lpi2c(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "CMP0."] + #[doc = "LPI2C (Reserved)."] #[must_use] #[inline(always)] - pub const fn cmp0(&self) -> Rule { + pub const fn rule1(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CMP0."] + #[doc = "LPI2C (Reserved)."] #[inline(always)] - pub const fn set_cmp0(&mut self, val: Rule) { + pub const fn set_rule1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "DAC0."] + #[doc = "LPUART."] #[must_use] #[inline(always)] - pub const fn dac0(&self) -> Rule { + pub const fn lpuart(&self) -> Rule { + let val = (self.0 >> 8usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "LPUART."] + #[inline(always)] + pub const fn set_lpuart(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } + #[doc = "LPUART (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn rule3(&self) -> Rule { + let val = (self.0 >> 12usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "LPUART (Reserved)."] + #[inline(always)] + pub const fn set_rule3(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + } + #[doc = "MUB."] + #[must_use] + #[inline(always)] + pub const fn mub(&self) -> Rule { let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DAC0."] + #[doc = "MUB."] #[inline(always)] - pub const fn set_dac0(&mut self, val: Rule) { + pub const fn set_mub(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "DAC1."] + #[doc = "PORT0."] #[must_use] #[inline(always)] - pub const fn dac1(&self) -> Rule { + pub const fn port0(&self) -> Rule { let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "DAC1."] + #[doc = "PORT0."] #[inline(always)] - pub const fn set_dac1(&mut self, val: Rule) { + pub const fn set_port0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } + #[doc = "ACMP."] + #[must_use] + #[inline(always)] + pub const fn acmp(&self) -> Rule { + let val = (self.0 >> 24usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "ACMP."] + #[inline(always)] + pub const fn set_acmp(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + } + #[doc = "ACMP (Reserved)."] + #[must_use] + #[inline(always)] + pub const fn rule7(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "ACMP (Reserved)."] + #[inline(always)] + pub const fn set_rule7(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + } } -impl Default for AipsBridgeGroup2memRule6 { +impl Default for AonDomainPeripheralMemRule0 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule6 { - AipsBridgeGroup2memRule6(0) + fn default() -> AonDomainPeripheralMemRule0 { + AonDomainPeripheralMemRule0(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule6 { +impl core::fmt::Debug for AonDomainPeripheralMemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule6") - .field("adc1", &self.adc1()) - .field("cmp0", &self.cmp0()) - .field("dac0", &self.dac0()) - .field("dac1", &self.dac1()) + f.debug_struct("AonDomainPeripheralMemRule0") + .field("lpi2c", &self.lpi2c()) + .field("rule1", &self.rule1()) + .field("lpuart", &self.lpuart()) + .field("rule3", &self.rule3()) + .field("mub", &self.mub()) + .field("port0", &self.port0()) + .field("acmp", &self.acmp()) + .field("rule7", &self.rule7()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule6 { +impl defmt::Format for AonDomainPeripheralMemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule6 {{ adc1: {:?}, cmp0: {:?}, dac0: {:?}, dac1: {:?} }}", - self.adc1(), - self.cmp0(), - self.dac0(), - self.dac1() + "AonDomainPeripheralMemRule0 {{ lpi2c: {:?}, rule1: {:?}, lpuart: {:?}, rule3: {:?}, mub: {:?}, port0: {:?}, acmp: {:?}, rule7: {:?} }}", + self.lpi2c(), + self.rule1(), + self.lpuart(), + self.rule3(), + self.mub(), + self.port0(), + self.acmp(), + self.rule7() ) } } -#[doc = "AIPS Bridge Group 2 Rule 7."] +#[doc = "AON Domain Peripheral Rule 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule7(pub u32); -impl AipsBridgeGroup2memRule7 { - #[doc = "VREF0."] - #[must_use] - #[inline(always)] - pub const fn vref0(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "VREF0."] - #[inline(always)] - pub const fn set_vref0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); - } - #[doc = "PORT0."] - #[must_use] - #[inline(always)] - pub const fn port0(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "PORT0."] - #[inline(always)] - pub const fn set_port0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); - } - #[doc = "PORT1."] +pub struct AonDomainPeripheralMemRule1(pub u32); +impl AonDomainPeripheralMemRule1 { + #[doc = "LPTIMER."] #[must_use] #[inline(always)] - pub const fn port1(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; + pub const fn lptimer(&self) -> Rule { + let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PORT1."] + #[doc = "LPTIMER."] #[inline(always)] - pub const fn set_port1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + pub const fn set_lptimer(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "PORT2."] + #[doc = "QTMR32_0."] #[must_use] #[inline(always)] - pub const fn port2(&self) -> Rule { + pub const fn qtmr32_0(&self) -> Rule { let val = (self.0 >> 24usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PORT2."] + #[doc = "QTMR32_0."] #[inline(always)] - pub const fn set_port2(&mut self, val: Rule) { + pub const fn set_qtmr32_0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "PORT3."] + #[doc = "QTMR32_1."] #[must_use] #[inline(always)] - pub const fn port3(&self) -> Rule { + pub const fn qtmr32_1(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PORT3."] + #[doc = "QTMR32_1."] #[inline(always)] - pub const fn set_port3(&mut self, val: Rule) { + pub const fn set_qtmr32_1(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup2memRule7 { +impl Default for AonDomainPeripheralMemRule1 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule7 { - AipsBridgeGroup2memRule7(0) + fn default() -> AonDomainPeripheralMemRule1 { + AonDomainPeripheralMemRule1(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule7 { +impl core::fmt::Debug for AonDomainPeripheralMemRule1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule7") - .field("vref0", &self.vref0()) - .field("port0", &self.port0()) - .field("port1", &self.port1()) - .field("port2", &self.port2()) - .field("port3", &self.port3()) + f.debug_struct("AonDomainPeripheralMemRule1") + .field("lptimer", &self.lptimer()) + .field("qtmr32_0", &self.qtmr32_0()) + .field("qtmr32_1", &self.qtmr32_1()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule7 { +impl defmt::Format for AonDomainPeripheralMemRule1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule7 {{ vref0: {:?}, port0: {:?}, port1: {:?}, port2: {:?}, port3: {:?} }}", - self.vref0(), - self.port0(), - self.port1(), - self.port2(), - self.port3() + "AonDomainPeripheralMemRule1 {{ lptimer: {:?}, qtmr32_0: {:?}, qtmr32_1: {:?} }}", + self.lptimer(), + self.qtmr32_0(), + self.qtmr32_1() ) } } -#[doc = "AIPS Bridge Group 2 Rule 8."] +#[doc = "AON Domain Peripheral Rule 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule8(pub u32); -impl AipsBridgeGroup2memRule8 { - #[doc = "PORT4."] +pub struct AonDomainPeripheralMemRule2(pub u32); +impl AonDomainPeripheralMemRule2 { + #[doc = "GP_GPR."] #[must_use] #[inline(always)] - pub const fn port4(&self) -> Rule { + pub const fn gp_gpr(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "PORT4."] + #[doc = "GP_GPR."] #[inline(always)] - pub const fn set_port4(&mut self, val: Rule) { + pub const fn set_gp_gpr(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "TSI0."] + #[doc = "INPUTMUX."] #[must_use] #[inline(always)] - pub const fn tsi0(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; + pub const fn inputmux(&self) -> Rule { + let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "TSI0."] + #[doc = "INPUTMUX."] #[inline(always)] - pub const fn set_tsi0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); + pub const fn set_inputmux(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "AOI0."] + #[doc = "LPADC."] #[must_use] #[inline(always)] - pub const fn aoi0(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; + pub const fn lpadc(&self) -> Rule { + let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "AOI0."] + #[doc = "LPADC."] #[inline(always)] - pub const fn set_aoi0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); + pub const fn set_lpadc(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "CRC0."] + #[doc = "SGLCD0."] #[must_use] #[inline(always)] - pub const fn crc0(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; + pub const fn sglcd(&self) -> Rule { + let val = (self.0 >> 16usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CRC0."] + #[doc = "SGLCD0."] #[inline(always)] - pub const fn set_crc0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + pub const fn set_sglcd(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "CMC."] + #[doc = "KPP."] #[must_use] #[inline(always)] - pub const fn cmc(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; + pub const fn kpp(&self) -> Rule { + let val = (self.0 >> 20usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CMC."] + #[doc = "KPP."] #[inline(always)] - pub const fn set_cmc(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + pub const fn set_kpp(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); } - #[doc = "EIM."] + #[doc = "KPP."] #[must_use] #[inline(always)] - pub const fn eim(&self) -> Rule { + pub const fn advc2(&self) -> Rule { let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "EIM."] + #[doc = "KPP."] #[inline(always)] - pub const fn set_eim(&mut self, val: Rule) { + pub const fn set_advc2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } } -impl Default for AipsBridgeGroup2memRule8 { +impl Default for AonDomainPeripheralMemRule2 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule8 { - AipsBridgeGroup2memRule8(0) + fn default() -> AonDomainPeripheralMemRule2 { + AonDomainPeripheralMemRule2(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule8 { +impl core::fmt::Debug for AonDomainPeripheralMemRule2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule8") - .field("port4", &self.port4()) - .field("tsi0", &self.tsi0()) - .field("aoi0", &self.aoi0()) - .field("crc0", &self.crc0()) - .field("cmc", &self.cmc()) - .field("eim", &self.eim()) + f.debug_struct("AonDomainPeripheralMemRule2") + .field("gp_gpr", &self.gp_gpr()) + .field("inputmux", &self.inputmux()) + .field("lpadc", &self.lpadc()) + .field("sglcd", &self.sglcd()) + .field("kpp", &self.kpp()) + .field("advc2", &self.advc2()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule8 { +impl defmt::Format for AonDomainPeripheralMemRule2 { fn format(&self, f: defmt::Formatter) { defmt::write!( - f, - "AipsBridgeGroup2memRule8 {{ port4: {:?}, tsi0: {:?}, aoi0: {:?}, crc0: {:?}, cmc: {:?}, eim: {:?} }}", - self.port4(), - self.tsi0(), - self.aoi0(), - self.crc0(), - self.cmc(), - self.eim() + f, + "AonDomainPeripheralMemRule2 {{ gp_gpr: {:?}, inputmux: {:?}, lpadc: {:?}, sglcd: {:?}, kpp: {:?}, advc2: {:?} }}", + self.gp_gpr(), + self.inputmux(), + self.lpadc(), + self.sglcd(), + self.kpp(), + self.advc2() ) } } -#[doc = "AIPS Bridge Group 2 Rule 9."] +#[doc = "AON Domain Peripheral Rule 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AipsBridgeGroup2memRule9(pub u32); -impl AipsBridgeGroup2memRule9 { - #[doc = "ERM."] +pub struct AonDomainPeripheralMemRule3(pub u32); +impl AonDomainPeripheralMemRule3 { + #[doc = "PMIC_CTRL."] #[must_use] #[inline(always)] - pub const fn erm(&self) -> Rule { + pub const fn pmic_ctrl(&self) -> Rule { let val = (self.0 >> 0usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "ERM."] + #[doc = "PMIC_CTRL."] #[inline(always)] - pub const fn set_erm(&mut self, val: Rule) { + pub const fn set_pmic_ctrl(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "MBC."] + #[doc = "CGU."] #[must_use] #[inline(always)] - pub const fn mbc(&self) -> Rule { + pub const fn cgu(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "MBC."] + #[doc = "CGU."] #[inline(always)] - pub const fn set_mbc(&mut self, val: Rule) { + pub const fn set_cgu(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "SCG."] + #[doc = "SMM."] #[must_use] #[inline(always)] - pub const fn scg(&self) -> Rule { + pub const fn smm(&self) -> Rule { let val = (self.0 >> 8usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "SCG."] + #[doc = "SMM."] #[inline(always)] - pub const fn set_scg(&mut self, val: Rule) { + pub const fn set_smm(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "SPC."] + #[doc = "LPCMP."] #[must_use] #[inline(always)] - pub const fn spc(&self) -> Rule { + pub const fn lpcmp(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "SPC."] + #[doc = "LPCMP."] #[inline(always)] - pub const fn set_spc(&mut self, val: Rule) { + pub const fn set_lpcmp(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } - #[doc = "CAN0 Region 0."] + #[doc = "AON_GPIO."] #[must_use] #[inline(always)] - pub const fn can0_region0(&self) -> Rule { - let val = (self.0 >> 16usize) & 0x03; + pub const fn aon_gpio(&self) -> Rule { + let val = (self.0 >> 28usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN0 Region 0."] - #[inline(always)] - pub const fn set_can0_region0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); - } - #[doc = "CAN0 Region 1."] - #[must_use] + #[doc = "AON_GPIO."] #[inline(always)] - pub const fn can0_region1(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; - Rule::from_bits(val as u8) + pub const fn set_aon_gpio(&mut self, val: Rule) { + self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); } - #[doc = "CAN0 Region 1."] +} +impl Default for AonDomainPeripheralMemRule3 { #[inline(always)] - pub const fn set_can0_region1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); + fn default() -> AonDomainPeripheralMemRule3 { + AonDomainPeripheralMemRule3(0) } - #[doc = "CAN0 Region 2."] - #[must_use] - #[inline(always)] - pub const fn can0_region2(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; - Rule::from_bits(val as u8) +} +impl core::fmt::Debug for AonDomainPeripheralMemRule3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AonDomainPeripheralMemRule3") + .field("pmic_ctrl", &self.pmic_ctrl()) + .field("cgu", &self.cgu()) + .field("smm", &self.smm()) + .field("lpcmp", &self.lpcmp()) + .field("aon_gpio", &self.aon_gpio()) + .finish() } - #[doc = "CAN0 Region 2."] - #[inline(always)] - pub const fn set_can0_region2(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for AonDomainPeripheralMemRule3 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AonDomainPeripheralMemRule3 {{ pmic_ctrl: {:?}, cgu: {:?}, smm: {:?}, lpcmp: {:?}, aon_gpio: {:?} }}", + self.pmic_ctrl(), + self.cgu(), + self.smm(), + self.lpcmp(), + self.aon_gpio() + ) } - #[doc = "CAN0 Region 3."] +} +#[doc = "AON Domain SRAM Memory Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct AonDomainSramMemRule0(pub u32); +impl AonDomainSramMemRule0 { + #[doc = "Rule 0."] #[must_use] #[inline(always)] - pub const fn can0_region3(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) } - #[doc = "CAN0 Region 3."] + #[doc = "Rule 0."] #[inline(always)] - pub const fn set_can0_region3(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for AipsBridgeGroup2memRule9 { +impl Default for AonDomainSramMemRule0 { #[inline(always)] - fn default() -> AipsBridgeGroup2memRule9 { - AipsBridgeGroup2memRule9(0) + fn default() -> AonDomainSramMemRule0 { + AonDomainSramMemRule0(0) } } -impl core::fmt::Debug for AipsBridgeGroup2memRule9 { +impl core::fmt::Debug for AonDomainSramMemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AipsBridgeGroup2memRule9") - .field("erm", &self.erm()) - .field("mbc", &self.mbc()) - .field("scg", &self.scg()) - .field("spc", &self.spc()) - .field("can0_region0", &self.can0_region0()) - .field("can0_region1", &self.can0_region1()) - .field("can0_region2", &self.can0_region2()) - .field("can0_region3", &self.can0_region3()) + f.debug_struct("AonDomainSramMemRule0") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AipsBridgeGroup2memRule9 { +impl defmt::Format for AonDomainSramMemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "AipsBridgeGroup2memRule9 {{ erm: {:?}, mbc: {:?}, scg: {:?}, spc: {:?}, can0_region0: {:?}, can0_region1: {:?}, can0_region2: {:?}, can0_region3: {:?} }}", - self.erm(), - self.mbc(), - self.scg(), - self.spc(), - self.can0_region0(), - self.can0_region1(), - self.can0_region2(), - self.can0_region3() + "AonDomainSramMemRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) ) } } -#[doc = "APB Bridge Group 0 Memory Rule Register 0."] +#[doc = "APB Bridge Group 0 Memory Rule 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct ApbPeripheralGroup0memRule0(pub u32); -impl ApbPeripheralGroup0memRule0 { - #[doc = "INPUTMUX."] +pub struct ApbPeripheralGroup0MemRule0(pub u32); +impl ApbPeripheralGroup0MemRule0 { + #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] - pub const fn inputmux(&self) -> Rule { + pub const fn inputmux0(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "INPUTMUX."] + #[doc = "INPUTMUX0."] #[inline(always)] - pub const fn set_inputmux(&mut self, val: Rule) { + pub const fn set_inputmux0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "I3C0."] - #[must_use] - #[inline(always)] - pub const fn i3c0(&self) -> Rule { - let val = (self.0 >> 8usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "I3C0."] - #[inline(always)] - pub const fn set_i3c0(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); - } - #[doc = "I3C1."] - #[must_use] - #[inline(always)] - pub const fn i3c1(&self) -> Rule { - let val = (self.0 >> 12usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "I3C1."] - #[inline(always)] - pub const fn set_i3c1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); - } #[doc = "CTIMER0."] #[must_use] #[inline(always)] @@ -2735,93 +2909,63 @@ impl ApbPeripheralGroup0memRule0 { pub const fn set_ctimer2(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "CTIMER3."] - #[must_use] - #[inline(always)] - pub const fn ctimer3(&self) -> Rule { - let val = (self.0 >> 28usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "CTIMER3."] - #[inline(always)] - pub const fn set_ctimer3(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 28usize)) | (((val.to_bits() as u32) & 0x03) << 28usize); - } } -impl Default for ApbPeripheralGroup0memRule0 { +impl Default for ApbPeripheralGroup0MemRule0 { #[inline(always)] - fn default() -> ApbPeripheralGroup0memRule0 { - ApbPeripheralGroup0memRule0(0) + fn default() -> ApbPeripheralGroup0MemRule0 { + ApbPeripheralGroup0MemRule0(0) } } -impl core::fmt::Debug for ApbPeripheralGroup0memRule0 { +impl core::fmt::Debug for ApbPeripheralGroup0MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ApbPeripheralGroup0memRule0") - .field("inputmux", &self.inputmux()) - .field("i3c0", &self.i3c0()) - .field("i3c1", &self.i3c1()) + f.debug_struct("ApbPeripheralGroup0MemRule0") + .field("inputmux0", &self.inputmux0()) .field("ctimer0", &self.ctimer0()) .field("ctimer1", &self.ctimer1()) .field("ctimer2", &self.ctimer2()) - .field("ctimer3", &self.ctimer3()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for ApbPeripheralGroup0memRule0 { +impl defmt::Format for ApbPeripheralGroup0MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "ApbPeripheralGroup0memRule0 {{ inputmux: {:?}, i3c0: {:?}, i3c1: {:?}, ctimer0: {:?}, ctimer1: {:?}, ctimer2: {:?}, ctimer3: {:?} }}", - self.inputmux(), - self.i3c0(), - self.i3c1(), + "ApbPeripheralGroup0MemRule0 {{ inputmux0: {:?}, ctimer0: {:?}, ctimer1: {:?}, ctimer2: {:?} }}", + self.inputmux0(), self.ctimer0(), self.ctimer1(), - self.ctimer2(), - self.ctimer3() + self.ctimer2() ) } } -#[doc = "APB Bridge Group 0 Memory Rule Register 1."] +#[doc = "APB Bridge Group 0 Memory Rule 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct ApbPeripheralGroup0memRule1(pub u32); -impl ApbPeripheralGroup0memRule1 { - #[doc = "CTIMER4."] - #[must_use] - #[inline(always)] - pub const fn ctimer4(&self) -> Rule { - let val = (self.0 >> 0usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "CTIMER4."] - #[inline(always)] - pub const fn set_ctimer4(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "FREQME."] +pub struct ApbPeripheralGroup0MemRule1(pub u32); +impl ApbPeripheralGroup0MemRule1 { + #[doc = "FREQME00."] #[must_use] #[inline(always)] - pub const fn freqme(&self) -> Rule { + pub const fn freqme00(&self) -> Rule { let val = (self.0 >> 4usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "FREQME."] + #[doc = "FREQME00."] #[inline(always)] - pub const fn set_freqme(&mut self, val: Rule) { + pub const fn set_freqme00(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "UTCIK0."] + #[doc = "UTICK0."] #[must_use] #[inline(always)] - pub const fn utick(&self) -> Rule { + pub const fn utick0(&self) -> Rule { let val = (self.0 >> 12usize) & 0x03; Rule::from_bits(val as u8) } - #[doc = "UTCIK0."] + #[doc = "UTICK0."] #[inline(always)] - pub const fn set_utick(&mut self, val: Rule) { + pub const fn set_utick0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize); } #[doc = "WWDT0."] @@ -2836,69 +2980,39 @@ impl ApbPeripheralGroup0memRule1 { pub const fn set_wwdt0(&mut self, val: Rule) { self.0 = (self.0 & !(0x03 << 16usize)) | (((val.to_bits() as u32) & 0x03) << 16usize); } - #[doc = "WWDT1."] - #[must_use] - #[inline(always)] - pub const fn wwdt1(&self) -> Rule { - let val = (self.0 >> 20usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "WWDT1."] - #[inline(always)] - pub const fn set_wwdt1(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 20usize)) | (((val.to_bits() as u32) & 0x03) << 20usize); - } - #[doc = "SmartDMA."] - #[must_use] - #[inline(always)] - pub const fn smartdma(&self) -> Rule { - let val = (self.0 >> 24usize) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "SmartDMA."] - #[inline(always)] - pub const fn set_smartdma(&mut self, val: Rule) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); - } } -impl Default for ApbPeripheralGroup0memRule1 { +impl Default for ApbPeripheralGroup0MemRule1 { #[inline(always)] - fn default() -> ApbPeripheralGroup0memRule1 { - ApbPeripheralGroup0memRule1(0) + fn default() -> ApbPeripheralGroup0MemRule1 { + ApbPeripheralGroup0MemRule1(0) } } -impl core::fmt::Debug for ApbPeripheralGroup0memRule1 { +impl core::fmt::Debug for ApbPeripheralGroup0MemRule1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ApbPeripheralGroup0memRule1") - .field("ctimer4", &self.ctimer4()) - .field("freqme", &self.freqme()) - .field("utick", &self.utick()) + f.debug_struct("ApbPeripheralGroup0MemRule1") + .field("freqme00", &self.freqme00()) + .field("utick0", &self.utick0()) .field("wwdt0", &self.wwdt0()) - .field("wwdt1", &self.wwdt1()) - .field("smartdma", &self.smartdma()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for ApbPeripheralGroup0memRule1 { +impl defmt::Format for ApbPeripheralGroup0MemRule1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "ApbPeripheralGroup0memRule1 {{ ctimer4: {:?}, freqme: {:?}, utick: {:?}, wwdt0: {:?}, wwdt1: {:?}, smartdma: {:?} }}", - self.ctimer4(), - self.freqme(), - self.utick(), - self.wwdt0(), - self.wwdt1(), - self.smartdma() + "ApbPeripheralGroup0MemRule1 {{ freqme00: {:?}, utick0: {:?}, wwdt0: {:?} }}", + self.freqme00(), + self.utick0(), + self.wwdt0() ) } } #[doc = "Miscellaneous CPU0 Control Signals."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Cpu0lockReg(pub u32); -impl Cpu0lockReg { +pub struct Cpu0LockReg(pub u32); +impl Cpu0LockReg { #[doc = "LOCK_NS_VTOR."] #[must_use] #[inline(always)] @@ -2926,25 +3040,25 @@ impl Cpu0lockReg { #[doc = "LOCK_S_VTAIRCR."] #[must_use] #[inline(always)] - pub const fn lock_s_vtaircr(&self) -> LockSvtaircr { + pub const fn lock_s_vtaircr(&self) -> LockSVtaircr { let val = (self.0 >> 4usize) & 0x03; - LockSvtaircr::from_bits(val as u8) + LockSVtaircr::from_bits(val as u8) } #[doc = "LOCK_S_VTAIRCR."] #[inline(always)] - pub const fn set_lock_s_vtaircr(&mut self, val: LockSvtaircr) { + pub const fn set_lock_s_vtaircr(&mut self, val: LockSVtaircr) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } #[doc = "LOCK_S_MPU."] #[must_use] #[inline(always)] - pub const fn lock_s_mpu(&self) -> LockSmpu { + pub const fn lock_s_mpu(&self) -> LockSMpu { let val = (self.0 >> 6usize) & 0x03; - LockSmpu::from_bits(val as u8) + LockSMpu::from_bits(val as u8) } #[doc = "LOCK_S_MPU."] #[inline(always)] - pub const fn set_lock_s_mpu(&mut self, val: LockSmpu) { + pub const fn set_lock_s_mpu(&mut self, val: LockSMpu) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } #[doc = "LOCK_SAU."] @@ -2960,216 +3074,47 @@ impl Cpu0lockReg { self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } } -impl Default for Cpu0lockReg { +impl Default for Cpu0LockReg { #[inline(always)] - fn default() -> Cpu0lockReg { - Cpu0lockReg(0) + fn default() -> Cpu0LockReg { + Cpu0LockReg(0) } } -impl core::fmt::Debug for Cpu0lockReg { +impl core::fmt::Debug for Cpu0LockReg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cpu0lockReg") + f.debug_struct("Cpu0LockReg") .field("lock_ns_vtor", &self.lock_ns_vtor()) .field("lock_ns_mpu", &self.lock_ns_mpu()) .field("lock_s_vtaircr", &self.lock_s_vtaircr()) .field("lock_s_mpu", &self.lock_s_mpu()) - .field("lock_sau", &self.lock_sau()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Cpu0lockReg { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Cpu0lockReg {{ lock_ns_vtor: {:?}, lock_ns_mpu: {:?}, lock_s_vtaircr: {:?}, lock_s_mpu: {:?}, lock_sau: {:?} }}", - self.lock_ns_vtor(), - self.lock_ns_mpu(), - self.lock_s_vtaircr(), - self.lock_s_mpu(), - self.lock_sau() - ) - } -} -#[doc = "Flash Memory Rule."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flash00memRule(pub u32); -impl Flash00memRule { - #[doc = "Rule 0."] - #[must_use] - #[inline(always)] - pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "Rule 0."] - #[inline(always)] - pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); - } -} -impl Default for Flash00memRule { - #[inline(always)] - fn default() -> Flash00memRule { - Flash00memRule(0) - } -} -impl core::fmt::Debug for Flash00memRule { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flash00memRule") - .field("rule[0]", &self.rule(0usize)) - .field("rule[1]", &self.rule(1usize)) - .field("rule[2]", &self.rule(2usize)) - .field("rule[3]", &self.rule(3usize)) - .field("rule[4]", &self.rule(4usize)) - .field("rule[5]", &self.rule(5usize)) - .field("rule[6]", &self.rule(6usize)) - .field("rule[7]", &self.rule(7usize)) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Flash00memRule { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Flash00memRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", - self.rule(0usize), - self.rule(1usize), - self.rule(2usize), - self.rule(3usize), - self.rule(4usize), - self.rule(5usize), - self.rule(6usize), - self.rule(7usize) - ) - } -} -#[doc = "Flash Memory Rule."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flash01memRule(pub u32); -impl Flash01memRule { - #[doc = "Rule 0."] - #[must_use] - #[inline(always)] - pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "Rule 0."] - #[inline(always)] - pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 8usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); - } -} -impl Default for Flash01memRule { - #[inline(always)] - fn default() -> Flash01memRule { - Flash01memRule(0) - } -} -impl core::fmt::Debug for Flash01memRule { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flash01memRule") - .field("rule[0]", &self.rule(0usize)) - .field("rule[1]", &self.rule(1usize)) - .field("rule[2]", &self.rule(2usize)) - .field("rule[3]", &self.rule(3usize)) - .field("rule[4]", &self.rule(4usize)) - .field("rule[5]", &self.rule(5usize)) - .field("rule[6]", &self.rule(6usize)) - .field("rule[7]", &self.rule(7usize)) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Flash01memRule { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Flash01memRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", - self.rule(0usize), - self.rule(1usize), - self.rule(2usize), - self.rule(3usize), - self.rule(4usize), - self.rule(5usize), - self.rule(6usize), - self.rule(7usize) - ) - } -} -#[doc = "Flash IFR0 Rule register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flash02memRule(pub u32); -impl Flash02memRule { - #[doc = "Rule 0."] - #[must_use] - #[inline(always)] - pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - let val = (self.0 >> offs) & 0x03; - Rule::from_bits(val as u8) - } - #[doc = "Rule 0."] - #[inline(always)] - pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 4usize); - let offs = 0usize + n * 4usize; - self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); - } -} -impl Default for Flash02memRule { - #[inline(always)] - fn default() -> Flash02memRule { - Flash02memRule(0) - } -} -impl core::fmt::Debug for Flash02memRule { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flash02memRule") - .field("rule[0]", &self.rule(0usize)) - .field("rule[1]", &self.rule(1usize)) - .field("rule[2]", &self.rule(2usize)) - .field("rule[3]", &self.rule(3usize)) + .field("lock_sau", &self.lock_sau()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Flash02memRule { +impl defmt::Format for Cpu0LockReg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Flash02memRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", - self.rule(0usize), - self.rule(1usize), - self.rule(2usize), - self.rule(3usize) + "Cpu0LockReg {{ lock_ns_vtor: {:?}, lock_ns_mpu: {:?}, lock_s_vtaircr: {:?}, lock_s_mpu: {:?}, lock_sau: {:?} }}", + self.lock_ns_vtor(), + self.lock_ns_mpu(), + self.lock_s_vtaircr(), + self.lock_s_mpu(), + self.lock_sau() ) } } #[doc = "Flash Memory Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flash03memRule(pub u32); -impl Flash03memRule { +pub struct Flash00MemRule(pub u32); +impl Flash00MemRule { #[doc = "Rule 0."] #[must_use] #[inline(always)] pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 4usize); + assert!(n < 8usize); let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) @@ -3177,50 +3122,58 @@ impl Flash03memRule { #[doc = "Rule 0."] #[inline(always)] pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 4usize); + assert!(n < 8usize); let offs = 0usize + n * 4usize; self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for Flash03memRule { +impl Default for Flash00MemRule { #[inline(always)] - fn default() -> Flash03memRule { - Flash03memRule(0) + fn default() -> Flash00MemRule { + Flash00MemRule(0) } } -impl core::fmt::Debug for Flash03memRule { +impl core::fmt::Debug for Flash00MemRule { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flash03memRule") + f.debug_struct("Flash00MemRule") .field("rule[0]", &self.rule(0usize)) .field("rule[1]", &self.rule(1usize)) .field("rule[2]", &self.rule(2usize)) .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Flash03memRule { +impl defmt::Format for Flash00MemRule { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Flash03memRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", + "Flash00MemRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", self.rule(0usize), self.rule(1usize), self.rule(2usize), - self.rule(3usize) + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) ) } } -#[doc = "FLEXSPI0 Region 0 Memory Rule."] +#[doc = "Flash Memory Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flexspi0region0memRule(pub u32); -impl Flexspi0region0memRule { +pub struct Flash01MemRule0(pub u32); +impl Flash01MemRule0 { #[doc = "Rule 0."] #[must_use] #[inline(always)] pub const fn rule(&self, n: usize) -> Rule { - assert!(n < 8usize); + assert!(n < 4usize); let offs = 0usize + n * 4usize; let val = (self.0 >> offs) & 0x03; Rule::from_bits(val as u8) @@ -3228,53 +3181,45 @@ impl Flexspi0region0memRule { #[doc = "Rule 0."] #[inline(always)] pub const fn set_rule(&mut self, n: usize, val: Rule) { - assert!(n < 8usize); + assert!(n < 4usize); let offs = 0usize + n * 4usize; self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for Flexspi0region0memRule { +impl Default for Flash01MemRule0 { #[inline(always)] - fn default() -> Flexspi0region0memRule { - Flexspi0region0memRule(0) + fn default() -> Flash01MemRule0 { + Flash01MemRule0(0) } } -impl core::fmt::Debug for Flexspi0region0memRule { +impl core::fmt::Debug for Flash01MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flexspi0region0memRule") + f.debug_struct("Flash01MemRule0") .field("rule[0]", &self.rule(0usize)) .field("rule[1]", &self.rule(1usize)) .field("rule[2]", &self.rule(2usize)) .field("rule[3]", &self.rule(3usize)) - .field("rule[4]", &self.rule(4usize)) - .field("rule[5]", &self.rule(5usize)) - .field("rule[6]", &self.rule(6usize)) - .field("rule[7]", &self.rule(7usize)) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Flexspi0region0memRule { +impl defmt::Format for Flash01MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Flexspi0region0memRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + "Flash01MemRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", self.rule(0usize), self.rule(1usize), self.rule(2usize), - self.rule(3usize), - self.rule(4usize), - self.rule(5usize), - self.rule(6usize), - self.rule(7usize) + self.rule(3usize) ) } } -#[doc = "FLEXSPI0 Region index Memory Rule."] +#[doc = "Flash Memory Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Flexspi0regionMemRule(pub u32); -impl Flexspi0regionMemRule { +pub struct Flash02MemRule0(pub u32); +impl Flash02MemRule0 { #[doc = "Rule 0."] #[must_use] #[inline(always)] @@ -3292,15 +3237,15 @@ impl Flexspi0regionMemRule { self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); } } -impl Default for Flexspi0regionMemRule { +impl Default for Flash02MemRule0 { #[inline(always)] - fn default() -> Flexspi0regionMemRule { - Flexspi0regionMemRule(0) + fn default() -> Flash02MemRule0 { + Flash02MemRule0(0) } } -impl core::fmt::Debug for Flexspi0regionMemRule { +impl core::fmt::Debug for Flash02MemRule0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Flexspi0regionMemRule") + f.debug_struct("Flash02MemRule0") .field("rule[0]", &self.rule(0usize)) .field("rule[1]", &self.rule(1usize)) .field("rule[2]", &self.rule(2usize)) @@ -3309,11 +3254,11 @@ impl core::fmt::Debug for Flexspi0regionMemRule { } } #[cfg(feature = "defmt")] -impl defmt::Format for Flexspi0regionMemRule { +impl defmt::Format for Flash02MemRule0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Flexspi0regionMemRule {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", + "Flash02MemRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?} }}", self.rule(0usize), self.rule(1usize), self.rule(2usize), @@ -3326,77 +3271,41 @@ impl defmt::Format for Flexspi0regionMemRule { #[derive(Copy, Clone, Eq, PartialEq)] pub struct MasterSecAntiPolReg(pub u32); impl MasterSecAntiPolReg { - #[doc = "SMARTDMA Data."] - #[must_use] - #[inline(always)] - pub const fn smartdma(&self) -> MasterSec { - let val = (self.0 >> 4usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "SMARTDMA Data."] - #[inline(always)] - pub const fn set_smartdma(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "eDMA0."] + #[doc = "DMA0."] #[must_use] #[inline(always)] pub const fn dma0(&self) -> MasterSec { - let val = (self.0 >> 6usize) & 0x03; + let val = (self.0 >> 2usize) & 0x03; MasterSec::from_bits(val as u8) } - #[doc = "eDMA0."] + #[doc = "DMA0."] #[inline(always)] pub const fn set_dma0(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); - } - #[doc = "eDMA1."] - #[must_use] - #[inline(always)] - pub const fn dma1(&self) -> MasterSec { - let val = (self.0 >> 8usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "eDMA1."] - #[inline(always)] - pub const fn set_dma1(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "PKC."] #[must_use] #[inline(always)] pub const fn pkc(&self) -> MasterSec { - let val = (self.0 >> 10usize) & 0x03; + let val = (self.0 >> 4usize) & 0x03; MasterSec::from_bits(val as u8) } #[doc = "PKC."] #[inline(always)] pub const fn set_pkc(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize); - } - #[doc = "ENET0."] - #[must_use] - #[inline(always)] - pub const fn enet0(&self) -> MasterSec { - let val = (self.0 >> 24usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "ENET0."] - #[inline(always)] - pub const fn set_enet0(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "USB1."] + #[doc = "DMA1."] #[must_use] #[inline(always)] - pub const fn usb1(&self) -> MasterSec { - let val = (self.0 >> 26usize) & 0x03; + pub const fn dma1(&self) -> MasterSec { + let val = (self.0 >> 6usize) & 0x03; MasterSec::from_bits(val as u8) } - #[doc = "USB1."] + #[doc = "DMA1."] #[inline(always)] - pub const fn set_usb1(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize); + pub const fn set_dma1(&mut self, val: MasterSec) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } } impl Default for MasterSecAntiPolReg { @@ -3408,12 +3317,9 @@ impl Default for MasterSecAntiPolReg { impl core::fmt::Debug for MasterSecAntiPolReg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("MasterSecAntiPolReg") - .field("smartdma", &self.smartdma()) .field("dma0", &self.dma0()) - .field("dma1", &self.dma1()) .field("pkc", &self.pkc()) - .field("enet0", &self.enet0()) - .field("usb1", &self.usb1()) + .field("dma1", &self.dma1()) .finish() } } @@ -3422,13 +3328,10 @@ impl defmt::Format for MasterSecAntiPolReg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MasterSecAntiPolReg {{ smartdma: {:?}, dma0: {:?}, dma1: {:?}, pkc: {:?}, enet0: {:?}, usb1: {:?} }}", - self.smartdma(), + "MasterSecAntiPolReg {{ dma0: {:?}, pkc: {:?}, dma1: {:?} }}", self.dma0(), - self.dma1(), self.pkc(), - self.enet0(), - self.usb1() + self.dma1() ) } } @@ -3437,77 +3340,41 @@ impl defmt::Format for MasterSecAntiPolReg { #[derive(Copy, Clone, Eq, PartialEq)] pub struct MasterSecLevel(pub u32); impl MasterSecLevel { - #[doc = "SMARTDMA Data."] - #[must_use] - #[inline(always)] - pub const fn smartdma(&self) -> MasterSec { - let val = (self.0 >> 4usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "SMARTDMA Data."] - #[inline(always)] - pub const fn set_smartdma(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); - } - #[doc = "eDMA0."] + #[doc = "DMA0."] #[must_use] #[inline(always)] pub const fn dma0(&self) -> MasterSec { - let val = (self.0 >> 6usize) & 0x03; + let val = (self.0 >> 2usize) & 0x03; MasterSec::from_bits(val as u8) } - #[doc = "eDMA0."] + #[doc = "DMA0."] #[inline(always)] pub const fn set_dma0(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); - } - #[doc = "eDMA1."] - #[must_use] - #[inline(always)] - pub const fn dma1(&self) -> MasterSec { - let val = (self.0 >> 8usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "eDMA1."] - #[inline(always)] - pub const fn set_dma1(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "PKC."] #[must_use] #[inline(always)] pub const fn pkc(&self) -> MasterSec { - let val = (self.0 >> 10usize) & 0x03; + let val = (self.0 >> 4usize) & 0x03; MasterSec::from_bits(val as u8) } #[doc = "PKC."] #[inline(always)] pub const fn set_pkc(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize); - } - #[doc = "ENET0."] - #[must_use] - #[inline(always)] - pub const fn enet0(&self) -> MasterSec { - let val = (self.0 >> 24usize) & 0x03; - MasterSec::from_bits(val as u8) - } - #[doc = "ENET0."] - #[inline(always)] - pub const fn set_enet0(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "USB1."] + #[doc = "DMA1."] #[must_use] #[inline(always)] - pub const fn usb1(&self) -> MasterSec { - let val = (self.0 >> 26usize) & 0x03; + pub const fn dma1(&self) -> MasterSec { + let val = (self.0 >> 6usize) & 0x03; MasterSec::from_bits(val as u8) } - #[doc = "USB1."] + #[doc = "DMA1."] #[inline(always)] - pub const fn set_usb1(&mut self, val: MasterSec) { - self.0 = (self.0 & !(0x03 << 26usize)) | (((val.to_bits() as u32) & 0x03) << 26usize); + pub const fn set_dma1(&mut self, val: MasterSec) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } } impl Default for MasterSecLevel { @@ -3519,12 +3386,9 @@ impl Default for MasterSecLevel { impl core::fmt::Debug for MasterSecLevel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("MasterSecLevel") - .field("smartdma", &self.smartdma()) .field("dma0", &self.dma0()) - .field("dma1", &self.dma1()) .field("pkc", &self.pkc()) - .field("enet0", &self.enet0()) - .field("usb1", &self.usb1()) + .field("dma1", &self.dma1()) .finish() } } @@ -3533,13 +3397,10 @@ impl defmt::Format for MasterSecLevel { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MasterSecLevel {{ smartdma: {:?}, dma0: {:?}, dma1: {:?}, pkc: {:?}, enet0: {:?}, usb1: {:?} }}", - self.smartdma(), + "MasterSecLevel {{ dma0: {:?}, pkc: {:?}, dma1: {:?} }}", self.dma0(), - self.dma1(), self.pkc(), - self.enet0(), - self.usb1() + self.dma1() ) } } @@ -3793,7 +3654,7 @@ impl defmt::Format for MiscCtrlReg { ) } } -#[doc = "RAMA Memory Rule 0."] +#[doc = "RAMA Memory Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct RamMemRule(pub u32); @@ -3852,6 +3713,65 @@ impl defmt::Format for RamMemRule { ) } } +#[doc = "RAMX Memory Rule."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RamxMemRule0(pub u32); +impl RamxMemRule0 { + #[doc = "Rule 0."] + #[must_use] + #[inline(always)] + pub const fn rule(&self, n: usize) -> Rule { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + Rule::from_bits(val as u8) + } + #[doc = "Rule 0."] + #[inline(always)] + pub const fn set_rule(&mut self, n: usize, val: Rule) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.to_bits() as u32) & 0x03) << offs); + } +} +impl Default for RamxMemRule0 { + #[inline(always)] + fn default() -> RamxMemRule0 { + RamxMemRule0(0) + } +} +impl core::fmt::Debug for RamxMemRule0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RamxMemRule0") + .field("rule[0]", &self.rule(0usize)) + .field("rule[1]", &self.rule(1usize)) + .field("rule[2]", &self.rule(2usize)) + .field("rule[3]", &self.rule(3usize)) + .field("rule[4]", &self.rule(4usize)) + .field("rule[5]", &self.rule(5usize)) + .field("rule[6]", &self.rule(6usize)) + .field("rule[7]", &self.rule(7usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for RamxMemRule0 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "RamxMemRule0 {{ rule[0]: {:?}, rule[1]: {:?}, rule[2]: {:?}, rule[3]: {:?}, rule[4]: {:?}, rule[5]: {:?}, rule[6]: {:?}, rule[7]: {:?} }}", + self.rule(0usize), + self.rule(1usize), + self.rule(2usize), + self.rule(3usize), + self.rule(4usize), + self.rule(5usize), + self.rule(6usize), + self.rule(7usize) + ) + } +} #[doc = "ROM Memory Rule."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4067,98 +3987,18 @@ impl SecVioInfoValid { #[doc = "Violation information valid flag for AHB port 0."] #[must_use] #[inline(always)] - pub const fn vio_info_valid0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + pub const fn vio_info_valid(&self, n: usize) -> bool { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; val != 0 } #[doc = "Violation information valid flag for AHB port 0."] #[inline(always)] - pub const fn set_vio_info_valid0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "Violation information valid flag for AHB port 1."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid1(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 1."] - #[inline(always)] - pub const fn set_vio_info_valid1(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); - } - #[doc = "Violation information valid flag for AHB port 2."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid2(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 2."] - #[inline(always)] - pub const fn set_vio_info_valid2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); - } - #[doc = "Violation information valid flag for AHB port 3."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid3(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 3."] - #[inline(always)] - pub const fn set_vio_info_valid3(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } - #[doc = "Violation information valid flag for AHB port 4."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid4(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 4."] - #[inline(always)] - pub const fn set_vio_info_valid4(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); - } - #[doc = "Violation information valid flag for AHB port 5."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid5(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 5."] - #[inline(always)] - pub const fn set_vio_info_valid5(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); - } - #[doc = "Violation information valid flag for AHB port 6."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid6(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 6."] - #[inline(always)] - pub const fn set_vio_info_valid6(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); - } - #[doc = "Violation information valid flag for AHB port 7."] - #[must_use] - #[inline(always)] - pub const fn vio_info_valid7(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 - } - #[doc = "Violation information valid flag for AHB port 7."] - #[inline(always)] - pub const fn set_vio_info_valid7(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + pub const fn set_vio_info_valid(&mut self, n: usize, val: bool) { + assert!(n < 8usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } } impl Default for SecVioInfoValid { @@ -4170,14 +4010,14 @@ impl Default for SecVioInfoValid { impl core::fmt::Debug for SecVioInfoValid { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("SecVioInfoValid") - .field("vio_info_valid0", &self.vio_info_valid0()) - .field("vio_info_valid1", &self.vio_info_valid1()) - .field("vio_info_valid2", &self.vio_info_valid2()) - .field("vio_info_valid3", &self.vio_info_valid3()) - .field("vio_info_valid4", &self.vio_info_valid4()) - .field("vio_info_valid5", &self.vio_info_valid5()) - .field("vio_info_valid6", &self.vio_info_valid6()) - .field("vio_info_valid7", &self.vio_info_valid7()) + .field("vio_info_valid[0]", &self.vio_info_valid(0usize)) + .field("vio_info_valid[1]", &self.vio_info_valid(1usize)) + .field("vio_info_valid[2]", &self.vio_info_valid(2usize)) + .field("vio_info_valid[3]", &self.vio_info_valid(3usize)) + .field("vio_info_valid[4]", &self.vio_info_valid(4usize)) + .field("vio_info_valid[5]", &self.vio_info_valid(5usize)) + .field("vio_info_valid[6]", &self.vio_info_valid(6usize)) + .field("vio_info_valid[7]", &self.vio_info_valid(7usize)) .finish() } } @@ -4186,15 +4026,15 @@ impl defmt::Format for SecVioInfoValid { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "SecVioInfoValid {{ vio_info_valid0: {=bool:?}, vio_info_valid1: {=bool:?}, vio_info_valid2: {=bool:?}, vio_info_valid3: {=bool:?}, vio_info_valid4: {=bool:?}, vio_info_valid5: {=bool:?}, vio_info_valid6: {=bool:?}, vio_info_valid7: {=bool:?} }}", - self.vio_info_valid0(), - self.vio_info_valid1(), - self.vio_info_valid2(), - self.vio_info_valid3(), - self.vio_info_valid4(), - self.vio_info_valid5(), - self.vio_info_valid6(), - self.vio_info_valid7() + "SecVioInfoValid {{ vio_info_valid[0]: {=bool:?}, vio_info_valid[1]: {=bool:?}, vio_info_valid[2]: {=bool:?}, vio_info_valid[3]: {=bool:?}, vio_info_valid[4]: {=bool:?}, vio_info_valid[5]: {=bool:?}, vio_info_valid[6]: {=bool:?}, vio_info_valid[7]: {=bool:?} }}", + self.vio_info_valid(0usize), + self.vio_info_valid(1usize), + self.vio_info_valid(2usize), + self.vio_info_valid(3usize), + self.vio_info_valid(4usize), + self.vio_info_valid(5usize), + self.vio_info_valid(6usize), + self.vio_info_valid(7usize) ) } } @@ -4290,9 +4130,9 @@ impl defmt::Format for SecVioMiscInfo { pub enum LockNsMpu { _RESERVED_0 = 0x0, #[doc = "CM33 (CPU0) LOCK_NS_MPU is 1."] - LOCK_NS_MPU_EQ_1 = 0x01, + LockNsMpuEq1 = 0x01, #[doc = "CM33 (CPU0) LOCK_NS_MPU is 0."] - LOCK_NS_MPU_EQ_0 = 0x02, + LockNsMpuEq0 = 0x02, _RESERVED_3 = 0x03, } impl LockNsMpu { @@ -4323,9 +4163,9 @@ impl From for u8 { pub enum LockNsVtor { _RESERVED_0 = 0x0, #[doc = "CM33 (CPU0) LOCKNSVTOR is 1."] - LOCK_NS_VTOR_EQ_1 = 0x01, + LockNsVtorEq1 = 0x01, #[doc = "CM33 (CPU0) LOCKNSVTOR is 0."] - LOCK_NS_VTOR_EQ_0 = 0x02, + LockNsVtorEq0 = 0x02, _RESERVED_3 = 0x03, } impl LockNsVtor { @@ -4353,17 +4193,17 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LockSau { +pub enum LockSMpu { _RESERVED_0 = 0x0, - #[doc = "CM33 (CPU0) LOCK_SAU is 1."] - LOCK_SAU_EQ_1 = 0x01, - #[doc = "CM33 (CPU0) LOCK_SAU is 0."] - LOCK_SAU_EQ_0 = 0x02, + #[doc = "CM33 (CPU0) LOCK_S_MPU is 1."] + LockSMpuEq1 = 0x01, + #[doc = "CM33 (CPU0) LOCK_S_MPU is 0."] + LockSMpuEq0 = 0x02, _RESERVED_3 = 0x03, } -impl LockSau { +impl LockSMpu { #[inline(always)] - pub const fn from_bits(val: u8) -> LockSau { + pub const fn from_bits(val: u8) -> LockSMpu { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -4371,32 +4211,32 @@ impl LockSau { unsafe { core::mem::transmute(self) } } } -impl From for LockSau { +impl From for LockSMpu { #[inline(always)] - fn from(val: u8) -> LockSau { - LockSau::from_bits(val) + fn from(val: u8) -> LockSMpu { + LockSMpu::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: LockSau) -> u8 { - LockSau::to_bits(val) + fn from(val: LockSMpu) -> u8 { + LockSMpu::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LockSmpu { +pub enum LockSVtaircr { _RESERVED_0 = 0x0, - #[doc = "CM33 (CPU0) LOCK_S_MPU is 1."] - LOCK_S_MPU_EQ_1 = 0x01, - #[doc = "CM33 (CPU0) LOCK_S_MPU is 0."] - LOCK_S_MPU_EQ_0 = 0x02, + #[doc = "CM33 (CPU0) LOCK_S_VTAIRCR is 1."] + LockSVtaircrEq1 = 0x01, + #[doc = "CM33 (CPU0) LOCK_S_VTAIRCR is 0."] + LockSVtaircrEq0 = 0x02, _RESERVED_3 = 0x03, } -impl LockSmpu { +impl LockSVtaircr { #[inline(always)] - pub const fn from_bits(val: u8) -> LockSmpu { + pub const fn from_bits(val: u8) -> LockSVtaircr { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -4404,32 +4244,32 @@ impl LockSmpu { unsafe { core::mem::transmute(self) } } } -impl From for LockSmpu { +impl From for LockSVtaircr { #[inline(always)] - fn from(val: u8) -> LockSmpu { - LockSmpu::from_bits(val) + fn from(val: u8) -> LockSVtaircr { + LockSVtaircr::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: LockSmpu) -> u8 { - LockSmpu::to_bits(val) + fn from(val: LockSVtaircr) -> u8 { + LockSVtaircr::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LockSvtaircr { +pub enum LockSau { _RESERVED_0 = 0x0, - #[doc = "CM33 (CPU0) LOCK_S_VTAIRCR is 1."] - LOCK_S_VTAIRCR_EQ_1 = 0x01, - #[doc = "CM33 (CPU0) LOCK_S_VTAIRCR is 0."] - LOCK_S_VTAIRCR_EQ_0 = 0x02, + #[doc = "CM33 (CPU0) LOCK_SAU is 1."] + LockSauEq1 = 0x01, + #[doc = "CM33 (CPU0) LOCK_SAU is 0."] + LockSauEq0 = 0x02, _RESERVED_3 = 0x03, } -impl LockSvtaircr { +impl LockSau { #[inline(always)] - pub const fn from_bits(val: u8) -> LockSvtaircr { + pub const fn from_bits(val: u8) -> LockSau { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -4437,30 +4277,30 @@ impl LockSvtaircr { unsafe { core::mem::transmute(self) } } } -impl From for LockSvtaircr { +impl From for LockSau { #[inline(always)] - fn from(val: u8) -> LockSvtaircr { - LockSvtaircr::from_bits(val) + fn from(val: u8) -> LockSau { + LockSau::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: LockSvtaircr) -> u8 { - LockSvtaircr::to_bits(val) + fn from(val: LockSau) -> u8 { + LockSau::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MasterSec { - #[doc = "Non-secure and non-privileged Master."] - NONSECURE_NONPRIV_MASTER = 0x0, - #[doc = "Non-secure and privileged Master."] - NONSECURE_PRIV_MASTER = 0x01, - #[doc = "Secure and non-privileged Master."] - SECURE_NONPRIV_MASTER = 0x02, #[doc = "Secure and privileged Master."] - SECURE_PRIV_MASTER = 0x03, + NonsecureNonprivMaster = 0x0, + #[doc = "Secure and non-privileged Master."] + NonsecurePrivMaster = 0x01, + #[doc = "Non-secure and privileged Master."] + SecureNonprivMaster = 0x02, + #[doc = "Non-secure and non-privileged Master."] + SecurePrivMaster = 0x03, } impl MasterSec { #[inline(always)] @@ -4490,9 +4330,9 @@ impl From for u8 { pub enum MiscCtrlEnable { _RESERVED_0 = 0x0, #[doc = "Enables the privilege checking of non-secure mode access."] - ENABLED = 0x01, + Enabled = 0x01, #[doc = "Disables the privilege checking of non-secure mode access."] - DISABLED = 0x02, + Disabled = 0x02, _RESERVED_3 = 0x03, } impl MiscCtrlEnable { @@ -4522,10 +4362,10 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MiscCtrlRegDisableStrictMode { _RESERVED_0 = 0x0, - #[doc = "Master can access memories and peripherals at the same level or below that level."] - AHBTM = 0x01, - #[doc = "Master can access memories and peripherals at same level only."] - AHBSM1 = 0x02, + #[doc = "Master strict mode is disabled and can access memories and peripherals at the same level or below that level."] + Ahbtm = 0x01, + #[doc = "Master strict mode is enabled and can access memories and peripherals at same level only."] + Ahbsm1 = 0x02, _RESERVED_3 = 0x03, } impl MiscCtrlRegDisableStrictMode { @@ -4556,9 +4396,9 @@ impl From for u8 { pub enum MiscCtrlRegDisableViolationAbort { _RESERVED_0 = 0x0, #[doc = "The violation detected by the secure checker will not cause an abort, but a secure_violation_irq (interrupt request) will still be asserted and serviced by ISR."] - NO_ABORT = 0x01, + NoAbort = 0x01, #[doc = "The violation detected by the secure checker will cause an abort."] - ABORT = 0x02, + Abort = 0x02, _RESERVED_3 = 0x03, } impl MiscCtrlRegDisableViolationAbort { @@ -4589,9 +4429,9 @@ impl From for u8 { pub enum MiscCtrlRegIdauAllNs { _RESERVED_0 = 0x0, #[doc = "IDAU is disabled, which means that all memories are attributed as non-secure memory."] - DISABLED = 0x01, + Disabled = 0x01, #[doc = "IDAU is enabled (restrictive mode)."] - ENABLED = 0x02, + Enabled = 0x02, _RESERVED_3 = 0x03, } impl MiscCtrlRegIdauAllNs { @@ -4622,9 +4462,9 @@ impl From for u8 { pub enum MiscCtrlRegWriteLock { _RESERVED_0 = 0x0, #[doc = "Writes to this register and to the Memory and Peripheral RULE registers are not allowed."] - LOCKED = 0x01, + Locked = 0x01, #[doc = "Writes to this register and to the Memory and Peripheral RULE registers are allowed."] - NOT_LOCKED = 0x02, + NotLocked = 0x02, _RESERVED_3 = 0x03, } impl MiscCtrlRegWriteLock { @@ -4654,13 +4494,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rule { #[doc = "Non-secure and non-privilege user access allowed."] - NONSECURE_NONPRIV_USER_ALLOWED = 0x0, + NonsecureNonprivUserAllowed = 0x0, #[doc = "Non-secure and privilege access allowed."] - NONSECURE_PRIV_USER_ALLOWED = 0x01, + NonsecurePrivUserAllowed = 0x01, #[doc = "Secure and non-privilege user access allowed."] - SECURE_NONPRIV_USER_ALLOWED = 0x02, + SecureNonprivUserAllowed = 0x02, #[doc = "Secure and privilege user access allowed."] - SECURE_PRIV_USER_ALLOWED = 0x03, + SecurePrivUserAllowed = 0x03, } impl Rule { #[inline(always)] @@ -4689,9 +4529,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SecVioInfoDataAccess { #[doc = "Code."] - CODE = 0x0, + Code = 0x0, #[doc = "Data."] - DATA = 0x01, + Data = 0x01, } impl SecVioInfoDataAccess { #[inline(always)] @@ -4719,30 +4559,25 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SecVioInfoMaster { - #[doc = "CM33 Code."] - CPU0_CODE = 0x0, - #[doc = "CM33 System."] - CPU0_SYS = 0x01, - #[doc = "SMARTDMA Instruction."] - SDMA_INSTR = 0x02, - #[doc = "SMARTDMA Data."] - SDMA_DATA = 0x03, - #[doc = "eDMA1."] - E_DMA1 = 0x04, - #[doc = "eDMA0."] - E_DMA0 = 0x05, - #[doc = "USB HS."] - USB_HS = 0x06, - _RESERVED_7 = 0x07, + #[doc = "M33 Code."] + Cpu0Code = 0x0, + #[doc = "M33 System."] + Cpu0Sys = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "DMA0."] + Dma0 = 0x05, + _RESERVED_6 = 0x06, + #[doc = "DMA1."] + Dma1 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, - #[doc = "eSPI."] - ESPI = 0x0a, + _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, #[doc = "PKC."] - PKC = 0x0c, - #[doc = "Ethernet."] - ENET = 0x0d, + Pkc = 0x0c, + _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, _RESERVED_f = 0x0f, _RESERVED_10 = 0x10, @@ -4789,9 +4624,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SecVioInfoWrite { #[doc = "Read access."] - READ = 0x0, + Read = 0x0, #[doc = "Write access."] - WRITE = 0x01, + Write = 0x01, } impl SecVioInfoWrite { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/CDOG.rs b/nxp-pac/src/meta_peripherals/mcxa/CDOG.rs index a4e9f93..5ac9040 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/CDOG.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/CDOG.rs @@ -1,7 +1,8 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] -#[doc = "CDOG."] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] +#[doc = "Code Watchdog Timer."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Cdog { ptr: *mut u8, @@ -34,6 +35,13 @@ impl Cdog { ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x08usize) as _) } } + #[doc = "Secure Counter Register."] + #[inline(always)] + pub const fn secure_counter( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0cusize) as _) } + } #[doc = "Status 1 Register."] #[inline(always)] pub const fn status(self) -> crate::pac::common::Reg { @@ -109,11 +117,6 @@ impl Cdog { pub const fn sub256(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x48usize) as _) } } - #[doc = "ASSERT16 Command Register."] - #[inline(always)] - pub const fn assert16(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x4cusize) as _) } - } } #[doc = "ADD Command Register."] #[repr(transparent)] @@ -257,43 +260,6 @@ impl defmt::Format for Add256 { defmt::write!(f, "Add256 {{ ad256: {=u32:?} }}", self.ad256()) } } -#[doc = "ASSERT16 Command Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Assert16(pub u32); -impl Assert16 { - #[doc = "ASSERT16 Command."] - #[must_use] - #[inline(always)] - pub const fn ast16(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "ASSERT16 Command."] - #[inline(always)] - pub const fn set_ast16(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for Assert16 { - #[inline(always)] - fn default() -> Assert16 { - Assert16(0) - } -} -impl core::fmt::Debug for Assert16 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Assert16") - .field("ast16", &self.ast16()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Assert16 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Assert16 {{ ast16: {=u32:?} }}", self.ast16()) - } -} #[doc = "Control Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -706,6 +672,43 @@ impl defmt::Format for Restart { defmt::write!(f, "Restart {{ rstrt: {=u32:?} }}", self.rstrt()) } } +#[doc = "Secure Counter Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct SecureCounter(pub u32); +impl SecureCounter { + #[doc = "Secure Counter."] + #[must_use] + #[inline(always)] + pub const fn seccnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Secure Counter."] + #[inline(always)] + pub const fn set_seccnt(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for SecureCounter { + #[inline(always)] + fn default() -> SecureCounter { + SecureCounter(0) + } +} +impl core::fmt::Debug for SecureCounter { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SecureCounter") + .field("seccnt", &self.seccnt()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for SecureCounter { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "SecureCounter {{ seccnt: {=u32:?} }}", self.seccnt()) + } +} #[doc = "START Command Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1076,12 +1079,12 @@ impl defmt::Format for Sub256 { pub enum Ctrl { _RESERVED_0 = 0x0, #[doc = "Enable reset."] - ENABLE_RESET = 0x01, + EnableReset = 0x01, #[doc = "Enable interrupt."] - ENABLE_INTERRUPT = 0x02, + EnableInterrupt = 0x02, _RESERVED_3 = 0x03, #[doc = "Disable both reset and interrupt."] - DISABLE_BOTH = 0x04, + DisableBoth = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, @@ -1114,9 +1117,9 @@ impl From for u8 { pub enum DebugHaltCtrl { _RESERVED_0 = 0x0, #[doc = "Keep the timer running."] - RUN_TIMER = 0x01, + RunTimer = 0x01, #[doc = "Stop the timer."] - PAUSE_TIMER = 0x02, + PauseTimer = 0x02, _RESERVED_3 = 0x03, } impl DebugHaltCtrl { @@ -1147,9 +1150,9 @@ impl From for u8 { pub enum IrqPause { _RESERVED_0 = 0x0, #[doc = "Keep the timer running."] - RUN_TIMER = 0x01, + RunTimer = 0x01, #[doc = "Stop the timer."] - PAUSE_TIMER = 0x02, + PauseTimer = 0x02, _RESERVED_3 = 0x03, } impl IrqPause { @@ -1180,9 +1183,9 @@ impl From for u8 { pub enum LockCtrl { _RESERVED_0 = 0x0, #[doc = "Locked."] - LOCKED = 0x01, + Locked = 0x01, #[doc = "Unlocked."] - UNLOCKED = 0x02, + Unlocked = 0x02, _RESERVED_3 = 0x03, } impl LockCtrl { diff --git a/nxp-pac/src/meta_peripherals/mcxa/CMC.rs b/nxp-pac/src/meta_peripherals/mcxa/CMC.rs index 31d16e8..6208c0b 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/CMC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/CMC.rs @@ -1,7 +1,8 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] -#[doc = "CMC."] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] +#[doc = "Core Mode Controller."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Cmc { ptr: *mut u8, @@ -22,6 +23,11 @@ impl Cmc { pub const fn verid(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize) as _) } } + #[doc = "Parameter."] + #[inline(always)] + pub const fn param(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04usize) as _) } + } #[doc = "Clock Control."] #[inline(always)] pub const fn ckctrl(self) -> crate::pac::common::Reg { @@ -82,11 +88,26 @@ impl Cmc { pub const fn fm0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xb0usize) as _) } } + #[doc = "SRAM Shut Down Register."] + #[inline(always)] + pub const fn sramdis0(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc0usize) as _) } + } + #[doc = "SRAM Deep Sleep Register."] + #[inline(always)] + pub const fn sramret0(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd0usize) as _) } + } #[doc = "Flash Control."] #[inline(always)] pub const fn flashcr(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe0usize) as _) } } + #[doc = "BootROM Status Register."] + #[inline(always)] + pub const fn bsr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0100usize) as _) } + } #[doc = "Core Control."] #[inline(always)] pub const fn corectl(self) -> crate::pac::common::Reg { @@ -97,6 +118,51 @@ impl Cmc { pub const fn dbgctl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize) as _) } } + #[doc = "Unlock Register."] + #[inline(always)] + pub const fn unlock(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0200usize) as _) } + } + #[doc = "Test Register."] + #[inline(always)] + pub const fn test(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0204usize) as _) } + } +} +#[doc = "BootROM Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Bsr(pub u32); +impl Bsr { + #[doc = "Provides status information written by the BootROM."] + #[must_use] + #[inline(always)] + pub const fn stat(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Provides status information written by the BootROM."] + #[inline(always)] + pub const fn set_stat(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Bsr { + #[inline(always)] + fn default() -> Bsr { + Bsr(0) + } +} +impl core::fmt::Debug for Bsr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Bsr").field("stat", &self.stat()).finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Bsr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Bsr {{ stat: {=u32:?} }}", self.stat()) + } } #[doc = "Clock Control."] #[repr(transparent)] @@ -106,13 +172,13 @@ impl Ckctrl { #[doc = "Clocking Mode."] #[must_use] #[inline(always)] - pub const fn ckmode(&self) -> CkctrlCkmode { + pub const fn ckmode(&self) -> Ckmode { let val = (self.0 >> 0usize) & 0x0f; - CkctrlCkmode::from_bits(val as u8) + Ckmode::from_bits(val as u8) } #[doc = "Clocking Mode."] #[inline(always)] - pub const fn set_ckmode(&mut self, val: CkctrlCkmode) { + pub const fn set_ckmode(&mut self, val: Ckmode) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); } #[doc = "Lock."] @@ -161,13 +227,13 @@ impl Ckstat { #[doc = "Low Power Status."] #[must_use] #[inline(always)] - pub const fn ckmode(&self) -> CkstatCkmode { + pub const fn ckmode(&self) -> Ckmode { let val = (self.0 >> 0usize) & 0x0f; - CkstatCkmode::from_bits(val as u8) + Ckmode::from_bits(val as u8) } #[doc = "Low Power Status."] #[inline(always)] - pub const fn set_ckmode(&mut self, val: CkstatCkmode) { + pub const fn set_ckmode(&mut self, val: Ckmode) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); } #[doc = "Wake-up Source."] @@ -442,14 +508,14 @@ impl defmt::Format for Gpmctrl { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mr0(pub u32); impl Mr0 { - #[doc = "In System Programming Mode."] + #[doc = "Boot Configuration."] #[must_use] #[inline(always)] pub const fn ispmode_n(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "In System Programming Mode."] + #[doc = "Boot Configuration."] #[inline(always)] pub const fn set_ispmode_n(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -635,6 +701,220 @@ impl defmt::Format for Rpc { ) } } +#[doc = "SRAM Shut Down Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sramdis0(pub u32); +impl Sramdis0 { + #[doc = "Shut Down Enable."] + #[must_use] + #[inline(always)] + pub const fn dis(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Shut Down Enable."] + #[inline(always)] + pub const fn set_dis(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Sramdis0 { + #[inline(always)] + fn default() -> Sramdis0 { + Sramdis0(0) + } +} +impl core::fmt::Debug for Sramdis0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sramdis0") + .field("dis[0]", &self.dis(0usize)) + .field("dis[1]", &self.dis(1usize)) + .field("dis[2]", &self.dis(2usize)) + .field("dis[3]", &self.dis(3usize)) + .field("dis[4]", &self.dis(4usize)) + .field("dis[5]", &self.dis(5usize)) + .field("dis[6]", &self.dis(6usize)) + .field("dis[7]", &self.dis(7usize)) + .field("dis[8]", &self.dis(8usize)) + .field("dis[9]", &self.dis(9usize)) + .field("dis[10]", &self.dis(10usize)) + .field("dis[11]", &self.dis(11usize)) + .field("dis[12]", &self.dis(12usize)) + .field("dis[13]", &self.dis(13usize)) + .field("dis[14]", &self.dis(14usize)) + .field("dis[15]", &self.dis(15usize)) + .field("dis[16]", &self.dis(16usize)) + .field("dis[17]", &self.dis(17usize)) + .field("dis[18]", &self.dis(18usize)) + .field("dis[19]", &self.dis(19usize)) + .field("dis[20]", &self.dis(20usize)) + .field("dis[21]", &self.dis(21usize)) + .field("dis[22]", &self.dis(22usize)) + .field("dis[23]", &self.dis(23usize)) + .field("dis[24]", &self.dis(24usize)) + .field("dis[25]", &self.dis(25usize)) + .field("dis[26]", &self.dis(26usize)) + .field("dis[27]", &self.dis(27usize)) + .field("dis[28]", &self.dis(28usize)) + .field("dis[29]", &self.dis(29usize)) + .field("dis[30]", &self.dis(30usize)) + .field("dis[31]", &self.dis(31usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sramdis0 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sramdis0 {{ dis[0]: {=bool:?}, dis[1]: {=bool:?}, dis[2]: {=bool:?}, dis[3]: {=bool:?}, dis[4]: {=bool:?}, dis[5]: {=bool:?}, dis[6]: {=bool:?}, dis[7]: {=bool:?}, dis[8]: {=bool:?}, dis[9]: {=bool:?}, dis[10]: {=bool:?}, dis[11]: {=bool:?}, dis[12]: {=bool:?}, dis[13]: {=bool:?}, dis[14]: {=bool:?}, dis[15]: {=bool:?}, dis[16]: {=bool:?}, dis[17]: {=bool:?}, dis[18]: {=bool:?}, dis[19]: {=bool:?}, dis[20]: {=bool:?}, dis[21]: {=bool:?}, dis[22]: {=bool:?}, dis[23]: {=bool:?}, dis[24]: {=bool:?}, dis[25]: {=bool:?}, dis[26]: {=bool:?}, dis[27]: {=bool:?}, dis[28]: {=bool:?}, dis[29]: {=bool:?}, dis[30]: {=bool:?}, dis[31]: {=bool:?} }}", + self.dis(0usize), + self.dis(1usize), + self.dis(2usize), + self.dis(3usize), + self.dis(4usize), + self.dis(5usize), + self.dis(6usize), + self.dis(7usize), + self.dis(8usize), + self.dis(9usize), + self.dis(10usize), + self.dis(11usize), + self.dis(12usize), + self.dis(13usize), + self.dis(14usize), + self.dis(15usize), + self.dis(16usize), + self.dis(17usize), + self.dis(18usize), + self.dis(19usize), + self.dis(20usize), + self.dis(21usize), + self.dis(22usize), + self.dis(23usize), + self.dis(24usize), + self.dis(25usize), + self.dis(26usize), + self.dis(27usize), + self.dis(28usize), + self.dis(29usize), + self.dis(30usize), + self.dis(31usize) + ) + } +} +#[doc = "SRAM Deep Sleep Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sramret0(pub u32); +impl Sramret0 { + #[doc = "Deep Sleep Enable."] + #[must_use] + #[inline(always)] + pub const fn ret(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Deep Sleep Enable."] + #[inline(always)] + pub const fn set_ret(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } +} +impl Default for Sramret0 { + #[inline(always)] + fn default() -> Sramret0 { + Sramret0(0) + } +} +impl core::fmt::Debug for Sramret0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sramret0") + .field("ret[0]", &self.ret(0usize)) + .field("ret[1]", &self.ret(1usize)) + .field("ret[2]", &self.ret(2usize)) + .field("ret[3]", &self.ret(3usize)) + .field("ret[4]", &self.ret(4usize)) + .field("ret[5]", &self.ret(5usize)) + .field("ret[6]", &self.ret(6usize)) + .field("ret[7]", &self.ret(7usize)) + .field("ret[8]", &self.ret(8usize)) + .field("ret[9]", &self.ret(9usize)) + .field("ret[10]", &self.ret(10usize)) + .field("ret[11]", &self.ret(11usize)) + .field("ret[12]", &self.ret(12usize)) + .field("ret[13]", &self.ret(13usize)) + .field("ret[14]", &self.ret(14usize)) + .field("ret[15]", &self.ret(15usize)) + .field("ret[16]", &self.ret(16usize)) + .field("ret[17]", &self.ret(17usize)) + .field("ret[18]", &self.ret(18usize)) + .field("ret[19]", &self.ret(19usize)) + .field("ret[20]", &self.ret(20usize)) + .field("ret[21]", &self.ret(21usize)) + .field("ret[22]", &self.ret(22usize)) + .field("ret[23]", &self.ret(23usize)) + .field("ret[24]", &self.ret(24usize)) + .field("ret[25]", &self.ret(25usize)) + .field("ret[26]", &self.ret(26usize)) + .field("ret[27]", &self.ret(27usize)) + .field("ret[28]", &self.ret(28usize)) + .field("ret[29]", &self.ret(29usize)) + .field("ret[30]", &self.ret(30usize)) + .field("ret[31]", &self.ret(31usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sramret0 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sramret0 {{ ret[0]: {=bool:?}, ret[1]: {=bool:?}, ret[2]: {=bool:?}, ret[3]: {=bool:?}, ret[4]: {=bool:?}, ret[5]: {=bool:?}, ret[6]: {=bool:?}, ret[7]: {=bool:?}, ret[8]: {=bool:?}, ret[9]: {=bool:?}, ret[10]: {=bool:?}, ret[11]: {=bool:?}, ret[12]: {=bool:?}, ret[13]: {=bool:?}, ret[14]: {=bool:?}, ret[15]: {=bool:?}, ret[16]: {=bool:?}, ret[17]: {=bool:?}, ret[18]: {=bool:?}, ret[19]: {=bool:?}, ret[20]: {=bool:?}, ret[21]: {=bool:?}, ret[22]: {=bool:?}, ret[23]: {=bool:?}, ret[24]: {=bool:?}, ret[25]: {=bool:?}, ret[26]: {=bool:?}, ret[27]: {=bool:?}, ret[28]: {=bool:?}, ret[29]: {=bool:?}, ret[30]: {=bool:?}, ret[31]: {=bool:?} }}", + self.ret(0usize), + self.ret(1usize), + self.ret(2usize), + self.ret(3usize), + self.ret(4usize), + self.ret(5usize), + self.ret(6usize), + self.ret(7usize), + self.ret(8usize), + self.ret(9usize), + self.ret(10usize), + self.ret(11usize), + self.ret(12usize), + self.ret(13usize), + self.ret(14usize), + self.ret(15usize), + self.ret(16usize), + self.ret(17usize), + self.ret(18usize), + self.ret(19usize), + self.ret(20usize), + self.ret(21usize), + self.ret(22usize), + self.ret(23usize), + self.ret(24usize), + self.ret(25usize), + self.ret(26usize), + self.ret(27usize), + self.ret(28usize), + self.ret(29usize), + self.ret(30usize), + self.ret(31usize) + ) + } +} #[doc = "System Reset Interrupt Enable."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -688,16 +968,16 @@ impl Srie { pub const fn set_scg(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[must_use] #[inline(always)] - pub const fn wwdt0(&self) -> bool { + pub const fn wdog0(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[inline(always)] - pub const fn set_wwdt0(&mut self, val: bool) { + pub const fn set_wdog0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } #[doc = "Software Reset."] @@ -724,6 +1004,18 @@ impl Srie { pub const fn set_lockup(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "Watchdog 1 Reset."] + #[must_use] + #[inline(always)] + pub const fn wdog1(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Watchdog 1 Reset."] + #[inline(always)] + pub const fn set_wdog1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } #[doc = "Code Watchdog 0 Reset."] #[must_use] #[inline(always)] @@ -762,9 +1054,10 @@ impl core::fmt::Debug for Srie { .field("dap", &self.dap()) .field("lpack", &self.lpack()) .field("scg", &self.scg()) - .field("wwdt0", &self.wwdt0()) + .field("wdog0", &self.wdog0()) .field("sw", &self.sw()) .field("lockup", &self.lockup()) + .field("wdog1", &self.wdog1()) .field("cdog0", &self.cdog0()) .field("cdog1", &self.cdog1()) .finish() @@ -775,14 +1068,15 @@ impl defmt::Format for Srie { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Srie {{ pin: {=bool:?}, dap: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wwdt0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?} }}", + "Srie {{ pin: {=bool:?}, dap: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wdog0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, wdog1: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?} }}", self.pin(), self.dap(), self.lpack(), self.scg(), - self.wwdt0(), + self.wdog0(), self.sw(), self.lockup(), + self.wdog1(), self.cdog0(), self.cdog1() ) @@ -829,16 +1123,16 @@ impl Srif { pub const fn set_lpack(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[must_use] #[inline(always)] - pub const fn wwdt0(&self) -> bool { + pub const fn wdog0(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[inline(always)] - pub const fn set_wwdt0(&mut self, val: bool) { + pub const fn set_wdog0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } #[doc = "Software Reset."] @@ -865,6 +1159,18 @@ impl Srif { pub const fn set_lockup(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "Watchdog 1 Reset."] + #[must_use] + #[inline(always)] + pub const fn wdog1(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Watchdog 1 Reset."] + #[inline(always)] + pub const fn set_wdog1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } #[doc = "Code Watchdog 0 Reset."] #[must_use] #[inline(always)] @@ -902,9 +1208,10 @@ impl core::fmt::Debug for Srif { .field("pin", &self.pin()) .field("dap", &self.dap()) .field("lpack", &self.lpack()) - .field("wwdt0", &self.wwdt0()) + .field("wdog0", &self.wdog0()) .field("sw", &self.sw()) .field("lockup", &self.lockup()) + .field("wdog1", &self.wdog1()) .field("cdog0", &self.cdog0()) .field("cdog1", &self.cdog1()) .finish() @@ -915,13 +1222,14 @@ impl defmt::Format for Srif { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Srif {{ pin: {=bool:?}, dap: {=bool:?}, lpack: {=bool:?}, wwdt0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?} }}", + "Srif {{ pin: {=bool:?}, dap: {=bool:?}, lpack: {=bool:?}, wdog0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, wdog1: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?} }}", self.pin(), self.dap(), self.lpack(), - self.wwdt0(), + self.wdog0(), self.sw(), self.lockup(), + self.wdog1(), self.cdog0(), self.cdog1() ) @@ -956,18 +1264,30 @@ impl Srs { pub const fn set_por(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Voltage Detect Reset."] + #[doc = "Low Voltage Detect Reset."] #[must_use] #[inline(always)] - pub const fn vd(&self) -> bool { + pub const fn lvd(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Voltage Detect Reset."] + #[doc = "Low Voltage Detect Reset."] #[inline(always)] - pub const fn set_vd(&mut self, val: bool) { + pub const fn set_lvd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } + #[doc = "High Voltage Detect Reset."] + #[must_use] + #[inline(always)] + pub const fn hvd(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "High Voltage Detect Reset."] + #[inline(always)] + pub const fn set_hvd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } #[doc = "Warm Reset."] #[must_use] #[inline(always)] @@ -1052,16 +1372,16 @@ impl Srs { pub const fn set_scg(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[must_use] #[inline(always)] - pub const fn wwdt0(&self) -> bool { + pub const fn wdog0(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[inline(always)] - pub const fn set_wwdt0(&mut self, val: bool) { + pub const fn set_wdog0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } #[doc = "Software Reset."] @@ -1088,6 +1408,18 @@ impl Srs { pub const fn set_lockup(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "Watchdog 1 Reset."] + #[must_use] + #[inline(always)] + pub const fn wdog1(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Watchdog 1 Reset."] + #[inline(always)] + pub const fn set_wdog1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } #[doc = "Code Watchdog 0 Reset."] #[must_use] #[inline(always)] @@ -1124,6 +1456,18 @@ impl Srs { pub const fn set_jtag(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } + #[doc = "Security Violation Reset."] + #[must_use] + #[inline(always)] + pub const fn secvio(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Security Violation Reset."] + #[inline(always)] + pub const fn set_secvio(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } #[doc = "Tamper Reset."] #[must_use] #[inline(always)] @@ -1148,7 +1492,8 @@ impl core::fmt::Debug for Srs { f.debug_struct("Srs") .field("wakeup", &self.wakeup()) .field("por", &self.por()) - .field("vd", &self.vd()) + .field("lvd", &self.lvd()) + .field("hvd", &self.hvd()) .field("warm", &self.warm()) .field("fatal", &self.fatal()) .field("pin", &self.pin()) @@ -1156,12 +1501,14 @@ impl core::fmt::Debug for Srs { .field("rstack", &self.rstack()) .field("lpack", &self.lpack()) .field("scg", &self.scg()) - .field("wwdt0", &self.wwdt0()) + .field("wdog0", &self.wdog0()) .field("sw", &self.sw()) .field("lockup", &self.lockup()) + .field("wdog1", &self.wdog1()) .field("cdog0", &self.cdog0()) .field("cdog1", &self.cdog1()) .field("jtag", &self.jtag()) + .field("secvio", &self.secvio()) .field("tamper", &self.tamper()) .finish() } @@ -1171,10 +1518,11 @@ impl defmt::Format for Srs { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Srs {{ wakeup: {=bool:?}, por: {=bool:?}, vd: {=bool:?}, warm: {=bool:?}, fatal: {=bool:?}, pin: {=bool:?}, dap: {=bool:?}, rstack: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wwdt0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?}, jtag: {=bool:?}, tamper: {=bool:?} }}", + "Srs {{ wakeup: {=bool:?}, por: {=bool:?}, lvd: {=bool:?}, hvd: {=bool:?}, warm: {=bool:?}, fatal: {=bool:?}, pin: {=bool:?}, dap: {=bool:?}, rstack: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wdog0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, wdog1: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?}, jtag: {=bool:?}, secvio: {=bool:?}, tamper: {=bool:?} }}", self.wakeup(), self.por(), - self.vd(), + self.lvd(), + self.hvd(), self.warm(), self.fatal(), self.pin(), @@ -1182,12 +1530,14 @@ impl defmt::Format for Srs { self.rstack(), self.lpack(), self.scg(), - self.wwdt0(), + self.wdog0(), self.sw(), self.lockup(), + self.wdog1(), self.cdog0(), self.cdog1(), self.jtag(), + self.secvio(), self.tamper() ) } @@ -1221,18 +1571,30 @@ impl Ssrs { pub const fn set_por(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Voltage Detect Reset."] + #[doc = "Low Voltage Detect Reset."] #[must_use] #[inline(always)] - pub const fn vd(&self) -> bool { + pub const fn lvd(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Voltage Detect Reset."] + #[doc = "Low Voltage Detect Reset."] #[inline(always)] - pub const fn set_vd(&mut self, val: bool) { + pub const fn set_lvd(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } + #[doc = "High Voltage Detect Reset."] + #[must_use] + #[inline(always)] + pub const fn hvd(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "High Voltage Detect Reset."] + #[inline(always)] + pub const fn set_hvd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } #[doc = "Warm Reset."] #[must_use] #[inline(always)] @@ -1317,16 +1679,16 @@ impl Ssrs { pub const fn set_scg(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[must_use] #[inline(always)] - pub const fn wwdt0(&self) -> bool { + pub const fn wdog0(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Windowed Watchdog 0 Reset."] + #[doc = "Watchdog 0 Reset."] #[inline(always)] - pub const fn set_wwdt0(&mut self, val: bool) { + pub const fn set_wdog0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } #[doc = "Software Reset."] @@ -1353,6 +1715,18 @@ impl Ssrs { pub const fn set_lockup(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "Watchdog 1 Reset."] + #[must_use] + #[inline(always)] + pub const fn wdog1(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Watchdog 1 Reset."] + #[inline(always)] + pub const fn set_wdog1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } #[doc = "Code Watchdog 0 Reset."] #[must_use] #[inline(always)] @@ -1389,6 +1763,18 @@ impl Ssrs { pub const fn set_jtag(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } + #[doc = "Security Violation Reset."] + #[must_use] + #[inline(always)] + pub const fn secvio(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Security Violation Reset."] + #[inline(always)] + pub const fn set_secvio(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } #[doc = "Tamper Reset."] #[must_use] #[inline(always)] @@ -1413,7 +1799,8 @@ impl core::fmt::Debug for Ssrs { f.debug_struct("Ssrs") .field("wakeup", &self.wakeup()) .field("por", &self.por()) - .field("vd", &self.vd()) + .field("lvd", &self.lvd()) + .field("hvd", &self.hvd()) .field("warm", &self.warm()) .field("fatal", &self.fatal()) .field("pin", &self.pin()) @@ -1421,12 +1808,14 @@ impl core::fmt::Debug for Ssrs { .field("rstack", &self.rstack()) .field("lpack", &self.lpack()) .field("scg", &self.scg()) - .field("wwdt0", &self.wwdt0()) + .field("wdog0", &self.wdog0()) .field("sw", &self.sw()) .field("lockup", &self.lockup()) + .field("wdog1", &self.wdog1()) .field("cdog0", &self.cdog0()) .field("cdog1", &self.cdog1()) .field("jtag", &self.jtag()) + .field("secvio", &self.secvio()) .field("tamper", &self.tamper()) .finish() } @@ -1436,10 +1825,11 @@ impl defmt::Format for Ssrs { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ssrs {{ wakeup: {=bool:?}, por: {=bool:?}, vd: {=bool:?}, warm: {=bool:?}, fatal: {=bool:?}, pin: {=bool:?}, dap: {=bool:?}, rstack: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wwdt0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?}, jtag: {=bool:?}, tamper: {=bool:?} }}", + "Ssrs {{ wakeup: {=bool:?}, por: {=bool:?}, lvd: {=bool:?}, hvd: {=bool:?}, warm: {=bool:?}, fatal: {=bool:?}, pin: {=bool:?}, dap: {=bool:?}, rstack: {=bool:?}, lpack: {=bool:?}, scg: {=bool:?}, wdog0: {=bool:?}, sw: {=bool:?}, lockup: {=bool:?}, wdog1: {=bool:?}, cdog0: {=bool:?}, cdog1: {=bool:?}, jtag: {=bool:?}, secvio: {=bool:?}, tamper: {=bool:?} }}", self.wakeup(), self.por(), - self.vd(), + self.lvd(), + self.hvd(), self.warm(), self.fatal(), self.pin(), @@ -1447,16 +1837,110 @@ impl defmt::Format for Ssrs { self.rstack(), self.lpack(), self.scg(), - self.wwdt0(), + self.wdog0(), self.sw(), self.lockup(), + self.wdog1(), self.cdog0(), self.cdog1(), self.jtag(), + self.secvio(), self.tamper() ) } } +#[doc = "Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Test(pub u32); +impl Test { + #[doc = "Observe."] + #[must_use] + #[inline(always)] + pub const fn observe(&self) -> Observe { + let val = (self.0 >> 0usize) & 0x0f; + Observe::from_bits(val as u8) + } + #[doc = "Observe."] + #[inline(always)] + pub const fn set_observe(&mut self, val: Observe) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + } +} +impl Default for Test { + #[inline(always)] + fn default() -> Test { + Test(0) + } +} +impl core::fmt::Debug for Test { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Test") + .field("observe", &self.observe()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Test { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Test {{ observe: {:?} }}", self.observe()) + } +} +#[doc = "Unlock Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Unlock(pub u32); +impl Unlock { + #[doc = "Allow Writes."] + #[must_use] + #[inline(always)] + pub const fn alwr(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Allow Writes."] + #[inline(always)] + pub const fn set_alwr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Value."] + #[must_use] + #[inline(always)] + pub const fn value(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Value."] + #[inline(always)] + pub const fn set_value(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Unlock { + #[inline(always)] + fn default() -> Unlock { + Unlock(0) + } +} +impl core::fmt::Debug for Unlock { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Unlock") + .field("alwr", &self.alwr()) + .field("value", &self.value()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Unlock { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Unlock {{ alwr: {=bool:?}, value: {=u16:?} }}", + self.alwr(), + self.value() + ) + } +} #[doc = "Version ID."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1529,17 +2013,19 @@ impl defmt::Format for Verid { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum CkctrlCkmode { +pub enum Ckmode { #[doc = "Core clock is on."] - CKMODE0000 = 0x0, + Ckmode0000 = 0x0, #[doc = "Core clock is off."] - CKMODE0001 = 0x01, + Ckmode0001 = 0x01, _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, + #[doc = "Core and platform clocks are off."] + Ckmode0011 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, + #[doc = "Core, platform, and peripheral clocks are off, but no change in Low-Power mode."] + Ckmode0111 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, @@ -1548,11 +2034,11 @@ pub enum CkctrlCkmode { _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode."] - CKMODE1111 = 0x0f, + Ckmode1111 = 0x0f, } -impl CkctrlCkmode { +impl Ckmode { #[inline(always)] - pub const fn from_bits(val: u8) -> CkctrlCkmode { + pub const fn from_bits(val: u8) -> Ckmode { unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] @@ -1560,32 +2046,38 @@ impl CkctrlCkmode { unsafe { core::mem::transmute(self) } } } -impl From for CkctrlCkmode { +impl From for Ckmode { #[inline(always)] - fn from(val: u8) -> CkctrlCkmode { - CkctrlCkmode::from_bits(val) + fn from(val: u8) -> Ckmode { + Ckmode::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: CkctrlCkmode) -> u8 { - CkctrlCkmode::to_bits(val) + fn from(val: Ckmode) -> u8 { + Ckmode::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum CkstatCkmode { - #[doc = "Core clock is on."] - CKMODE0000 = 0x0, - #[doc = "Core clock is off."] - CKMODE0001 = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, +pub enum Observe { + #[doc = "Core Active (not sleeping, halted or in reset)."] + Test0 = 0x0, + #[doc = "Core clock gated."] + Test1 = 0x01, + #[doc = "Bus master clock gated."] + Test10 = 0x02, + #[doc = "Bus slave clock gated."] + Test11 = 0x03, + #[doc = "Peripherals clock gated."] + Test100 = 0x04, + #[doc = "Flash clock gated."] + Test101 = 0x05, + #[doc = "All clocks gated."] + Test110 = 0x06, + #[doc = "CMC clock gated."] + Test111 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, @@ -1593,12 +2085,11 @@ pub enum CkstatCkmode { _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, - #[doc = "Core, platform, and peripheral clocks are off, and core enters Low-Power mode."] - CKMODE1111 = 0x0f, + _RESERVED_f = 0x0f, } -impl CkstatCkmode { +impl Observe { #[inline(always)] - pub const fn from_bits(val: u8) -> CkstatCkmode { + pub const fn from_bits(val: u8) -> Observe { unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] @@ -1606,33 +2097,34 @@ impl CkstatCkmode { unsafe { core::mem::transmute(self) } } } -impl From for CkstatCkmode { +impl From for Observe { #[inline(always)] - fn from(val: u8) -> CkstatCkmode { - CkstatCkmode::from_bits(val) + fn from(val: u8) -> Observe { + Observe::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: CkstatCkmode) -> u8 { - CkstatCkmode::to_bits(val) + fn from(val: Observe) -> u8 { + Observe::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PmctrlmainLpmode { - #[doc = "Active/Sleep."] - LPMODE0000 = 0x0, - #[doc = "Deep Sleep."] - LPMODE0001 = 0x01, + #[doc = "Active."] + Lpmode0000 = 0x0, + #[doc = "Sleep."] + Lpmode0001 = 0x01, _RESERVED_2 = 0x02, - #[doc = "Power Down."] - LPMODE0011 = 0x03, + #[doc = "Deep Sleep."] + Lpmode0011 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, + #[doc = "Power Down."] + Lpmode0111 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, @@ -1641,7 +2133,7 @@ pub enum PmctrlmainLpmode { _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, #[doc = "Deep-Power Down."] - LPMODE1111 = 0x0f, + Lpmode1111 = 0x0f, } impl PmctrlmainLpmode { #[inline(always)] @@ -1670,37 +2162,37 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PmprotLpmode { #[doc = "Not allowed."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Allowed."] - EN = 0x01, + En = 0x01, #[doc = "Allowed."] - EN1 = 0x02, + En1 = 0x02, #[doc = "Allowed."] - EN2 = 0x03, + En2 = 0x03, #[doc = "Allowed."] - EN3 = 0x04, + En3 = 0x04, #[doc = "Allowed."] - EN4 = 0x05, + En4 = 0x05, #[doc = "Allowed."] - EN5 = 0x06, + En5 = 0x06, #[doc = "Allowed."] - EN6 = 0x07, + En6 = 0x07, #[doc = "Allowed."] - EN7 = 0x08, + En7 = 0x08, #[doc = "Allowed."] - EN8 = 0x09, + En8 = 0x09, #[doc = "Allowed."] - EN9 = 0x0a, + En9 = 0x0a, #[doc = "Allowed."] - EN10 = 0x0b, + En10 = 0x0b, #[doc = "Allowed."] - EN11 = 0x0c, + En11 = 0x0c, #[doc = "Allowed."] - EN12 = 0x0d, + En12 = 0x0d, #[doc = "Allowed."] - EN13 = 0x0e, + En13 = 0x0e, #[doc = "Allowed."] - EN14 = 0x0f, + En14 = 0x0f, } impl PmprotLpmode { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/CRC.rs b/nxp-pac/src/meta_peripherals/mcxa/CRC.rs index 279ee58..28ac2c4 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/CRC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/CRC.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "CRC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Crc { @@ -144,152 +145,14 @@ impl defmt::Format for Ctrl { ) } } -#[doc = "Data."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Data(pub u32); -impl Data { - #[doc = "Lower Part of Low Byte."] - #[must_use] - #[inline(always)] - pub const fn ll(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Lower Part of Low Byte."] - #[inline(always)] - pub const fn set_ll(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Upper Part of Low Byte."] - #[must_use] - #[inline(always)] - pub const fn lu(&self) -> u8 { - let val = (self.0 >> 8usize) & 0xff; - val as u8 - } - #[doc = "Upper Part of Low Byte."] - #[inline(always)] - pub const fn set_lu(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); - } - #[doc = "Lower Part of High Byte."] - #[must_use] - #[inline(always)] - pub const fn hl(&self) -> u8 { - let val = (self.0 >> 16usize) & 0xff; - val as u8 - } - #[doc = "Lower Part of High Byte."] - #[inline(always)] - pub const fn set_hl(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); - } - #[doc = "Upper Part of High Byte."] - #[must_use] - #[inline(always)] - pub const fn hu(&self) -> u8 { - let val = (self.0 >> 24usize) & 0xff; - val as u8 - } - #[doc = "Upper Part of High Byte."] - #[inline(always)] - pub const fn set_hu(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize); - } -} -impl Default for Data { - #[inline(always)] - fn default() -> Data { - Data(0) - } -} -impl core::fmt::Debug for Data { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Data") - .field("ll", &self.ll()) - .field("lu", &self.lu()) - .field("hl", &self.hl()) - .field("hu", &self.hu()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Data { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Data {{ ll: {=u8:?}, lu: {=u8:?}, hl: {=u8:?}, hu: {=u8:?} }}", - self.ll(), - self.lu(), - self.hl(), - self.hu() - ) - } -} -#[doc = "Polynomial."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Gpoly(pub u32); -impl Gpoly { - #[doc = "Low Half-Word."] - #[must_use] - #[inline(always)] - pub const fn low(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Low Half-Word."] - #[inline(always)] - pub const fn set_low(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } - #[doc = "High Half-Word."] - #[must_use] - #[inline(always)] - pub const fn high(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "High Half-Word."] - #[inline(always)] - pub const fn set_high(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } -} -impl Default for Gpoly { - #[inline(always)] - fn default() -> Gpoly { - Gpoly(0) - } -} -impl core::fmt::Debug for Gpoly { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gpoly") - .field("low", &self.low()) - .field("high", &self.high()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Gpoly { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Gpoly {{ low: {=u16:?}, high: {=u16:?} }}", - self.low(), - self.high() - ) - } -} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fxor { #[doc = "Disables XOR on reading data."] - NOXOR = 0x0, + Noxor = 0x0, #[doc = "Inverts or complements the read value of the CRC Data."] - INVERT = 0x01, + Invert = 0x01, } impl Fxor { #[inline(always)] @@ -349,13 +212,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tot { #[doc = "No transposition."] - NOTRNPS = 0x0, + Notrnps = 0x0, #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - BTS_TRNPS = 0x01, + BtsTrnps = 0x01, #[doc = "Both bits in bytes and bytes are transposed."] - BYTS_BTS_TRNPS = 0x02, + BytsBtsTrnps = 0x02, #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - BYTS_TRNPS = 0x03, + BytsTrnps = 0x03, } impl Tot { #[inline(always)] @@ -384,13 +247,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Totr { #[doc = "No transposition."] - NOTRNPS = 0x0, + Notrnps = 0x0, #[doc = "Bits in bytes are transposed, but bytes are not transposed."] - BTS_TRNPS = 0x01, + BtsTrnps = 0x01, #[doc = "Both bits in bytes and bytes are transposed."] - BYTS_BTS_TRNPS = 0x02, + BytsBtsTrnps = 0x02, #[doc = "Only bytes are transposed, no bits in a byte are transposed."] - BYTS_TRNPS = 0x03, + BytsTrnps = 0x03, } impl Totr { #[inline(always)] @@ -419,9 +282,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Was { #[doc = "Data values."] - DATA = 0x0, + Data = 0x0, #[doc = "Seed values."] - SEED = 0x01, + Seed = 0x01, } impl Was { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/CTIMER.rs b/nxp-pac/src/meta_peripherals/mcxa/CTIMER.rs index a395e1b..ed1bf46 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/CTIMER.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/CTIMER.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Standard Counter or Timer."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ctimer { @@ -100,146 +101,146 @@ impl Ccr { #[doc = "Rising Edge of Capture Channel 0."] #[must_use] #[inline(always)] - pub const fn cap0re(&self) -> Capre { + pub const fn cap0re(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - Capre::from_bits(val as u8) + val != 0 } #[doc = "Rising Edge of Capture Channel 0."] #[inline(always)] - pub const fn set_cap0re(&mut self, val: Capre) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_cap0re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Falling Edge of Capture Channel 0."] #[must_use] #[inline(always)] - pub const fn cap0fe(&self) -> Capfe { + pub const fn cap0fe(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - Capfe::from_bits(val as u8) + val != 0 } #[doc = "Falling Edge of Capture Channel 0."] #[inline(always)] - pub const fn set_cap0fe(&mut self, val: Capfe) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_cap0fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "Generate Interrupt on Channel 0 Capture Event."] #[must_use] #[inline(always)] - pub const fn cap0i(&self) -> Capi { + pub const fn cap0i(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - Capi::from_bits(val as u8) + val != 0 } #[doc = "Generate Interrupt on Channel 0 Capture Event."] #[inline(always)] - pub const fn set_cap0i(&mut self, val: Capi) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_cap0i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } #[doc = "Rising Edge of Capture Channel 1."] #[must_use] #[inline(always)] - pub const fn cap1re(&self) -> Capre { + pub const fn cap1re(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - Capre::from_bits(val as u8) + val != 0 } #[doc = "Rising Edge of Capture Channel 1."] #[inline(always)] - pub const fn set_cap1re(&mut self, val: Capre) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_cap1re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } #[doc = "Falling Edge of Capture Channel 1."] #[must_use] #[inline(always)] - pub const fn cap1fe(&self) -> Capfe { + pub const fn cap1fe(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - Capfe::from_bits(val as u8) + val != 0 } #[doc = "Falling Edge of Capture Channel 1."] #[inline(always)] - pub const fn set_cap1fe(&mut self, val: Capfe) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_cap1fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } #[doc = "Generate Interrupt on Channel 1 Capture Event."] #[must_use] #[inline(always)] - pub const fn cap1i(&self) -> Capi { + pub const fn cap1i(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; - Capi::from_bits(val as u8) + val != 0 } #[doc = "Generate Interrupt on Channel 1 Capture Event."] #[inline(always)] - pub const fn set_cap1i(&mut self, val: Capi) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_cap1i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } #[doc = "Rising Edge of Capture Channel 2."] #[must_use] #[inline(always)] - pub const fn cap2re(&self) -> Capre { + pub const fn cap2re(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; - Capre::from_bits(val as u8) + val != 0 } #[doc = "Rising Edge of Capture Channel 2."] #[inline(always)] - pub const fn set_cap2re(&mut self, val: Capre) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + pub const fn set_cap2re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } #[doc = "Falling Edge of Capture Channel 2."] #[must_use] #[inline(always)] - pub const fn cap2fe(&self) -> Capfe { + pub const fn cap2fe(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; - Capfe::from_bits(val as u8) + val != 0 } #[doc = "Falling Edge of Capture Channel 2."] #[inline(always)] - pub const fn set_cap2fe(&mut self, val: Capfe) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + pub const fn set_cap2fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } #[doc = "Generate Interrupt on Channel 2 Capture Event."] #[must_use] #[inline(always)] - pub const fn cap2i(&self) -> Capi { + pub const fn cap2i(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; - Capi::from_bits(val as u8) + val != 0 } #[doc = "Generate Interrupt on Channel 2 Capture Event."] #[inline(always)] - pub const fn set_cap2i(&mut self, val: Capi) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + pub const fn set_cap2i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } #[doc = "Rising Edge of Capture Channel 3."] #[must_use] #[inline(always)] - pub const fn cap3re(&self) -> Capre { + pub const fn cap3re(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; - Capre::from_bits(val as u8) + val != 0 } #[doc = "Rising Edge of Capture Channel 3."] #[inline(always)] - pub const fn set_cap3re(&mut self, val: Capre) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + pub const fn set_cap3re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } #[doc = "Falling Edge of Capture Channel 3."] #[must_use] #[inline(always)] - pub const fn cap3fe(&self) -> Capfe { + pub const fn cap3fe(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; - Capfe::from_bits(val as u8) + val != 0 } #[doc = "Falling Edge of Capture Channel 3."] #[inline(always)] - pub const fn set_cap3fe(&mut self, val: Capfe) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_cap3fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } #[doc = "Generate Interrupt on Channel 3 Capture Event."] #[must_use] #[inline(always)] - pub const fn cap3i(&self) -> Capi { + pub const fn cap3i(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; - Capi::from_bits(val as u8) + val != 0 } #[doc = "Generate Interrupt on Channel 3 Capture Event."] #[inline(always)] - pub const fn set_cap3i(&mut self, val: Capi) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + pub const fn set_cap3i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } } impl Default for Ccr { @@ -271,7 +272,7 @@ impl defmt::Format for Ccr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ccr {{ cap0re: {:?}, cap0fe: {:?}, cap0i: {:?}, cap1re: {:?}, cap1fe: {:?}, cap1i: {:?}, cap2re: {:?}, cap2fe: {:?}, cap2i: {:?}, cap3re: {:?}, cap3fe: {:?}, cap3i: {:?} }}", + "Ccr {{ cap0re: {=bool:?}, cap0fe: {=bool:?}, cap0i: {=bool:?}, cap1re: {=bool:?}, cap1fe: {=bool:?}, cap1i: {=bool:?}, cap2re: {=bool:?}, cap2fe: {=bool:?}, cap2i: {=bool:?}, cap3re: {=bool:?}, cap3fe: {=bool:?}, cap3i: {=bool:?} }}", self.cap0re(), self.cap0fe(), self.cap0i(), @@ -413,50 +414,50 @@ impl Emr { #[doc = "External Match 0."] #[must_use] #[inline(always)] - pub const fn em0(&self) -> Em { + pub const fn em0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - Em::from_bits(val as u8) + val != 0 } #[doc = "External Match 0."] #[inline(always)] - pub const fn set_em0(&mut self, val: Em) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_em0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "External Match 1."] #[must_use] #[inline(always)] - pub const fn em1(&self) -> Em { + pub const fn em1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - Em::from_bits(val as u8) + val != 0 } #[doc = "External Match 1."] #[inline(always)] - pub const fn set_em1(&mut self, val: Em) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_em1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "External Match 2."] #[must_use] #[inline(always)] - pub const fn em2(&self) -> Em { + pub const fn em2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - Em::from_bits(val as u8) + val != 0 } #[doc = "External Match 2."] #[inline(always)] - pub const fn set_em2(&mut self, val: Em) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_em2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } #[doc = "External Match 3."] #[must_use] #[inline(always)] - pub const fn em3(&self) -> Em { + pub const fn em3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - Em::from_bits(val as u8) + val != 0 } #[doc = "External Match 3."] #[inline(always)] - pub const fn set_em3(&mut self, val: Em) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_em3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } #[doc = "External Match Control 0."] #[must_use] @@ -532,7 +533,7 @@ impl defmt::Format for Emr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Emr {{ em0: {:?}, em1: {:?}, em2: {:?}, em3: {:?}, emc0: {:?}, emc1: {:?}, emc2: {:?}, emc3: {:?} }}", + "Emr {{ em0: {=bool:?}, em1: {=bool:?}, em2: {=bool:?}, em3: {=bool:?}, emc0: {:?}, emc1: {:?}, emc2: {:?}, emc3: {:?} }}", self.em0(), self.em1(), self.em2(), @@ -691,194 +692,194 @@ impl Mcr { #[doc = "Interrupt on MR0."] #[must_use] #[inline(always)] - pub const fn mr0i(&self) -> Mri { + pub const fn mr0i(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - Mri::from_bits(val as u8) + val != 0 } #[doc = "Interrupt on MR0."] #[inline(always)] - pub const fn set_mr0i(&mut self, val: Mri) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_mr0i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Reset on MR0."] #[must_use] #[inline(always)] - pub const fn mr0r(&self) -> Mrr { + pub const fn mr0r(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - Mrr::from_bits(val as u8) + val != 0 } #[doc = "Reset on MR0."] #[inline(always)] - pub const fn set_mr0r(&mut self, val: Mrr) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_mr0r(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "Stop on MR0."] #[must_use] #[inline(always)] - pub const fn mr0s(&self) -> Mrs { + pub const fn mr0s(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - Mrs::from_bits(val as u8) + val != 0 } #[doc = "Stop on MR0."] #[inline(always)] - pub const fn set_mr0s(&mut self, val: Mrs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_mr0s(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } #[doc = "Interrupt on MR1."] #[must_use] #[inline(always)] - pub const fn mr1i(&self) -> Mri { + pub const fn mr1i(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - Mri::from_bits(val as u8) + val != 0 } #[doc = "Interrupt on MR1."] #[inline(always)] - pub const fn set_mr1i(&mut self, val: Mri) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_mr1i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } #[doc = "Reset on MR1."] #[must_use] #[inline(always)] - pub const fn mr1r(&self) -> Mrr { + pub const fn mr1r(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - Mrr::from_bits(val as u8) + val != 0 } #[doc = "Reset on MR1."] #[inline(always)] - pub const fn set_mr1r(&mut self, val: Mrr) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_mr1r(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } #[doc = "Stop on MR1."] #[must_use] #[inline(always)] - pub const fn mr1s(&self) -> Mrs { + pub const fn mr1s(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; - Mrs::from_bits(val as u8) + val != 0 } #[doc = "Stop on MR1."] #[inline(always)] - pub const fn set_mr1s(&mut self, val: Mrs) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_mr1s(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } #[doc = "Interrupt on MR2."] #[must_use] #[inline(always)] - pub const fn mr2i(&self) -> Mri { + pub const fn mr2i(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; - Mri::from_bits(val as u8) + val != 0 } #[doc = "Interrupt on MR2."] #[inline(always)] - pub const fn set_mr2i(&mut self, val: Mri) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + pub const fn set_mr2i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } #[doc = "Reset on MR2."] #[must_use] #[inline(always)] - pub const fn mr2r(&self) -> Mrr { + pub const fn mr2r(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; - Mrr::from_bits(val as u8) + val != 0 } #[doc = "Reset on MR2."] #[inline(always)] - pub const fn set_mr2r(&mut self, val: Mrr) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + pub const fn set_mr2r(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } #[doc = "Stop on MR2."] #[must_use] #[inline(always)] - pub const fn mr2s(&self) -> Mrs { + pub const fn mr2s(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; - Mrs::from_bits(val as u8) + val != 0 } #[doc = "Stop on MR2."] #[inline(always)] - pub const fn set_mr2s(&mut self, val: Mrs) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + pub const fn set_mr2s(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } #[doc = "Interrupt on MR3."] #[must_use] #[inline(always)] - pub const fn mr3i(&self) -> Mri { + pub const fn mr3i(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; - Mri::from_bits(val as u8) + val != 0 } #[doc = "Interrupt on MR3."] #[inline(always)] - pub const fn set_mr3i(&mut self, val: Mri) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + pub const fn set_mr3i(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } #[doc = "Reset on MR3."] #[must_use] #[inline(always)] - pub const fn mr3r(&self) -> Mrr { + pub const fn mr3r(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; - Mrr::from_bits(val as u8) + val != 0 } #[doc = "Reset on MR3."] #[inline(always)] - pub const fn set_mr3r(&mut self, val: Mrr) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_mr3r(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } #[doc = "Stop on MR3."] #[must_use] #[inline(always)] - pub const fn mr3s(&self) -> Mrs { + pub const fn mr3s(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; - Mrs::from_bits(val as u8) + val != 0 } #[doc = "Stop on MR3."] #[inline(always)] - pub const fn set_mr3s(&mut self, val: Mrs) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + pub const fn set_mr3s(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } #[doc = "Reload MR."] #[must_use] #[inline(always)] - pub const fn mr0rl(&self) -> Mrrl { + pub const fn mr0rl(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; - Mrrl::from_bits(val as u8) + val != 0 } #[doc = "Reload MR."] #[inline(always)] - pub const fn set_mr0rl(&mut self, val: Mrrl) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + pub const fn set_mr0rl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } #[doc = "Reload MR."] #[must_use] #[inline(always)] - pub const fn mr1rl(&self) -> Mrrl { + pub const fn mr1rl(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; - Mrrl::from_bits(val as u8) + val != 0 } #[doc = "Reload MR."] #[inline(always)] - pub const fn set_mr1rl(&mut self, val: Mrrl) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize); + pub const fn set_mr1rl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } #[doc = "Reload MR."] #[must_use] #[inline(always)] - pub const fn mr2rl(&self) -> Mrrl { + pub const fn mr2rl(&self) -> bool { let val = (self.0 >> 26usize) & 0x01; - Mrrl::from_bits(val as u8) + val != 0 } #[doc = "Reload MR."] #[inline(always)] - pub const fn set_mr2rl(&mut self, val: Mrrl) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + pub const fn set_mr2rl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } #[doc = "Reload MR."] #[must_use] #[inline(always)] - pub const fn mr3rl(&self) -> Mrrl { + pub const fn mr3rl(&self) -> bool { let val = (self.0 >> 27usize) & 0x01; - Mrrl::from_bits(val as u8) + val != 0 } #[doc = "Reload MR."] #[inline(always)] - pub const fn set_mr3rl(&mut self, val: Mrrl) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); + pub const fn set_mr3rl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); } } impl Default for Mcr { @@ -914,7 +915,7 @@ impl defmt::Format for Mcr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mcr {{ mr0i: {:?}, mr0r: {:?}, mr0s: {:?}, mr1i: {:?}, mr1r: {:?}, mr1s: {:?}, mr2i: {:?}, mr2r: {:?}, mr2s: {:?}, mr3i: {:?}, mr3r: {:?}, mr3s: {:?}, mr0rl: {:?}, mr1rl: {:?}, mr2rl: {:?}, mr3rl: {:?} }}", + "Mcr {{ mr0i: {=bool:?}, mr0r: {=bool:?}, mr0s: {=bool:?}, mr1i: {=bool:?}, mr1r: {=bool:?}, mr1s: {=bool:?}, mr2i: {=bool:?}, mr2r: {=bool:?}, mr2s: {=bool:?}, mr3i: {=bool:?}, mr3r: {=bool:?}, mr3s: {=bool:?}, mr0rl: {=bool:?}, mr1rl: {=bool:?}, mr2rl: {=bool:?}, mr3rl: {=bool:?} }}", self.mr0i(), self.mr0r(), self.mr0s(), @@ -1282,108 +1283,15 @@ impl defmt::Format for Tcr { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Capfe { - #[doc = "Does not load."] - CAPFE0 = 0x0, - #[doc = "Loads."] - CAPFE1 = 0x01, -} -impl Capfe { - #[inline(always)] - pub const fn from_bits(val: u8) -> Capfe { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Capfe { - #[inline(always)] - fn from(val: u8) -> Capfe { - Capfe::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Capfe) -> u8 { - Capfe::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Capi { - #[doc = "Does not generate."] - CAPI0 = 0x0, - #[doc = "Generates."] - CAPI1 = 0x01, -} -impl Capi { - #[inline(always)] - pub const fn from_bits(val: u8) -> Capi { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Capi { - #[inline(always)] - fn from(val: u8) -> Capi { - Capi::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Capi) -> u8 { - Capi::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Capre { - #[doc = "Does not load."] - CAPRE0 = 0x0, - #[doc = "Loads."] - CAPRE1 = 0x01, -} -impl Capre { - #[inline(always)] - pub const fn from_bits(val: u8) -> Capre { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Capre { - #[inline(always)] - fn from(val: u8) -> Capre { - Capre::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Capre) -> u8 { - Capre::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cinsel { #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn."] - CHANNEL_0 = 0x0, + Channel0 = 0x0, #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn."] - CHANNEL_1 = 0x01, + Channel1 = 0x01, #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn."] - CHANNEL_2 = 0x02, + Channel2 = 0x02, #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn."] - CHANNEL_3 = 0x03, + Channel3 = 0x03, } impl Cinsel { #[inline(always)] @@ -1412,13 +1320,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ctmode { #[doc = "Timer mode."] - TIMER = 0x0, + Timer = 0x0, #[doc = "Counter mode rising edge."] - COUNTER_RISING_EDGE = 0x01, + CounterRisingEdge = 0x01, #[doc = "Counter mode falling edge."] - COUNTER_FALLING_EDGE = 0x02, + CounterFallingEdge = 0x02, #[doc = "Counter mode dual edge."] - COUNTER_DUAL_EDGE = 0x03, + CounterDualEdge = 0x03, } impl Ctmode { #[inline(always)] @@ -1445,46 +1353,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Em { - #[doc = "Low."] - CLEAR = 0x0, - #[doc = "High."] - SET = 0x01, -} -impl Em { - #[inline(always)] - pub const fn from_bits(val: u8) -> Em { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Em { - #[inline(always)] - fn from(val: u8) -> Em { - Em::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Em) -> u8 { - Em::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Emc { #[doc = "Does nothing."] - DO_NOTHING = 0x0, + DoNothing = 0x0, #[doc = "Goes low."] - CLEAR = 0x01, + Clear = 0x01, #[doc = "Goes high."] - SET = 0x02, + Set = 0x02, #[doc = "Toggles."] - TOGGLE = 0x03, + Toggle = 0x03, } impl Emc { #[inline(always)] @@ -1511,135 +1388,11 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Mri { - #[doc = "Does not generate."] - MRI0 = 0x0, - #[doc = "Generates."] - MRI1 = 0x01, -} -impl Mri { - #[inline(always)] - pub const fn from_bits(val: u8) -> Mri { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Mri { - #[inline(always)] - fn from(val: u8) -> Mri { - Mri::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Mri) -> u8 { - Mri::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Mrr { - #[doc = "Does not reset."] - MRR0 = 0x0, - #[doc = "Resets."] - MRR1 = 0x01, -} -impl Mrr { - #[inline(always)] - pub const fn from_bits(val: u8) -> Mrr { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Mrr { - #[inline(always)] - fn from(val: u8) -> Mrr { - Mrr::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Mrr) -> u8 { - Mrr::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Mrrl { - #[doc = "Does not reload."] - MRRL0 = 0x0, - #[doc = "Reloads."] - MRRL1 = 0x01, -} -impl Mrrl { - #[inline(always)] - pub const fn from_bits(val: u8) -> Mrrl { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Mrrl { - #[inline(always)] - fn from(val: u8) -> Mrrl { - Mrrl::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Mrrl) -> u8 { - Mrrl::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Mrs { - #[doc = "Does not stop."] - MRS0 = 0x0, - #[doc = "Stops."] - MRS1 = 0x01, -} -impl Mrs { - #[inline(always)] - pub const fn from_bits(val: u8) -> Mrs { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Mrs { - #[inline(always)] - fn from(val: u8) -> Mrs { - Mrs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Mrs) -> u8 { - Mrs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pwmen { #[doc = "Disable."] - MATCH = 0x0, + Match = 0x0, #[doc = "Enable."] - PWM = 0x01, + Pwm = 0x01, } impl Pwmen { #[inline(always)] @@ -1668,21 +1421,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Selcc { #[doc = "Capture channel 0 rising edge."] - CHANNEL_0_RISING = 0x0, + Channel0Rising = 0x0, #[doc = "Capture channel 0 falling edge."] - CHANNEL_0_FALLING = 0x01, + Channel0Falling = 0x01, #[doc = "Capture channel 1 rising edge."] - CHANNEL_1_RISING = 0x02, + Channel1Rising = 0x02, #[doc = "Capture channel 1 falling edge."] - CHANNEL_1_FALLING = 0x03, + Channel1Falling = 0x03, #[doc = "Capture channel 2 rising edge."] - CHANNEL_2_RISING = 0x04, + Channel2Rising = 0x04, #[doc = "Capture channel 2 falling edge."] - CHANNEL_2_FALLING = 0x05, + Channel2Falling = 0x05, #[doc = "Capture channel 3 rising edge."] - CHANNEL_3_RISING = 0x06, + Channel3Rising = 0x06, #[doc = "Capture channel 3 falling edge."] - CHANNEL_3_FALLING = 0x07, + Channel3Falling = 0x07, } impl Selcc { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/DMA.rs b/nxp-pac/src/meta_peripherals/mcxa/DMA.rs index f6c7acd..4a26afb 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/DMA.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/DMA.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "DMA MP."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Dma12 { @@ -1301,9 +1302,9 @@ impl defmt::Format for MpInt { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Active { #[doc = "eDMA is idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "eDMA is executing a channel."] - EXECUTION = 0x01, + Execution = 0x01, } impl Active { #[inline(always)] @@ -1332,9 +1333,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cx { #[doc = "Normal operation."] - NORMAL_OPERATION = 0x0, + NormalOperation = 0x0, #[doc = "Cancel the remaining data transfer."] - DATA_TRANSFER_CANCEL = 0x01, + DataTransferCancel = 0x01, } impl Cx { #[inline(always)] @@ -1363,9 +1364,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dae { #[doc = "No destination address configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a configuration error detected in the TCDn_DADDR field."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Dae { #[inline(always)] @@ -1394,9 +1395,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dbe { #[doc = "No destination bus error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a bus error on a destination write."] - BUS_ERROR = 0x01, + BusError = 0x01, } impl Dbe { #[inline(always)] @@ -1425,9 +1426,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Doe { #[doc = "No destination offset configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a configuration error detected in the TCDn_DOFF field."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Doe { #[inline(always)] @@ -1456,9 +1457,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hae { #[doc = "Normal operation."] - NORMAL_OPERATION = 0x0, + NormalOperation = 0x0, #[doc = "Any error causes the HALT field to be set to 1."] - HALT = 0x01, + Halt = 0x01, } impl Hae { #[inline(always)] @@ -1487,9 +1488,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Halt { #[doc = "Normal operation."] - NORMAL_OPERATION = 0x0, + NormalOperation = 0x0, #[doc = "Stall the start of any new channels."] - STALL = 0x01, + Stall = 0x01, } impl Halt { #[inline(always)] @@ -1580,9 +1581,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Nce { #[doc = "No NBYTES/CITER configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Nce { #[inline(always)] @@ -1611,9 +1612,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sae { #[doc = "No source address configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a configuration error detected in the TCDn_SADDR field."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Sae { #[inline(always)] @@ -1642,9 +1643,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sbe { #[doc = "No source bus error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a bus error on a source read."] - BUS_ERROR = 0x01, + BusError = 0x01, } impl Sbe { #[inline(always)] @@ -1673,9 +1674,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sge { #[doc = "No scatter/gather configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Sge { #[inline(always)] @@ -1704,9 +1705,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Soe { #[doc = "No source offset configuration error."] - NO_ERROR = 0x0, + NoError = 0x0, #[doc = "Last recorded error was a configuration error detected in the TCDn_SOFF field."] - CONFIGURATION_ERROR = 0x01, + ConfigurationError = 0x01, } impl Soe { #[inline(always)] @@ -1735,9 +1736,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Vld { #[doc = "No CHn_ES\\[ERR\\] fields are set to 1."] - NO_FIELD_SET_ONE = 0x0, + NoFieldSetOne = 0x0, #[doc = "At least one CHn_ES\\[ERR\\] field is set to 1, indicating a valid error exists that software has not cleared."] - ATLEAST_ONE_FIELD = 0x01, + AtleastOneField = 0x01, } impl Vld { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/EDMA_TCD.rs b/nxp-pac/src/meta_peripherals/mcxa/EDMA_TCD.rs index 053acaf..5c1a4fc 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/EDMA_TCD.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/EDMA_TCD.rs @@ -1,7 +1,8 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] -#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_MUX, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF."] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] +#[doc = "Array of registers: CH_CSR, CH_ES, CH_INT, CH_PRI, CH_SBR, TCD_ATTR, TCD_BITER_ELINKNO, TCD_BITER_ELINKYES, TCD_CITER_ELINKNO, TCD_CITER_ELINKYES, TCD_CSR, TCD_DADDR, TCD_DLAST_SGA, TCD_DOFF, TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES, TCD_SADDR, TCD_SLAST_SDA, TCD_SOFF."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Tcd { ptr: *mut u8, @@ -600,6 +601,18 @@ impl ChSbr { pub const fn set_mid(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); } + #[doc = "Security Level."] + #[must_use] + #[inline(always)] + pub const fn sec(&self) -> Sec { + let val = (self.0 >> 14usize) & 0x01; + Sec::from_bits(val as u8) + } + #[doc = "Security Level."] + #[inline(always)] + pub const fn set_sec(&mut self, val: Sec) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize); + } #[doc = "Privileged Access Level."] #[must_use] #[inline(always)] @@ -624,6 +637,18 @@ impl ChSbr { pub const fn set_emi(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } + #[doc = "Attribute Output."] + #[must_use] + #[inline(always)] + pub const fn attr(&self) -> u8 { + let val = (self.0 >> 17usize) & 0x0f; + val as u8 + } + #[doc = "Attribute Output."] + #[inline(always)] + pub const fn set_attr(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 17usize)) | (((val as u32) & 0x0f) << 17usize); + } } impl Default for ChSbr { #[inline(always)] @@ -635,8 +660,10 @@ impl core::fmt::Debug for ChSbr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("ChSbr") .field("mid", &self.mid()) + .field("sec", &self.sec()) .field("pal", &self.pal()) .field("emi", &self.emi()) + .field("attr", &self.attr()) .finish() } } @@ -645,10 +672,12 @@ impl defmt::Format for ChSbr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "ChSbr {{ mid: {=u8:?}, pal: {:?}, emi: {=bool:?} }}", + "ChSbr {{ mid: {=u8:?}, sec: {:?}, pal: {:?}, emi: {=bool:?}, attr: {=u8:?} }}", self.mid(), + self.sec(), self.pal(), - self.emi() + self.emi(), + self.attr() ) } } @@ -696,14 +725,14 @@ impl TcdAttr { #[doc = "Source Address Modulo."] #[must_use] #[inline(always)] - pub const fn smod(&self) -> Smod { + pub const fn smod(&self) -> u8 { let val = (self.0 >> 11usize) & 0x1f; - Smod::from_bits(val as u8) + val as u8 } #[doc = "Source Address Modulo."] #[inline(always)] - pub const fn set_smod(&mut self, val: Smod) { - self.0 = (self.0 & !(0x1f << 11usize)) | (((val.to_bits() as u16) & 0x1f) << 11usize); + pub const fn set_smod(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 11usize)) | (((val as u16) & 0x1f) << 11usize); } } impl Default for TcdAttr { @@ -727,7 +756,7 @@ impl defmt::Format for TcdAttr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "TcdAttr {{ dsize: {:?}, dmod: {=u8:?}, ssize: {:?}, smod: {:?} }}", + "TcdAttr {{ dsize: {:?}, dmod: {=u8:?}, ssize: {:?}, smod: {=u8:?} }}", self.dsize(), self.dmod(), self.ssize(), @@ -811,13 +840,13 @@ impl TcdBiterElinkyes { #[must_use] #[inline(always)] pub const fn linkch(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x07; + let val = (self.0 >> 9usize) & 0x0f; val as u8 } #[doc = "Link Channel Number."] #[inline(always)] pub const fn set_linkch(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 9usize)) | (((val as u16) & 0x07) << 9usize); + self.0 = (self.0 & !(0x0f << 9usize)) | (((val as u16) & 0x0f) << 9usize); } #[doc = "Enable Link."] #[must_use] @@ -935,13 +964,13 @@ impl TcdCiterElinkyes { #[must_use] #[inline(always)] pub const fn linkch(&self) -> u8 { - let val = (self.0 >> 9usize) & 0x07; + let val = (self.0 >> 9usize) & 0x0f; val as u8 } #[doc = "Minor Loop Link Channel Number."] #[inline(always)] pub const fn set_linkch(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 9usize)) | (((val as u16) & 0x07) << 9usize); + self.0 = (self.0 & !(0x0f << 9usize)) | (((val as u16) & 0x0f) << 9usize); } #[doc = "Enable Link."] #[must_use] @@ -1088,13 +1117,13 @@ impl TcdCsr { #[must_use] #[inline(always)] pub const fn majorlinkch(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x07; + let val = (self.0 >> 8usize) & 0x0f; val as u8 } #[doc = "Major Loop Link Channel Number."] #[inline(always)] pub const fn set_majorlinkch(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u16) & 0x07) << 8usize); + self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u16) & 0x0f) << 8usize); } #[doc = "Bandwidth Control."] #[must_use] @@ -1529,12 +1558,12 @@ impl defmt::Format for TcdSoff { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Bwc { #[doc = "No eDMA engine stalls."] - NO_STALL = 0x0, + NoStall = 0x0, _RESERVED_1 = 0x01, #[doc = "eDMA engine stalls for 4 cycles after each R/W."] - ENGINE_STALLS_FOUR = 0x02, + EngineStallsFour = 0x02, #[doc = "eDMA engine stalls for 8 cycles after each R/W."] - ENGINE_STALLS_EIGHT = 0x03, + EngineStallsEight = 0x03, } impl Bwc { #[inline(always)] @@ -1563,9 +1592,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dpa { #[doc = "Channel can suspend a lower-priority channel."] - SUSPEND = 0x0, + Suspend = 0x0, #[doc = "Channel cannot suspend any other channel, regardless of channel priority."] - CANNOT_SUSPEND = 0x01, + CannotSuspend = 0x01, } impl Dpa { #[inline(always)] @@ -1594,9 +1623,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dreq { #[doc = "No operation."] - CHANNEL_NOT_AFFECTED = 0x0, + ChannelNotAffected = 0x0, #[doc = "Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests."] - ERQ_FIELD_CLEAR = 0x01, + ErqFieldClear = 0x01, } impl Dreq { #[inline(always)] @@ -1625,9 +1654,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ecp { #[doc = "Channel cannot be suspended by a higher-priority channel's service request."] - CANNOT_SUSPEND = 0x0, + CannotSuspend = 0x0, #[doc = "Channel can be temporarily suspended by a higher-priority channel's service request."] - SUSPEND = 0x01, + Suspend = 0x01, } impl Ecp { #[inline(always)] @@ -1656,9 +1685,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Esg { #[doc = "Current channel's TCD is normal format."] - NORMAL_FORMAT = 0x0, + NormalFormat = 0x0, #[doc = "Current channel's TCD specifies scatter/gather format."] - SCATTER_GATHER_FORMAT = 0x01, + ScatterGatherFormat = 0x01, } impl Esg { #[inline(always)] @@ -1687,9 +1716,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pal { #[doc = "User protection level for DMA transfers."] - USER_PROTECTION = 0x0, + UserProtection = 0x0, #[doc = "Privileged protection level for DMA transfers."] - PRIVILEGED_PROTECTION = 0x01, + PrivilegedProtection = 0x01, } impl Pal { #[inline(always)] @@ -1716,19 +1745,50 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Sec { + #[doc = "Nonsecure protection level for DMA transfers."] + NonsecureProtection = 0x0, + #[doc = "Secure protection level for DMA transfers."] + SecureProtection = 0x01, +} +impl Sec { + #[inline(always)] + pub const fn from_bits(val: u8) -> Sec { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Sec { + #[inline(always)] + fn from(val: u8) -> Sec { + Sec::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Sec) -> u8 { + Sec::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Size { #[doc = "8-bit."] - EIGHT_BIT = 0x0, + EightBit = 0x0, #[doc = "16-bit."] - SIXTEEN_BIT = 0x01, + SixteenBit = 0x01, #[doc = "32-bit."] - THIRTYTWO_BIT = 0x02, + ThirtytwoBit = 0x02, #[doc = "64-bit."] - SIXTYFOUR_BIT = 0x03, + SixtyfourBit = 0x03, #[doc = "16-byte."] - SIXTEEN_BYTE = 0x04, + SixteenByte = 0x04, #[doc = "32-byte."] - THIRTYTWO_BYTE = 0x05, + ThirtytwoByte = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, } @@ -1757,71 +1817,11 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Smod { - #[doc = "Source address modulo feature disabled."] - DISABLE = 0x0, - _RESERVED_1 = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, - _RESERVED_10 = 0x10, - _RESERVED_11 = 0x11, - _RESERVED_12 = 0x12, - _RESERVED_13 = 0x13, - _RESERVED_14 = 0x14, - _RESERVED_15 = 0x15, - _RESERVED_16 = 0x16, - _RESERVED_17 = 0x17, - _RESERVED_18 = 0x18, - _RESERVED_19 = 0x19, - _RESERVED_1a = 0x1a, - _RESERVED_1b = 0x1b, - _RESERVED_1c = 0x1c, - _RESERVED_1d = 0x1d, - _RESERVED_1e = 0x1e, - _RESERVED_1f = 0x1f, -} -impl Smod { - #[inline(always)] - pub const fn from_bits(val: u8) -> Smod { - unsafe { core::mem::transmute(val & 0x1f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Smod { - #[inline(always)] - fn from(val: u8) -> Smod { - Smod::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Smod) -> u8 { - Smod::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Start { #[doc = "Channel not explicitly started."] - CHANNEL_NOT_STARTED = 0x0, + ChannelNotStarted = 0x0, #[doc = "Channel explicitly started via a software-initiated service request."] - CHANNEL_STARTED = 0x01, + ChannelStarted = 0x01, } impl Start { #[inline(always)] @@ -1850,9 +1850,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcdNbytesMloffnoDmloe { #[doc = "Minor loop offset not applied to DADDR."] - OFFSET_NOT_APPLIED = 0x0, + OffsetNotApplied = 0x0, #[doc = "Minor loop offset applied to DADDR."] - OFFSET_APPLIED = 0x01, + OffsetApplied = 0x01, } impl TcdNbytesMloffnoDmloe { #[inline(always)] @@ -1881,9 +1881,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcdNbytesMloffnoSmloe { #[doc = "Minor loop offset not applied to SADDR."] - OFFSET_NOT_APPLIED = 0x0, + OffsetNotApplied = 0x0, #[doc = "Minor loop offset applied to SADDR."] - OFFSET_APPLIED = 0x01, + OffsetApplied = 0x01, } impl TcdNbytesMloffnoSmloe { #[inline(always)] @@ -1912,9 +1912,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcdNbytesMloffyesDmloe { #[doc = "Minor loop offset not applied to DADDR."] - OFFSET_NOT_APPLIED = 0x0, + OffsetNotApplied = 0x0, #[doc = "Minor loop offset applied to DADDR."] - OFFSET_APPLIED = 0x01, + OffsetApplied = 0x01, } impl TcdNbytesMloffyesDmloe { #[inline(always)] @@ -1943,9 +1943,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TcdNbytesMloffyesSmloe { #[doc = "Minor loop offset not applied to SADDR."] - OFFSET_NOT_APPLIED = 0x0, + OffsetNotApplied = 0x0, #[doc = "Minor loop offset applied to SADDR."] - OFFSET_APPLIED = 0x01, + OffsetApplied = 0x01, } impl TcdNbytesMloffyesSmloe { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/FLEXPWM.rs b/nxp-pac/src/meta_peripherals/mcxa/FLEXPWM.rs index 78e5120..c0fceef 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/FLEXPWM.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/FLEXPWM.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "PWM."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Flexpwm { @@ -2993,9 +2994,9 @@ impl defmt::Format for Swcout { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fauto { #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."] - MANUAL = 0x0, + Manual = 0x0, #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."] - AUTOMATIC = 0x01, + Automatic = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3038,9 +3039,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fflag { #[doc = "No fault on the FAULTx pin."] - NO_FLAG = 0x0, + NoFlag = 0x0, #[doc = "Fault on the FAULTx pin."] - FLAG = 0x01, + Flag = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3083,9 +3084,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ffull { #[doc = "PWM outputs are not re-enabled at the start of a full cycle."] - PWM_OUTPUTS_NOT_REENABLED = 0x0, + PwmOutputsNotReenabled = 0x0, #[doc = "PWM outputs are re-enabled at the start of a full cycle."] - PWM_OUTPUTS_REENABLED = 0x01, + PwmOutputsReenabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3128,9 +3129,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fhalf { #[doc = "PWM outputs are not re-enabled at the start of a half cycle."] - PWM_OUTPUTS_NOT_REENABLED = 0x0, + PwmOutputsNotReenabled = 0x0, #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."] - PWM_OUTPUTS_REENABLED = 0x01, + PwmOutputsReenabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3173,9 +3174,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fie { #[doc = "FAULTx CPU interrupt requests disabled."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "FAULTx CPU interrupt requests enabled."] - ENABLED = 0x01, + Enabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3218,9 +3219,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Flvl { #[doc = "A logic 0 on the fault input indicates a fault condition."] - LOGIC_0 = 0x0, + Logic0 = 0x0, #[doc = "A logic 1 on the fault input indicates a fault condition."] - LOGIC_1 = 0x01, + Logic1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3263,9 +3264,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fsafe { #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."] - SAFE = 0x01, + Safe = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3308,9 +3309,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ipol { #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."] - PWM23 = 0x0, + Pwm23 = 0x0, #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."] - PWM45 = 0x01, + Pwm45 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3353,9 +3354,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ldok { #[doc = "Do not load new values."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."] - ENABLED = 0x01, + Enabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3398,9 +3399,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Nocomb { #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."] - DISABLED = 0x01, + Disabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3443,9 +3444,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Run { #[doc = "PWM counter is stopped, but PWM outputs hold the current state."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "PWM counter is started in the corresponding submodule."] - ENABLED = 0x01, + Enabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3488,13 +3489,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmcaptctrlxEdgx { #[doc = "Disabled."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Capture falling edges."] - FALLING_EDGE = 0x01, + FallingEdge = 0x01, #[doc = "Capture rising edges."] - RISING_EDGE = 0x02, + RisingEdge = 0x02, #[doc = "Capture any edge."] - ANY_EDGE = 0x03, + AnyEdge = 0x03, } impl SmcaptctrlxEdgx { #[inline(always)] @@ -3523,9 +3524,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmcaptctrlxInpSelx { #[doc = "Raw PWM_X input signal selected as source."] - PWM_X = 0x0, + PwmX = 0x0, #[doc = "Edge Counter."] - EDGE_COUNTER = 0x01, + EdgeCounter = 0x01, } impl SmcaptctrlxInpSelx { #[inline(always)] @@ -3554,9 +3555,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmcaptctrlxOneshotx { #[doc = "Free Running."] - FREE_RUNNING = 0x0, + FreeRunning = 0x0, #[doc = "One Shot."] - ONE_SHOT = 0x01, + OneShot = 0x01, } impl SmcaptctrlxOneshotx { #[inline(always)] @@ -3585,11 +3586,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlClkSel { #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."] - IPBUS = 0x0, + Ipbus = 0x0, #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."] - EXT_CLK = 0x01, + ExtClk = 0x01, #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it forces the clock to logic 0."] - AUX_CLK = 0x02, + AuxClk = 0x02, _RESERVED_3 = 0x03, } impl SmctrlClkSel { @@ -3619,9 +3620,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlCompmode { #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period maintains this state until a match with VAL3 clears the output in the following period."] - EQUAL_TO = 0x0, + EqualTo = 0x0, #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."] - EQUAL_TO_OR_GREATER_THAN = 0x01, + EqualToOrGreaterThan = 0x01, } impl SmctrlCompmode { #[inline(always)] @@ -3650,21 +3651,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlForceSel { #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."] - LOCAL = 0x0, + Local = 0x0, #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it holds the FORCE OUTPUT signal to logic 0."] - MASTER = 0x01, + Master = 0x01, #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."] - LOCAL_RELOAD = 0x02, + LocalReload = 0x02, #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MASTER_RELOAD = 0x03, + MasterReload = 0x03, #[doc = "The local sync signal from this submodule is used to force updates."] - LOCAL_SYNC = 0x04, + LocalSync = 0x04, #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0."] - MASTER_SYNC = 0x05, + MasterSync = 0x05, #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."] - EXT_FORCE = 0x06, + ExtForce = 0x06, #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."] - EXT_SYNC = 0x07, + ExtSync = 0x07, } impl SmctrlForceSel { #[inline(always)] @@ -3693,9 +3694,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlIndep { #[doc = "PWM_A and PWM_B form a complementary PWM pair."] - COMPLEMENTARY = 0x0, + Complementary = 0x0, #[doc = "PWM_A and PWM_B outputs are independent PWMs."] - INDEPENDENT = 0x01, + Independent = 0x01, } impl SmctrlIndep { #[inline(always)] @@ -3724,13 +3725,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlInitSel { #[doc = "Local sync (PWM_X) causes initialization."] - PWM_X = 0x0, + PwmX = 0x0, #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload occurs."] - MASTER_RELOAD = 0x01, + MasterReload = 0x01, #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0."] - MASTER_SYNC = 0x02, + MasterSync = 0x02, #[doc = "EXT_SYNC causes initialization."] - EXT_SYNC = 0x03, + ExtSync = 0x03, } impl SmctrlInitSel { #[inline(always)] @@ -3759,37 +3760,37 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlLdfq { #[doc = "Every PWM opportunity."] - EVERYPWM = 0x0, + Everypwm = 0x0, #[doc = "Every 2 PWM opportunities."] - EVERY2PWM = 0x01, + Every2pwm = 0x01, #[doc = "Every 3 PWM opportunities."] - EVERY3PWM = 0x02, + Every3pwm = 0x02, #[doc = "Every 4 PWM opportunities."] - EVERY4PWM = 0x03, + Every4pwm = 0x03, #[doc = "Every 5 PWM opportunities."] - EVERY5PWM = 0x04, + Every5pwm = 0x04, #[doc = "Every 6 PWM opportunities."] - EVERY6PWM = 0x05, + Every6pwm = 0x05, #[doc = "Every 7 PWM opportunities."] - EVERY7PWM = 0x06, + Every7pwm = 0x06, #[doc = "Every 8 PWM opportunities."] - EVERY8PWM = 0x07, + Every8pwm = 0x07, #[doc = "Every 9 PWM opportunities."] - EVERY9PWM = 0x08, + Every9pwm = 0x08, #[doc = "Every 10 PWM opportunities."] - EVERY10PWM = 0x09, + Every10pwm = 0x09, #[doc = "Every 11 PWM opportunities."] - EVERY11PWM = 0x0a, + Every11pwm = 0x0a, #[doc = "Every 12 PWM opportunities."] - EVERY12PWM = 0x0b, + Every12pwm = 0x0b, #[doc = "Every 13 PWM opportunities."] - EVERY13PWM = 0x0c, + Every13pwm = 0x0c, #[doc = "Every 14 PWM opportunities."] - EVERY14PWM = 0x0d, + Every14pwm = 0x0d, #[doc = "Every 15 PWM opportunities."] - EVERY15PWM = 0x0e, + Every15pwm = 0x0e, #[doc = "Every 16 PWM opportunities."] - EVERY16PWM = 0x0f, + Every16pwm = 0x0f, } impl SmctrlLdfq { #[inline(always)] @@ -3818,9 +3819,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlLdmod { #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."] - NEXT_PWM_RELOAD = 0x0, + NextPwmReload = 0x0, #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case, it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."] - MTCTRL_LDOK_SET = 0x01, + MtctrlLdokSet = 0x01, } impl SmctrlLdmod { #[inline(always)] @@ -3849,21 +3850,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlPrsc { #[doc = "Prescaler 1."] - ONE = 0x0, + One = 0x0, #[doc = "Prescaler 2."] - TWO = 0x01, + Two = 0x01, #[doc = "Prescaler 4."] - FOUR = 0x02, + Four = 0x02, #[doc = "Prescaler 8."] - EIGHT = 0x03, + Eight = 0x03, #[doc = "Prescaler 16."] - SIXTEEN = 0x04, + Sixteen = 0x04, #[doc = "Prescaler 32."] - THIRTYTWO = 0x05, + Thirtytwo = 0x05, #[doc = "Prescaler 64."] - SIXTYFOUR = 0x06, + Sixtyfour = 0x06, #[doc = "Prescaler 128."] - HUNDREDTWENTYEIGHT = 0x07, + Hundredtwentyeight = 0x07, } impl SmctrlPrsc { #[inline(always)] @@ -3892,9 +3893,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmctrlReloadSel { #[doc = "The local RELOAD signal is used to reload registers."] - LOCAL = 0x0, + Local = 0x0, #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it forces the RELOAD signal to logic 0."] - MASTER = 0x01, + Master = 0x01, } impl SmctrlReloadSel { #[inline(always)] @@ -3923,13 +3924,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmdmaenCaptde { #[doc = "Read DMA requests disabled."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to be set to determine which watermark(s) the DMA request is sensitive."] - EXCEEDFIFO = 0x01, + Exceedfifo = 0x01, #[doc = "A local synchronization (VAL1 matches counter) sets the read DMA request."] - LOCAL_SYNC = 0x02, + LocalSync = 0x02, #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."] - LOCAL_RELOAD = 0x03, + LocalReload = 0x03, } impl SmdmaenCaptde { #[inline(always)] @@ -3958,9 +3959,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmdmaenFand { #[doc = "Selected FIFO watermarks are OR'ed together."] - OR = 0x0, + Or = 0x0, #[doc = "Selected FIFO watermarks are AND'ed together."] - AND = 0x01, + And = 0x01, } impl SmdmaenFand { #[inline(always)] @@ -3989,9 +3990,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmintenCmpie { #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."] - ENABLED = 0x01, + Enabled = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -4082,13 +4083,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmoctrlPwmafs { #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - LOGIC_0 = 0x0, + Logic0 = 0x0, #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - LOGIC_1 = 0x01, + Logic1 = 0x01, #[doc = "Output is put in a high-impedance state."] - TRISTATED_2 = 0x02, + Tristated2 = 0x02, #[doc = "Output is put in a high-impedance state."] - TRISTATED_3 = 0x03, + Tristated3 = 0x03, } impl SmoctrlPwmafs { #[inline(always)] @@ -4117,13 +4118,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmoctrlPwmbfs { #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - LOGIC_0 = 0x0, + Logic0 = 0x0, #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - LOGIC_1 = 0x01, + Logic1 = 0x01, #[doc = "Output is put in a high-impedance state."] - TRISTATED_2 = 0x02, + Tristated2 = 0x02, #[doc = "Output is put in a high-impedance state."] - TRISTATED_3 = 0x03, + Tristated3 = 0x03, } impl SmoctrlPwmbfs { #[inline(always)] @@ -4152,13 +4153,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmoctrlPwmxfs { #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."] - LOGIC_0 = 0x0, + Logic0 = 0x0, #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."] - LOGIC_1 = 0x01, + Logic1 = 0x01, #[doc = "Output is put in a high-impedance state."] - TRISTATED_2 = 0x02, + Tristated2 = 0x02, #[doc = "Output is put in a high-impedance state."] - TRISTATED_3 = 0x03, + Tristated3 = 0x03, } impl SmoctrlPwmxfs { #[inline(always)] @@ -4187,9 +4188,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Smout { #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - LOGIC_0 = 0x0, + Logic0 = 0x0, #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."] - LOGIC_1 = 0x01, + Logic1 = 0x01, } impl Smout { #[inline(always)] @@ -4218,13 +4219,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Smsel23 { #[doc = "Generated SM0PWM23 signal used by the deadtime logic."] - PWM = 0x0, + pwm = 0x0, #[doc = "Inverted generated SM0PWM23 signal used by the deadtime logic."] - INVERTED_PWM = 0x01, + Invertedpwm = 0x01, #[doc = "SWCOUT\\[SM0OUT23\\] used by the deadtime logic."] - OUT = 0x02, + out = 0x02, #[doc = "PWM0_EXTA signal used by the deadtime logic."] - PWM_EXTA = 0x03, + PwmExta = 0x03, } impl Smsel23 { #[inline(always)] @@ -4253,11 +4254,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Smsel45 { #[doc = "Generated SM0PWM45 signal used by the deadtime logic."] - PWM = 0x0, + pwm = 0x0, #[doc = "Inverted generated SM0PWM45 signal used by the deadtime logic."] - INVERTED_PWM = 0x01, + Invertedpwm = 0x01, #[doc = "SWCOUT\\[SM0OUT45\\] used by the deadtime logic."] - OUT = 0x02, + out = 0x02, _RESERVED_3 = 0x03, } impl Smsel45 { @@ -4287,9 +4288,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmstsCmpf { #[doc = "No compare event has occurred for a particular VALx value."] - NO_EVENT = 0x0, + NoEvent = 0x0, #[doc = "A compare event has occurred for a particular VALx value."] - EVENT = 0x01, + Event = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -4381,7 +4382,7 @@ impl From for u8 { pub enum SmtctrlOutTrigEn { _RESERVED_0 = 0x0, #[doc = "PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value."] - VAL0 = 0x01, + Val0 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -4472,9 +4473,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmtctrlPwaot { #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port."] - PWM_OUT_TRIG0_SIGNAL = 0x0, + PwmOutTrig0Signal = 0x0, #[doc = "Route the PWM_A output to the PWM_MUX_TRIG0 port."] - PWMA_OUTPUT = 0x01, + PwmaOutput = 0x01, } impl SmtctrlPwaot { #[inline(always)] @@ -4503,9 +4504,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmtctrlPwbot { #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port."] - PWM_OUT_TRIG1_SIGNAL = 0x0, + PwmOutTrig1Signal = 0x0, #[doc = "Route the PWM_B output to the PWM_MUX_TRIG1 port."] - PWMB_OUTPUT = 0x01, + PwmbOutput = 0x01, } impl SmtctrlPwbot { #[inline(always)] @@ -4534,9 +4535,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmtctrlTrgfrq { #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - EVERYPWM = 0x0, + Everypwm = 0x0, #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."] - FINALPWM = 0x01, + Finalpwm = 0x01, } impl SmtctrlTrgfrq { #[inline(always)] @@ -4565,13 +4566,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum StretchCntPrsc { #[doc = "Stretch count is zero, no stretch."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period."] - ENABLED = 0x01, + Enabled = 0x01, #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period."] - DISABLED_LOCKED = 0x02, + DisabledLocked = 0x02, #[doc = "Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period."] - ENABLED_LOCKED = 0x03, + EnabledLocked = 0x03, } impl StretchCntPrsc { #[inline(always)] @@ -4600,13 +4601,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Wrprot { #[doc = "Write protection off (default)."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Write protection on."] - ENABLED = 0x01, + Enabled = 0x01, #[doc = "Write protection off and locked until chip reset."] - DISABLED_LOCKED = 0x02, + DisabledLocked = 0x02, #[doc = "Write protection on and locked until chip reset."] - ENABLED_LOCKED = 0x03, + EnabledLocked = 0x03, } impl Wrprot { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/FMU.rs b/nxp-pac/src/meta_peripherals/mcxa/FMU.rs index a7b9776..ba47a75 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/FMU.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/FMU.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Flash."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Fmu { @@ -32,6 +33,11 @@ impl Fmu { pub const fn fctrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x08usize) as _) } } + #[doc = "Flash Test Register."] + #[inline(always)] + pub const fn ftest(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0cusize) as _) } + } #[doc = "Flash Common Command Object Registers."] #[inline(always)] pub const fn fccob(self, n: usize) -> crate::pac::common::Reg { @@ -49,13 +55,13 @@ impl Fccob { #[doc = "CCOBn."] #[must_use] #[inline(always)] - pub const fn ccobn(&self) -> u32 { + pub const fn cco_bn(&self) -> u32 { let val = (self.0 >> 0usize) & 0xffff_ffff; val as u32 } #[doc = "CCOBn."] #[inline(always)] - pub const fn set_ccobn(&mut self, val: u32) { + pub const fn set_cco_bn(&mut self, val: u32) { self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } @@ -68,14 +74,14 @@ impl Default for Fccob { impl core::fmt::Debug for Fccob { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Fccob") - .field("ccobn", &self.ccobn()) + .field("cco_bn", &self.cco_bn()) .finish() } } #[cfg(feature = "defmt")] impl defmt::Format for Fccob { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Fccob {{ ccobn: {=u32:?} }}", self.ccobn()) + defmt::write!(f, "Fccob {{ cco_bn: {=u32:?} }}", self.cco_bn()) } } #[doc = "Flash Configuration Register."] @@ -467,14 +473,111 @@ impl defmt::Format for Fstat { ) } } +#[doc = "Flash Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ftest(pub u32); +impl Ftest { + #[doc = "Test Mode Entry Control."] + #[must_use] + #[inline(always)] + pub const fn tmectl(&self) -> Tmectl { + let val = (self.0 >> 0usize) & 0x01; + Tmectl::from_bits(val as u8) + } + #[doc = "Test Mode Entry Control."] + #[inline(always)] + pub const fn set_tmectl(&mut self, val: Tmectl) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "Test Mode Entry Writable."] + #[must_use] + #[inline(always)] + pub const fn tmewr(&self) -> Tmewr { + let val = (self.0 >> 1usize) & 0x01; + Tmewr::from_bits(val as u8) + } + #[doc = "Test Mode Entry Writable."] + #[inline(always)] + pub const fn set_tmewr(&mut self, val: Tmewr) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + #[doc = "Test Mode Entry."] + #[must_use] + #[inline(always)] + pub const fn tme(&self) -> Tme { + let val = (self.0 >> 2usize) & 0x01; + Tme::from_bits(val as u8) + } + #[doc = "Test Mode Entry."] + #[inline(always)] + pub const fn set_tme(&mut self, val: Tme) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "Test Mode Status."] + #[must_use] + #[inline(always)] + pub const fn tmode(&self) -> Tmode { + let val = (self.0 >> 3usize) & 0x01; + Tmode::from_bits(val as u8) + } + #[doc = "Test Mode Status."] + #[inline(always)] + pub const fn set_tmode(&mut self, val: Tmode) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "Test Mode Entry Lock."] + #[must_use] + #[inline(always)] + pub const fn tmelock(&self) -> Tmelock { + let val = (self.0 >> 4usize) & 0x01; + Tmelock::from_bits(val as u8) + } + #[doc = "Test Mode Entry Lock."] + #[inline(always)] + pub const fn set_tmelock(&mut self, val: Tmelock) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } +} +impl Default for Ftest { + #[inline(always)] + fn default() -> Ftest { + Ftest(0) + } +} +impl core::fmt::Debug for Ftest { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ftest") + .field("tmectl", &self.tmectl()) + .field("tmewr", &self.tmewr()) + .field("tme", &self.tme()) + .field("tmode", &self.tmode()) + .field("tmelock", &self.tmelock()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ftest { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Ftest {{ tmectl: {:?}, tmewr: {:?}, tme: {:?}, tmode: {:?}, tmelock: {:?} }}", + self.tmectl(), + self.tmewr(), + self.tme(), + self.tmode(), + self.tmelock() + ) + } +} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Abtreq { #[doc = "No request to abort a command write sequence."] - ABTREQ0 = 0x0, + Abtreq0 = 0x0, #[doc = "Request to abort a command write sequence."] - ABTREQ1 = 0x01, + Abtreq1 = 0x01, } impl Abtreq { #[inline(always)] @@ -503,9 +606,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Accerr { #[doc = "No access error detected."] - ACCERR0 = 0x0, + Accerr0 = 0x0, #[doc = "Access error detected."] - ACCERR1 = 0x01, + Accerr1 = 0x01, } impl Accerr { #[inline(always)] @@ -534,9 +637,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ccie { #[doc = "Command complete interrupt disabled."] - CCIE0 = 0x0, + Ccie0 = 0x0, #[doc = "Command complete interrupt enabled."] - CCIE1 = 0x01, + Ccie1 = 0x01, } impl Ccie { #[inline(always)] @@ -565,9 +668,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ccif { #[doc = "Flash command, initialization, or power mode recovery in progress."] - CCIF0 = 0x0, + Ccif0 = 0x0, #[doc = "Flash command, initialization, or power mode recovery has completed."] - CCIF1 = 0x01, + Ccif1 = 0x01, } impl Ccif { #[inline(always)] @@ -596,9 +699,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmdabt { #[doc = "No command abort detected."] - CMDABT0 = 0x0, + Cmdabt0 = 0x0, #[doc = "Command abort detected."] - CMDABT1 = 0x01, + Cmdabt1 = 0x01, } impl Cmdabt { #[inline(always)] @@ -627,9 +730,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmdp { #[doc = "Command protection level and domain ID are stale."] - CMDP0 = 0x0, + Cmdp0 = 0x0, #[doc = "Command protection level (CMDPRT) and domain ID (CMDDID) are set."] - CMDP1 = 0x01, + Cmdp1 = 0x01, } impl Cmdp { #[inline(always)] @@ -658,13 +761,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cmdprt { #[doc = "Secure, normal access."] - CMDPRT00 = 0x0, + Cmdprt00 = 0x0, #[doc = "Secure, privileged access."] - CMDPRT01 = 0x01, + Cmdprt01 = 0x01, #[doc = "Nonsecure, normal access."] - CMDPRT10 = 0x02, + Cmdprt10 = 0x02, #[doc = "Nonsecure, privileged access."] - CMDPRT11 = 0x03, + Cmdprt11 = 0x03, } impl Cmdprt { #[inline(always)] @@ -693,9 +796,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cwsabt { #[doc = "Command write sequence not aborted."] - CWSABT0 = 0x0, + Cwsabt0 = 0x0, #[doc = "Command write sequence aborted."] - CWSABT1 = 0x01, + Cwsabt1 = 0x01, } impl Cwsabt { #[inline(always)] @@ -724,9 +827,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dfdie { #[doc = "Double bit fault detect interrupt disabled."] - DFDIE0 = 0x0, + Dfdie0 = 0x0, #[doc = "Double bit fault detect interrupt enabled."] - DFDIE1 = 0x01, + Dfdie1 = 0x01, } impl Dfdie { #[inline(always)] @@ -755,9 +858,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dfdif { #[doc = "Double bit fault not detected during a valid flash read access."] - DFDIF0 = 0x0, + Dfdif0 = 0x0, #[doc = "Double bit fault detected (or FCTRL\\[FDFD\\] is set) during a valid flash read access."] - DFDIF1 = 0x01, + Dfdif1 = 0x01, } impl Dfdif { #[inline(always)] @@ -786,9 +889,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ersien0 { #[doc = "Block 0 IFR Sector X is protected from erase by ERSSCR command."] - ERSIEN00 = 0x0, + Ersien00 = 0x0, #[doc = "Block 0 IFR Sector X is not protected from erase by ERSSCR command."] - ERSIEN01 = 0x01, + Ersien01 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -831,9 +934,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ersien1 { #[doc = "Block 1 IFR Sector X is protected from erase by ERSSCR command."] - ERSIEN10 = 0x0, + Ersien10 = 0x0, #[doc = "Block 1 IFR Sector X is not protected from erase by ERSSCR command."] - ERSIEN11 = 0x01, + Ersien11 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -876,9 +979,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ersreq { #[doc = "No request or request complete."] - ERSREQ0 = 0x0, + Ersreq0 = 0x0, #[doc = "Request to run the Mass Erase operation."] - ERSREQ1 = 0x01, + Ersreq1 = 0x01, } impl Ersreq { #[inline(always)] @@ -907,9 +1010,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fail { #[doc = "Error not detected."] - FAIL0 = 0x0, + Fail0 = 0x0, #[doc = "Error detected."] - FAIL1 = 0x01, + Fail1 = 0x01, } impl Fail { #[inline(always)] @@ -938,9 +1041,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fdfd { #[doc = "FSTAT\\[DFDIF\\] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller."] - FDFD0 = 0x0, + Fdfd0 = 0x0, #[doc = "FSTAT\\[DFDIF\\] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set."] - FDFD1 = 0x01, + Fdfd1 = 0x01, } impl Fdfd { #[inline(always)] @@ -969,9 +1072,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lsactive { #[doc = "Full speed active mode requested."] - LSACTIVE0 = 0x0, + Lsactive0 = 0x0, #[doc = "Low speed active mode requested."] - LSACTIVE1 = 0x01, + Lsactive1 = 0x01, } impl Lsactive { #[inline(always)] @@ -1000,9 +1103,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Perdy { #[doc = "Program or sector erase command operation not stalled."] - PERDY0 = 0x0, + Perdy0 = 0x0, #[doc = "Program or sector erase command operation ready to execute."] - PERDY1 = 0x01, + Perdy1 = 0x01, } impl Perdy { #[inline(always)] @@ -1031,11 +1134,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pewen { #[doc = "Writes are not enabled."] - PEWEN00 = 0x0, + Pewen00 = 0x0, #[doc = "Writes are enabled for one flash or IFR phrase (phrase programming, sector erase)."] - PEWEN01 = 0x01, + Pewen01 = 0x01, #[doc = "Writes are enabled for one flash or IFR page (page programming)."] - PEWEN10 = 0x02, + Pewen10 = 0x02, _RESERVED_3 = 0x03, } impl Pewen { @@ -1065,9 +1168,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pviol { #[doc = "No protection violation detected."] - PVIOL0 = 0x0, + Pviol0 = 0x0, #[doc = "Protection violation detected."] - PVIOL1 = 0x01, + Pviol1 = 0x01, } impl Pviol { #[inline(always)] @@ -1096,9 +1199,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SalvUsed { #[doc = "Salvage not used during last operation."] - SALV_USED0 = 0x0, + SalvUsed0 = 0x0, #[doc = "Salvage used during the last erase operation."] - SALV_USED1 = 0x01, + SalvUsed1 = 0x01, } impl SalvUsed { #[inline(always)] @@ -1122,3 +1225,158 @@ impl From for u8 { SalvUsed::to_bits(val) } } +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Tme { + #[doc = "Test mode entry not requested."] + Tme0 = 0x0, + #[doc = "Test mode entry requested."] + Tme1 = 0x01, +} +impl Tme { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tme { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Tme { + #[inline(always)] + fn from(val: u8) -> Tme { + Tme::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tme) -> u8 { + Tme::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Tmectl { + #[doc = "FTEST register always reads 0 and writes to FTEST are ignored."] + Tmectl0 = 0x0, + #[doc = "FTEST register is readable and can be written to enable writability of TME."] + Tmectl1 = 0x01, +} +impl Tmectl { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tmectl { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Tmectl { + #[inline(always)] + fn from(val: u8) -> Tmectl { + Tmectl::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tmectl) -> u8 { + Tmectl::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Tmelock { + #[doc = "FTEST register not locked from accepting writes."] + Tmelock0 = 0x0, + #[doc = "FTEST register locked from accepting writes."] + Tmelock1 = 0x01, +} +impl Tmelock { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tmelock { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Tmelock { + #[inline(always)] + fn from(val: u8) -> Tmelock { + Tmelock::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tmelock) -> u8 { + Tmelock::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Tmewr { + #[doc = "TME bit is not writable."] + Tmewr0 = 0x0, + #[doc = "TME bit is writable."] + Tmewr1 = 0x01, +} +impl Tmewr { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tmewr { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Tmewr { + #[inline(always)] + fn from(val: u8) -> Tmewr { + Tmewr::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tmewr) -> u8 { + Tmewr::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Tmode { + #[doc = "Test mode not active."] + Tmode0 = 0x0, + #[doc = "Test mode active."] + Tmode1 = 0x01, +} +impl Tmode { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tmode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Tmode { + #[inline(always)] + fn from(val: u8) -> Tmode { + Tmode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tmode) -> u8 { + Tmode::to_bits(val) + } +} diff --git a/nxp-pac/src/meta_peripherals/mcxa/GPIO.rs b/nxp-pac/src/meta_peripherals/mcxa/GPIO.rs index d5d713d..590cfb4 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/GPIO.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/GPIO.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "GPIO."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Gpio { @@ -27,6 +28,31 @@ impl Gpio { pub const fn param(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04usize) as _) } } + #[doc = "Lock."] + #[inline(always)] + pub const fn lock(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0cusize) as _) } + } + #[doc = "Pin Control Nonsecure."] + #[inline(always)] + pub const fn pcns(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize) as _) } + } + #[doc = "Interrupt Control Nonsecure."] + #[inline(always)] + pub const fn icns(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x14usize) as _) } + } + #[doc = "Pin Control Nonprivilege."] + #[inline(always)] + pub const fn pcnp(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x18usize) as _) } + } + #[doc = "Interrupt Control Nonprivilege."] + #[inline(always)] + pub const fn icnp(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x1cusize) as _) } + } #[doc = "Port Data Output."] #[inline(always)] pub const fn pdor(self) -> crate::pac::common::Reg { @@ -91,9 +117,9 @@ impl Gpio { #[doc = "Interrupt Status Flag."] #[inline(always)] pub const fn isfr(self, n: usize) -> crate::pac::common::Reg { - assert!(n < 1usize); + assert!(n < 2usize); unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize + n * 0usize) as _) + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize + n * 4usize) as _) } } } @@ -105,971 +131,757 @@ impl Gichr { #[doc = "Global Interrupt Write Enable."] #[must_use] #[inline(always)] - pub const fn giwe16(&self) -> Giwe16 { - let val = (self.0 >> 0usize) & 0x01; - Giwe16::from_bits(val as u8) + pub const fn giwe(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 } #[doc = "Global Interrupt Write Enable."] #[inline(always)] - pub const fn set_giwe16(&mut self, val: Giwe16) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_giwe(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Global Interrupt Write Data."] #[must_use] #[inline(always)] - pub const fn giwe17(&self) -> Giwe17 { - let val = (self.0 >> 1usize) & 0x01; - Giwe17::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe17(&mut self, val: Giwe17) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn giwd(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 } - #[doc = "Global Interrupt Write Enable."] - #[must_use] + #[doc = "Global Interrupt Write Data."] #[inline(always)] - pub const fn giwe18(&self) -> Giwe18 { - let val = (self.0 >> 2usize) & 0x01; - Giwe18::from_bits(val as u8) + pub const fn set_giwd(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); } - #[doc = "Global Interrupt Write Enable."] +} +impl Default for Gichr { #[inline(always)] - pub const fn set_giwe18(&mut self, val: Giwe18) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + fn default() -> Gichr { + Gichr(0) } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe19(&self) -> Giwe19 { - let val = (self.0 >> 3usize) & 0x01; - Giwe19::from_bits(val as u8) +} +impl core::fmt::Debug for Gichr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gichr") + .field("giwe[0]", &self.giwe(0usize)) + .field("giwe[1]", &self.giwe(1usize)) + .field("giwe[2]", &self.giwe(2usize)) + .field("giwe[3]", &self.giwe(3usize)) + .field("giwe[4]", &self.giwe(4usize)) + .field("giwe[5]", &self.giwe(5usize)) + .field("giwe[6]", &self.giwe(6usize)) + .field("giwe[7]", &self.giwe(7usize)) + .field("giwe[8]", &self.giwe(8usize)) + .field("giwe[9]", &self.giwe(9usize)) + .field("giwe[10]", &self.giwe(10usize)) + .field("giwe[11]", &self.giwe(11usize)) + .field("giwe[12]", &self.giwe(12usize)) + .field("giwe[13]", &self.giwe(13usize)) + .field("giwe[14]", &self.giwe(14usize)) + .field("giwe[15]", &self.giwe(15usize)) + .field("giwd", &self.giwd()) + .finish() } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe19(&mut self, val: Giwe19) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for Gichr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Gichr {{ giwe[0]: {=bool:?}, giwe[1]: {=bool:?}, giwe[2]: {=bool:?}, giwe[3]: {=bool:?}, giwe[4]: {=bool:?}, giwe[5]: {=bool:?}, giwe[6]: {=bool:?}, giwe[7]: {=bool:?}, giwe[8]: {=bool:?}, giwe[9]: {=bool:?}, giwe[10]: {=bool:?}, giwe[11]: {=bool:?}, giwe[12]: {=bool:?}, giwe[13]: {=bool:?}, giwe[14]: {=bool:?}, giwe[15]: {=bool:?}, giwd: {=u16:?} }}", + self.giwe(0usize), + self.giwe(1usize), + self.giwe(2usize), + self.giwe(3usize), + self.giwe(4usize), + self.giwe(5usize), + self.giwe(6usize), + self.giwe(7usize), + self.giwe(8usize), + self.giwe(9usize), + self.giwe(10usize), + self.giwe(11usize), + self.giwe(12usize), + self.giwe(13usize), + self.giwe(14usize), + self.giwe(15usize), + self.giwd() + ) } +} +#[doc = "Global Interrupt Control Low."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Giclr(pub u32); +impl Giclr { #[doc = "Global Interrupt Write Enable."] #[must_use] #[inline(always)] - pub const fn giwe20(&self) -> Giwe20 { - let val = (self.0 >> 4usize) & 0x01; - Giwe20::from_bits(val as u8) + pub const fn giwe(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 } #[doc = "Global Interrupt Write Enable."] #[inline(always)] - pub const fn set_giwe20(&mut self, val: Giwe20) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_giwe(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Global Interrupt Write Data."] #[must_use] #[inline(always)] - pub const fn giwe21(&self) -> Giwe21 { - let val = (self.0 >> 5usize) & 0x01; - Giwe21::from_bits(val as u8) + pub const fn giwd(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Global Interrupt Write Data."] #[inline(always)] - pub const fn set_giwe21(&mut self, val: Giwe21) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_giwd(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); } - #[doc = "Global Interrupt Write Enable."] - #[must_use] +} +impl Default for Giclr { #[inline(always)] - pub const fn giwe22(&self) -> Giwe22 { - let val = (self.0 >> 6usize) & 0x01; - Giwe22::from_bits(val as u8) + fn default() -> Giclr { + Giclr(0) } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe22(&mut self, val: Giwe22) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); +} +impl core::fmt::Debug for Giclr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Giclr") + .field("giwe[0]", &self.giwe(0usize)) + .field("giwe[1]", &self.giwe(1usize)) + .field("giwe[2]", &self.giwe(2usize)) + .field("giwe[3]", &self.giwe(3usize)) + .field("giwe[4]", &self.giwe(4usize)) + .field("giwe[5]", &self.giwe(5usize)) + .field("giwe[6]", &self.giwe(6usize)) + .field("giwe[7]", &self.giwe(7usize)) + .field("giwe[8]", &self.giwe(8usize)) + .field("giwe[9]", &self.giwe(9usize)) + .field("giwe[10]", &self.giwe(10usize)) + .field("giwe[11]", &self.giwe(11usize)) + .field("giwe[12]", &self.giwe(12usize)) + .field("giwe[13]", &self.giwe(13usize)) + .field("giwe[14]", &self.giwe(14usize)) + .field("giwe[15]", &self.giwe(15usize)) + .field("giwd", &self.giwd()) + .finish() } - #[doc = "Global Interrupt Write Enable."] +} +#[cfg(feature = "defmt")] +impl defmt::Format for Giclr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Giclr {{ giwe[0]: {=bool:?}, giwe[1]: {=bool:?}, giwe[2]: {=bool:?}, giwe[3]: {=bool:?}, giwe[4]: {=bool:?}, giwe[5]: {=bool:?}, giwe[6]: {=bool:?}, giwe[7]: {=bool:?}, giwe[8]: {=bool:?}, giwe[9]: {=bool:?}, giwe[10]: {=bool:?}, giwe[11]: {=bool:?}, giwe[12]: {=bool:?}, giwe[13]: {=bool:?}, giwe[14]: {=bool:?}, giwe[15]: {=bool:?}, giwd: {=u16:?} }}", + self.giwe(0usize), + self.giwe(1usize), + self.giwe(2usize), + self.giwe(3usize), + self.giwe(4usize), + self.giwe(5usize), + self.giwe(6usize), + self.giwe(7usize), + self.giwe(8usize), + self.giwe(9usize), + self.giwe(10usize), + self.giwe(11usize), + self.giwe(12usize), + self.giwe(13usize), + self.giwe(14usize), + self.giwe(15usize), + self.giwd() + ) + } +} +#[doc = "Interrupt Control Nonprivilege."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Icnp(pub u32); +impl Icnp { + #[doc = "Nonprivilege Enable."] #[must_use] #[inline(always)] - pub const fn giwe23(&self) -> Giwe23 { - let val = (self.0 >> 7usize) & 0x01; - Giwe23::from_bits(val as u8) + pub const fn npe0(&self) -> IcnpNpe0 { + let val = (self.0 >> 0usize) & 0x01; + IcnpNpe0::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonprivilege Enable."] #[inline(always)] - pub const fn set_giwe23(&mut self, val: Giwe23) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + pub const fn set_npe0(&mut self, val: IcnpNpe0) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonprivilege Enable."] #[must_use] #[inline(always)] - pub const fn giwe24(&self) -> Giwe24 { - let val = (self.0 >> 8usize) & 0x01; - Giwe24::from_bits(val as u8) + pub const fn npe1(&self) -> IcnpNpe1 { + let val = (self.0 >> 1usize) & 0x01; + IcnpNpe1::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonprivilege Enable."] #[inline(always)] - pub const fn set_giwe24(&mut self, val: Giwe24) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + pub const fn set_npe1(&mut self, val: IcnpNpe1) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Global Interrupt Write Enable."] - #[must_use] +} +impl Default for Icnp { #[inline(always)] - pub const fn giwe25(&self) -> Giwe25 { - let val = (self.0 >> 9usize) & 0x01; - Giwe25::from_bits(val as u8) + fn default() -> Icnp { + Icnp(0) } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe25(&mut self, val: Giwe25) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); +} +impl core::fmt::Debug for Icnp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Icnp") + .field("npe0", &self.npe0()) + .field("npe1", &self.npe1()) + .finish() } - #[doc = "Global Interrupt Write Enable."] +} +#[cfg(feature = "defmt")] +impl defmt::Format for Icnp { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Icnp {{ npe0: {:?}, npe1: {:?} }}", + self.npe0(), + self.npe1() + ) + } +} +#[doc = "Interrupt Control Nonsecure."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Icns(pub u32); +impl Icns { + #[doc = "Nonsecure Enable."] #[must_use] #[inline(always)] - pub const fn giwe26(&self) -> Giwe26 { - let val = (self.0 >> 10usize) & 0x01; - Giwe26::from_bits(val as u8) + pub const fn nse0(&self) -> IcnsNse0 { + let val = (self.0 >> 0usize) & 0x01; + IcnsNse0::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonsecure Enable."] #[inline(always)] - pub const fn set_giwe26(&mut self, val: Giwe26) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_nse0(&mut self, val: IcnsNse0) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonsecure Enable."] #[must_use] #[inline(always)] - pub const fn giwe27(&self) -> Giwe27 { - let val = (self.0 >> 11usize) & 0x01; - Giwe27::from_bits(val as u8) + pub const fn nse1(&self) -> IcnsNse1 { + let val = (self.0 >> 1usize) & 0x01; + IcnsNse1::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Nonsecure Enable."] #[inline(always)] - pub const fn set_giwe27(&mut self, val: Giwe27) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + pub const fn set_nse1(&mut self, val: IcnsNse1) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } - #[doc = "Global Interrupt Write Enable."] - #[must_use] +} +impl Default for Icns { #[inline(always)] - pub const fn giwe28(&self) -> Giwe28 { - let val = (self.0 >> 12usize) & 0x01; - Giwe28::from_bits(val as u8) + fn default() -> Icns { + Icns(0) } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe28(&mut self, val: Giwe28) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); +} +impl core::fmt::Debug for Icns { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Icns") + .field("nse0", &self.nse0()) + .field("nse1", &self.nse1()) + .finish() } - #[doc = "Global Interrupt Write Enable."] +} +#[cfg(feature = "defmt")] +impl defmt::Format for Icns { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Icns {{ nse0: {:?}, nse1: {:?} }}", + self.nse0(), + self.nse1() + ) + } +} +#[doc = "Interrupt Control index."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Icr(pub u32); +impl Icr { + #[doc = "Interrupt Configuration."] #[must_use] #[inline(always)] - pub const fn giwe29(&self) -> Giwe29 { - let val = (self.0 >> 13usize) & 0x01; - Giwe29::from_bits(val as u8) + pub const fn irqc(&self) -> Irqc { + let val = (self.0 >> 16usize) & 0x0f; + Irqc::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Configuration."] #[inline(always)] - pub const fn set_giwe29(&mut self, val: Giwe29) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize); + pub const fn set_irqc(&mut self, val: Irqc) { + self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Select."] #[must_use] #[inline(always)] - pub const fn giwe30(&self) -> Giwe30 { - let val = (self.0 >> 14usize) & 0x01; - Giwe30::from_bits(val as u8) + pub const fn irqs(&self) -> Irqs { + let val = (self.0 >> 20usize) & 0x01; + Irqs::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Select."] #[inline(always)] - pub const fn set_giwe30(&mut self, val: Giwe30) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize); + pub const fn set_irqs(&mut self, val: Irqs) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Lock."] #[must_use] #[inline(always)] - pub const fn giwe31(&self) -> Giwe31 { - let val = (self.0 >> 15usize) & 0x01; - Giwe31::from_bits(val as u8) + pub const fn lk(&self) -> Lk { + let val = (self.0 >> 23usize) & 0x01; + Lk::from_bits(val as u8) } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Lock."] #[inline(always)] - pub const fn set_giwe31(&mut self, val: Giwe31) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize); + pub const fn set_lk(&mut self, val: Lk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); } - #[doc = "Global Interrupt Write Data."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwd(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 + pub const fn isf(&self) -> Isf { + let val = (self.0 >> 24usize) & 0x01; + Isf::from_bits(val as u8) } - #[doc = "Global Interrupt Write Data."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwd(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + pub const fn set_isf(&mut self, val: Isf) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); } } -impl Default for Gichr { +impl Default for Icr { #[inline(always)] - fn default() -> Gichr { - Gichr(0) + fn default() -> Icr { + Icr(0) } } -impl core::fmt::Debug for Gichr { +impl core::fmt::Debug for Icr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Gichr") - .field("giwe16", &self.giwe16()) - .field("giwe17", &self.giwe17()) - .field("giwe18", &self.giwe18()) - .field("giwe19", &self.giwe19()) - .field("giwe20", &self.giwe20()) - .field("giwe21", &self.giwe21()) - .field("giwe22", &self.giwe22()) - .field("giwe23", &self.giwe23()) - .field("giwe24", &self.giwe24()) - .field("giwe25", &self.giwe25()) - .field("giwe26", &self.giwe26()) - .field("giwe27", &self.giwe27()) - .field("giwe28", &self.giwe28()) - .field("giwe29", &self.giwe29()) - .field("giwe30", &self.giwe30()) - .field("giwe31", &self.giwe31()) - .field("giwd", &self.giwd()) + f.debug_struct("Icr") + .field("irqc", &self.irqc()) + .field("irqs", &self.irqs()) + .field("lk", &self.lk()) + .field("isf", &self.isf()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Gichr { +impl defmt::Format for Icr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Gichr {{ giwe16: {:?}, giwe17: {:?}, giwe18: {:?}, giwe19: {:?}, giwe20: {:?}, giwe21: {:?}, giwe22: {:?}, giwe23: {:?}, giwe24: {:?}, giwe25: {:?}, giwe26: {:?}, giwe27: {:?}, giwe28: {:?}, giwe29: {:?}, giwe30: {:?}, giwe31: {:?}, giwd: {=u16:?} }}", - self.giwe16(), - self.giwe17(), - self.giwe18(), - self.giwe19(), - self.giwe20(), - self.giwe21(), - self.giwe22(), - self.giwe23(), - self.giwe24(), - self.giwe25(), - self.giwe26(), - self.giwe27(), - self.giwe28(), - self.giwe29(), - self.giwe30(), - self.giwe31(), - self.giwd() + "Icr {{ irqc: {:?}, irqs: {:?}, lk: {:?}, isf: {:?} }}", + self.irqc(), + self.irqs(), + self.lk(), + self.isf() ) } } -#[doc = "Global Interrupt Control Low."] +#[doc = "Interrupt Status Flag."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Giclr(pub u32); -impl Giclr { - #[doc = "Global Interrupt Write Enable."] +pub struct Isfr(pub u32); +impl Isfr { + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe0(&self) -> Giwe0 { + pub const fn isf0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - Giwe0::from_bits(val as u8) + val != 0 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwe0(&mut self, val: Giwe0) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_isf0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe1(&self) -> Giwe1 { + pub const fn isf1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - Giwe1::from_bits(val as u8) + val != 0 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwe1(&mut self, val: Giwe1) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_isf1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe2(&self) -> Giwe2 { + pub const fn isf2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - Giwe2::from_bits(val as u8) + val != 0 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwe2(&mut self, val: Giwe2) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_isf2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe3(&self) -> Giwe3 { + pub const fn isf3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - Giwe3::from_bits(val as u8) + val != 0 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwe3(&mut self, val: Giwe3) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_isf3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe4(&self) -> Giwe4 { + pub const fn isf4(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - Giwe4::from_bits(val as u8) + val != 0 } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_giwe4(&mut self, val: Giwe4) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_isf4(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Global Interrupt Write Enable."] + #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn giwe5(&self) -> Giwe5 { + pub const fn isf5(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; - Giwe5::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe5(&mut self, val: Giwe5) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe6(&self) -> Giwe6 { - let val = (self.0 >> 6usize) & 0x01; - Giwe6::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe6(&mut self, val: Giwe6) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe7(&self) -> Giwe7 { - let val = (self.0 >> 7usize) & 0x01; - Giwe7::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe7(&mut self, val: Giwe7) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe8(&self) -> Giwe8 { - let val = (self.0 >> 8usize) & 0x01; - Giwe8::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe8(&mut self, val: Giwe8) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe9(&self) -> Giwe9 { - let val = (self.0 >> 9usize) & 0x01; - Giwe9::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe9(&mut self, val: Giwe9) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe10(&self) -> Giwe10 { - let val = (self.0 >> 10usize) & 0x01; - Giwe10::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe10(&mut self, val: Giwe10) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe11(&self) -> Giwe11 { - let val = (self.0 >> 11usize) & 0x01; - Giwe11::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe11(&mut self, val: Giwe11) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe12(&self) -> Giwe12 { - let val = (self.0 >> 12usize) & 0x01; - Giwe12::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe12(&mut self, val: Giwe12) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe13(&self) -> Giwe13 { - let val = (self.0 >> 13usize) & 0x01; - Giwe13::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe13(&mut self, val: Giwe13) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe14(&self) -> Giwe14 { - let val = (self.0 >> 14usize) & 0x01; - Giwe14::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe14(&mut self, val: Giwe14) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize); - } - #[doc = "Global Interrupt Write Enable."] - #[must_use] - #[inline(always)] - pub const fn giwe15(&self) -> Giwe15 { - let val = (self.0 >> 15usize) & 0x01; - Giwe15::from_bits(val as u8) - } - #[doc = "Global Interrupt Write Enable."] - #[inline(always)] - pub const fn set_giwe15(&mut self, val: Giwe15) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize); - } - #[doc = "Global Interrupt Write Data."] - #[must_use] - #[inline(always)] - pub const fn giwd(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Global Interrupt Write Data."] - #[inline(always)] - pub const fn set_giwd(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } -} -impl Default for Giclr { - #[inline(always)] - fn default() -> Giclr { - Giclr(0) - } -} -impl core::fmt::Debug for Giclr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Giclr") - .field("giwe0", &self.giwe0()) - .field("giwe1", &self.giwe1()) - .field("giwe2", &self.giwe2()) - .field("giwe3", &self.giwe3()) - .field("giwe4", &self.giwe4()) - .field("giwe5", &self.giwe5()) - .field("giwe6", &self.giwe6()) - .field("giwe7", &self.giwe7()) - .field("giwe8", &self.giwe8()) - .field("giwe9", &self.giwe9()) - .field("giwe10", &self.giwe10()) - .field("giwe11", &self.giwe11()) - .field("giwe12", &self.giwe12()) - .field("giwe13", &self.giwe13()) - .field("giwe14", &self.giwe14()) - .field("giwe15", &self.giwe15()) - .field("giwd", &self.giwd()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Giclr { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Giclr {{ giwe0: {:?}, giwe1: {:?}, giwe2: {:?}, giwe3: {:?}, giwe4: {:?}, giwe5: {:?}, giwe6: {:?}, giwe7: {:?}, giwe8: {:?}, giwe9: {:?}, giwe10: {:?}, giwe11: {:?}, giwe12: {:?}, giwe13: {:?}, giwe14: {:?}, giwe15: {:?}, giwd: {=u16:?} }}", - self.giwe0(), - self.giwe1(), - self.giwe2(), - self.giwe3(), - self.giwe4(), - self.giwe5(), - self.giwe6(), - self.giwe7(), - self.giwe8(), - self.giwe9(), - self.giwe10(), - self.giwe11(), - self.giwe12(), - self.giwe13(), - self.giwe14(), - self.giwe15(), - self.giwd() - ) - } -} -#[doc = "Interrupt Control index."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Icr(pub u32); -impl Icr { - #[doc = "Interrupt Configuration."] - #[must_use] - #[inline(always)] - pub const fn irqc(&self) -> Irqc { - let val = (self.0 >> 16usize) & 0x0f; - Irqc::from_bits(val as u8) - } - #[doc = "Interrupt Configuration."] - #[inline(always)] - pub const fn set_irqc(&mut self, val: Irqc) { - self.0 = (self.0 & !(0x0f << 16usize)) | (((val.to_bits() as u32) & 0x0f) << 16usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf(&self) -> Isf { - let val = (self.0 >> 24usize) & 0x01; - Isf::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf(&mut self, val: Isf) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); - } -} -impl Default for Icr { - #[inline(always)] - fn default() -> Icr { - Icr(0) - } -} -impl core::fmt::Debug for Icr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Icr") - .field("irqc", &self.irqc()) - .field("isf", &self.isf()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Icr { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Icr {{ irqc: {:?}, isf: {:?} }}", - self.irqc(), - self.isf() - ) - } -} -#[doc = "Interrupt Status Flag."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Isfr(pub u32); -impl Isfr { - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf0(&self) -> Isf0 { - let val = (self.0 >> 0usize) & 0x01; - Isf0::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf0(&mut self, val: Isf0) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf1(&self) -> Isf1 { - let val = (self.0 >> 1usize) & 0x01; - Isf1::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf1(&mut self, val: Isf1) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf2(&self) -> Isf2 { - let val = (self.0 >> 2usize) & 0x01; - Isf2::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf2(&mut self, val: Isf2) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf3(&self) -> Isf3 { - let val = (self.0 >> 3usize) & 0x01; - Isf3::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf3(&mut self, val: Isf3) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf4(&self) -> Isf4 { - let val = (self.0 >> 4usize) & 0x01; - Isf4::from_bits(val as u8) - } - #[doc = "Interrupt Status Flag."] - #[inline(always)] - pub const fn set_isf4(&mut self, val: Isf4) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); - } - #[doc = "Interrupt Status Flag."] - #[must_use] - #[inline(always)] - pub const fn isf5(&self) -> Isf5 { - let val = (self.0 >> 5usize) & 0x01; - Isf5::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf5(&mut self, val: Isf5) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_isf5(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf6(&self) -> Isf6 { + pub const fn isf6(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; - Isf6::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf6(&mut self, val: Isf6) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + pub const fn set_isf6(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf7(&self) -> Isf7 { + pub const fn isf7(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; - Isf7::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf7(&mut self, val: Isf7) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); + pub const fn set_isf7(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf8(&self) -> Isf8 { + pub const fn isf8(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; - Isf8::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf8(&mut self, val: Isf8) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + pub const fn set_isf8(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf9(&self) -> Isf9 { + pub const fn isf9(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; - Isf9::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf9(&mut self, val: Isf9) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + pub const fn set_isf9(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf10(&self) -> Isf10 { + pub const fn isf10(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; - Isf10::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf10(&mut self, val: Isf10) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_isf10(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf11(&self) -> Isf11 { + pub const fn isf11(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; - Isf11::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf11(&mut self, val: Isf11) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + pub const fn set_isf11(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf12(&self) -> Isf12 { + pub const fn isf12(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; - Isf12::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf12(&mut self, val: Isf12) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); + pub const fn set_isf12(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf13(&self) -> Isf13 { + pub const fn isf13(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; - Isf13::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf13(&mut self, val: Isf13) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize); + pub const fn set_isf13(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf14(&self) -> Isf14 { + pub const fn isf14(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; - Isf14::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf14(&mut self, val: Isf14) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val.to_bits() as u32) & 0x01) << 14usize); + pub const fn set_isf14(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf15(&self) -> Isf15 { + pub const fn isf15(&self) -> bool { let val = (self.0 >> 15usize) & 0x01; - Isf15::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf15(&mut self, val: Isf15) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u32) & 0x01) << 15usize); + pub const fn set_isf15(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf16(&self) -> Isf16 { + pub const fn isf16(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; - Isf16::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf16(&mut self, val: Isf16) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize); + pub const fn set_isf16(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf17(&self) -> Isf17 { + pub const fn isf17(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; - Isf17::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf17(&mut self, val: Isf17) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + pub const fn set_isf17(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf18(&self) -> Isf18 { + pub const fn isf18(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; - Isf18::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf18(&mut self, val: Isf18) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val.to_bits() as u32) & 0x01) << 18usize); + pub const fn set_isf18(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf19(&self) -> Isf19 { + pub const fn isf19(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; - Isf19::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf19(&mut self, val: Isf19) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val.to_bits() as u32) & 0x01) << 19usize); + pub const fn set_isf19(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf20(&self) -> Isf20 { + pub const fn isf20(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; - Isf20::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf20(&mut self, val: Isf20) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val.to_bits() as u32) & 0x01) << 20usize); + pub const fn set_isf20(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf21(&self) -> Isf21 { + pub const fn isf21(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; - Isf21::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf21(&mut self, val: Isf21) { - self.0 = (self.0 & !(0x01 << 21usize)) | (((val.to_bits() as u32) & 0x01) << 21usize); + pub const fn set_isf21(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf22(&self) -> Isf22 { + pub const fn isf22(&self) -> bool { let val = (self.0 >> 22usize) & 0x01; - Isf22::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf22(&mut self, val: Isf22) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize); + pub const fn set_isf22(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf23(&self) -> Isf23 { + pub const fn isf23(&self) -> bool { let val = (self.0 >> 23usize) & 0x01; - Isf23::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf23(&mut self, val: Isf23) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + pub const fn set_isf23(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf24(&self) -> Isf24 { + pub const fn isf24(&self) -> bool { let val = (self.0 >> 24usize) & 0x01; - Isf24::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf24(&mut self, val: Isf24) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + pub const fn set_isf24(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf25(&self) -> Isf25 { + pub const fn isf25(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; - Isf25::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf25(&mut self, val: Isf25) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val.to_bits() as u32) & 0x01) << 25usize); + pub const fn set_isf25(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf26(&self) -> Isf26 { + pub const fn isf26(&self) -> bool { let val = (self.0 >> 26usize) & 0x01; - Isf26::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf26(&mut self, val: Isf26) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + pub const fn set_isf26(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf27(&self) -> Isf27 { + pub const fn isf27(&self) -> bool { let val = (self.0 >> 27usize) & 0x01; - Isf27::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf27(&mut self, val: Isf27) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); + pub const fn set_isf27(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf28(&self) -> Isf28 { + pub const fn isf28(&self) -> bool { let val = (self.0 >> 28usize) & 0x01; - Isf28::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf28(&mut self, val: Isf28) { - self.0 = (self.0 & !(0x01 << 28usize)) | (((val.to_bits() as u32) & 0x01) << 28usize); + pub const fn set_isf28(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf29(&self) -> Isf29 { + pub const fn isf29(&self) -> bool { let val = (self.0 >> 29usize) & 0x01; - Isf29::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf29(&mut self, val: Isf29) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + pub const fn set_isf29(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf30(&self) -> Isf30 { + pub const fn isf30(&self) -> bool { let val = (self.0 >> 30usize) & 0x01; - Isf30::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf30(&mut self, val: Isf30) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); + pub const fn set_isf30(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); } #[doc = "Interrupt Status Flag."] #[must_use] #[inline(always)] - pub const fn isf31(&self) -> Isf31 { + pub const fn isf31(&self) -> bool { let val = (self.0 >> 31usize) & 0x01; - Isf31::from_bits(val as u8) + val != 0 } #[doc = "Interrupt Status Flag."] #[inline(always)] - pub const fn set_isf31(&mut self, val: Isf31) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_isf31(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } impl Default for Isfr { @@ -1121,7 +933,7 @@ impl defmt::Format for Isfr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Isfr {{ isf0: {:?}, isf1: {:?}, isf2: {:?}, isf3: {:?}, isf4: {:?}, isf5: {:?}, isf6: {:?}, isf7: {:?}, isf8: {:?}, isf9: {:?}, isf10: {:?}, isf11: {:?}, isf12: {:?}, isf13: {:?}, isf14: {:?}, isf15: {:?}, isf16: {:?}, isf17: {:?}, isf18: {:?}, isf19: {:?}, isf20: {:?}, isf21: {:?}, isf22: {:?}, isf23: {:?}, isf24: {:?}, isf25: {:?}, isf26: {:?}, isf27: {:?}, isf28: {:?}, isf29: {:?}, isf30: {:?}, isf31: {:?} }}", + "Isfr {{ isf0: {=bool:?}, isf1: {=bool:?}, isf2: {=bool:?}, isf3: {=bool:?}, isf4: {=bool:?}, isf5: {=bool:?}, isf6: {=bool:?}, isf7: {=bool:?}, isf8: {=bool:?}, isf9: {=bool:?}, isf10: {=bool:?}, isf11: {=bool:?}, isf12: {=bool:?}, isf13: {=bool:?}, isf14: {=bool:?}, isf15: {=bool:?}, isf16: {=bool:?}, isf17: {=bool:?}, isf18: {=bool:?}, isf19: {=bool:?}, isf20: {=bool:?}, isf21: {=bool:?}, isf22: {=bool:?}, isf23: {=bool:?}, isf24: {=bool:?}, isf25: {=bool:?}, isf26: {=bool:?}, isf27: {=bool:?}, isf28: {=bool:?}, isf29: {=bool:?}, isf30: {=bool:?}, isf31: {=bool:?} }}", self.isf0(), self.isf1(), self.isf2(), @@ -1157,11 +969,94 @@ impl defmt::Format for Isfr { ) } } -#[doc = "Parameter."] +#[doc = "Lock."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Param(pub u32); -impl Param { +pub struct Lock(pub u32); +impl Lock { + #[doc = "Lock PCNS."] + #[must_use] + #[inline(always)] + pub const fn pcns(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Lock PCNS."] + #[inline(always)] + pub const fn set_pcns(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Lock ICNS."] + #[must_use] + #[inline(always)] + pub const fn icns(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Lock ICNS."] + #[inline(always)] + pub const fn set_icns(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Lock PCNP."] + #[must_use] + #[inline(always)] + pub const fn pcnp(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Lock PCNP."] + #[inline(always)] + pub const fn set_pcnp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Lock ICNP."] + #[must_use] + #[inline(always)] + pub const fn icnp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Lock ICNP."] + #[inline(always)] + pub const fn set_icnp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } +} +impl Default for Lock { + #[inline(always)] + fn default() -> Lock { + Lock(0) + } +} +impl core::fmt::Debug for Lock { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lock") + .field("pcns", &self.pcns()) + .field("icns", &self.icns()) + .field("pcnp", &self.pcnp()) + .field("icnp", &self.icnp()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Lock { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Lock {{ pcns: {=bool:?}, icns: {=bool:?}, pcnp: {=bool:?}, icnp: {=bool:?} }}", + self.pcns(), + self.icns(), + self.pcnp(), + self.icnp() + ) + } +} +#[doc = "Parameter."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Param(pub u32); +impl Param { #[doc = "Interrupt Number."] #[must_use] #[inline(always)] @@ -1194,6 +1089,220 @@ impl defmt::Format for Param { defmt::write!(f, "Param {{ irqnum: {=u8:?} }}", self.irqnum()) } } +#[doc = "Pin Control Nonprivilege."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pcnp(pub u32); +impl Pcnp { + #[doc = "Nonprivilege Enable."] + #[must_use] + #[inline(always)] + pub const fn npe(&self, n: usize) -> PcnpNpe0 { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + PcnpNpe0::from_bits(val as u8) + } + #[doc = "Nonprivilege Enable."] + #[inline(always)] + pub const fn set_npe(&mut self, n: usize, val: PcnpNpe0) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs); + } +} +impl Default for Pcnp { + #[inline(always)] + fn default() -> Pcnp { + Pcnp(0) + } +} +impl core::fmt::Debug for Pcnp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Pcnp") + .field("npe[0]", &self.npe(0usize)) + .field("npe[1]", &self.npe(1usize)) + .field("npe[2]", &self.npe(2usize)) + .field("npe[3]", &self.npe(3usize)) + .field("npe[4]", &self.npe(4usize)) + .field("npe[5]", &self.npe(5usize)) + .field("npe[6]", &self.npe(6usize)) + .field("npe[7]", &self.npe(7usize)) + .field("npe[8]", &self.npe(8usize)) + .field("npe[9]", &self.npe(9usize)) + .field("npe[10]", &self.npe(10usize)) + .field("npe[11]", &self.npe(11usize)) + .field("npe[12]", &self.npe(12usize)) + .field("npe[13]", &self.npe(13usize)) + .field("npe[14]", &self.npe(14usize)) + .field("npe[15]", &self.npe(15usize)) + .field("npe[16]", &self.npe(16usize)) + .field("npe[17]", &self.npe(17usize)) + .field("npe[18]", &self.npe(18usize)) + .field("npe[19]", &self.npe(19usize)) + .field("npe[20]", &self.npe(20usize)) + .field("npe[21]", &self.npe(21usize)) + .field("npe[22]", &self.npe(22usize)) + .field("npe[23]", &self.npe(23usize)) + .field("npe[24]", &self.npe(24usize)) + .field("npe[25]", &self.npe(25usize)) + .field("npe[26]", &self.npe(26usize)) + .field("npe[27]", &self.npe(27usize)) + .field("npe[28]", &self.npe(28usize)) + .field("npe[29]", &self.npe(29usize)) + .field("npe[30]", &self.npe(30usize)) + .field("npe[31]", &self.npe(31usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Pcnp { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Pcnp {{ npe[0]: {:?}, npe[1]: {:?}, npe[2]: {:?}, npe[3]: {:?}, npe[4]: {:?}, npe[5]: {:?}, npe[6]: {:?}, npe[7]: {:?}, npe[8]: {:?}, npe[9]: {:?}, npe[10]: {:?}, npe[11]: {:?}, npe[12]: {:?}, npe[13]: {:?}, npe[14]: {:?}, npe[15]: {:?}, npe[16]: {:?}, npe[17]: {:?}, npe[18]: {:?}, npe[19]: {:?}, npe[20]: {:?}, npe[21]: {:?}, npe[22]: {:?}, npe[23]: {:?}, npe[24]: {:?}, npe[25]: {:?}, npe[26]: {:?}, npe[27]: {:?}, npe[28]: {:?}, npe[29]: {:?}, npe[30]: {:?}, npe[31]: {:?} }}", + self.npe(0usize), + self.npe(1usize), + self.npe(2usize), + self.npe(3usize), + self.npe(4usize), + self.npe(5usize), + self.npe(6usize), + self.npe(7usize), + self.npe(8usize), + self.npe(9usize), + self.npe(10usize), + self.npe(11usize), + self.npe(12usize), + self.npe(13usize), + self.npe(14usize), + self.npe(15usize), + self.npe(16usize), + self.npe(17usize), + self.npe(18usize), + self.npe(19usize), + self.npe(20usize), + self.npe(21usize), + self.npe(22usize), + self.npe(23usize), + self.npe(24usize), + self.npe(25usize), + self.npe(26usize), + self.npe(27usize), + self.npe(28usize), + self.npe(29usize), + self.npe(30usize), + self.npe(31usize) + ) + } +} +#[doc = "Pin Control Nonsecure."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Pcns(pub u32); +impl Pcns { + #[doc = "Nonsecure Enable."] + #[must_use] + #[inline(always)] + pub const fn nse(&self, n: usize) -> PcnsNse0 { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + PcnsNse0::from_bits(val as u8) + } + #[doc = "Nonsecure Enable."] + #[inline(always)] + pub const fn set_nse(&mut self, n: usize, val: PcnsNse0) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.to_bits() as u32) & 0x01) << offs); + } +} +impl Default for Pcns { + #[inline(always)] + fn default() -> Pcns { + Pcns(0) + } +} +impl core::fmt::Debug for Pcns { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Pcns") + .field("nse[0]", &self.nse(0usize)) + .field("nse[1]", &self.nse(1usize)) + .field("nse[2]", &self.nse(2usize)) + .field("nse[3]", &self.nse(3usize)) + .field("nse[4]", &self.nse(4usize)) + .field("nse[5]", &self.nse(5usize)) + .field("nse[6]", &self.nse(6usize)) + .field("nse[7]", &self.nse(7usize)) + .field("nse[8]", &self.nse(8usize)) + .field("nse[9]", &self.nse(9usize)) + .field("nse[10]", &self.nse(10usize)) + .field("nse[11]", &self.nse(11usize)) + .field("nse[12]", &self.nse(12usize)) + .field("nse[13]", &self.nse(13usize)) + .field("nse[14]", &self.nse(14usize)) + .field("nse[15]", &self.nse(15usize)) + .field("nse[16]", &self.nse(16usize)) + .field("nse[17]", &self.nse(17usize)) + .field("nse[18]", &self.nse(18usize)) + .field("nse[19]", &self.nse(19usize)) + .field("nse[20]", &self.nse(20usize)) + .field("nse[21]", &self.nse(21usize)) + .field("nse[22]", &self.nse(22usize)) + .field("nse[23]", &self.nse(23usize)) + .field("nse[24]", &self.nse(24usize)) + .field("nse[25]", &self.nse(25usize)) + .field("nse[26]", &self.nse(26usize)) + .field("nse[27]", &self.nse(27usize)) + .field("nse[28]", &self.nse(28usize)) + .field("nse[29]", &self.nse(29usize)) + .field("nse[30]", &self.nse(30usize)) + .field("nse[31]", &self.nse(31usize)) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Pcns { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Pcns {{ nse[0]: {:?}, nse[1]: {:?}, nse[2]: {:?}, nse[3]: {:?}, nse[4]: {:?}, nse[5]: {:?}, nse[6]: {:?}, nse[7]: {:?}, nse[8]: {:?}, nse[9]: {:?}, nse[10]: {:?}, nse[11]: {:?}, nse[12]: {:?}, nse[13]: {:?}, nse[14]: {:?}, nse[15]: {:?}, nse[16]: {:?}, nse[17]: {:?}, nse[18]: {:?}, nse[19]: {:?}, nse[20]: {:?}, nse[21]: {:?}, nse[22]: {:?}, nse[23]: {:?}, nse[24]: {:?}, nse[25]: {:?}, nse[26]: {:?}, nse[27]: {:?}, nse[28]: {:?}, nse[29]: {:?}, nse[30]: {:?}, nse[31]: {:?} }}", + self.nse(0usize), + self.nse(1usize), + self.nse(2usize), + self.nse(3usize), + self.nse(4usize), + self.nse(5usize), + self.nse(6usize), + self.nse(7usize), + self.nse(8usize), + self.nse(9usize), + self.nse(10usize), + self.nse(11usize), + self.nse(12usize), + self.nse(13usize), + self.nse(14usize), + self.nse(15usize), + self.nse(16usize), + self.nse(17usize), + self.nse(18usize), + self.nse(19usize), + self.nse(20usize), + self.nse(21usize), + self.nse(22usize), + self.nse(23usize), + self.nse(24usize), + self.nse(25usize), + self.nse(26usize), + self.nse(27usize), + self.nse(28usize), + self.nse(29usize), + self.nse(30usize), + self.nse(31usize) + ) + } +} #[doc = "Port Clear Output."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1986,14 +2095,14 @@ impl Verid { #[doc = "Feature Specification Number."] #[must_use] #[inline(always)] - pub const fn feature(&self) -> Feature { + pub const fn feature(&self) -> u16 { let val = (self.0 >> 0usize) & 0xffff; - Feature::from_bits(val as u16) + val as u16 } #[doc = "Feature Specification Number."] #[inline(always)] - pub const fn set_feature(&mut self, val: Feature) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val.to_bits() as u32) & 0xffff) << 0usize); + pub const fn set_feature(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } #[doc = "Minor Version Number."] #[must_use] @@ -2040,228 +2149,25 @@ impl defmt::Format for Verid { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Verid {{ feature: {:?}, minor: {=u8:?}, major: {=u8:?} }}", + "Verid {{ feature: {=u16:?}, minor: {=u8:?}, major: {=u8:?} }}", self.feature(), self.minor(), self.major() ) } } -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct Feature(u16); -impl Feature { - #[doc = "Basic implementation."] - pub const FEATURE0: Self = Self(0x0); - #[doc = "Protection registers implemented."] - pub const FEATURE1: Self = Self(0x01); -} -impl Feature { - pub const fn from_bits(val: u16) -> Feature { - Self(val & 0xffff) - } - pub const fn to_bits(self) -> u16 { - self.0 - } -} -impl core::fmt::Debug for Feature { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - match self.0 { - 0x0 => f.write_str("FEATURE0"), - 0x01 => f.write_str("FEATURE1"), - other => core::write!(f, "0x{:02X}", other), - } - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Feature { - fn format(&self, f: defmt::Formatter) { - match self.0 { - 0x0 => defmt::write!(f, "FEATURE0"), - 0x01 => defmt::write!(f, "FEATURE1"), - other => defmt::write!(f, "0x{:02X}", other), - } - } -} -impl From for Feature { - #[inline(always)] - fn from(val: u16) -> Feature { - Feature::from_bits(val) - } -} -impl From for u16 { - #[inline(always)] - fn from(val: Feature) -> u16 { - Feature::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe0 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe0 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe0 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe0 { - #[inline(always)] - fn from(val: u8) -> Giwe0 { - Giwe0::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe0) -> u8 { - Giwe0::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe1 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe1 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe1 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe1 { - #[inline(always)] - fn from(val: u8) -> Giwe1 { - Giwe1::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe1) -> u8 { - Giwe1::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe10 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe10 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe10 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe10 { - #[inline(always)] - fn from(val: u8) -> Giwe10 { - Giwe10::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe10) -> u8 { - Giwe10::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe11 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe11 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe11 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe11 { - #[inline(always)] - fn from(val: u8) -> Giwe11 { - Giwe11::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe11) -> u8 { - Giwe11::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe12 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe12 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe12 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe12 { - #[inline(always)] - fn from(val: u8) -> Giwe12 { - Giwe12::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe12) -> u8 { - Giwe12::to_bits(val) - } -} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe13 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum IcnpNpe0 { + #[doc = "Privilege access."] + Npe0 = 0x0, + #[doc = "Nonprivilege access."] + Npe1 = 0x01, } -impl Giwe13 { +impl IcnpNpe0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe13 { + pub const fn from_bits(val: u8) -> IcnpNpe0 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2269,30 +2175,30 @@ impl Giwe13 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe13 { +impl From for IcnpNpe0 { #[inline(always)] - fn from(val: u8) -> Giwe13 { - Giwe13::from_bits(val) + fn from(val: u8) -> IcnpNpe0 { + IcnpNpe0::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe13) -> u8 { - Giwe13::to_bits(val) + fn from(val: IcnpNpe0) -> u8 { + IcnpNpe0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe14 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum IcnpNpe1 { + #[doc = "Privilege access."] + Npe0 = 0x0, + #[doc = "Nonprivilege access."] + Npe1 = 0x01, } -impl Giwe14 { +impl IcnpNpe1 { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe14 { + pub const fn from_bits(val: u8) -> IcnpNpe1 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2300,30 +2206,30 @@ impl Giwe14 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe14 { +impl From for IcnpNpe1 { #[inline(always)] - fn from(val: u8) -> Giwe14 { - Giwe14::from_bits(val) + fn from(val: u8) -> IcnpNpe1 { + IcnpNpe1::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe14) -> u8 { - Giwe14::to_bits(val) + fn from(val: IcnpNpe1) -> u8 { + IcnpNpe1::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe15 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum IcnsNse0 { + #[doc = "Secure access."] + Nse0 = 0x0, + #[doc = "Nonsecure access."] + Nse1 = 0x01, } -impl Giwe15 { +impl IcnsNse0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe15 { + pub const fn from_bits(val: u8) -> IcnsNse0 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2331,30 +2237,30 @@ impl Giwe15 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe15 { +impl From for IcnsNse0 { #[inline(always)] - fn from(val: u8) -> Giwe15 { - Giwe15::from_bits(val) + fn from(val: u8) -> IcnsNse0 { + IcnsNse0::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe15) -> u8 { - Giwe15::to_bits(val) + fn from(val: IcnsNse0) -> u8 { + IcnsNse0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe16 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum IcnsNse1 { + #[doc = "Secure access."] + Nse0 = 0x0, + #[doc = "Nonsecure access."] + Nse1 = 0x01, } -impl Giwe16 { +impl IcnsNse1 { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe16 { + pub const fn from_bits(val: u8) -> IcnsNse1 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2362,61 +2268,87 @@ impl Giwe16 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe16 { +impl From for IcnsNse1 { #[inline(always)] - fn from(val: u8) -> Giwe16 { - Giwe16::from_bits(val) + fn from(val: u8) -> IcnsNse1 { + IcnsNse1::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe16) -> u8 { - Giwe16::to_bits(val) + fn from(val: IcnsNse1) -> u8 { + IcnsNse1::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe17 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum Irqc { + #[doc = "ISF is disabled."] + Irqc0 = 0x0, + #[doc = "ISF and DMA request on rising edge."] + Irqc1 = 0x01, + #[doc = "ISF and DMA request on falling edge."] + Irqc2 = 0x02, + #[doc = "ISF and DMA request on either edge."] + Irqc3 = 0x03, + _RESERVED_4 = 0x04, + #[doc = "ISF sets on rising edge."] + Irqc5 = 0x05, + #[doc = "ISF sets on falling edge."] + Irqc6 = 0x06, + #[doc = "ISF sets on either edge."] + Irqc7 = 0x07, + #[doc = "ISF and interrupt when logic 0."] + Irqc8 = 0x08, + #[doc = "ISF and interrupt on rising edge."] + Irqc9 = 0x09, + #[doc = "ISF and interrupt on falling edge."] + Irqc10 = 0x0a, + #[doc = "ISF and Interrupt on either edge."] + Irqc11 = 0x0b, + #[doc = "ISF and interrupt when logic 1."] + Irqc12 = 0x0c, + #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)."] + Irqc13 = 0x0d, + #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)."] + Irqc14 = 0x0e, + _RESERVED_f = 0x0f, } -impl Giwe17 { +impl Irqc { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe17 { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> Irqc { + unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe17 { +impl From for Irqc { #[inline(always)] - fn from(val: u8) -> Giwe17 { - Giwe17::from_bits(val) + fn from(val: u8) -> Irqc { + Irqc::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe17) -> u8 { - Giwe17::to_bits(val) + fn from(val: Irqc) -> u8 { + Irqc::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe18 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum Irqs { + #[doc = "Interrupt, trigger output, or DMA request 0."] + Irqs0 = 0x0, + #[doc = "Interrupt, trigger output, or DMA request 1."] + Irqs1 = 0x01, } -impl Giwe18 { +impl Irqs { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe18 { + pub const fn from_bits(val: u8) -> Irqs { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2424,30 +2356,30 @@ impl Giwe18 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe18 { +impl From for Irqs { #[inline(always)] - fn from(val: u8) -> Giwe18 { - Giwe18::from_bits(val) + fn from(val: u8) -> Irqs { + Irqs::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe18) -> u8 { - Giwe18::to_bits(val) + fn from(val: Irqs) -> u8 { + Irqs::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe19 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum Isf { + #[doc = "Not detected."] + Isf0 = 0x0, + #[doc = "Detected."] + Isf1 = 0x01, } -impl Giwe19 { +impl Isf { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe19 { + pub const fn from_bits(val: u8) -> Isf { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2455,30 +2387,30 @@ impl Giwe19 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe19 { +impl From for Isf { #[inline(always)] - fn from(val: u8) -> Giwe19 { - Giwe19::from_bits(val) + fn from(val: u8) -> Isf { + Isf::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe19) -> u8 { - Giwe19::to_bits(val) + fn from(val: Isf) -> u8 { + Isf::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe2 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum Lk { + #[doc = "Not locked."] + Lk0 = 0x0, + #[doc = "Locked."] + Lk1 = 0x01, } -impl Giwe2 { +impl Lk { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe2 { + pub const fn from_bits(val: u8) -> Lk { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2486,30 +2418,30 @@ impl Giwe2 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe2 { +impl From for Lk { #[inline(always)] - fn from(val: u8) -> Giwe2 { - Giwe2::from_bits(val) + fn from(val: u8) -> Lk { + Lk::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe2) -> u8 { - Giwe2::to_bits(val) + fn from(val: Lk) -> u8 { + Lk::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe20 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, +pub enum PcnpNpe0 { + #[doc = "Privilege access."] + Npe0 = 0x0, + #[doc = "Nonprivilege access."] + Npe1 = 0x01, } -impl Giwe20 { +impl PcnpNpe0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe20 { + pub const fn from_bits(val: u8) -> PcnpNpe0 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2517,1637 +2449,30 @@ impl Giwe20 { unsafe { core::mem::transmute(self) } } } -impl From for Giwe20 { +impl From for PcnpNpe0 { #[inline(always)] - fn from(val: u8) -> Giwe20 { - Giwe20::from_bits(val) + fn from(val: u8) -> PcnpNpe0 { + PcnpNpe0::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Giwe20) -> u8 { - Giwe20::to_bits(val) + fn from(val: PcnpNpe0) -> u8 { + PcnpNpe0::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe21 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe21 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe21 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe21 { - #[inline(always)] - fn from(val: u8) -> Giwe21 { - Giwe21::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe21) -> u8 { - Giwe21::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe22 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe22 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe22 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe22 { - #[inline(always)] - fn from(val: u8) -> Giwe22 { - Giwe22::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe22) -> u8 { - Giwe22::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe23 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe23 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe23 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe23 { - #[inline(always)] - fn from(val: u8) -> Giwe23 { - Giwe23::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe23) -> u8 { - Giwe23::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe24 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe24 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe24 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe24 { - #[inline(always)] - fn from(val: u8) -> Giwe24 { - Giwe24::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe24) -> u8 { - Giwe24::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe25 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe25 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe25 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe25 { - #[inline(always)] - fn from(val: u8) -> Giwe25 { - Giwe25::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe25) -> u8 { - Giwe25::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe26 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe26 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe26 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe26 { - #[inline(always)] - fn from(val: u8) -> Giwe26 { - Giwe26::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe26) -> u8 { - Giwe26::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe27 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe27 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe27 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe27 { - #[inline(always)] - fn from(val: u8) -> Giwe27 { - Giwe27::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe27) -> u8 { - Giwe27::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe28 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe28 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe28 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe28 { - #[inline(always)] - fn from(val: u8) -> Giwe28 { - Giwe28::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe28) -> u8 { - Giwe28::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe29 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe29 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe29 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe29 { - #[inline(always)] - fn from(val: u8) -> Giwe29 { - Giwe29::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe29) -> u8 { - Giwe29::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe3 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe3 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe3 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe3 { - #[inline(always)] - fn from(val: u8) -> Giwe3 { - Giwe3::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe3) -> u8 { - Giwe3::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe30 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe30 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe30 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe30 { - #[inline(always)] - fn from(val: u8) -> Giwe30 { - Giwe30::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe30) -> u8 { - Giwe30::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe31 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe31 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe31 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe31 { - #[inline(always)] - fn from(val: u8) -> Giwe31 { - Giwe31::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe31) -> u8 { - Giwe31::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe4 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe4 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe4 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe4 { - #[inline(always)] - fn from(val: u8) -> Giwe4 { - Giwe4::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe4) -> u8 { - Giwe4::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe5 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe5 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe5 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe5 { - #[inline(always)] - fn from(val: u8) -> Giwe5 { - Giwe5::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe5) -> u8 { - Giwe5::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe6 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe6 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe6 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe6 { - #[inline(always)] - fn from(val: u8) -> Giwe6 { - Giwe6::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe6) -> u8 { - Giwe6::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe7 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe7 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe7 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe7 { - #[inline(always)] - fn from(val: u8) -> Giwe7 { - Giwe7::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe7) -> u8 { - Giwe7::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe8 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe8 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe8 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe8 { - #[inline(always)] - fn from(val: u8) -> Giwe8 { - Giwe8::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe8) -> u8 { - Giwe8::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Giwe9 { - #[doc = "Not updated."] - GIWE0 = 0x0, - #[doc = "Updated."] - GIWE1 = 0x01, -} -impl Giwe9 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Giwe9 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Giwe9 { - #[inline(always)] - fn from(val: u8) -> Giwe9 { - Giwe9::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Giwe9) -> u8 { - Giwe9::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Irqc { - #[doc = "ISF is disabled."] - IRQC0 = 0x0, - #[doc = "ISF and DMA request on rising edge."] - IRQC1 = 0x01, - #[doc = "ISF and DMA request on falling edge."] - IRQC2 = 0x02, - #[doc = "ISF and DMA request on either edge."] - IRQC3 = 0x03, - _RESERVED_4 = 0x04, - #[doc = "ISF sets on rising edge."] - IRQC5 = 0x05, - #[doc = "ISF sets on falling edge."] - IRQC6 = 0x06, - #[doc = "ISF sets on either edge."] - IRQC7 = 0x07, - #[doc = "ISF and interrupt when logic 0."] - IRQC8 = 0x08, - #[doc = "ISF and interrupt on rising edge."] - IRQC9 = 0x09, - #[doc = "ISF and interrupt on falling edge."] - IRQC10 = 0x0a, - #[doc = "ISF and Interrupt on either edge."] - IRQC11 = 0x0b, - #[doc = "ISF and interrupt when logic 1."] - IRQC12 = 0x0c, - #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)."] - IRQC13 = 0x0d, - #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)."] - IRQC14 = 0x0e, - _RESERVED_f = 0x0f, -} -impl Irqc { - #[inline(always)] - pub const fn from_bits(val: u8) -> Irqc { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Irqc { - #[inline(always)] - fn from(val: u8) -> Irqc { - Irqc::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Irqc) -> u8 { - Irqc::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf { - #[inline(always)] - fn from(val: u8) -> Isf { - Isf::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf) -> u8 { - Isf::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf0 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf0 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf0 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf0 { - #[inline(always)] - fn from(val: u8) -> Isf0 { - Isf0::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf0) -> u8 { - Isf0::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf1 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf1 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf1 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf1 { - #[inline(always)] - fn from(val: u8) -> Isf1 { - Isf1::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf1) -> u8 { - Isf1::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf10 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf10 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf10 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf10 { - #[inline(always)] - fn from(val: u8) -> Isf10 { - Isf10::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf10) -> u8 { - Isf10::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf11 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf11 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf11 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf11 { - #[inline(always)] - fn from(val: u8) -> Isf11 { - Isf11::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf11) -> u8 { - Isf11::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf12 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf12 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf12 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf12 { - #[inline(always)] - fn from(val: u8) -> Isf12 { - Isf12::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf12) -> u8 { - Isf12::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf13 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf13 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf13 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf13 { - #[inline(always)] - fn from(val: u8) -> Isf13 { - Isf13::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf13) -> u8 { - Isf13::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf14 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf14 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf14 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf14 { - #[inline(always)] - fn from(val: u8) -> Isf14 { - Isf14::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf14) -> u8 { - Isf14::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf15 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf15 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf15 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf15 { - #[inline(always)] - fn from(val: u8) -> Isf15 { - Isf15::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf15) -> u8 { - Isf15::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf16 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf16 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf16 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf16 { - #[inline(always)] - fn from(val: u8) -> Isf16 { - Isf16::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf16) -> u8 { - Isf16::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf17 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf17 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf17 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf17 { - #[inline(always)] - fn from(val: u8) -> Isf17 { - Isf17::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf17) -> u8 { - Isf17::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf18 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf18 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf18 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf18 { - #[inline(always)] - fn from(val: u8) -> Isf18 { - Isf18::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf18) -> u8 { - Isf18::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf19 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf19 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf19 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf19 { - #[inline(always)] - fn from(val: u8) -> Isf19 { - Isf19::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf19) -> u8 { - Isf19::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf2 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf2 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf2 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf2 { - #[inline(always)] - fn from(val: u8) -> Isf2 { - Isf2::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf2) -> u8 { - Isf2::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf20 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf20 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf20 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf20 { - #[inline(always)] - fn from(val: u8) -> Isf20 { - Isf20::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf20) -> u8 { - Isf20::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf21 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf21 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf21 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf21 { - #[inline(always)] - fn from(val: u8) -> Isf21 { - Isf21::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf21) -> u8 { - Isf21::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf22 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf22 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf22 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf22 { - #[inline(always)] - fn from(val: u8) -> Isf22 { - Isf22::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf22) -> u8 { - Isf22::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf23 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf23 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf23 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf23 { - #[inline(always)] - fn from(val: u8) -> Isf23 { - Isf23::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf23) -> u8 { - Isf23::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf24 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf24 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf24 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf24 { - #[inline(always)] - fn from(val: u8) -> Isf24 { - Isf24::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf24) -> u8 { - Isf24::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf25 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf25 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf25 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf25 { - #[inline(always)] - fn from(val: u8) -> Isf25 { - Isf25::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf25) -> u8 { - Isf25::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf26 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf26 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf26 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf26 { - #[inline(always)] - fn from(val: u8) -> Isf26 { - Isf26::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf26) -> u8 { - Isf26::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf27 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf27 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf27 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf27 { - #[inline(always)] - fn from(val: u8) -> Isf27 { - Isf27::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf27) -> u8 { - Isf27::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf28 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf28 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf28 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf28 { - #[inline(always)] - fn from(val: u8) -> Isf28 { - Isf28::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf28) -> u8 { - Isf28::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf29 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf29 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf29 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf29 { - #[inline(always)] - fn from(val: u8) -> Isf29 { - Isf29::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf29) -> u8 { - Isf29::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf3 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf3 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf3 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf3 { - #[inline(always)] - fn from(val: u8) -> Isf3 { - Isf3::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf3) -> u8 { - Isf3::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf30 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf30 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf30 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf30 { - #[inline(always)] - fn from(val: u8) -> Isf30 { - Isf30::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf30) -> u8 { - Isf30::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf31 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf31 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf31 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf31 { - #[inline(always)] - fn from(val: u8) -> Isf31 { - Isf31::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf31) -> u8 { - Isf31::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf4 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf4 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf4 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf4 { - #[inline(always)] - fn from(val: u8) -> Isf4 { - Isf4::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf4) -> u8 { - Isf4::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf5 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf5 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf5 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf5 { - #[inline(always)] - fn from(val: u8) -> Isf5 { - Isf5::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf5) -> u8 { - Isf5::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf6 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf6 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf6 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf6 { - #[inline(always)] - fn from(val: u8) -> Isf6 { - Isf6::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf6) -> u8 { - Isf6::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf7 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf7 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf7 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf7 { - #[inline(always)] - fn from(val: u8) -> Isf7 { - Isf7::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf7) -> u8 { - Isf7::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf8 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, -} -impl Isf8 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Isf8 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Isf8 { - #[inline(always)] - fn from(val: u8) -> Isf8 { - Isf8::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Isf8) -> u8 { - Isf8::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Isf9 { - #[doc = "Not detected."] - ISF0 = 0x0, - #[doc = "Detected."] - ISF1 = 0x01, +pub enum PcnsNse0 { + #[doc = "Secure access."] + Nse0 = 0x0, + #[doc = "Nonsecure access."] + Nse1 = 0x01, } -impl Isf9 { +impl PcnsNse0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Isf9 { + pub const fn from_bits(val: u8) -> PcnsNse0 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -4155,16 +2480,16 @@ impl Isf9 { unsafe { core::mem::transmute(self) } } } -impl From for Isf9 { +impl From for PcnsNse0 { #[inline(always)] - fn from(val: u8) -> Isf9 { - Isf9::from_bits(val) + fn from(val: u8) -> PcnsNse0 { + PcnsNse0::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Isf9) -> u8 { - Isf9::to_bits(val) + fn from(val: PcnsNse0) -> u8 { + PcnsNse0::to_bits(val) } } #[repr(u8)] @@ -4172,9 +2497,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pd { #[doc = "Logic zero."] - PD0 = 0x0, + Pd0 = 0x0, #[doc = "Logic one."] - PD1 = 0x01, + Pd1 = 0x01, } impl Pd { #[inline(always)] @@ -4203,9 +2528,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pdd { #[doc = "Input."] - PDD0 = 0x0, + Pdd0 = 0x0, #[doc = "Output."] - PDD1 = 0x01, + Pdd1 = 0x01, } impl Pdd { #[inline(always)] @@ -4234,9 +2559,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pid { #[doc = "Configured for general-purpose input."] - PID0 = 0x0, + Pid0 = 0x0, #[doc = "Disabled for general-purpose input."] - PID1 = 0x01, + Pid1 = 0x01, } impl Pid { #[inline(always)] @@ -4265,9 +2590,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ptco { #[doc = "No change."] - PTCO0 = 0x0, + Ptco0 = 0x0, #[doc = "Corresponding field in PDOR becomes 0."] - PTCO1 = 0x01, + Ptco1 = 0x01, } impl Ptco { #[inline(always)] @@ -4296,9 +2621,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ptso { #[doc = "No change."] - PTSO0 = 0x0, + Ptso0 = 0x0, #[doc = "Corresponding field in PDOR becomes 1."] - PTSO1 = 0x01, + Ptso1 = 0x01, } impl Ptso { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/I3C.rs b/nxp-pac/src/meta_peripherals/mcxa/I3C.rs index 6e0cf62..94350a2 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/I3C.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/I3C.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Improved Inter-Integrated Circuit."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct I3c { @@ -62,6 +63,16 @@ impl I3c { pub const fn sdmactrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } } + #[doc = "Target HDR-BT Configuration."] + #[inline(always)] + pub const fn shdrbtcfg(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x24usize) as _) } + } + #[doc = "Target HDR-Last."] + #[inline(always)] + pub const fn shdrbtlast(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x28usize) as _) } + } #[doc = "Target Data Control."] #[inline(always)] pub const fn sdatactrl(self) -> crate::pac::common::Reg { @@ -102,11 +113,6 @@ impl I3c { pub const fn swdatab1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x54usize) as _) } } - #[doc = "Target Write Data Halfword."] - #[inline(always)] - pub const fn swdatah1(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x54usize) as _) } - } #[doc = "Target Capabilities 2."] #[inline(always)] pub const fn scapabilities2( @@ -121,11 +127,6 @@ impl I3c { ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x60usize) as _) } } - #[doc = "Target Dynamic Address."] - #[inline(always)] - pub const fn sdynaddr(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x64usize) as _) } - } #[doc = "Target Maximum Limits."] #[inline(always)] pub const fn smaxlimits(self) -> crate::pac::common::Reg { @@ -201,6 +202,16 @@ impl I3c { pub const fn mdmactrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa0usize) as _) } } + #[doc = "Controller HDR-BT Configuration."] + #[inline(always)] + pub const fn mhdrbtcfg(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa4usize) as _) } + } + #[doc = "Controller HDR-Last."] + #[inline(always)] + pub const fn mhdrbtlast(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa8usize) as _) } + } #[doc = "Controller Data Control."] #[inline(always)] pub const fn mdatactrl(self) -> crate::pac::common::Reg { @@ -241,11 +252,6 @@ impl I3c { pub const fn mwdatab1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xccusize) as _) } } - #[doc = "Controller Write Halfword Data (to Bus)."] - #[inline(always)] - pub const fn mwdatah1(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xccusize) as _) } - } #[doc = "Controller Write Message Control in SDR mode."] #[inline(always)] pub const fn mwmsg_sdr_control( @@ -296,11 +302,26 @@ impl I3c { pub const fn mdynaddr(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe4usize) as _) } } + #[doc = "Write Word Data (to Bus)."] + #[inline(always)] + pub const fn mwdataw(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf0usize) as _) } + } + #[doc = "Read Word Data (from Bus)."] + #[inline(always)] + pub const fn mrdataw(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf8usize) as _) } + } #[doc = "Map Feature Control 0."] #[inline(always)] pub const fn smapctrl0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x011cusize) as _) } } + #[doc = "Map Feature Control 1."] + #[inline(always)] + pub const fn smapctrl1(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize) as _) } + } #[doc = "Extended IBI Data 1."] #[inline(always)] pub const fn ibiext1(self) -> crate::pac::common::Reg { @@ -311,6 +332,16 @@ impl I3c { pub const fn ibiext2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0144usize) as _) } } + #[doc = "Target Write Word Data (to Bus)."] + #[inline(always)] + pub const fn swdataw(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0150usize) as _) } + } + #[doc = "Target Read Word Data (from Bus)."] + #[inline(always)] + pub const fn srdataw(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0158usize) as _) } + } #[doc = "Target Module ID."] #[inline(always)] pub const fn sid(self) -> crate::pac::common::Reg { @@ -1288,6 +1319,126 @@ impl defmt::Format for Merrwarn { ) } } +#[doc = "Controller HDR-BT Configuration."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mhdrbtcfg(pub u32); +impl Mhdrbtcfg { + #[doc = "Multi-Lane HDR."] + #[must_use] + #[inline(always)] + pub const fn mlhdr(&self) -> Mlhdr { + let val = (self.0 >> 0usize) & 0x03; + Mlhdr::from_bits(val as u8) + } + #[doc = "Multi-Lane HDR."] + #[inline(always)] + pub const fn set_mlhdr(&mut self, val: Mlhdr) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "Multi-Lane Data."] + #[must_use] + #[inline(always)] + pub const fn mldat(&self) -> Mldat { + let val = (self.0 >> 2usize) & 0x03; + Mldat::from_bits(val as u8) + } + #[doc = "Multi-Lane Data."] + #[inline(always)] + pub const fn set_mldat(&mut self, val: Mldat) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); + } + #[doc = "CRC32."] + #[must_use] + #[inline(always)] + pub const fn crc32(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC32."] + #[inline(always)] + pub const fn set_crc32(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Data Length."] + #[must_use] + #[inline(always)] + pub const fn datalen(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Data Length."] + #[inline(always)] + pub const fn set_datalen(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Mhdrbtcfg { + #[inline(always)] + fn default() -> Mhdrbtcfg { + Mhdrbtcfg(0) + } +} +impl core::fmt::Debug for Mhdrbtcfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mhdrbtcfg") + .field("mlhdr", &self.mlhdr()) + .field("mldat", &self.mldat()) + .field("crc32", &self.crc32()) + .field("datalen", &self.datalen()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Mhdrbtcfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Mhdrbtcfg {{ mlhdr: {:?}, mldat: {:?}, crc32: {=bool:?}, datalen: {=u16:?} }}", + self.mlhdr(), + self.mldat(), + self.crc32(), + self.datalen() + ) + } +} +#[doc = "Controller HDR-Last."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mhdrbtlast(pub u32); +impl Mhdrbtlast { + #[doc = "Data Length."] + #[must_use] + #[inline(always)] + pub const fn datalen(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Data Length."] + #[inline(always)] + pub const fn set_datalen(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Mhdrbtlast { + #[inline(always)] + fn default() -> Mhdrbtlast { + Mhdrbtlast(0) + } +} +impl core::fmt::Debug for Mhdrbtlast { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mhdrbtlast") + .field("datalen", &self.datalen()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Mhdrbtlast { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Mhdrbtlast {{ datalen: {=u16:?} }}", self.datalen()) + } +} #[doc = "Controller In-band Interrupt Registry and Rules."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1922,6 +2073,43 @@ impl defmt::Format for Mrdatah { ) } } +#[doc = "Read Word Data (from Bus)."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mrdataw(pub u32); +impl Mrdataw { + #[doc = "Value."] + #[must_use] + #[inline(always)] + pub const fn value(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Value."] + #[inline(always)] + pub const fn set_value(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Mrdataw { + #[inline(always)] + fn default() -> Mrdataw { + Mrdataw(0) + } +} +impl core::fmt::Debug for Mrdataw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mrdataw") + .field("value", &self.value()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Mrdataw { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Mrdataw {{ value: {=u32:?} }}", self.value()) + } +} #[doc = "Controller Read Message in DDR mode."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2417,43 +2605,6 @@ impl defmt::Format for Mwdatah { ) } } -#[doc = "Controller Write Halfword Data (to Bus)."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mwdatah1(pub u32); -impl Mwdatah1 { - #[doc = "Value."] - #[must_use] - #[inline(always)] - pub const fn value(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Value."] - #[inline(always)] - pub const fn set_value(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Mwdatah1 { - #[inline(always)] - fn default() -> Mwdatah1 { - Mwdatah1(0) - } -} -impl core::fmt::Debug for Mwdatah1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mwdatah1") - .field("value", &self.value()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Mwdatah1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Mwdatah1 {{ value: {=u16:?} }}", self.value()) - } -} #[doc = "Controller Write Data Halfword End."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2509,6 +2660,43 @@ impl defmt::Format for Mwdatahe { ) } } +#[doc = "Write Word Data (to Bus)."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Mwdataw(pub u32); +impl Mwdataw { + #[doc = "Data."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Mwdataw { + #[inline(always)] + fn default() -> Mwdataw { + Mwdataw(0) + } +} +impl core::fmt::Debug for Mwdataw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Mwdataw") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Mwdataw { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Mwdataw {{ data: {=u32:?} }}", self.data()) + } +} #[doc = "Controller Write Message in DDR mode: First Control Word."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3201,16 +3389,16 @@ impl Sconfig { pub const fn set_s0ignore(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "HDR OK."] + #[doc = "Double Data Rate OK."] #[must_use] #[inline(always)] - pub const fn hdrok(&self) -> bool { + pub const fn ddrok(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "HDR OK."] + #[doc = "Double Data Rate OK."] #[inline(always)] - pub const fn set_hdrok(&mut self, val: bool) { + pub const fn set_ddrok(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } #[doc = "Offline."] @@ -3263,7 +3451,7 @@ impl core::fmt::Debug for Sconfig { .field("nack", &self.nack()) .field("matchss", &self.matchss()) .field("s0ignore", &self.s0ignore()) - .field("hdrok", &self.hdrok()) + .field("ddrok", &self.ddrok()) .field("offline", &self.offline()) .field("bamatch", &self.bamatch()) .field("saddr", &self.saddr()) @@ -3275,12 +3463,12 @@ impl defmt::Format for Sconfig { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sconfig {{ slvena: {=bool:?}, nack: {=bool:?}, matchss: {=bool:?}, s0ignore: {=bool:?}, hdrok: {=bool:?}, offline: {=bool:?}, bamatch: {=u8:?}, saddr: {=u8:?} }}", + "Sconfig {{ slvena: {=bool:?}, nack: {=bool:?}, matchss: {=bool:?}, s0ignore: {=bool:?}, ddrok: {=bool:?}, offline: {=bool:?}, bamatch: {=u8:?}, saddr: {=u8:?} }}", self.slvena(), self.nack(), self.matchss(), self.s0ignore(), - self.hdrok(), + self.ddrok(), self.offline(), self.bamatch(), self.saddr() @@ -3316,6 +3504,18 @@ impl Sctrl { pub const fn set_extdata(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } + #[doc = "Map Index."] + #[must_use] + #[inline(always)] + pub const fn mapidx(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Map Index."] + #[inline(always)] + pub const fn set_mapidx(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } #[doc = "In-Band Interrupt Data."] #[must_use] #[inline(always)] @@ -3376,6 +3576,7 @@ impl core::fmt::Debug for Sctrl { f.debug_struct("Sctrl") .field("event", &self.event()) .field("extdata", &self.extdata()) + .field("mapidx", &self.mapidx()) .field("ibidata", &self.ibidata()) .field("pendint", &self.pendint()) .field("actstate", &self.actstate()) @@ -3388,9 +3589,10 @@ impl defmt::Format for Sctrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sctrl {{ event: {:?}, extdata: {=bool:?}, ibidata: {=u8:?}, pendint: {=u8:?}, actstate: {=u8:?}, vendinfo: {=u8:?} }}", + "Sctrl {{ event: {:?}, extdata: {=bool:?}, mapidx: {=bool:?}, ibidata: {=u8:?}, pendint: {=u8:?}, actstate: {=u8:?}, vendinfo: {=u8:?} }}", self.event(), self.extdata(), + self.mapidx(), self.ibidata(), self.pendint(), self.actstate(), @@ -3620,103 +3822,6 @@ impl defmt::Format for Sdmactrl { ) } } -#[doc = "Target Dynamic Address."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sdynaddr(pub u32); -impl Sdynaddr { - #[doc = "Dynamic Address Valid."] - #[must_use] - #[inline(always)] - pub const fn davalid(&self) -> SdynaddrDavalid { - let val = (self.0 >> 0usize) & 0x01; - SdynaddrDavalid::from_bits(val as u8) - } - #[doc = "Dynamic Address Valid."] - #[inline(always)] - pub const fn set_davalid(&mut self, val: SdynaddrDavalid) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); - } - #[doc = "Dynamic Address."] - #[must_use] - #[inline(always)] - pub const fn daddr(&self) -> u8 { - let val = (self.0 >> 1usize) & 0x7f; - val as u8 - } - #[doc = "Dynamic Address."] - #[inline(always)] - pub const fn set_daddr(&mut self, val: u8) { - self.0 = (self.0 & !(0x7f << 1usize)) | (((val as u32) & 0x7f) << 1usize); - } - #[doc = "Map a Static Address."] - #[must_use] - #[inline(always)] - pub const fn mapsa(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 - } - #[doc = "Map a Static Address."] - #[inline(always)] - pub const fn set_mapsa(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); - } - #[doc = "10-Bit Static Address."] - #[must_use] - #[inline(always)] - pub const fn sa10b(&self) -> u8 { - let val = (self.0 >> 13usize) & 0x07; - val as u8 - } - #[doc = "10-Bit Static Address."] - #[inline(always)] - pub const fn set_sa10b(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 13usize)) | (((val as u32) & 0x07) << 13usize); - } - #[doc = "Key."] - #[must_use] - #[inline(always)] - pub const fn key(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 - } - #[doc = "Key."] - #[inline(always)] - pub const fn set_key(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); - } -} -impl Default for Sdynaddr { - #[inline(always)] - fn default() -> Sdynaddr { - Sdynaddr(0) - } -} -impl core::fmt::Debug for Sdynaddr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sdynaddr") - .field("davalid", &self.davalid()) - .field("daddr", &self.daddr()) - .field("mapsa", &self.mapsa()) - .field("sa10b", &self.sa10b()) - .field("key", &self.key()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Sdynaddr { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Sdynaddr {{ davalid: {:?}, daddr: {=u8:?}, mapsa: {=bool:?}, sa10b: {=u8:?}, key: {=u16:?} }}", - self.davalid(), - self.daddr(), - self.mapsa(), - self.sa10b(), - self.key() - ) - } -} #[doc = "Target Errors and Warnings."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -3830,16 +3935,28 @@ impl Serrwarn { pub const fn set_s0s1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Over-Read Error Flag."] + #[doc = "HDR-BT Invalid Request Flag."] #[must_use] #[inline(always)] - pub const fn oread(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + pub const fn hinvreq(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "Over-Read Error Flag."] + #[doc = "HDR-BT Invalid Request Flag."] #[inline(always)] - pub const fn set_oread(&mut self, val: bool) { + pub const fn set_hinvreq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Over-Read Error Flag."] + #[must_use] + #[inline(always)] + pub const fn oread(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Over-Read Error Flag."] + #[inline(always)] + pub const fn set_oread(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } #[doc = "Over-Write Error Flag."] @@ -3873,6 +3990,7 @@ impl core::fmt::Debug for Serrwarn { .field("hpar", &self.hpar()) .field("hcrc", &self.hcrc()) .field("s0s1", &self.s0s1()) + .field("hinvreq", &self.hinvreq()) .field("oread", &self.oread()) .field("owrite", &self.owrite()) .finish() @@ -3883,7 +4001,7 @@ impl defmt::Format for Serrwarn { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Serrwarn {{ orun: {=bool:?}, urun: {=bool:?}, urunnack: {=bool:?}, term: {=bool:?}, invstart: {=bool:?}, spar: {=bool:?}, hpar: {=bool:?}, hcrc: {=bool:?}, s0s1: {=bool:?}, oread: {=bool:?}, owrite: {=bool:?} }}", + "Serrwarn {{ orun: {=bool:?}, urun: {=bool:?}, urunnack: {=bool:?}, term: {=bool:?}, invstart: {=bool:?}, spar: {=bool:?}, hpar: {=bool:?}, hcrc: {=bool:?}, s0s1: {=bool:?}, hinvreq: {=bool:?}, oread: {=bool:?}, owrite: {=bool:?} }}", self.orun(), self.urun(), self.urunnack(), @@ -3893,11 +4011,118 @@ impl defmt::Format for Serrwarn { self.hpar(), self.hcrc(), self.s0s1(), + self.hinvreq(), self.oread(), self.owrite() ) } } +#[doc = "Target HDR-BT Configuration."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Shdrbtcfg(pub u32); +impl Shdrbtcfg { + #[doc = "CRC32 Select."] + #[must_use] + #[inline(always)] + pub const fn crc32(&self) -> ShdrbtcfgCrc32 { + let val = (self.0 >> 2usize) & 0x01; + ShdrbtcfgCrc32::from_bits(val as u8) + } + #[doc = "CRC32 Select."] + #[inline(always)] + pub const fn set_crc32(&mut self, val: ShdrbtcfgCrc32) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "Maximum Data."] + #[must_use] + #[inline(always)] + pub const fn wdatamax(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "Maximum Data."] + #[inline(always)] + pub const fn set_wdatamax(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + #[doc = "Read Data Length."] + #[must_use] + #[inline(always)] + pub const fn datalen(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Read Data Length."] + #[inline(always)] + pub const fn set_datalen(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Shdrbtcfg { + #[inline(always)] + fn default() -> Shdrbtcfg { + Shdrbtcfg(0) + } +} +impl core::fmt::Debug for Shdrbtcfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Shdrbtcfg") + .field("crc32", &self.crc32()) + .field("wdatamax", &self.wdatamax()) + .field("datalen", &self.datalen()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Shdrbtcfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Shdrbtcfg {{ crc32: {:?}, wdatamax: {=u16:?}, datalen: {=u16:?} }}", + self.crc32(), + self.wdatamax(), + self.datalen() + ) + } +} +#[doc = "Target HDR-Last."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Shdrbtlast(pub u32); +impl Shdrbtlast { + #[doc = "Data Length."] + #[must_use] + #[inline(always)] + pub const fn datalen(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Data Length."] + #[inline(always)] + pub const fn set_datalen(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for Shdrbtlast { + #[inline(always)] + fn default() -> Shdrbtlast { + Shdrbtlast(0) + } +} +impl core::fmt::Debug for Shdrbtlast { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Shdrbtlast") + .field("datalen", &self.datalen()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Shdrbtlast { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Shdrbtlast {{ datalen: {=u16:?} }}", self.datalen()) + } +} #[doc = "Target Module ID."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4637,6 +4862,103 @@ impl defmt::Format for Smapctrl0 { ) } } +#[doc = "Map Feature Control 1."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Smapctrl1(pub u32); +impl Smapctrl1 { + #[doc = "Enable."] + #[must_use] + #[inline(always)] + pub const fn ena(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Enable."] + #[inline(always)] + pub const fn set_ena(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Address."] + #[must_use] + #[inline(always)] + pub const fn addr(&self) -> u8 { + let val = (self.0 >> 1usize) & 0x7f; + val as u8 + } + #[doc = "Address."] + #[inline(always)] + pub const fn set_addr(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 1usize)) | (((val as u32) & 0x7f) << 1usize); + } + #[doc = "MAP Static Address."] + #[must_use] + #[inline(always)] + pub const fn mapsa(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "MAP Static Address."] + #[inline(always)] + pub const fn set_mapsa(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Static Address 10-Bit Extension."] + #[must_use] + #[inline(always)] + pub const fn sa10b(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x07; + val as u8 + } + #[doc = "Static Address 10-Bit Extension."] + #[inline(always)] + pub const fn set_sa10b(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 9usize)) | (((val as u32) & 0x07) << 9usize); + } + #[doc = "Not Acknowledged."] + #[must_use] + #[inline(always)] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Not Acknowledged."] + #[inline(always)] + pub const fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } +} +impl Default for Smapctrl1 { + #[inline(always)] + fn default() -> Smapctrl1 { + Smapctrl1(0) + } +} +impl core::fmt::Debug for Smapctrl1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Smapctrl1") + .field("ena", &self.ena()) + .field("addr", &self.addr()) + .field("mapsa", &self.mapsa()) + .field("sa10b", &self.sa10b()) + .field("nack", &self.nack()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Smapctrl1 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Smapctrl1 {{ ena: {=bool:?}, addr: {=u8:?}, mapsa: {=bool:?}, sa10b: {=u8:?}, nack: {=bool:?} }}", + self.ena(), + self.addr(), + self.mapsa(), + self.sa10b(), + self.nack() + ) + } +} #[doc = "Target Maximum Limits."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -4867,6 +5189,43 @@ impl defmt::Format for Srdatah { ) } } +#[doc = "Target Read Word Data (from Bus)."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Srdataw(pub u32); +impl Srdataw { + #[doc = "Value."] + #[must_use] + #[inline(always)] + pub const fn value(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Value."] + #[inline(always)] + pub const fn set_value(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Srdataw { + #[inline(always)] + fn default() -> Srdataw { + Srdataw(0) + } +} +impl core::fmt::Debug for Srdataw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Srdataw") + .field("value", &self.value()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Srdataw { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Srdataw {{ value: {=u32:?} }}", self.value()) + } +} #[doc = "Target Status."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -5534,43 +5893,6 @@ impl defmt::Format for Swdatah { ) } } -#[doc = "Target Write Data Halfword."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Swdatah1(pub u32); -impl Swdatah1 { - #[doc = "Data."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Data."] - #[inline(always)] - pub const fn set_data(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); - } -} -impl Default for Swdatah1 { - #[inline(always)] - fn default() -> Swdatah1 { - Swdatah1(0) - } -} -impl core::fmt::Debug for Swdatah1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Swdatah1") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Swdatah1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Swdatah1 {{ data: {=u16:?} }}", self.data()) - } -} #[doc = "Target Write Data Halfword End."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -5626,18 +5948,55 @@ impl defmt::Format for Swdatahe { ) } } +#[doc = "Target Write Word Data (to Bus)."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Swdataw(pub u32); +impl Swdataw { + #[doc = "Data."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Swdataw { + #[inline(always)] + fn default() -> Swdataw { + Swdataw(0) + } +} +impl core::fmt::Debug for Swdataw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Swdataw") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Swdataw { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Swdataw {{ data: {=u32:?} }}", self.data()) + } +} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Actstate { #[doc = "NO_LATENCY (normal bus operations)."] - NO_LATENCY = 0x0, + NoLatency = 0x0, #[doc = "LATENCY_1MS (1 ms of latency)."] - LATENCY_1MS = 0x01, + Latency1ms = 0x01, #[doc = "LATENCY_100MS (100 ms of latency)."] - LATENCY_100MS = 0x02, + Latency100ms = 0x02, #[doc = "LATENCY_10S (10 seconds of latency)."] - LATENCY_10S = 0x03, + Latency10s = 0x03, } impl Actstate { #[inline(always)] @@ -5666,15 +6025,15 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cause { #[doc = "No information (this value occurs when not configured to write DA)."] - NONE = 0x0, + None = 0x0, #[doc = "Set using ENTDAA."] - ENTDAA = 0x01, + Entdaa = 0x01, #[doc = "Set using SETDASA, SETAASA, or SETNEWDA."] - SETDASA = 0x02, + Setdasa = 0x02, #[doc = "Cleared using RSTDAA."] - RSTDAA = 0x03, + Rstdaa = 0x03, #[doc = "Auto MAP change happened last."] - AUTOMAP = 0x04, + Automap = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, @@ -5706,9 +6065,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ccchandle { #[doc = "All handling features disabled."] - ALL_DISABLED = 0x0, + AllDisabled = 0x0, #[doc = "The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items."] - BLOCK_HANDLE = 0x01, + BlockHandle = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -5751,9 +6110,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Disto { #[doc = "Enabled."] - ENABLE = 0x0, - #[doc = "Disabled, if configured."] - DISABLE = 0x01, + Enable = 0x0, + #[doc = "Disabled."] + Disable = 0x01, } impl Disto { #[inline(always)] @@ -5782,9 +6141,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dma { #[doc = "Not supported."] - DMANO = 0x0, + Dmano = 0x0, #[doc = "Supported."] - DMAYES = 0x01, + Dmayes = 0x01, } impl Dma { #[inline(always)] @@ -5813,13 +6172,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Evdet { #[doc = "NONE (no event or no pending event)."] - NONE = 0x0, + None = 0x0, #[doc = "NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ))."] - NO_REQUEST = 0x01, + NoRequest = 0x01, #[doc = "NACKed (not acknowledged, request sent and rejected); I3C tries again."] - NACKED = 0x02, + Nacked = 0x02, #[doc = "ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent)."] - ACKED = 0x03, + Acked = 0x03, } impl Evdet { #[inline(always)] @@ -5848,11 +6207,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Extfifo { #[doc = "No external FIFO available."] - NO_EXT_FIFO = 0x0, + NoExtFifo = 0x0, #[doc = "Standard available or free external FIFO."] - STD_EXT_FIFO = 0x01, + StdExtFifo = 0x01, #[doc = "Request track external FIFO."] - REQUEST_EXT_FIFO = 0x02, + RequestExtFifo = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, @@ -5886,13 +6245,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fiforx { #[doc = "Two or three."] - FIFO_2BYTE = 0x0, + Fifo2byte = 0x0, #[doc = "Four."] - FIFO_4BYTE = 0x01, + Fifo4byte = 0x01, #[doc = "Eight."] - FIFO_8BYTE = 0x02, + Fifo8byte = 0x02, #[doc = "16 or larger."] - FIFO_16BYTE = 0x03, + Fifo16byte = 0x03, } impl Fiforx { #[inline(always)] @@ -5921,13 +6280,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fifotx { #[doc = "Two."] - FIFO_2BYTE = 0x0, + Fifo2byte = 0x0, #[doc = "Four."] - FIFO_4BYTE = 0x01, + Fifo4byte = 0x01, #[doc = "Eight."] - FIFO_8BYTE = 0x02, + Fifo8byte = 0x02, #[doc = "16 or larger."] - FIFO_16BYTE = 0x03, + Fifo16byte = 0x03, } impl Fifotx { #[inline(always)] @@ -5956,13 +6315,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Group { #[doc = "v1.1 group addressing not supported."] - NOTSUPPORTED = 0x0, + Notsupported = 0x0, #[doc = "One group supported."] - ONE = 0x01, + One = 0x01, #[doc = "Two groups supported."] - TWO = 0x02, + Two = 0x02, #[doc = "Three groups supported."] - THREE = 0x03, + Three = 0x03, } impl Group { #[inline(always)] @@ -5991,9 +6350,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hdrsupp { #[doc = "No HDR modes supported."] - NO_HDR = 0x0, + NoHdr = 0x0, #[doc = "DDR mode supported."] - DDR = 0x01, + Ddr = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -6024,9 +6383,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hjdis { #[doc = "Enabled."] - MR_ENABLED = 0x0, + MrEnabled = 0x0, #[doc = "Disabled."] - MR_DISABLED = 0x01, + MrDisabled = 0x01, } impl Hjdis { #[inline(always)] @@ -6055,13 +6414,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hkeep { #[doc = "None."] - NONE = 0x0, + None = 0x0, #[doc = "WIRED_IN."] - WIRED_IN = 0x01, + WiredIn = 0x01, #[doc = "PASSIVE_SDA (I2C mode, no clock stretches mode)."] - PASSIVE_SDA = 0x02, + PassiveSda = 0x02, #[doc = "PASSIVE_ON_SDA_SCL."] - PASSIVE_ON_SDA_SCL = 0x03, + PassiveOnSdaScl = 0x03, } impl Hkeep { #[inline(always)] @@ -6090,9 +6449,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I2c { #[doc = "I3C message."] - I3CMESSAGE = 0x0, + I3cmessage = 0x0, #[doc = "I2C message."] - I2CMESSAGE = 0x01, + I2cmessage = 0x01, } impl I2c { #[inline(always)] @@ -6121,13 +6480,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3cCasDel { #[doc = "No delay."] - NO_DELAY = 0x0, + NoDelay = 0x0, #[doc = "Increases SCL clock period by 1/2."] - ONE_HALF_CLK = 0x01, + OneHalfClk = 0x01, #[doc = "Increases SCL clock period by 1."] - ONE_CLK = 0x02, + OneClk = 0x02, #[doc = "Increases SCL clock period by 3/2."] - ONE_AND_ONE_HALF_CLK = 0x03, + OneAndOneHalfClk = 0x03, } impl I3cCasDel { #[inline(always)] @@ -6156,13 +6515,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3cCasrDel { #[doc = "No delay."] - NO_DELAY = 0x0, + NoDelay = 0x0, #[doc = "Increases SCL clock period by 1/2."] - ONE_HALF_CLK = 0x01, + OneHalfClk = 0x01, #[doc = "Increases SCL clock period by 1."] - ONE_CLK = 0x02, + OneClk = 0x02, #[doc = "Increases SCL clock period by 1 1/2."] - ONE_AND_ONE_HALF_CLK = 0x03, + OneAndOneHalfClk = 0x03, } impl I3cCasrDel { #[inline(always)] @@ -6191,9 +6550,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IbiMrHj { #[doc = "Application cannot generate IBI, CR, or HJ."] - ALL_DISABLED = 0x0, + AllDisabled = 0x0, #[doc = "Application can generate an IBI."] - IBI = 0x01, + Ibi = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -6252,9 +6611,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ibidis { #[doc = "Enabled."] - INTERRUPTS_ENABLED = 0x0, + InterruptsEnabled = 0x0, #[doc = "Disabled."] - INTERRUPTS_DISABLED = 0x01, + InterruptsDisabled = 0x01, } impl Ibidis { #[inline(always)] @@ -6283,13 +6642,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ibiresp { #[doc = "ACK (acknowledge)."] - ACK = 0x0, + Ack = 0x0, #[doc = "NACK (reject)."] - NACK = 0x01, + Nack = 0x01, #[doc = "Acknowledge with mandatory byte."] - ACK_WITH_MANDATORY = 0x02, + AckWithMandatory = 0x02, #[doc = "Manual."] - MANUAL = 0x03, + Manual = 0x03, } impl Ibiresp { #[inline(always)] @@ -6318,13 +6677,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ibitype { #[doc = "NONE (no IBI: this status occurs when MSTATUS\\[IBIWON\\] becomes 0)."] - NONE = 0x0, + None = 0x0, #[doc = "IBI."] - IBI = 0x01, + Ibi = 0x01, #[doc = "CR."] - MR = 0x02, + Mr = 0x02, #[doc = "HJ."] - HJ = 0x03, + Hj = 0x03, } impl Ibitype { #[inline(always)] @@ -6353,13 +6712,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Idena { #[doc = "Application."] - APPLICATION = 0x0, + Application = 0x0, #[doc = "Hardware."] - HW = 0x01, + Hw = 0x01, #[doc = "Hardware, but the I3C module instance handles ID 48b."] - HW_BUT = 0x02, + HwBut = 0x02, #[doc = "A part number register (PARTNO)."] - PARTNO = 0x03, + Partno = 0x03, } impl Idena { #[inline(always)] @@ -6388,9 +6747,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Idreg { #[doc = "All ID register features disabled."] - ALL_DISABLED = 0x0, + AllDisabled = 0x0, #[doc = "ID Instance is a register; used if there is no PARTNO register."] - ID_INSTANCE = 0x01, + IdInstance = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -6433,9 +6792,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Int { #[doc = "Not supported."] - INTERRUPTSNO = 0x0, + Interruptsno = 0x0, #[doc = "Supported."] - INTERRUPTSYES = 0x01, + Interruptsyes = 0x01, } impl Int { #[inline(always)] @@ -6464,9 +6823,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Laststatic { #[doc = "I3C dynamic address."] - I3C = 0x0, + I3c = 0x0, #[doc = "I2C static address."] - I2C = 0x01, + I2c = 0x01, } impl Laststatic { #[inline(always)] @@ -6495,9 +6854,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Master { #[doc = "Not supported."] - MASTERNOTSUPPORTED = 0x0, + Masternotsupported = 0x0, #[doc = "Supported."] - MASTERSUPPORTED = 0x01, + Mastersupported = 0x01, } impl Master { #[inline(always)] @@ -6526,9 +6885,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MctrlDir { #[doc = "Write."] - DIRWRITE = 0x0, + Dirwrite = 0x0, #[doc = "Read."] - DIRREAD = 0x01, + Dirread = 0x01, } impl MctrlDir { #[inline(always)] @@ -6557,13 +6916,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdatactrlRxtrig { #[doc = "Trigger when not empty (default)."] - NOT_EMPTY = 0x0, + NotEmpty = 0x0, #[doc = "Trigger when 1/4 full or more."] - QUARTER_OR_MORE = 0x01, + QuarterOrMore = 0x01, #[doc = "Trigger when 1/2 full or more."] - HALF_OR_MORE = 0x02, + HalfOrMore = 0x02, #[doc = "Trigger when 3/4 full or more."] - THREE_QUARTER_OR_MORE = 0x03, + ThreeQuarterOrMore = 0x03, } impl MdatactrlRxtrig { #[inline(always)] @@ -6592,13 +6951,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdatactrlTxtrig { #[doc = "Trigger when empty."] - EMPTY = 0x0, + Empty = 0x0, #[doc = "Trigger when 1/4 full or less."] - QUARTER_OR_LESS = 0x01, + QuarterOrLess = 0x01, #[doc = "Trigger when 1/2 full or less."] - HALF_OR_LESS = 0x02, + HalfOrLess = 0x02, #[doc = "Trigger when 1 less than full or less (default)."] - FULL_OR_LESS = 0x03, + FullOrLess = 0x03, } impl MdatactrlTxtrig { #[inline(always)] @@ -6627,11 +6986,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmactrlDmafb { #[doc = "DMA not used."] - NOT_USED = 0x0, + NotUsed = 0x0, #[doc = "Enable DMA for one frame."] - ENABLE_ONE_FRAME = 0x01, + EnableOneFrame = 0x01, #[doc = "Enable DMA until DMA is turned off."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl MdmactrlDmafb { @@ -6661,11 +7020,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmactrlDmatb { #[doc = "DMA not used."] - NOT_USED = 0x0, + NotUsed = 0x0, #[doc = "Enable DMA for one frame (ended by DMA or terminated)."] - ENABLE_ONE_FRAME = 0x01, + EnableOneFrame = 0x01, #[doc = "Enable DMA until DMA is turned off."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl MdmactrlDmatb { @@ -6695,11 +7054,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MdmactrlDmawidth { #[doc = "Byte."] - BYTE_0 = 0x0, + Byte0 = 0x0, #[doc = "Byte."] - BYTE_1 = 0x01, + Byte1 = 0x01, #[doc = "Halfword (16 bits)."] - HALF_WORD = 0x02, + HalfWord = 0x02, _RESERVED_3 = 0x03, } impl MdmactrlDmawidth { @@ -6727,11 +7086,79 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Mldat { + #[doc = "Single lane for data."] + Single = 0x0, + #[doc = "Dual lane for data."] + Dual = 0x01, + _RESERVED_2 = 0x02, + #[doc = "Quad-lane data."] + Quad = 0x03, +} +impl Mldat { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mldat { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mldat { + #[inline(always)] + fn from(val: u8) -> Mldat { + Mldat::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mldat) -> u8 { + Mldat::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Mlhdr { + #[doc = "Single lane for header."] + Single = 0x0, + #[doc = "Dual lane for header."] + Dual = 0x01, + _RESERVED_2 = 0x02, + #[doc = "Quad-lane header."] + Quad = 0x03, +} +impl Mlhdr { + #[inline(always)] + pub const fn from_bits(val: u8) -> Mlhdr { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Mlhdr { + #[inline(always)] + fn from(val: u8) -> Mlhdr { + Mlhdr::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Mlhdr) -> u8 { + Mlhdr::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mrdis { #[doc = "Enabled."] - MR_ENABLED = 0x0, + MrEnabled = 0x0, #[doc = "Disabled."] - MR_DISABLED = 0x01, + MrDisabled = 0x01, } impl Mrdis { #[inline(always)] @@ -6760,13 +7187,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mstena { #[doc = "CONTROLLER_OFF."] - MASTER_OFF = 0x0, + MasterOff = 0x0, #[doc = "CONTROLLER_ON."] - MASTER_ON = 0x01, + MasterOn = 0x01, #[doc = "CONTROLLER_CAPABLE."] - MASTER_CAPABLE = 0x02, + MasterCapable = 0x02, #[doc = "I2C_CONTROLLER_MODE."] - I2C_MASTER_MODE = 0x03, + I2cMasterMode = 0x03, } impl Mstena { #[inline(always)] @@ -6795,9 +7222,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MwmsgSdrControlDir { #[doc = "Write."] - WRITE = 0x0, + Write = 0x0, #[doc = "Read."] - READ = 0x01, + Read = 0x01, } impl MwmsgSdrControlDir { #[inline(always)] @@ -6826,9 +7253,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Nobyte { #[doc = "With mandatory IBI byte."] - IBIBYTE = 0x0, + Ibibyte = 0x0, #[doc = "Without mandatory IBI byte."] - NO_IBIBYTE = 0x01, + NoIbibyte = 0x01, } impl Nobyte { #[inline(always)] @@ -6857,20 +7284,20 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Request { #[doc = "NONE."] - NONE = 0x0, + None = 0x0, #[doc = "EMITSTARTADDR."] - EMITSTARTADDR = 0x01, + Emitstartaddr = 0x01, #[doc = "EMITSTOP."] - EMITSTOP = 0x02, + Emitstop = 0x02, #[doc = "IBIACKNACK."] - IBIACKNACK = 0x03, + Ibiacknack = 0x03, #[doc = "PROCESSDAA."] - PROCESSDAA = 0x04, + Processdaa = 0x04, _RESERVED_5 = 0x05, #[doc = "Force Exit and Target Reset."] - FORCEEXIT = 0x06, + Forceexit = 0x06, #[doc = "AUTOIBI."] - AUTOIBI = 0x07, + Autoibi = 0x07, } impl Request { #[inline(always)] @@ -6899,13 +7326,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Saddr { #[doc = "No static address."] - NO_STATIC = 0x0, + NoStatic = 0x0, #[doc = "Static address is fixed in hardware."] - STATIC = 0x01, + Static = 0x01, #[doc = "Hardware controls the static address dynamically (for example, from the pin strap)."] - HW_CONTROL = 0x02, + HwControl = 0x02, #[doc = "SCONFIG register supplies the static address."] - CONFIG = 0x03, + Config = 0x03, } impl Saddr { #[inline(always)] @@ -6934,9 +7361,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ScapabilitiesTimectrl { #[doc = "No time control supported."] - NO_TIME_CONTROL_TYPE = 0x0, + NoTimeControlType = 0x0, #[doc = "At least one time-control type supported."] - ATLEAST1_TIME_CONTROL = 0x01, + Atleast1TimeControl = 0x01, } impl ScapabilitiesTimectrl { #[inline(always)] @@ -6965,13 +7392,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SctrlEvent { #[doc = "NORMAL_MODE."] - NORMAL_MODE = 0x0, + NormalMode = 0x0, #[doc = "IBI."] - IBI = 0x01, + Ibi = 0x01, #[doc = "CONTROLLER_REQUEST."] - MASTER_REQUEST = 0x02, + MasterRequest = 0x02, #[doc = "HOT_JOIN_REQUEST."] - HOT_JOIN_REQUEST = 0x03, + HotJoinRequest = 0x03, } impl SctrlEvent { #[inline(always)] @@ -7000,9 +7427,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdatactrlRxempty { #[doc = "Not empty."] - RXISNOTEMPTY = 0x0, + Rxisnotempty = 0x0, #[doc = "Empty."] - RXISEMPTY = 0x01, + Rxisempty = 0x01, } impl SdatactrlRxempty { #[inline(always)] @@ -7031,13 +7458,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdatactrlRxtrig { #[doc = "Trigger when not empty (default)."] - TRIGGRNOTEMPTY = 0x0, + Triggrnotempty = 0x0, #[doc = "Trigger when 1/4 or more full."] - TRIGGRONEFOURTH = 0x01, + Triggronefourth = 0x01, #[doc = "Trigger when 1/2 or more full."] - TRIGGRONEHALF = 0x02, + Triggronehalf = 0x02, #[doc = "Trigger when 3/4 or more full."] - TRIGGRTHREEFOURTHS = 0x03, + Triggrthreefourths = 0x03, } impl SdatactrlRxtrig { #[inline(always)] @@ -7066,9 +7493,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdatactrlTxfull { #[doc = "Not full."] - TXISNOTFULL = 0x0, + Txisnotfull = 0x0, #[doc = "Full."] - TXISFULL = 0x01, + Txisfull = 0x01, } impl SdatactrlTxfull { #[inline(always)] @@ -7097,13 +7524,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdatactrlTxtrig { #[doc = "Trigger when empty."] - TRIGGREMPTY = 0x0, + Triggrempty = 0x0, #[doc = "Trigger when 1/4 full or less."] - TRIGGRONEFOURTH = 0x01, + Triggronefourth = 0x01, #[doc = "Trigger when 1/2 full or less."] - TRIGGRONEHALF = 0x02, + Triggronehalf = 0x02, #[doc = "Default (trigger when 1 less than full or less)."] - TRIGGRONELESS = 0x03, + Triggroneless = 0x03, } impl SdatactrlTxtrig { #[inline(always)] @@ -7132,11 +7559,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdmactrlDmafb { #[doc = "DMA not used."] - NOT_USED = 0x0, + NotUsed = 0x0, #[doc = "DMA enabled for one frame."] - ENABLE_ONE_FRAME = 0x01, + EnableOneFrame = 0x01, #[doc = "DMA enabled until turned off."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl SdmactrlDmafb { @@ -7166,11 +7593,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdmactrlDmatb { #[doc = "DMA not used."] - NOT_USED = 0x0, + NotUsed = 0x0, #[doc = "DMA enabled for one frame."] - ENABLE_ONE_FRAME = 0x01, + EnableOneFrame = 0x01, #[doc = "DMA enabled until turned off."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl SdmactrlDmatb { @@ -7200,11 +7627,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SdmactrlDmawidth { #[doc = "Byte."] - BYTE_0 = 0x0, + Byte0 = 0x0, #[doc = "Byte."] - BYTE_1 = 0x01, + Byte1 = 0x01, #[doc = "Halfword (16 bits) (this value ensures that two bytes are available in the FIFO)."] - HALF_WORD = 0x02, + HalfWord = 0x02, _RESERVED_3 = 0x03, } impl SdmactrlDmawidth { @@ -7232,15 +7659,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum SdynaddrDavalid { - #[doc = "DANOTASSIGNED: a dynamic address is not assigned."] - DANOTASSIGNED = 0x0, - #[doc = "DAASSIGNED: a dynamic address is assigned."] - DAASSIGNED = 0x01, +pub enum ShdrbtcfgCrc32 { + #[doc = "CRC16."] + UseCrc16 = 0x0, + #[doc = "CRC32."] + UseCrc32 = 0x01, } -impl SdynaddrDavalid { +impl ShdrbtcfgCrc32 { #[inline(always)] - pub const fn from_bits(val: u8) -> SdynaddrDavalid { + pub const fn from_bits(val: u8) -> ShdrbtcfgCrc32 { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -7248,16 +7675,16 @@ impl SdynaddrDavalid { unsafe { core::mem::transmute(self) } } } -impl From for SdynaddrDavalid { +impl From for ShdrbtcfgCrc32 { #[inline(always)] - fn from(val: u8) -> SdynaddrDavalid { - SdynaddrDavalid::from_bits(val) + fn from(val: u8) -> ShdrbtcfgCrc32 { + ShdrbtcfgCrc32::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: SdynaddrDavalid) -> u8 { - SdynaddrDavalid::to_bits(val) + fn from(val: ShdrbtcfgCrc32) -> u8 { + ShdrbtcfgCrc32::to_bits(val) } } #[repr(u8)] @@ -7265,9 +7692,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SstatusStart { #[doc = "Not detected."] - START_NOT_DETECTED = 0x0, + StartNotDetected = 0x0, #[doc = "Detected."] - START_DETECTED = 0x01, + StartDetected = 0x01, } impl SstatusStart { #[inline(always)] @@ -7296,13 +7723,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SstatusTimectrl { #[doc = "NO_TIME_CONTROL (no time control is enabled)."] - NO_TIME_CONTROL = 0x0, + NoTimeControl = 0x0, #[doc = "SYNC_MODE (Synchronous mode is enabled)."] - SYNC = 0x01, + Sync = 0x01, #[doc = "ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled)."] - ASYNC_MODE = 0x02, + AsyncMode = 0x02, #[doc = "BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled)."] - BOTHSYNCASYNC = 0x03, + Bothsyncasync = 0x03, } impl SstatusTimectrl { #[inline(always)] @@ -7331,9 +7758,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SstatusTxnotfull { #[doc = "Transmit buffer full."] - FULL = 0x0, + Full = 0x0, #[doc = "Transmit buffer not full."] - NOT_FULL = 0x01, + NotFull = 0x01, } impl SstatusTxnotfull { #[inline(always)] @@ -7362,21 +7789,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum State { #[doc = "IDLE (bus has stopped)."] - IDLE = 0x0, + Idle = 0x0, #[doc = "SLVREQ (target request)."] - SLVREQ = 0x01, + Slvreq = 0x01, #[doc = "MSGSDR."] - MSGSDR = 0x02, + Msgsdr = 0x02, #[doc = "NORMACT."] - NORMACT = 0x03, + Normact = 0x03, #[doc = "MSGDDR."] - DDR = 0x04, + Ddr = 0x04, #[doc = "DAA."] - DAA = 0x05, + Daa = 0x05, #[doc = "IBIACK."] - IBIACK = 0x06, + Ibiack = 0x06, #[doc = "IBIRCV."] - IBIRCV = 0x07, + Ibircv = 0x07, } impl State { #[inline(always)] @@ -7405,9 +7832,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Stccch { #[doc = "No CCC message handled."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Handled automatically."] - BUSY = 0x01, + Busy = 0x01, } impl Stccch { #[inline(always)] @@ -7436,9 +7863,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Stmsg { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl Stmsg { #[inline(always)] @@ -7467,9 +7894,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Stnotstop { #[doc = "In STOP condition."] - STOPPED = 0x0, + Stopped = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl Stnotstop { #[inline(always)] @@ -7498,9 +7925,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Streqrd { #[doc = "Not an SDR read."] - IDLE = 0x0, + Idle = 0x0, #[doc = "SDR read from this target or an IBI is being pushed out."] - BUSY = 0x01, + Busy = 0x01, } impl Streqrd { #[inline(always)] @@ -7529,9 +7956,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Streqwr { #[doc = "Not an SDR write."] - IDLE = 0x0, + Idle = 0x0, #[doc = "SDR write data from the controller, but not in ENTDAA mode."] - BUSY = 0x01, + Busy = 0x01, } impl Streqwr { #[inline(always)] @@ -7560,11 +7987,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Type { #[doc = "I3C."] - I3C = 0x0, + I3c = 0x0, #[doc = "I2C."] - I2C = 0x01, + I2c = 0x01, #[doc = "DDR."] - DDR = 0x02, + Ddr = 0x02, _RESERVED_3 = 0x03, } impl Type { diff --git a/nxp-pac/src/meta_peripherals/mcxa/INPUTMUX.rs b/nxp-pac/src/meta_peripherals/mcxa/INPUTMUX.rs index 23942f1..87c9f49 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/INPUTMUX.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/INPUTMUX.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "INPUTMUX."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Inputmux { @@ -76,6 +77,26 @@ impl Inputmux { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa0usize + n * 4usize) as _) } } + #[doc = "LPSPI2 trigger input connections."] + #[inline(always)] + pub const fn lpspi2_trig(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc0usize) as _) } + } + #[doc = "LPSPI3 trigger input connections."] + #[inline(always)] + pub const fn lpspi3_trig(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe0usize) as _) } + } + #[doc = "LPSPI4 trigger input connections."] + #[inline(always)] + pub const fn lpspi4_trig(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0100usize) as _) } + } + #[doc = "LPSPI5 trigger input connections."] + #[inline(always)] + pub const fn lpspi5_trig(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0120usize) as _) } + } #[doc = "Selection for frequency measurement reference clock."] #[inline(always)] pub const fn freqmeas_ref( @@ -122,17 +143,6 @@ impl Inputmux { pub const fn timer4trig(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01d0usize) as _) } } - #[doc = "AOI1 trigger input connections 0."] - #[inline(always)] - pub const fn aoi1_input( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 16usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0200usize + n * 4usize) as _) - } - } #[doc = "CMP0 input connections."] #[inline(always)] pub const fn cmp0_trig(self) -> crate::pac::common::Reg { @@ -151,17 +161,6 @@ impl Inputmux { } #[doc = "ADC Trigger input connections."] #[inline(always)] - pub const fn adc2_trig( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 4usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x02a0usize + n * 4usize) as _) - } - } - #[doc = "ADC Trigger input connections."] - #[inline(always)] pub const fn adc1_trig( self, n: usize, @@ -171,293 +170,45 @@ impl Inputmux { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x02c0usize + n * 4usize) as _) } } - #[doc = "ADC Trigger input connections."] - #[inline(always)] - pub const fn adc3_trig( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 4usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x02e0usize + n * 4usize) as _) - } - } - #[doc = "DAC0 Trigger input connections."] + #[doc = "DAC0 trigger."] #[inline(always)] pub const fn dac0_trig(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0300usize) as _) } } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_trig(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0360usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_home(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0364usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_index(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0368usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_phaseb(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x036cusize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_phasea(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0370usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_icap1(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0374usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_icap2(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0378usize) as _) } - } - #[doc = "QDC0 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc0_icap3(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x037cusize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_trig(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0380usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_home(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0384usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_index(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0388usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_phaseb(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x038cusize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_phasea(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0390usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_icap1(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0394usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_icap2(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0398usize) as _) } - } - #[doc = "QDC1 Trigger Input Connections."] - #[inline(always)] - pub const fn qdc1_icap3(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x039cusize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm0_exta0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03a0usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm0_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03a4usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm1_exta( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03a8usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm1_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03acusize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm2_exta( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03b0usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm2_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03b4usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm3_exta0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03b8usize) as _) } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_sm3_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03bcusize) as _) } - } - #[doc = "PWM0 Fault Input Trigger Connections."] - #[inline(always)] - pub const fn flex_pwm0_fault( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 4usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03c0usize + n * 4usize) as _) - } - } - #[doc = "PWM0 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm0_force(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03d0usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm0_exta0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03e0usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm0_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03e4usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm1_exta( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03e8usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm1_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03ecusize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm2_exta( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03f0usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm2_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03f4usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm3_exta0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03f8usize) as _) } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_sm3_extsync( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03fcusize) as _) } - } - #[doc = "PWM1 Fault Input Trigger Connections."] - #[inline(always)] - pub const fn flex_pwm1_fault( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 4usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0400usize + n * 4usize) as _) - } - } - #[doc = "PWM1 input trigger connections."] - #[inline(always)] - pub const fn flex_pwm1_force(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0410usize) as _) } - } - #[doc = "PWM0 external clock trigger."] - #[inline(always)] - pub const fn pwm0_ext_clk(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0420usize) as _) } - } - #[doc = "PWM1 external clock trigger."] + #[doc = "DAC1 trigger."] #[inline(always)] - pub const fn pwm1_ext_clk(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0424usize) as _) } + pub const fn dac1_trig(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0320usize) as _) } } #[doc = "AOI0 trigger input connections 0."] #[inline(always)] pub const fn aoi0_input( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 16usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0440usize + n * 4usize) as _) } } - #[doc = "USB-FS trigger input connections."] + #[doc = "TSI0 trigger input connections."] #[inline(always)] - pub const fn usbfs_trig(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0480usize) as _) } + pub const fn tsi0_trig_input( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04a0usize) as _) } } #[doc = "EXT trigger connections."] #[inline(always)] - pub const fn ext_trig( + pub const fn trig_out( self, n: usize, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { assert!(n < 8usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04c0usize + n * 4usize) as _) } } - #[doc = "CMP1 input connections."] - #[inline(always)] - pub const fn cmp1_trig(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04e0usize) as _) } - } - #[doc = "CMP2 input connections."] - #[inline(always)] - pub const fn cmp2_trig(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0500usize) as _) } - } #[doc = "LPI2C2 trigger input connections."] #[inline(always)] pub const fn lpi2c2_trig(self) -> crate::pac::common::Reg { @@ -507,31 +258,6 @@ impl Inputmux { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x06e0usize + n * 4usize) as _) } } - #[doc = "Trigger filter prescaller."] - #[inline(always)] - pub const fn trigfil_prsc( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0a00usize) as _) } - } - #[doc = "Trigger filter stat."] - #[inline(always)] - pub const fn trigfil_stat0( - self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0a04usize) as _) } - } - #[doc = "TRIGFIL control."] - #[inline(always)] - pub const fn trigfil( - self, - n: usize, - ) -> crate::pac::common::Reg { - assert!(n < 12usize); - unsafe { - crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0a10usize + n * 4usize) as _) - } - } } #[doc = "ADC Trigger input connections."] #[repr(transparent)] @@ -573,8 +299,8 @@ impl defmt::Format for AdcTrig { #[doc = "AOI0 trigger input connections 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct AoiInput(pub u32); -impl AoiInput { +pub struct Aoi0Input(pub u32); +impl Aoi0Input { #[doc = "AOI0 trigger input connections."] #[must_use] #[inline(always)] @@ -588,23 +314,23 @@ impl AoiInput { self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); } } -impl Default for AoiInput { +impl Default for Aoi0Input { #[inline(always)] - fn default() -> AoiInput { - AoiInput(0) + fn default() -> Aoi0Input { + Aoi0Input(0) } } -impl core::fmt::Debug for AoiInput { +impl core::fmt::Debug for Aoi0Input { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AoiInput") + f.debug_struct("Aoi0Input") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for AoiInput { +impl defmt::Format for Aoi0Input { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "AoiInput {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "Aoi0Input {{ inp: {:?} }}", self.inp()) } } #[doc = "CMP0 input connections."] @@ -653,13 +379,13 @@ impl Ctimer0cap { #[must_use] #[inline(always)] pub const fn inp(&self) -> Ctimer0capInp { - let val = (self.0 >> 0usize) & 0x7f; + let val = (self.0 >> 0usize) & 0xff; Ctimer0capInp::from_bits(val as u8) } #[doc = "Input number for CTIMER0."] #[inline(always)] pub const fn set_inp(&mut self, val: Ctimer0capInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } impl Default for Ctimer0cap { @@ -690,13 +416,13 @@ impl Ctimer1cap { #[must_use] #[inline(always)] pub const fn inp(&self) -> Ctimer1capInp { - let val = (self.0 >> 0usize) & 0x7f; + let val = (self.0 >> 0usize) & 0xff; Ctimer1capInp::from_bits(val as u8) } #[doc = "Input number for CTIMER1."] #[inline(always)] pub const fn set_inp(&mut self, val: Ctimer1capInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } impl Default for Ctimer1cap { @@ -727,13 +453,13 @@ impl Ctimer2cap { #[must_use] #[inline(always)] pub const fn inp(&self) -> Ctimer2capInp { - let val = (self.0 >> 0usize) & 0x7f; + let val = (self.0 >> 0usize) & 0xff; Ctimer2capInp::from_bits(val as u8) } #[doc = "Input number for CTIMER2."] #[inline(always)] pub const fn set_inp(&mut self, val: Ctimer2capInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } impl Default for Ctimer2cap { @@ -764,13 +490,13 @@ impl Ctimer3cap { #[must_use] #[inline(always)] pub const fn inp(&self) -> Ctimer3capInp { - let val = (self.0 >> 0usize) & 0x7f; + let val = (self.0 >> 0usize) & 0xff; Ctimer3capInp::from_bits(val as u8) } #[doc = "Input number for CTIMER3."] #[inline(always)] pub const fn set_inp(&mut self, val: Ctimer3capInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } impl Default for Ctimer3cap { @@ -801,13 +527,13 @@ impl Ctimer4cap { #[must_use] #[inline(always)] pub const fn inp(&self) -> Ctimer4capInp { - let val = (self.0 >> 0usize) & 0x7f; + let val = (self.0 >> 0usize) & 0xff; Ctimer4capInp::from_bits(val as u8) } #[doc = "Input number for CTIMER4."] #[inline(always)] pub const fn set_inp(&mut self, val: Ctimer4capInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } impl Default for Ctimer4cap { @@ -829,22 +555,22 @@ impl defmt::Format for Ctimer4cap { defmt::write!(f, "Ctimer4cap {{ inp: {:?} }}", self.inp()) } } -#[doc = "DAC0 Trigger input connections."] +#[doc = "DAC0 trigger."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct DacTrig(pub u32); impl DacTrig { - #[doc = "DAC0 trigger input."] + #[doc = "This register selects the DAC0 trigger inputs."] #[must_use] #[inline(always)] pub const fn trigin(&self) -> DacTrigTrigin { - let val = (self.0 >> 0usize) & 0x3f; + let val = (self.0 >> 0usize) & 0x7f; DacTrigTrigin::from_bits(val as u8) } - #[doc = "DAC0 trigger input."] + #[doc = "This register selects the DAC0 trigger inputs."] #[inline(always)] pub const fn set_trigin(&mut self, val: DacTrigTrigin) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val.to_bits() as u32) & 0x3f) << 0usize); + self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); } } impl Default for DacTrig { @@ -866,78 +592,6 @@ impl defmt::Format for DacTrig { defmt::write!(f, "DacTrig {{ trigin: {:?} }}", self.trigin()) } } -#[doc = "EXT trigger connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct ExtTrig(pub u32); -impl ExtTrig { - #[doc = "EXT trigger input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> ExtTrigInp { - let val = (self.0 >> 0usize) & 0x1f; - ExtTrigInp::from_bits(val as u8) - } - #[doc = "EXT trigger input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: ExtTrigInp) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val.to_bits() as u32) & 0x1f) << 0usize); - } -} -impl Default for ExtTrig { - #[inline(always)] - fn default() -> ExtTrig { - ExtTrig(0) - } -} -impl core::fmt::Debug for ExtTrig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ExtTrig").field("inp", &self.inp()).finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for ExtTrig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "ExtTrig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "PWM0 Fault Input Trigger Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexPwm(pub u32); -impl FlexPwm { - #[doc = "FAULT input connections for PWM0."] - #[must_use] - #[inline(always)] - pub const fn trigin(&self) -> FlexPwmTrigin { - let val = (self.0 >> 0usize) & 0x3f; - FlexPwmTrigin::from_bits(val as u8) - } - #[doc = "FAULT input connections for PWM0."] - #[inline(always)] - pub const fn set_trigin(&mut self, val: FlexPwmTrigin) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val.to_bits() as u32) & 0x3f) << 0usize); - } -} -impl Default for FlexPwm { - #[inline(always)] - fn default() -> FlexPwm { - FlexPwm(0) - } -} -impl core::fmt::Debug for FlexPwm { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexPwm") - .field("trigin", &self.trigin()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexPwm { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexPwm {{ trigin: {:?} }}", self.trigin()) - } -} #[doc = "FlexIO Trigger Input Connections."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1158,4651 +812,543 @@ impl defmt::Format for Lpuart { defmt::write!(f, "Lpuart {{ inp: {:?} }}", self.inp()) } } -#[doc = "PWM0 external clock trigger."] +#[doc = "SmartDMA Trigger Input Connections."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwm0extClk(pub u32); -impl Pwm0extClk { - #[doc = "Trigger input connections for PWM."] +pub struct SmartDmaTrig(pub u32); +impl SmartDmaTrig { + #[doc = "Input number for FlexIO0."] #[must_use] #[inline(always)] - pub const fn trigin(&self) -> Pwm0extClkTrigin { - let val = (self.0 >> 0usize) & 0x0f; - Pwm0extClkTrigin::from_bits(val as u8) + pub const fn inp(&self) -> SmartDmaTrigInp { + let val = (self.0 >> 0usize) & 0x7f; + SmartDmaTrigInp::from_bits(val as u8) } - #[doc = "Trigger input connections for PWM."] + #[doc = "Input number for FlexIO0."] #[inline(always)] - pub const fn set_trigin(&mut self, val: Pwm0extClkTrigin) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + pub const fn set_inp(&mut self, val: SmartDmaTrigInp) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); } } -impl Default for Pwm0extClk { +impl Default for SmartDmaTrig { #[inline(always)] - fn default() -> Pwm0extClk { - Pwm0extClk(0) + fn default() -> SmartDmaTrig { + SmartDmaTrig(0) } } -impl core::fmt::Debug for Pwm0extClk { +impl core::fmt::Debug for SmartDmaTrig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Pwm0extClk") - .field("trigin", &self.trigin()) + f.debug_struct("SmartDmaTrig") + .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Pwm0extClk { +impl defmt::Format for SmartDmaTrig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Pwm0extClk {{ trigin: {:?} }}", self.trigin()) + defmt::write!(f, "SmartDmaTrig {{ inp: {:?} }}", self.inp()) } } -#[doc = "PWM1 external clock trigger."] +#[doc = "Trigger register for TIMER0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Pwm1extClk(pub u32); -impl Pwm1extClk { - #[doc = "Trigger input connections for PWM."] +pub struct Timer0trig(pub u32); +impl Timer0trig { + #[doc = "Input number for CTIMER0."] #[must_use] #[inline(always)] - pub const fn trigin(&self) -> Pwm1extClkTrigin { - let val = (self.0 >> 0usize) & 0x0f; - Pwm1extClkTrigin::from_bits(val as u8) + pub const fn inp(&self) -> Timer0trigInp { + let val = (self.0 >> 0usize) & 0xff; + Timer0trigInp::from_bits(val as u8) } - #[doc = "Trigger input connections for PWM."] + #[doc = "Input number for CTIMER0."] #[inline(always)] - pub const fn set_trigin(&mut self, val: Pwm1extClkTrigin) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); + pub const fn set_inp(&mut self, val: Timer0trigInp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } -impl Default for Pwm1extClk { +impl Default for Timer0trig { #[inline(always)] - fn default() -> Pwm1extClk { - Pwm1extClk(0) + fn default() -> Timer0trig { + Timer0trig(0) } } -impl core::fmt::Debug for Pwm1extClk { +impl core::fmt::Debug for Timer0trig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Pwm1extClk") - .field("trigin", &self.trigin()) + f.debug_struct("Timer0trig") + .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Pwm1extClk { +impl defmt::Format for Timer0trig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Pwm1extClk {{ trigin: {:?} }}", self.trigin()) + defmt::write!(f, "Timer0trig {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC0 Trigger Input Connections."] +#[doc = "Trigger register for TIMER1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0home(pub u32); -impl Qdc0home { - #[doc = "QDC0 input connections."] +pub struct Timer1trig(pub u32); +impl Timer1trig { + #[doc = "Input number for CTIMER1."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> QdcHomeInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcHomeInp::from_bits(val as u8) - } - #[doc = "QDC0 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: QdcHomeInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc0home { - #[inline(always)] - fn default() -> Qdc0home { - Qdc0home(0) - } -} -impl core::fmt::Debug for Qdc0home { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0home") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc0home { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0home {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC0 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0icap1(pub u32); -impl Qdc0icap1 { - #[doc = "QDC0 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) - } - #[doc = "QDC0 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc0icap1 { - #[inline(always)] - fn default() -> Qdc0icap1 { - Qdc0icap1(0) - } -} -impl core::fmt::Debug for Qdc0icap1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0icap1") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc0icap1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0icap1 {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC0 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0icap2(pub u32); -impl Qdc0icap2 { - #[doc = "QDC0 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) - } - #[doc = "QDC0 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc0icap2 { - #[inline(always)] - fn default() -> Qdc0icap2 { - Qdc0icap2(0) - } -} -impl core::fmt::Debug for Qdc0icap2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0icap2") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc0icap2 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0icap2 {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC0 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0icap3(pub u32); -impl Qdc0icap3 { - #[doc = "QDC0 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) + pub const fn inp(&self) -> Timer1trigInp { + let val = (self.0 >> 0usize) & 0xff; + Timer1trigInp::from_bits(val as u8) } - #[doc = "QDC0 input connections."] + #[doc = "Input number for CTIMER1."] #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn set_inp(&mut self, val: Timer1trigInp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } -impl Default for Qdc0icap3 { +impl Default for Timer1trig { #[inline(always)] - fn default() -> Qdc0icap3 { - Qdc0icap3(0) + fn default() -> Timer1trig { + Timer1trig(0) } } -impl core::fmt::Debug for Qdc0icap3 { +impl core::fmt::Debug for Timer1trig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0icap3") + f.debug_struct("Timer1trig") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc0icap3 { +impl defmt::Format for Timer1trig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0icap3 {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "Timer1trig {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC0 Trigger Input Connections."] +#[doc = "Trigger register for TIMER2 inputs."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0index(pub u32); -impl Qdc0index { - #[doc = "QDC0 input connections."] +pub struct Timer2trig(pub u32); +impl Timer2trig { + #[doc = "Input number for CTIMER2."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> QdcIndexInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIndexInp::from_bits(val as u8) + pub const fn inp(&self) -> Timer2trigInp { + let val = (self.0 >> 0usize) & 0xff; + Timer2trigInp::from_bits(val as u8) } - #[doc = "QDC0 input connections."] + #[doc = "Input number for CTIMER2."] #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIndexInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn set_inp(&mut self, val: Timer2trigInp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } -impl Default for Qdc0index { +impl Default for Timer2trig { #[inline(always)] - fn default() -> Qdc0index { - Qdc0index(0) + fn default() -> Timer2trig { + Timer2trig(0) } } -impl core::fmt::Debug for Qdc0index { +impl core::fmt::Debug for Timer2trig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0index") + f.debug_struct("Timer2trig") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc0index { +impl defmt::Format for Timer2trig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0index {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "Timer2trig {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC0 Trigger Input Connections."] +#[doc = "Trigger register for TIMER3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0phasea(pub u32); -impl Qdc0phasea { - #[doc = "QDC0 input connections."] +pub struct Timer3trig(pub u32); +impl Timer3trig { + #[doc = "Input number for CTIMER3."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> Qdc0phaseaInp { - let val = (self.0 >> 0usize) & 0x7f; - Qdc0phaseaInp::from_bits(val as u8) + pub const fn inp(&self) -> Timer3trigInp { + let val = (self.0 >> 0usize) & 0xff; + Timer3trigInp::from_bits(val as u8) } - #[doc = "QDC0 input connections."] + #[doc = "Input number for CTIMER3."] #[inline(always)] - pub const fn set_inp(&mut self, val: Qdc0phaseaInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn set_inp(&mut self, val: Timer3trigInp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } -impl Default for Qdc0phasea { +impl Default for Timer3trig { #[inline(always)] - fn default() -> Qdc0phasea { - Qdc0phasea(0) + fn default() -> Timer3trig { + Timer3trig(0) } } -impl core::fmt::Debug for Qdc0phasea { +impl core::fmt::Debug for Timer3trig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0phasea") + f.debug_struct("Timer3trig") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc0phasea { +impl defmt::Format for Timer3trig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0phasea {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "Timer3trig {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC0 Trigger Input Connections."] +#[doc = "Trigger register for TIMER4."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc0phaseb(pub u32); -impl Qdc0phaseb { - #[doc = "QDC0 input connections."] +pub struct Timer4trig(pub u32); +impl Timer4trig { + #[doc = "Input number for CTIMER4."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> Qdc0phasebInp { - let val = (self.0 >> 0usize) & 0x7f; - Qdc0phasebInp::from_bits(val as u8) + pub const fn inp(&self) -> Timer4trigInp { + let val = (self.0 >> 0usize) & 0xff; + Timer4trigInp::from_bits(val as u8) } - #[doc = "QDC0 input connections."] + #[doc = "Input number for CTIMER4."] #[inline(always)] - pub const fn set_inp(&mut self, val: Qdc0phasebInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn set_inp(&mut self, val: Timer4trigInp) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); } } -impl Default for Qdc0phaseb { +impl Default for Timer4trig { #[inline(always)] - fn default() -> Qdc0phaseb { - Qdc0phaseb(0) + fn default() -> Timer4trig { + Timer4trig(0) } } -impl core::fmt::Debug for Qdc0phaseb { +impl core::fmt::Debug for Timer4trig { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc0phaseb") + f.debug_struct("Timer4trig") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc0phaseb { +impl defmt::Format for Timer4trig { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc0phaseb {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "Timer4trig {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC1 Trigger Input Connections."] +#[doc = "EXT trigger connections."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1home(pub u32); -impl Qdc1home { - #[doc = "QDC1 input connections."] +pub struct TrigOut(pub u32); +impl TrigOut { + #[doc = "EXT trigger input connections."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> QdcHomeInp { + pub const fn inp(&self) -> TrigOutInp { let val = (self.0 >> 0usize) & 0x7f; - QdcHomeInp::from_bits(val as u8) + TrigOutInp::from_bits(val as u8) } - #[doc = "QDC1 input connections."] + #[doc = "EXT trigger input connections."] #[inline(always)] - pub const fn set_inp(&mut self, val: QdcHomeInp) { + pub const fn set_inp(&mut self, val: TrigOutInp) { self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); } } -impl Default for Qdc1home { +impl Default for TrigOut { #[inline(always)] - fn default() -> Qdc1home { - Qdc1home(0) + fn default() -> TrigOut { + TrigOut(0) } } -impl core::fmt::Debug for Qdc1home { +impl core::fmt::Debug for TrigOut { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1home") - .field("inp", &self.inp()) - .finish() + f.debug_struct("TrigOut").field("inp", &self.inp()).finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc1home { +impl defmt::Format for TrigOut { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1home {{ inp: {:?} }}", self.inp()) + defmt::write!(f, "TrigOut {{ inp: {:?} }}", self.inp()) } } -#[doc = "QDC1 Trigger Input Connections."] +#[doc = "TSI0 trigger input connections."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1icap1(pub u32); -impl Qdc1icap1 { - #[doc = "QDC1 input connections."] +pub struct Tsi0TrigInput(pub u32); +impl Tsi0TrigInput { + #[doc = "TSI0 trigger input connections."] #[must_use] #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) + pub const fn inp(&self) -> Tsi0TrigInputInp { + let val = (self.0 >> 0usize) & 0x3f; + Tsi0TrigInputInp::from_bits(val as u8) } - #[doc = "QDC1 input connections."] + #[doc = "TSI0 trigger input connections."] #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn set_inp(&mut self, val: Tsi0TrigInputInp) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val.to_bits() as u32) & 0x3f) << 0usize); } } -impl Default for Qdc1icap1 { +impl Default for Tsi0TrigInput { #[inline(always)] - fn default() -> Qdc1icap1 { - Qdc1icap1(0) + fn default() -> Tsi0TrigInput { + Tsi0TrigInput(0) } } -impl core::fmt::Debug for Qdc1icap1 { +impl core::fmt::Debug for Tsi0TrigInput { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1icap1") + f.debug_struct("Tsi0TrigInput") .field("inp", &self.inp()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Qdc1icap1 { +impl defmt::Format for Tsi0TrigInput { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1icap1 {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC1 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1icap2(pub u32); -impl Qdc1icap2 { - #[doc = "QDC1 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) - } - #[doc = "QDC1 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc1icap2 { - #[inline(always)] - fn default() -> Qdc1icap2 { - Qdc1icap2(0) - } -} -impl core::fmt::Debug for Qdc1icap2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1icap2") - .field("inp", &self.inp()) - .finish() + defmt::write!(f, "Tsi0TrigInput {{ inp: {:?} }}", self.inp()) } } -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc1icap2 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1icap2 {{ inp: {:?} }}", self.inp()) - } +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AdcTrigTrigin { + _RESERVED_0 = 0x0, + #[doc = "ARM_TXEV input is selected."] + Val1 = 0x01, + #[doc = "AOI0_OUT0 input is selected."] + Val2 = 0x02, + #[doc = "AOI0_OUT1 input is selected."] + Val3 = 0x03, + #[doc = "AOI0_OUT2 input is selected."] + Val4 = 0x04, + #[doc = "AOI0_OUT3 input is selected."] + Val5 = 0x05, + #[doc = "CMP0_OUT input is selected."] + Val6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + #[doc = "CTimer0_MAT0 input is selected."] + Val9 = 0x09, + #[doc = "CTimer0_MAT1 input is selected."] + Val10 = 0x0a, + #[doc = "CTimer1_MAT0 input is selected."] + Val11 = 0x0b, + #[doc = "CTimer1_MAT1 input is selected."] + Val12 = 0x0c, + #[doc = "CTimer2_MAT0 input is selected."] + Val13 = 0x0d, + #[doc = "CTimer2_MAT1 input is selected."] + Val14 = 0x0e, + #[doc = "LPTMR0 input is selected."] + Val15 = 0x0f, + _RESERVED_10 = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + _RESERVED_19 = 0x19, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val26 = 0x1a, + #[doc = "GPIO1 Pin Event Trig 0 input is selected."] + Val27 = 0x1b, + #[doc = "GPIO2 Pin Event Trig 0 input is selected."] + Val28 = 0x1c, + #[doc = "GPIO3 Pin Event Trig 0 input is selected."] + Val29 = 0x1d, + #[doc = "GPIO4 Pin Event Trig 0 input is selected."] + Val30 = 0x1e, + #[doc = "WUU."] + Val31 = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + _RESERVED_23 = 0x23, + _RESERVED_24 = 0x24, + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + Val37 = 0x25, + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + Val38 = 0x26, + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + Val39 = 0x27, + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + Val40 = 0x28, + #[doc = "CTimer3_MAT0 input is selected."] + Val41 = 0x29, + #[doc = "CTimer3_MAT1 input is selected."] + Val42 = 0x2a, + #[doc = "CTimer4_MAT0 input is selected."] + Val43 = 0x2b, + #[doc = "CTimer4_MAT1 input is selected."] + Val44 = 0x2c, + #[doc = "FlexIO0 CH0 input is selected."] + Val45 = 0x2d, + #[doc = "FlexIO0 CH1 input is selected."] + Val46 = 0x2e, + #[doc = "FlexIO0 CH2 input is selected."] + Val47 = 0x2f, + #[doc = "FlexIO0 CH3 input is selected."] + Val48 = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + _RESERVED_38 = 0x38, + _RESERVED_39 = 0x39, + _RESERVED_3a = 0x3a, + _RESERVED_3b = 0x3b, + _RESERVED_3c = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, } -#[doc = "QDC1 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1icap3(pub u32); -impl Qdc1icap3 { - #[doc = "QDC1 input connections."] - #[must_use] +impl AdcTrigTrigin { #[inline(always)] - pub const fn inp(&self) -> QdcIcapInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIcapInp::from_bits(val as u8) + pub const fn from_bits(val: u8) -> AdcTrigTrigin { + unsafe { core::mem::transmute(val & 0x3f) } } - #[doc = "QDC1 input connections."] #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIcapInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } -impl Default for Qdc1icap3 { +impl From for AdcTrigTrigin { #[inline(always)] - fn default() -> Qdc1icap3 { - Qdc1icap3(0) - } -} -impl core::fmt::Debug for Qdc1icap3 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1icap3") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc1icap3 { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1icap3 {{ inp: {:?} }}", self.inp()) + fn from(val: u8) -> AdcTrigTrigin { + AdcTrigTrigin::from_bits(val) } } -#[doc = "QDC1 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1index(pub u32); -impl Qdc1index { - #[doc = "QDC1 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcIndexInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcIndexInp::from_bits(val as u8) - } - #[doc = "QDC1 input connections."] +impl From for u8 { #[inline(always)] - pub const fn set_inp(&mut self, val: QdcIndexInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc1index { - #[inline(always)] - fn default() -> Qdc1index { - Qdc1index(0) - } -} -impl core::fmt::Debug for Qdc1index { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1index") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc1index { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1index {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC1 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1phasea(pub u32); -impl Qdc1phasea { - #[doc = "QDC0 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Qdc1phaseaInp { - let val = (self.0 >> 0usize) & 0x7f; - Qdc1phaseaInp::from_bits(val as u8) - } - #[doc = "QDC0 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Qdc1phaseaInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc1phasea { - #[inline(always)] - fn default() -> Qdc1phasea { - Qdc1phasea(0) - } -} -impl core::fmt::Debug for Qdc1phasea { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1phasea") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc1phasea { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1phasea {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC1 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Qdc1phaseb(pub u32); -impl Qdc1phaseb { - #[doc = "QDC1 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Qdc1phasebInp { - let val = (self.0 >> 0usize) & 0x7f; - Qdc1phasebInp::from_bits(val as u8) - } - #[doc = "QDC1 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Qdc1phasebInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Qdc1phaseb { - #[inline(always)] - fn default() -> Qdc1phaseb { - Qdc1phaseb(0) - } -} -impl core::fmt::Debug for Qdc1phaseb { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Qdc1phaseb") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Qdc1phaseb { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Qdc1phaseb {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "QDC0 Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct QdcTrig(pub u32); -impl QdcTrig { - #[doc = "QDC0 input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> QdcTrigInp { - let val = (self.0 >> 0usize) & 0x7f; - QdcTrigInp::from_bits(val as u8) - } - #[doc = "QDC0 input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: QdcTrigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for QdcTrig { - #[inline(always)] - fn default() -> QdcTrig { - QdcTrig(0) - } -} -impl core::fmt::Debug for QdcTrig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("QdcTrig").field("inp", &self.inp()).finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for QdcTrig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "QdcTrig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "SmartDMA Trigger Input Connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct SmartDmaTrig(pub u32); -impl SmartDmaTrig { - #[doc = "Input number for SmartDMA."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> SmartDmaTrigInp { - let val = (self.0 >> 0usize) & 0x7f; - SmartDmaTrigInp::from_bits(val as u8) - } - #[doc = "Input number for SmartDMA."] - #[inline(always)] - pub const fn set_inp(&mut self, val: SmartDmaTrigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for SmartDmaTrig { - #[inline(always)] - fn default() -> SmartDmaTrig { - SmartDmaTrig(0) - } -} -impl core::fmt::Debug for SmartDmaTrig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SmartDmaTrig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for SmartDmaTrig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "SmartDmaTrig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "Trigger register for TIMER0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer0trig(pub u32); -impl Timer0trig { - #[doc = "Input number for CTIMER0."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Timer0trigInp { - let val = (self.0 >> 0usize) & 0x7f; - Timer0trigInp::from_bits(val as u8) - } - #[doc = "Input number for CTIMER0."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Timer0trigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Timer0trig { - #[inline(always)] - fn default() -> Timer0trig { - Timer0trig(0) - } -} -impl core::fmt::Debug for Timer0trig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer0trig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Timer0trig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Timer0trig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "Trigger register for TIMER1."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer1trig(pub u32); -impl Timer1trig { - #[doc = "Input number for CTIMER1."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Timer1trigInp { - let val = (self.0 >> 0usize) & 0x7f; - Timer1trigInp::from_bits(val as u8) - } - #[doc = "Input number for CTIMER1."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Timer1trigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Timer1trig { - #[inline(always)] - fn default() -> Timer1trig { - Timer1trig(0) - } -} -impl core::fmt::Debug for Timer1trig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer1trig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Timer1trig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Timer1trig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "Trigger register for TIMER2 inputs."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer2trig(pub u32); -impl Timer2trig { - #[doc = "Input number for CTIMER2."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Timer2trigInp { - let val = (self.0 >> 0usize) & 0x7f; - Timer2trigInp::from_bits(val as u8) - } - #[doc = "Input number for CTIMER2."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Timer2trigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Timer2trig { - #[inline(always)] - fn default() -> Timer2trig { - Timer2trig(0) - } -} -impl core::fmt::Debug for Timer2trig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer2trig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Timer2trig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Timer2trig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "Trigger register for TIMER3."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer3trig(pub u32); -impl Timer3trig { - #[doc = "Input number for CTIMER3."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Timer3trigInp { - let val = (self.0 >> 0usize) & 0x7f; - Timer3trigInp::from_bits(val as u8) - } - #[doc = "Input number for CTIMER3."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Timer3trigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Timer3trig { - #[inline(always)] - fn default() -> Timer3trig { - Timer3trig(0) - } -} -impl core::fmt::Debug for Timer3trig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer3trig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Timer3trig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Timer3trig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "Trigger register for TIMER4."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Timer4trig(pub u32); -impl Timer4trig { - #[doc = "Input number for CTIMER4."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> Timer4trigInp { - let val = (self.0 >> 0usize) & 0x7f; - Timer4trigInp::from_bits(val as u8) - } - #[doc = "Input number for CTIMER4."] - #[inline(always)] - pub const fn set_inp(&mut self, val: Timer4trigInp) { - self.0 = (self.0 & !(0x7f << 0usize)) | (((val.to_bits() as u32) & 0x7f) << 0usize); - } -} -impl Default for Timer4trig { - #[inline(always)] - fn default() -> Timer4trig { - Timer4trig(0) - } -} -impl core::fmt::Debug for Timer4trig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer4trig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Timer4trig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Timer4trig {{ inp: {:?} }}", self.inp()) - } -} -#[doc = "TRIGFIL control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Trigfil(pub u32); -impl Trigfil { - #[doc = "Input Filter Sample Period."] - #[must_use] - #[inline(always)] - pub const fn filt_per(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 - } - #[doc = "Input Filter Sample Period."] - #[inline(always)] - pub const fn set_filt_per(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); - } - #[doc = "Input Filter Sample Count."] - #[must_use] - #[inline(always)] - pub const fn filt_cnt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x07; - val as u8 - } - #[doc = "Input Filter Sample Count."] - #[inline(always)] - pub const fn set_filt_cnt(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 8usize)) | (((val as u32) & 0x07) << 8usize); - } -} -impl Default for Trigfil { - #[inline(always)] - fn default() -> Trigfil { - Trigfil(0) - } -} -impl core::fmt::Debug for Trigfil { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Trigfil") - .field("filt_per", &self.filt_per()) - .field("filt_cnt", &self.filt_cnt()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Trigfil { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Trigfil {{ filt_per: {=u8:?}, filt_cnt: {=u8:?} }}", - self.filt_per(), - self.filt_cnt() - ) - } -} -#[doc = "Trigger filter prescaller."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct TrigfilPrsc(pub u32); -impl TrigfilPrsc { - #[doc = "Filter Prescaller Value."] - #[must_use] - #[inline(always)] - pub const fn filt_scale_val(&self) -> FiltScaleVal { - let val = (self.0 >> 0usize) & 0x03; - FiltScaleVal::from_bits(val as u8) - } - #[doc = "Filter Prescaller Value."] - #[inline(always)] - pub const fn set_filt_scale_val(&mut self, val: FiltScaleVal) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } - #[doc = "Enable trigger filter prescaller."] - #[must_use] - #[inline(always)] - pub const fn filt_scale_en(&self) -> FiltScaleEn { - let val = (self.0 >> 31usize) & 0x01; - FiltScaleEn::from_bits(val as u8) - } - #[doc = "Enable trigger filter prescaller."] - #[inline(always)] - pub const fn set_filt_scale_en(&mut self, val: FiltScaleEn) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for TrigfilPrsc { - #[inline(always)] - fn default() -> TrigfilPrsc { - TrigfilPrsc(0) - } -} -impl core::fmt::Debug for TrigfilPrsc { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TrigfilPrsc") - .field("filt_scale_val", &self.filt_scale_val()) - .field("filt_scale_en", &self.filt_scale_en()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for TrigfilPrsc { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "TrigfilPrsc {{ filt_scale_val: {:?}, filt_scale_en: {:?} }}", - self.filt_scale_val(), - self.filt_scale_en() - ) - } -} -#[doc = "Trigger filter stat."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct TrigfilStat(pub u32); -impl TrigfilStat { - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in0_val(&self) -> TrigInVal { - let val = (self.0 >> 0usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in0_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in1_val(&self) -> TrigInVal { - let val = (self.0 >> 1usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in1_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in2_val(&self) -> TrigInVal { - let val = (self.0 >> 2usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in2_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in3_val(&self) -> TrigInVal { - let val = (self.0 >> 3usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in3_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in4_val(&self) -> TrigInVal { - let val = (self.0 >> 4usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in4_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in5_val(&self) -> TrigInVal { - let val = (self.0 >> 5usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in5_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in6_val(&self) -> TrigInVal { - let val = (self.0 >> 6usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in6_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in7_val(&self) -> TrigInVal { - let val = (self.0 >> 7usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in7_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in8_val(&self) -> TrigInVal { - let val = (self.0 >> 8usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in8_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in9_val(&self) -> TrigInVal { - let val = (self.0 >> 9usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in9_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in10_val(&self) -> TrigInVal { - let val = (self.0 >> 10usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in10_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); - } - #[doc = "TRIG_IN value."] - #[must_use] - #[inline(always)] - pub const fn trig_in11_val(&self) -> TrigInVal { - let val = (self.0 >> 11usize) & 0x01; - TrigInVal::from_bits(val as u8) - } - #[doc = "TRIG_IN value."] - #[inline(always)] - pub const fn set_trig_in11_val(&mut self, val: TrigInVal) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); - } -} -impl Default for TrigfilStat { - #[inline(always)] - fn default() -> TrigfilStat { - TrigfilStat(0) - } -} -impl core::fmt::Debug for TrigfilStat { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TrigfilStat") - .field("trig_in0_val", &self.trig_in0_val()) - .field("trig_in1_val", &self.trig_in1_val()) - .field("trig_in2_val", &self.trig_in2_val()) - .field("trig_in3_val", &self.trig_in3_val()) - .field("trig_in4_val", &self.trig_in4_val()) - .field("trig_in5_val", &self.trig_in5_val()) - .field("trig_in6_val", &self.trig_in6_val()) - .field("trig_in7_val", &self.trig_in7_val()) - .field("trig_in8_val", &self.trig_in8_val()) - .field("trig_in9_val", &self.trig_in9_val()) - .field("trig_in10_val", &self.trig_in10_val()) - .field("trig_in11_val", &self.trig_in11_val()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for TrigfilStat { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "TrigfilStat {{ trig_in0_val: {:?}, trig_in1_val: {:?}, trig_in2_val: {:?}, trig_in3_val: {:?}, trig_in4_val: {:?}, trig_in5_val: {:?}, trig_in6_val: {:?}, trig_in7_val: {:?}, trig_in8_val: {:?}, trig_in9_val: {:?}, trig_in10_val: {:?}, trig_in11_val: {:?} }}", - self.trig_in0_val(), - self.trig_in1_val(), - self.trig_in2_val(), - self.trig_in3_val(), - self.trig_in4_val(), - self.trig_in5_val(), - self.trig_in6_val(), - self.trig_in7_val(), - self.trig_in8_val(), - self.trig_in9_val(), - self.trig_in10_val(), - self.trig_in11_val() - ) - } -} -#[doc = "USB-FS trigger input connections."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct UsbfsTrig(pub u32); -impl UsbfsTrig { - #[doc = "USB-FS trigger input connections."] - #[must_use] - #[inline(always)] - pub const fn inp(&self) -> UsbfsTrigInp { - let val = (self.0 >> 0usize) & 0x0f; - UsbfsTrigInp::from_bits(val as u8) - } - #[doc = "USB-FS trigger input connections."] - #[inline(always)] - pub const fn set_inp(&mut self, val: UsbfsTrigInp) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); - } -} -impl Default for UsbfsTrig { - #[inline(always)] - fn default() -> UsbfsTrig { - UsbfsTrig(0) - } -} -impl core::fmt::Debug for UsbfsTrig { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UsbfsTrig") - .field("inp", &self.inp()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for UsbfsTrig { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "UsbfsTrig {{ inp: {:?} }}", self.inp()) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum AdcTrigTrigin { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT0 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT1 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT0 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT1 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT0 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT1 input is selected."] - VAL14 = 0x0e, - #[doc = "LPTMR0 input is selected."] - VAL15 = 0x0f, - _RESERVED_10 = 0x10, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM0_OUT_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM0_OUT_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM1_OUT_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM1_OUT_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM2_OUT_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM2_OUT_TRIG1 input is selected."] - VAL23 = 0x17, - #[doc = "PWM0_SM3_OUT_TRIG0 input is selected."] - VAL24 = 0x18, - #[doc = "PWM0_SM3_OUT_TRIG1 input is selected."] - VAL25 = 0x19, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL26 = 0x1a, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL27 = 0x1b, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL30 = 0x1e, - #[doc = "WUU."] - VAL31 = 0x1f, - _RESERVED_20 = 0x20, - #[doc = "AOI1_OUT0 input is selected."] - VAL33 = 0x21, - #[doc = "AOI1_OUT1 input is selected."] - VAL34 = 0x22, - #[doc = "AOI1_OUT2 input is selected."] - VAL35 = 0x23, - #[doc = "AOI1_OUT3 input is selected."] - VAL36 = 0x24, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL37 = 0x25, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL38 = 0x26, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL39 = 0x27, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL40 = 0x28, - #[doc = "CTimer3_MAT0 input is selected."] - VAL41 = 0x29, - #[doc = "CTimer3_MAT1 input is selected."] - VAL42 = 0x2a, - #[doc = "CTimer4_MAT0 input is selected."] - VAL43 = 0x2b, - #[doc = "CTimer4_MAT1 input is selected."] - VAL44 = 0x2c, - #[doc = "FlexIO CH0 input is selected."] - VAL45 = 0x2d, - #[doc = "FlexIO CH1 input is selected."] - VAL46 = 0x2e, - #[doc = "FlexIO CH2 input is selected."] - VAL47 = 0x2f, - #[doc = "FlexIO CH3 input is selected."] - VAL48 = 0x30, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL49 = 0x31, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL50 = 0x32, - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - VAL51 = 0x33, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL52 = 0x34, - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - VAL53 = 0x35, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL54 = 0x36, - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - VAL55 = 0x37, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL56 = 0x38, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL57 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl AdcTrigTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> AdcTrigTrigin { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for AdcTrigTrigin { - #[inline(always)] - fn from(val: u8) -> AdcTrigTrigin { - AdcTrigTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: AdcTrigTrigin) -> u8 { - AdcTrigTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum AoiInputInp { - _RESERVED_0 = 0x0, - #[doc = "ADC0_tcomp\\[0\\] input is selected."] - VAL1 = 0x01, - #[doc = "ADC0_tcomp\\[1\\] input is selected."] - VAL2 = 0x02, - #[doc = "ADC0_tcomp\\[2\\] input is selected."] - VAL3 = 0x03, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL4 = 0x04, - #[doc = "CMP0_OUT input is selected."] - VAL5 = 0x05, - #[doc = "CMP1_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP2_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CTimer0_MAT0 input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT1 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT2 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer0_MAT3 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT0 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer1_MAT1 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer1_MAT2 input is selected."] - VAL14 = 0x0e, - #[doc = "CTimer1_MAT3 input is selected."] - VAL15 = 0x0f, - #[doc = "CTimer2_MAT0 input is selected."] - VAL16 = 0x10, - #[doc = "CTimer2_MAT1 input is selected."] - VAL17 = 0x11, - #[doc = "CTimer2_MAT2 input is selected."] - VAL18 = 0x12, - #[doc = "CTimer2_MAT3 input is selected."] - VAL19 = 0x13, - #[doc = "LPTMR0 input is selected."] - VAL20 = 0x14, - _RESERVED_15 = 0x15, - #[doc = "QDC0_CMP_FLAG0 input is selected."] - VAL22 = 0x16, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL23 = 0x17, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL24 = 0x18, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL25 = 0x19, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL26 = 0x1a, - #[doc = "PWM0_SM0_MUX_TRIG0 0 input is selected."] - VAL27 = 0x1b, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL28 = 0x1c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL29 = 0x1d, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL30 = 0x1e, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL31 = 0x1f, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL32 = 0x20, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL33 = 0x21, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL34 = 0x22, - #[doc = "TRIG_IN0 input is selected."] - VAL35 = 0x23, - #[doc = "TRIG_IN1 input is selected."] - VAL36 = 0x24, - #[doc = "TRIG_IN2 input is selected."] - VAL37 = 0x25, - #[doc = "TRIG_IN3 input is selected."] - VAL38 = 0x26, - #[doc = "TRIG_IN4 input is selected."] - VAL39 = 0x27, - #[doc = "TRIG_IN5 input is selected."] - VAL40 = 0x28, - #[doc = "TRIG_IN6 input is selected."] - VAL41 = 0x29, - #[doc = "TRIG_IN7 input is selected."] - VAL42 = 0x2a, - #[doc = "TRIG_IN8 input is selected."] - VAL43 = 0x2b, - #[doc = "TRIG_IN9 input is selected."] - VAL44 = 0x2c, - #[doc = "TRIG_IN10 input is selected."] - VAL45 = 0x2d, - #[doc = "TRIG_IN11 input is selected."] - VAL46 = 0x2e, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL47 = 0x2f, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL48 = 0x30, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL49 = 0x31, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL50 = 0x32, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL51 = 0x33, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL52 = 0x34, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL53 = 0x35, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL54 = 0x36, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL55 = 0x37, - #[doc = "CTimer3_MAT0 input is selected."] - VAL56 = 0x38, - #[doc = "CTimer3_MAT1 input is selected."] - VAL57 = 0x39, - #[doc = "CTimer3_MAT2 input is selected."] - VAL58 = 0x3a, - #[doc = "CTimer3_MAT3 input is selected."] - VAL59 = 0x3b, - #[doc = "CTimer4_MAT0 input is selected."] - VAL60 = 0x3c, - #[doc = "CTimer4_MAT1 input is selected."] - VAL61 = 0x3d, - #[doc = "CTimer4_MAT2 input is selected."] - VAL62 = 0x3e, - #[doc = "CTimer4_MAT3 input is selected."] - VAL63 = 0x3f, - #[doc = "FlexIO CH0 input is selected."] - VAL64 = 0x40, - #[doc = "FlexIO CH1 input is selected."] - VAL65 = 0x41, - #[doc = "FlexIO CH2 input is selected."] - VAL66 = 0x42, - #[doc = "FlexIO CH3 input is selected."] - VAL67 = 0x43, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL68 = 0x44, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL69 = 0x45, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL70 = 0x46, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL71 = 0x47, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL72 = 0x48, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL73 = 0x49, - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - VAL74 = 0x4a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL75 = 0x4b, - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - VAL76 = 0x4c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL77 = 0x4d, - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - VAL78 = 0x4e, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL79 = 0x4f, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL80 = 0x50, - #[doc = "PWM0_SM0_A_Output."] - VAL81 = 0x51, - #[doc = "PWM0_SM0_B_Output."] - VAL82 = 0x52, - #[doc = "PWM0_SM1_A_Output."] - VAL83 = 0x53, - #[doc = "PWM0_SM1_B_Output."] - VAL84 = 0x54, - #[doc = "PWM0_SM2_A_Output."] - VAL85 = 0x55, - #[doc = "PWM0_SM2_B_Output."] - VAL86 = 0x56, - #[doc = "PWM0_SM3_A_Output."] - VAL87 = 0x57, - #[doc = "PWM0_SM3_B_Output."] - VAL88 = 0x58, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL89 = 0x59, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL90 = 0x5a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL91 = 0x5b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL92 = 0x5c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL93 = 0x5d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL94 = 0x5e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL95 = 0x5f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL96 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl AoiInputInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> AoiInputInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for AoiInputInp { - #[inline(always)] - fn from(val: u8) -> AoiInputInp { - AoiInputInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: AoiInputInp) -> u8 { - AoiInputInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum CmpTrigTrigin { - _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP1_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP2_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CTimer0_MAT0 input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer1_MAT0."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer2_MAT0 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "LPTMR0 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "QDC0_POS_MATCH0."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL23 = 0x17, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL24 = 0x18, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL25 = 0x19, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL26 = 0x1a, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL27 = 0x1b, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "WUU input is selected."] - VAL30 = 0x1e, - #[doc = "AOI1_OUT0 input is selected."] - VAL31 = 0x1f, - #[doc = "AOI1_OUT1 input is selected."] - VAL32 = 0x20, - #[doc = "AOI1_OUT2 input is selected."] - VAL33 = 0x21, - #[doc = "AOI1_OUT3 input is selected."] - VAL34 = 0x22, - _RESERVED_23 = 0x23, - _RESERVED_24 = 0x24, - _RESERVED_25 = 0x25, - _RESERVED_26 = 0x26, - #[doc = "CTimer3_MAT0."] - VAL39 = 0x27, - #[doc = "CTimer3_MAT1."] - VAL40 = 0x28, - #[doc = "CTimer4_MAT0 input is selected."] - VAL41 = 0x29, - #[doc = "CTimer4_MAT1 input is selected."] - VAL42 = 0x2a, - _RESERVED_2b = 0x2b, - _RESERVED_2c = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL47 = 0x2f, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL48 = 0x30, - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - VAL49 = 0x31, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL50 = 0x32, - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - VAL51 = 0x33, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL52 = 0x34, - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - VAL53 = 0x35, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL54 = 0x36, - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - VAL55 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl CmpTrigTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> CmpTrigTrigin { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for CmpTrigTrigin { - #[inline(always)] - fn from(val: u8) -> CmpTrigTrigin { - CmpTrigTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: CmpTrigTrigin) -> u8 { - CmpTrigTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ctimer0capInp { - _RESERVED_0 = 0x0, - #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, - #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, - #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, - #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, - #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, - #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, - #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, - #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, - #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, - #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, - #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, - #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, - #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, - #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, - #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, - #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, - #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, - #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, - #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, - #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, - #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, - #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, - #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, - #[doc = "CTimer1_MAT1 input is selected."] - VAL33 = 0x21, - #[doc = "CTimer1_MAT2 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer1_MAT3 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer2_MAT1 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer2_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer2_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, - #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, - #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, - #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, - #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, - #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, - #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, - #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, - #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, - #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, - #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, - #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, - #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, - #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, - #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, - #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, - #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, - #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, - #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, - #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, - #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, - #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, - #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, - #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, - #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, - #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, - #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, - #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, - #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, - #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, - #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, - #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, - #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl Ctimer0capInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ctimer0capInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ctimer0capInp { - #[inline(always)] - fn from(val: u8) -> Ctimer0capInp { - Ctimer0capInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ctimer0capInp) -> u8 { - Ctimer0capInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ctimer1capInp { - _RESERVED_0 = 0x0, - #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, - #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, - #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, - #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, - #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, - #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, - #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, - #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, - #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, - #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, - #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, - #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, - #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, - #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, - #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, - #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, - #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, - #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, - #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, - #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, - #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, - #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, - #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, - #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, - #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer2_MAT1 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer2_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer2_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, - #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, - #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, - #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, - #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, - #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, - #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, - #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, - #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, - #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, - #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, - #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, - #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, - #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, - #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, - #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, - #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, - #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, - #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, - #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, - #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, - #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, - #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, - #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, - #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, - #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, - #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, - #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, - #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, - #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, - #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, - #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, - #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl Ctimer1capInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ctimer1capInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ctimer1capInp { - #[inline(always)] - fn from(val: u8) -> Ctimer1capInp { - Ctimer1capInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ctimer1capInp) -> u8 { - Ctimer1capInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ctimer2capInp { - _RESERVED_0 = 0x0, - #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, - #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, - #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, - #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, - #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, - #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, - #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, - #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, - #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, - #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, - #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, - #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, - #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, - #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, - #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, - #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, - #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, - #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, - #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, - #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, - #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, - #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, - #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, - #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, - #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, - #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, - #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, - #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, - #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, - #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, - #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, - #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, - #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, - #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, - #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, - #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, - #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, - #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, - #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, - #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, - #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, - #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, - #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, - #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, - #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, - #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, - #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, - #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, - #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, - #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, - #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, - #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, - #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, - #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, - #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, - #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, - #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl Ctimer2capInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ctimer2capInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ctimer2capInp { - #[inline(always)] - fn from(val: u8) -> Ctimer2capInp { - Ctimer2capInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ctimer2capInp) -> u8 { - Ctimer2capInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ctimer3capInp { - _RESERVED_0 = 0x0, - #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, - #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, - #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, - #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, - #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, - #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, - #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, - #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, - #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, - #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, - #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, - #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, - #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, - #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, - #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, - #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, - #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, - #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, - #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, - #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, - #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, - #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, - #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, - #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, - #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, - #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, - #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, - #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, - #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, - #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, - #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, - #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, - #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, - #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, - #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, - #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, - #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, - #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, - #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, - #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, - #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, - #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, - #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, - #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, - #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, - #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, - #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer2_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer2_MAT2 input is selected."] - VAL80 = 0x50, - #[doc = "CTimer2_MAT3 input is selected."] - VAL81 = 0x51, - #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, - #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, - #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, - #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, - #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, - #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, - #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, - #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, - #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - #[doc = "TRIG_IN0 input is selected."] - VAL113 = 0x71, - #[doc = "TRIG_IN1 input is selected."] - VAL114 = 0x72, - #[doc = "TRIG_IN2 input is selected."] - VAL115 = 0x73, - #[doc = "TRIG_IN3 input is selected."] - VAL116 = 0x74, - #[doc = "TRIG_IN4 input is selected."] - VAL117 = 0x75, - #[doc = "TRIG_IN5 input is selected."] - VAL118 = 0x76, - #[doc = "TRIG_IN6 input is selected."] - VAL119 = 0x77, - #[doc = "TRIG_IN7 input is selected."] - VAL120 = 0x78, - #[doc = "TRIG_IN8 input is selected."] - VAL121 = 0x79, - #[doc = "TRIG_IN9 input is selected."] - VAL122 = 0x7a, - #[doc = "TRIG_IN10 input is selected."] - VAL123 = 0x7b, - #[doc = "TRIG_IN11 input is selected."] - VAL124 = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl Ctimer3capInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ctimer3capInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ctimer3capInp { - #[inline(always)] - fn from(val: u8) -> Ctimer3capInp { - Ctimer3capInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ctimer3capInp) -> u8 { - Ctimer3capInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ctimer4capInp { - _RESERVED_0 = 0x0, - #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, - #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, - #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, - #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, - #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, - #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, - #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, - #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, - #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, - #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, - #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, - #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, - #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, - #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, - #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, - #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, - #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, - #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, - #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, - #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, - #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, - #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, - #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, - #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, - #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, - #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, - #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, - #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, - #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, - #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, - #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, - #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, - #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, - #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, - #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, - #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, - #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, - #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, - #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, - #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, - #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, - #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, - #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, - #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, - #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, - #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, - #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer2_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer2_MAT2 input is selected."] - VAL80 = 0x50, - #[doc = "CTimer2_MAT3 input is selected."] - VAL81 = 0x51, - #[doc = "CTimer3_MAT1 input is selected."] - VAL82 = 0x52, - #[doc = "CTimer3_MAT2 input is selected."] - VAL83 = 0x53, - #[doc = "CTimer3_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, - #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, - #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, - #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, - #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, - #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, - #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - #[doc = "TRIG_IN0 input is selected."] - VAL113 = 0x71, - #[doc = "TRIG_IN1 input is selected."] - VAL114 = 0x72, - #[doc = "TRIG_IN2 input is selected."] - VAL115 = 0x73, - #[doc = "TRIG_IN3 input is selected."] - VAL116 = 0x74, - #[doc = "TRIG_IN4 input is selected."] - VAL117 = 0x75, - #[doc = "TRIG_IN5 input is selected."] - VAL118 = 0x76, - #[doc = "TRIG_IN6 input is selected."] - VAL119 = 0x77, - #[doc = "TRIG_IN7 input is selected."] - VAL120 = 0x78, - #[doc = "TRIG_IN8 input is selected."] - VAL121 = 0x79, - #[doc = "TRIG_IN9 input is selected."] - VAL122 = 0x7a, - #[doc = "TRIG_IN10 input is selected."] - VAL123 = 0x7b, - #[doc = "TRIG_IN11 input is selected."] - VAL124 = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl Ctimer4capInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ctimer4capInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ctimer4capInp { - #[inline(always)] - fn from(val: u8) -> Ctimer4capInp { - Ctimer4capInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ctimer4capInp) -> u8 { - Ctimer4capInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum DacTrigTrigin { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV."] - VAL1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT0 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT1 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT0 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT1 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT0 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT1 input is selected."] - VAL14 = 0x0e, - #[doc = "LPTMR0 input is selected."] - VAL15 = 0x0f, - _RESERVED_10 = 0x10, - _RESERVED_11 = 0x11, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - _RESERVED_16 = 0x16, - _RESERVED_17 = 0x17, - _RESERVED_18 = 0x18, - _RESERVED_19 = 0x19, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL26 = 0x1a, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL27 = 0x1b, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL30 = 0x1e, - #[doc = "WUU input is selected."] - VAL31 = 0x1f, - _RESERVED_20 = 0x20, - #[doc = "AOI1_OUT0 input is selected."] - VAL33 = 0x21, - #[doc = "AOI1_OUT1 input is selected."] - VAL34 = 0x22, - #[doc = "AOI1_OUT2 input is selected."] - VAL35 = 0x23, - #[doc = "AOI1_OUT3 input is selected."] - VAL36 = 0x24, - #[doc = "ADC0_tcomp\\[0\\] input is selected."] - VAL37 = 0x25, - #[doc = "ADC0_tcomp\\[1\\] input is selected."] - VAL38 = 0x26, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL39 = 0x27, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL40 = 0x28, - #[doc = "CTimer3_MAT0 input is selected."] - VAL41 = 0x29, - #[doc = "CTimer3_MAT1 input is selected."] - VAL42 = 0x2a, - #[doc = "CTimer4_MAT0 input is selected."] - VAL43 = 0x2b, - #[doc = "CTimer4_MAT1 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - _RESERVED_31 = 0x31, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL50 = 0x32, - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - VAL51 = 0x33, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL52 = 0x34, - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - VAL53 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL58 = 0x3a, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL59 = 0x3b, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL60 = 0x3c, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL61 = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl DacTrigTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> DacTrigTrigin { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for DacTrigTrigin { - #[inline(always)] - fn from(val: u8) -> DacTrigTrigin { - DacTrigTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: DacTrigTrigin) -> u8 { - DacTrigTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum ExtTrigInp { - _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "LPUART0 ipp_do_lpuart_txd input is selected."] - VAL9 = 0x09, - #[doc = "LPUART1 ipp_do_lpuart_txd input is selected."] - VAL10 = 0x0a, - #[doc = "LPUART2 ipp_do_lpuart_txd input is selected."] - VAL11 = 0x0b, - #[doc = "LPUART3 ipp_do_lpuart_txd input is selected."] - VAL12 = 0x0c, - #[doc = "LPUART4 ipp_do_lpuart_txd input is selected."] - VAL13 = 0x0d, - #[doc = "AOI1_OUT0 input is selected."] - VAL14 = 0x0e, - #[doc = "AOI1_OUT1 input is selected."] - VAL15 = 0x0f, - #[doc = "AOI1_OUT2 input is selected."] - VAL16 = 0x10, - #[doc = "RTC_1Hz_CLK input is selected."] - VAL17 = 0x11, - #[doc = "LPUART5 ipp_do_lpuart_txd input is selected."] - VAL18 = 0x12, - _RESERVED_13 = 0x13, - _RESERVED_14 = 0x14, - _RESERVED_15 = 0x15, - _RESERVED_16 = 0x16, - _RESERVED_17 = 0x17, - _RESERVED_18 = 0x18, - _RESERVED_19 = 0x19, - _RESERVED_1a = 0x1a, - _RESERVED_1b = 0x1b, - _RESERVED_1c = 0x1c, - _RESERVED_1d = 0x1d, - _RESERVED_1e = 0x1e, - _RESERVED_1f = 0x1f, -} -impl ExtTrigInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> ExtTrigInp { - unsafe { core::mem::transmute(val & 0x1f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for ExtTrigInp { - #[inline(always)] - fn from(val: u8) -> ExtTrigInp { - ExtTrigInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: ExtTrigInp) -> u8 { - ExtTrigInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FiltScaleEn { - #[doc = "Disable prescaller."] - VAL2 = 0x0, - #[doc = "Enabled prescaller."] - VAL1 = 0x01, -} -impl FiltScaleEn { - #[inline(always)] - pub const fn from_bits(val: u8) -> FiltScaleEn { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for FiltScaleEn { - #[inline(always)] - fn from(val: u8) -> FiltScaleEn { - FiltScaleEn::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FiltScaleEn) -> u8 { - FiltScaleEn::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FiltScaleVal { - #[doc = "Bypass the clock."] - VAL0 = 0x0, - #[doc = "Divide 2."] - VAL1 = 0x01, - #[doc = "Divide 4."] - VAL2 = 0x02, - #[doc = "Divide 8."] - VAL3 = 0x03, -} -impl FiltScaleVal { - #[inline(always)] - pub const fn from_bits(val: u8) -> FiltScaleVal { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for FiltScaleVal { - #[inline(always)] - fn from(val: u8) -> FiltScaleVal { - FiltScaleVal::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FiltScaleVal) -> u8 { - FiltScaleVal::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FlexPwmTrigin { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - #[doc = "QDC0_CMP_FLAG0 input is selected."] - VAL15 = 0x0f, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL16 = 0x10, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL17 = 0x11, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL18 = 0x12, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL19 = 0x13, - #[doc = "TRIG_IN0 input is selected."] - VAL20 = 0x14, - #[doc = "TRIG_IN1 input is selected."] - VAL21 = 0x15, - #[doc = "TRIG_IN2 input is selected."] - VAL22 = 0x16, - #[doc = "TRIG_IN3 input is selected."] - VAL23 = 0x17, - #[doc = "TRIG_IN4 input is selected."] - VAL24 = 0x18, - #[doc = "TRIG_IN5 input is selected."] - VAL25 = 0x19, - #[doc = "TRIG_IN6 input is selected."] - VAL26 = 0x1a, - #[doc = "TRIG_IN7 input is selected."] - VAL27 = 0x1b, - #[doc = "TRIG_IN8 input is selected."] - VAL28 = 0x1c, - #[doc = "TRIG_IN9 input is selected."] - VAL29 = 0x1d, - #[doc = "TRIG_IN10 input is selected."] - VAL30 = 0x1e, - #[doc = "TRIG_IN11 input is selected."] - VAL31 = 0x1f, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL32 = 0x20, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL33 = 0x21, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL34 = 0x22, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL36 = 0x24, - #[doc = "AOI1_OUT0 input is selected."] - VAL37 = 0x25, - #[doc = "AOI1_OUT1 input is selected."] - VAL38 = 0x26, - #[doc = "AOI1_OUT2 input is selected."] - VAL39 = 0x27, - #[doc = "AOI1_OUT3 input is selected."] - VAL40 = 0x28, - _RESERVED_29 = 0x29, - _RESERVED_2a = 0x2a, - _RESERVED_2b = 0x2b, - _RESERVED_2c = 0x2c, - #[doc = "CTimer3_MAT2 input is selected."] - VAL45 = 0x2d, - #[doc = "CTimer3_MAT3 input is selected."] - VAL46 = 0x2e, - #[doc = "CTimer4_MAT2 input is selected."] - VAL47 = 0x2f, - #[doc = "CTimer4_MAT3 input is selected."] - VAL48 = 0x30, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL49 = 0x31, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL50 = 0x32, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL51 = 0x33, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL52 = 0x34, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL53 = 0x35, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL54 = 0x36, - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - VAL55 = 0x37, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL56 = 0x38, - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - VAL57 = 0x39, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL58 = 0x3a, - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - VAL59 = 0x3b, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL60 = 0x3c, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL61 = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl FlexPwmTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> FlexPwmTrigin { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for FlexPwmTrigin { - #[inline(always)] - fn from(val: u8) -> FlexPwmTrigin { - FlexPwmTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FlexPwmTrigin) -> u8 { - FlexPwmTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FlexioTrigInp { - _RESERVED_0 = 0x0, - #[doc = "AOI0_OUT0 input is selected."] - VAL1 = 0x01, - #[doc = "AOI0_OUT1 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT2 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT3 input is selected."] - VAL4 = 0x04, - #[doc = "ADC0_tcomp\\[0\\] input is selected."] - VAL5 = 0x05, - #[doc = "ADC0_tcomp\\[1\\] input is selected."] - VAL6 = 0x06, - #[doc = "ADC0_tcomp\\[2\\] input is selected."] - VAL7 = 0x07, - #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL8 = 0x08, - #[doc = "CMP0_OUT input is selected."] - VAL9 = 0x09, - #[doc = "CMP1_OUT input is selected."] - VAL10 = 0x0a, - #[doc = "CMP2_OUT input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer0_MAT1 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer0_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer1_MAT1 input is selected."] - VAL14 = 0x0e, - #[doc = "CTimer1_MAT2 input is selected."] - VAL15 = 0x0f, - #[doc = "CTimer2_MAT1 input is selected."] - VAL16 = 0x10, - #[doc = "CTimer2_MAT2 input is selected."] - VAL17 = 0x11, - #[doc = "LPTMR0 input is selected."] - VAL18 = 0x12, - _RESERVED_13 = 0x13, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL23 = 0x17, - #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, - #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, - #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, - #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, - #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, - #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, - #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, - #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL32 = 0x20, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL33 = 0x21, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL34 = 0x22, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL36 = 0x24, - #[doc = "WUU input is selected."] - VAL37 = 0x25, - #[doc = "LPI2C0 Master End of Packet."] - VAL38 = 0x26, - #[doc = "LPI2C0 Slave End of Packet."] - VAL39 = 0x27, - #[doc = "LPI2C1 Master End of Packet."] - VAL40 = 0x28, - #[doc = "LPI2C1 Slave End of Packet."] - VAL41 = 0x29, - #[doc = "LPSPI0 End of Frame."] - VAL42 = 0x2a, - #[doc = "LPSPI0 Received Data Word."] - VAL43 = 0x2b, - #[doc = "LPSPI1 End of Frame."] - VAL44 = 0x2c, - #[doc = "LPSPI1 Received Data Word."] - VAL45 = 0x2d, - #[doc = "LPUART0 Received Data Word."] - VAL46 = 0x2e, - #[doc = "LPUART0 Transmitted Data Word."] - VAL47 = 0x2f, - #[doc = "LPUART0 Receive Line Idle."] - VAL48 = 0x30, - #[doc = "LPUART1 Received Data Word."] - VAL49 = 0x31, - #[doc = "LPUART1 Transmitted Data Word."] - VAL50 = 0x32, - #[doc = "LPUART1 Receive Line Idle."] - VAL51 = 0x33, - #[doc = "LPUART2 Received Data Word."] - VAL52 = 0x34, - #[doc = "LPUART2 Transmitted Data Word."] - VAL53 = 0x35, - #[doc = "LPUART2 Receive Line Idle."] - VAL54 = 0x36, - #[doc = "LPUART3 Received Data Word."] - VAL55 = 0x37, - #[doc = "LPUART3 Transmitted Data Word."] - VAL56 = 0x38, - #[doc = "LPUART3 Receive Line Idle."] - VAL57 = 0x39, - #[doc = "LPUART4 Received Data Word."] - VAL58 = 0x3a, - #[doc = "LPUART4 Transmitted Data Word."] - VAL59 = 0x3b, - #[doc = "LPUART4 Receive Line Idle."] - VAL60 = 0x3c, - #[doc = "AOI1_OUT0 input is selected."] - VAL61 = 0x3d, - #[doc = "AOI1_OUT1 input is selected."] - VAL62 = 0x3e, - #[doc = "AOI1_OUT2 input is selected."] - VAL63 = 0x3f, - #[doc = "AOI1_OUT3 input is selected."] - VAL64 = 0x40, - #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL65 = 0x41, - #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL66 = 0x42, - #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL67 = 0x43, - #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL68 = 0x44, - #[doc = "CTimer3_MAT2 input is selected."] - VAL69 = 0x45, - #[doc = "CTimer3_MAT3 input is selected."] - VAL70 = 0x46, - #[doc = "CTimer4_MAT2 input is selected."] - VAL71 = 0x47, - #[doc = "CTimer4_MAT3 input is selected."] - VAL72 = 0x48, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL73 = 0x49, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL74 = 0x4a, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL75 = 0x4b, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL76 = 0x4c, - #[doc = "LPI2C2 Master End of Packet."] - VAL77 = 0x4d, - #[doc = "LPI2C2 Slave End of Packet."] - VAL78 = 0x4e, - #[doc = "LPI2C3 Master End of Packet."] - VAL79 = 0x4f, - #[doc = "LPI2C3 Slave End of Packet."] - VAL80 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, -} -impl FlexioTrigInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> FlexioTrigInp { - unsafe { core::mem::transmute(val & 0x7f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for FlexioTrigInp { - #[inline(always)] - fn from(val: u8) -> FlexioTrigInp { - FlexioTrigInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FlexioTrigInp) -> u8 { - FlexioTrigInp::to_bits(val) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FreqmeasRefInp(u8); -impl FreqmeasRefInp { - #[doc = "clk_in input is selected."] - pub const VAL1: Self = Self(0x01); - #[doc = "FRO_OSC_12M input is selected."] - pub const VAL2: Self = Self(0x02); - #[doc = "fro_hf_div input is selected."] - pub const VAL3: Self = Self(0x03); - #[doc = "clk_16k\\[1\\] input is selected."] - pub const VAL5: Self = Self(0x05); - #[doc = "SLOW_CLK input is selected."] - pub const VAL6: Self = Self(0x06); - #[doc = "FREQME_CLK_IN0 input is selected."] - pub const VAL7: Self = Self(0x07); - #[doc = "FREQME_CLK_IN1 input is selected input is selected."] - pub const VAL8: Self = Self(0x08); - #[doc = "AOI0_OUT0 input is selected."] - pub const VAL9: Self = Self(0x09); - #[doc = "AOI0_OUT1."] - pub const VAL10: Self = Self(0x0a); - #[doc = "PWM0_SM0_MUX_TRIG0."] - pub const VAL11: Self = Self(0x0b); - #[doc = "PWM0_SM0_MUX_TRIG1."] - pub const VAL12: Self = Self(0x0c); - #[doc = "PWM0_SM1_MUX_TRIG0."] - pub const VAL13: Self = Self(0x0d); - #[doc = "PWM0_SM1_MUX_TRIG1."] - pub const VAL14: Self = Self(0x0e); - #[doc = "PWM0_SM2_MUX_TRIG0."] - pub const VAL15: Self = Self(0x0f); - #[doc = "PWM0_SM2_MUX_TRIG1."] - pub const VAL16: Self = Self(0x10); - #[doc = "PWM0_SM3_MUX_TRIG0."] - pub const VAL17: Self = Self(0x11); - #[doc = "PWM0_SM3_MUX_TRIG1."] - pub const VAL18: Self = Self(0x12); - #[doc = "AOI1_OUT0 input is selected."] - pub const VAL32: Self = Self(0x20); - #[doc = "AOI1_OUT1 input is selected."] - pub const VAL33: Self = Self(0x21); - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - pub const VAL34: Self = Self(0x22); - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - pub const VAL35: Self = Self(0x23); - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - pub const VAL36: Self = Self(0x24); - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - pub const VAL37: Self = Self(0x25); - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - pub const VAL38: Self = Self(0x26); - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - pub const VAL39: Self = Self(0x27); - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - pub const VAL40: Self = Self(0x28); - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - pub const VAL41: Self = Self(0x29); -} -impl FreqmeasRefInp { - pub const fn from_bits(val: u8) -> FreqmeasRefInp { - Self(val & 0x7f) - } - pub const fn to_bits(self) -> u8 { - self.0 - } -} -impl core::fmt::Debug for FreqmeasRefInp { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - match self.0 { - 0x01 => f.write_str("VAL1"), - 0x02 => f.write_str("VAL2"), - 0x03 => f.write_str("VAL3"), - 0x05 => f.write_str("VAL5"), - 0x06 => f.write_str("VAL6"), - 0x07 => f.write_str("VAL7"), - 0x08 => f.write_str("VAL8"), - 0x09 => f.write_str("VAL9"), - 0x0a => f.write_str("VAL10"), - 0x0b => f.write_str("VAL11"), - 0x0c => f.write_str("VAL12"), - 0x0d => f.write_str("VAL13"), - 0x0e => f.write_str("VAL14"), - 0x0f => f.write_str("VAL15"), - 0x10 => f.write_str("VAL16"), - 0x11 => f.write_str("VAL17"), - 0x12 => f.write_str("VAL18"), - 0x20 => f.write_str("VAL32"), - 0x21 => f.write_str("VAL33"), - 0x22 => f.write_str("VAL34"), - 0x23 => f.write_str("VAL35"), - 0x24 => f.write_str("VAL36"), - 0x25 => f.write_str("VAL37"), - 0x26 => f.write_str("VAL38"), - 0x27 => f.write_str("VAL39"), - 0x28 => f.write_str("VAL40"), - 0x29 => f.write_str("VAL41"), - other => core::write!(f, "0x{:02X}", other), - } - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FreqmeasRefInp { - fn format(&self, f: defmt::Formatter) { - match self.0 { - 0x01 => defmt::write!(f, "VAL1"), - 0x02 => defmt::write!(f, "VAL2"), - 0x03 => defmt::write!(f, "VAL3"), - 0x05 => defmt::write!(f, "VAL5"), - 0x06 => defmt::write!(f, "VAL6"), - 0x07 => defmt::write!(f, "VAL7"), - 0x08 => defmt::write!(f, "VAL8"), - 0x09 => defmt::write!(f, "VAL9"), - 0x0a => defmt::write!(f, "VAL10"), - 0x0b => defmt::write!(f, "VAL11"), - 0x0c => defmt::write!(f, "VAL12"), - 0x0d => defmt::write!(f, "VAL13"), - 0x0e => defmt::write!(f, "VAL14"), - 0x0f => defmt::write!(f, "VAL15"), - 0x10 => defmt::write!(f, "VAL16"), - 0x11 => defmt::write!(f, "VAL17"), - 0x12 => defmt::write!(f, "VAL18"), - 0x20 => defmt::write!(f, "VAL32"), - 0x21 => defmt::write!(f, "VAL33"), - 0x22 => defmt::write!(f, "VAL34"), - 0x23 => defmt::write!(f, "VAL35"), - 0x24 => defmt::write!(f, "VAL36"), - 0x25 => defmt::write!(f, "VAL37"), - 0x26 => defmt::write!(f, "VAL38"), - 0x27 => defmt::write!(f, "VAL39"), - 0x28 => defmt::write!(f, "VAL40"), - 0x29 => defmt::write!(f, "VAL41"), - other => defmt::write!(f, "0x{:02X}", other), - } - } -} -impl From for FreqmeasRefInp { - #[inline(always)] - fn from(val: u8) -> FreqmeasRefInp { - FreqmeasRefInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FreqmeasRefInp) -> u8 { - FreqmeasRefInp::to_bits(val) - } -} -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct FreqmeasTarInp(u8); -impl FreqmeasTarInp { - #[doc = "clk_in input is selected."] - pub const VAL1: Self = Self(0x01); - #[doc = "FRO_OSC_12M input is selected."] - pub const VAL2: Self = Self(0x02); - #[doc = "fro_hf_div input is selected."] - pub const VAL3: Self = Self(0x03); - #[doc = "clk_16k\\[1\\] input is selected."] - pub const VAL5: Self = Self(0x05); - #[doc = "SLOW_CLK input is selected."] - pub const VAL6: Self = Self(0x06); - #[doc = "FREQME_CLK_IN0 input is selected."] - pub const VAL7: Self = Self(0x07); - #[doc = "FREQME_CLK_IN1 input is selected input is selected."] - pub const VAL8: Self = Self(0x08); - #[doc = "AOI0_OUT0 input is selected."] - pub const VAL9: Self = Self(0x09); - #[doc = "AOI0_OUT1."] - pub const VAL10: Self = Self(0x0a); - #[doc = "PWM0_SM0_MUX_TRIG0."] - pub const VAL11: Self = Self(0x0b); - #[doc = "PWM0_SM0_MUX_TRIG1."] - pub const VAL12: Self = Self(0x0c); - #[doc = "PWM0_SM1_MUX_TRIG0."] - pub const VAL13: Self = Self(0x0d); - #[doc = "PWM0_SM1_MUX_TRIG1."] - pub const VAL14: Self = Self(0x0e); - #[doc = "PWM0_SM2_MUX_TRIG0."] - pub const VAL15: Self = Self(0x0f); - #[doc = "PWM0_SM2_MUX_TRIG1."] - pub const VAL16: Self = Self(0x10); - #[doc = "PWM0_SM3_MUX_TRIG0."] - pub const VAL17: Self = Self(0x11); - #[doc = "PWM0_SM3_MUX_TRIG1."] - pub const VAL18: Self = Self(0x12); - #[doc = "AOI1_OUT0 input is selected."] - pub const VAL32: Self = Self(0x20); - #[doc = "AOI1_OUT1 input is selected."] - pub const VAL33: Self = Self(0x21); - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - pub const VAL34: Self = Self(0x22); - #[doc = "PWM1_SM0_MUX_TRIG1 input is selected."] - pub const VAL35: Self = Self(0x23); - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - pub const VAL36: Self = Self(0x24); - #[doc = "PWM1_SM1_MUX_TRIG1 input is selected."] - pub const VAL37: Self = Self(0x25); - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - pub const VAL38: Self = Self(0x26); - #[doc = "PWM1_SM2_MUX_TRIG1 input is selected."] - pub const VAL39: Self = Self(0x27); - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - pub const VAL40: Self = Self(0x28); - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - pub const VAL41: Self = Self(0x29); -} -impl FreqmeasTarInp { - pub const fn from_bits(val: u8) -> FreqmeasTarInp { - Self(val & 0x7f) - } - pub const fn to_bits(self) -> u8 { - self.0 - } -} -impl core::fmt::Debug for FreqmeasTarInp { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - match self.0 { - 0x01 => f.write_str("VAL1"), - 0x02 => f.write_str("VAL2"), - 0x03 => f.write_str("VAL3"), - 0x05 => f.write_str("VAL5"), - 0x06 => f.write_str("VAL6"), - 0x07 => f.write_str("VAL7"), - 0x08 => f.write_str("VAL8"), - 0x09 => f.write_str("VAL9"), - 0x0a => f.write_str("VAL10"), - 0x0b => f.write_str("VAL11"), - 0x0c => f.write_str("VAL12"), - 0x0d => f.write_str("VAL13"), - 0x0e => f.write_str("VAL14"), - 0x0f => f.write_str("VAL15"), - 0x10 => f.write_str("VAL16"), - 0x11 => f.write_str("VAL17"), - 0x12 => f.write_str("VAL18"), - 0x20 => f.write_str("VAL32"), - 0x21 => f.write_str("VAL33"), - 0x22 => f.write_str("VAL34"), - 0x23 => f.write_str("VAL35"), - 0x24 => f.write_str("VAL36"), - 0x25 => f.write_str("VAL37"), - 0x26 => f.write_str("VAL38"), - 0x27 => f.write_str("VAL39"), - 0x28 => f.write_str("VAL40"), - 0x29 => f.write_str("VAL41"), - other => core::write!(f, "0x{:02X}", other), - } - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FreqmeasTarInp { - fn format(&self, f: defmt::Formatter) { - match self.0 { - 0x01 => defmt::write!(f, "VAL1"), - 0x02 => defmt::write!(f, "VAL2"), - 0x03 => defmt::write!(f, "VAL3"), - 0x05 => defmt::write!(f, "VAL5"), - 0x06 => defmt::write!(f, "VAL6"), - 0x07 => defmt::write!(f, "VAL7"), - 0x08 => defmt::write!(f, "VAL8"), - 0x09 => defmt::write!(f, "VAL9"), - 0x0a => defmt::write!(f, "VAL10"), - 0x0b => defmt::write!(f, "VAL11"), - 0x0c => defmt::write!(f, "VAL12"), - 0x0d => defmt::write!(f, "VAL13"), - 0x0e => defmt::write!(f, "VAL14"), - 0x0f => defmt::write!(f, "VAL15"), - 0x10 => defmt::write!(f, "VAL16"), - 0x11 => defmt::write!(f, "VAL17"), - 0x12 => defmt::write!(f, "VAL18"), - 0x20 => defmt::write!(f, "VAL32"), - 0x21 => defmt::write!(f, "VAL33"), - 0x22 => defmt::write!(f, "VAL34"), - 0x23 => defmt::write!(f, "VAL35"), - 0x24 => defmt::write!(f, "VAL36"), - 0x25 => defmt::write!(f, "VAL37"), - 0x26 => defmt::write!(f, "VAL38"), - 0x27 => defmt::write!(f, "VAL39"), - 0x28 => defmt::write!(f, "VAL40"), - 0x29 => defmt::write!(f, "VAL41"), - other => defmt::write!(f, "0x{:02X}", other), - } - } -} -impl From for FreqmeasTarInp { - #[inline(always)] - fn from(val: u8) -> FreqmeasTarInp { - FreqmeasTarInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: FreqmeasTarInp) -> u8 { - FreqmeasTarInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Lpi2cTrigInp { - _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT0 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT1 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT0 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT1 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT0 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT1 input is selected."] - VAL14 = 0x0e, - #[doc = "LPTMR0 input is selected."] - VAL15 = 0x0f, - _RESERVED_10 = 0x10, - #[doc = "TRIG_IN0 input is selected."] - VAL17 = 0x11, - #[doc = "TRIG_IN1 input is selected."] - VAL18 = 0x12, - #[doc = "TRIG_IN2 input is selected."] - VAL19 = 0x13, - #[doc = "TRIG_IN3 input is selected."] - VAL20 = 0x14, - #[doc = "TRIG_IN4 input is selected."] - VAL21 = 0x15, - #[doc = "TRIG_IN5 input is selected."] - VAL22 = 0x16, - #[doc = "TRIG_IN6 input is selected."] - VAL23 = 0x17, - #[doc = "TRIG_IN7 input is selected."] - VAL24 = 0x18, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL25 = 0x19, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL26 = 0x1a, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL27 = 0x1b, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "WUU input is selected."] - VAL30 = 0x1e, - #[doc = "AOI1_OUT0 input is selected."] - VAL31 = 0x1f, - #[doc = "AOI1_OUT1 input is selected."] - VAL32 = 0x20, - #[doc = "AOI1_OUT2 input is selected."] - VAL33 = 0x21, - #[doc = "AOI1_OUT3 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer3_MAT2 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer3_MAT3 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer4_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer4_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "FlexIO CH0 input is selected."] - VAL39 = 0x27, - #[doc = "FlexIO CH1 input is selected."] - VAL40 = 0x28, - #[doc = "FlexIO CH2 input is selected."] - VAL41 = 0x29, - #[doc = "FlexIO CH3 input is selected."] - VAL42 = 0x2a, - _RESERVED_2b = 0x2b, - _RESERVED_2c = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - _RESERVED_31 = 0x31, - _RESERVED_32 = 0x32, - _RESERVED_33 = 0x33, - _RESERVED_34 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl Lpi2cTrigInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Lpi2cTrigInp { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Lpi2cTrigInp { - #[inline(always)] - fn from(val: u8) -> Lpi2cTrigInp { - Lpi2cTrigInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Lpi2cTrigInp) -> u8 { - Lpi2cTrigInp::to_bits(val) + fn from(val: AdcTrigTrigin) -> u8 { + AdcTrigTrigin::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LpspiTrigInp { +pub enum AoiInputInp { _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + Val1 = 0x01, + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + Val2 = 0x02, + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + Val3 = 0x03, + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + Val4 = 0x04, #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + Val5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + #[doc = "CTimer0_MAT0 input is selected."] + Val8 = 0x08, #[doc = "CTimer0_MAT1 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT2 input is selected."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT1 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT2 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT1 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT2 input is selected."] - VAL14 = 0x0e, - #[doc = "LPTMR0 input is selected."] - VAL15 = 0x0f, - _RESERVED_10 = 0x10, - #[doc = "TRIG_IN0 input is selected."] - VAL17 = 0x11, - #[doc = "TRIG_IN1 input is selected."] - VAL18 = 0x12, - #[doc = "TRIG_IN2 input is selected."] - VAL19 = 0x13, - #[doc = "TRIG_IN3 input is selected."] - VAL20 = 0x14, - #[doc = "TRIG_IN4 input is selected."] - VAL21 = 0x15, - #[doc = "TRIG_IN5 input is selected."] - VAL22 = 0x16, - #[doc = "TRIG_IN6 input is selected."] - VAL23 = 0x17, - #[doc = "TRIG_IN7 input is selected."] - VAL24 = 0x18, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL25 = 0x19, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL26 = 0x1a, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL27 = 0x1b, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "WUU input is selected."] - VAL30 = 0x1e, - #[doc = "AOI1_OUT0 input is selected."] - VAL31 = 0x1f, - #[doc = "AOI1_OUT1 input is selected."] - VAL32 = 0x20, - #[doc = "AOI1_OUT2 input is selected."] - VAL33 = 0x21, - #[doc = "AOI1_OUT3 input is selected."] - VAL34 = 0x22, - #[doc = "CTimer3_MAT2 input is selected."] - VAL35 = 0x23, - #[doc = "CTimer3_MAT3 input is selected."] - VAL36 = 0x24, - #[doc = "CTimer4_MAT2 input is selected."] - VAL37 = 0x25, - #[doc = "CTimer4_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "FlexIO CH0 input is selected."] - VAL39 = 0x27, - #[doc = "FlexIO CH1 input is selected."] - VAL40 = 0x28, - #[doc = "FlexIO CH2 input is selected."] - VAL41 = 0x29, - #[doc = "FlexIO CH3 input is selected."] - VAL42 = 0x2a, - _RESERVED_2b = 0x2b, - _RESERVED_2c = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - _RESERVED_31 = 0x31, - _RESERVED_32 = 0x32, - _RESERVED_33 = 0x33, - _RESERVED_34 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl LpspiTrigInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> LpspiTrigInp { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for LpspiTrigInp { - #[inline(always)] - fn from(val: u8) -> LpspiTrigInp { - LpspiTrigInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: LpspiTrigInp) -> u8 { - LpspiTrigInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LpuartInp { - _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + Val9 = 0x09, #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, + Val10 = 0x0a, #[doc = "CTimer0_MAT3 input is selected."] - VAL10 = 0x0a, + Val11 = 0x0b, + #[doc = "CTimer1_MAT0 input is selected."] + Val12 = 0x0c, + #[doc = "CTimer1_MAT1 input is selected."] + Val13 = 0x0d, #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, + Val14 = 0x0e, #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + Val15 = 0x0f, + #[doc = "CTimer2_MAT0 input is selected."] + Val16 = 0x10, + #[doc = "CTimer2_MAT1 input is selected."] + Val17 = 0x11, #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, + Val18 = 0x12, #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, + Val19 = 0x13, #[doc = "LPTMR0 input is selected."] - VAL15 = 0x0f, - _RESERVED_10 = 0x10, - #[doc = "TRIG_IN0 input is selected."] - VAL17 = 0x11, - #[doc = "TRIG_IN1 input is selected."] - VAL18 = 0x12, - #[doc = "TRIG_IN2 input is selected."] - VAL19 = 0x13, - #[doc = "TRIG_IN3 input is selected."] - VAL20 = 0x14, - #[doc = "TRIG_IN4 input is selected."] - VAL21 = 0x15, - #[doc = "TRIG_IN5 input is selected."] - VAL22 = 0x16, - #[doc = "TRIG_IN6 input is selected."] - VAL23 = 0x17, - #[doc = "TRIG_IN7 input is selected."] - VAL24 = 0x18, - #[doc = "TRIG_IN8 input is selected."] - VAL25 = 0x19, - #[doc = "TRIG_IN9 input is selected."] - VAL26 = 0x1a, - #[doc = "TRIG_IN10 input is selected."] - VAL27 = 0x1b, - #[doc = "TRIG_IN11 input is selected."] - VAL28 = 0x1c, - #[doc = "GPIO0 Pin Event Trig 0 input is selected."] - VAL29 = 0x1d, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL30 = 0x1e, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL31 = 0x1f, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL32 = 0x20, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL33 = 0x21, - #[doc = "WUU selected."] - VAL34 = 0x22, - #[doc = "USB0 ipp_ind_uart_rxd_usbmux input is selected."] - VAL35 = 0x23, - #[doc = "AOI1_OUT0 input is selected."] - VAL36 = 0x24, - #[doc = "AOI1_OUT1 input is selected."] - VAL37 = 0x25, - #[doc = "AOI1_OUT2 input is selected."] - VAL38 = 0x26, - #[doc = "AOI1_OUT3 input is selected."] - VAL39 = 0x27, - #[doc = "CTimer3_MAT2 input is selected."] - VAL40 = 0x28, - #[doc = "CTimer3_MAT3 input is selected."] - VAL41 = 0x29, - #[doc = "CTimer4_MAT2 input is selected."] - VAL42 = 0x2a, - #[doc = "CTimer4_MAT3 input is selected."] - VAL43 = 0x2b, - #[doc = "FlexIO CH0 input is selected."] - VAL44 = 0x2c, - #[doc = "FlexIO CH1 input is selected."] - VAL45 = 0x2d, - #[doc = "FlexIO CH2 input is selected."] - VAL46 = 0x2e, - #[doc = "FlexIO CH3 input is selected."] - VAL47 = 0x2f, - _RESERVED_30 = 0x30, - _RESERVED_31 = 0x31, - _RESERVED_32 = 0x32, - _RESERVED_33 = 0x33, - _RESERVED_34 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - _RESERVED_3e = 0x3e, - _RESERVED_3f = 0x3f, -} -impl LpuartInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> LpuartInp { - unsafe { core::mem::transmute(val & 0x3f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for LpuartInp { - #[inline(always)] - fn from(val: u8) -> LpuartInp { - LpuartInp::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: LpuartInp) -> u8 { - LpuartInp::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Pwm0extClkTrigin { - _RESERVED_0 = 0x0, - #[doc = "clk_16k\\[1\\] input is selected."] - VAL1 = 0x01, - #[doc = "clk_in input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT0 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT1 input is selected."] - VAL4 = 0x04, - #[doc = "EXTTRIG_IN0 input is selected."] - VAL5 = 0x05, - #[doc = "EXTTRIG_IN7 input is selected."] - VAL6 = 0x06, - #[doc = "AOI1_OUT0 input is selected."] - VAL7 = 0x07, - #[doc = "AOI1_OUT1 input is selected."] - VAL8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, -} -impl Pwm0extClkTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwm0extClkTrigin { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwm0extClkTrigin { - #[inline(always)] - fn from(val: u8) -> Pwm0extClkTrigin { - Pwm0extClkTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwm0extClkTrigin) -> u8 { - Pwm0extClkTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Pwm1extClkTrigin { - _RESERVED_0 = 0x0, - #[doc = "clk_16k\\[1\\] input is selected."] - VAL1 = 0x01, - #[doc = "clk_in input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT0 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT1 input is selected."] - VAL4 = 0x04, - #[doc = "EXTTRIG_IN0 input is selected."] - VAL5 = 0x05, - #[doc = "EXTTRIG_IN7 input is selected."] - VAL6 = 0x06, - #[doc = "AOI1_OUT0 input is selected."] - VAL7 = 0x07, - #[doc = "AOI1_OUT1 input is selected."] - VAL8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, -} -impl Pwm1extClkTrigin { - #[inline(always)] - pub const fn from_bits(val: u8) -> Pwm1extClkTrigin { - unsafe { core::mem::transmute(val & 0x0f) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Pwm1extClkTrigin { - #[inline(always)] - fn from(val: u8) -> Pwm1extClkTrigin { - Pwm1extClkTrigin::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Pwm1extClkTrigin) -> u8 { - Pwm1extClkTrigin::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Qdc0phaseaInp { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, - #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, - #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, - #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, - #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, + Val20 = 0x14, + _RESERVED_15 = 0x15, _RESERVED_16 = 0x16, _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + _RESERVED_19 = 0x19, + _RESERVED_1a = 0x1a, + _RESERVED_1b = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + _RESERVED_1e = 0x1e, + _RESERVED_1f = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + Val35 = 0x23, #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + Val36 = 0x24, #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + Val37 = 0x25, #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + Val38 = 0x26, #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + Val39 = 0x27, #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + Val40 = 0x28, #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + Val41 = 0x29, #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, + Val42 = 0x2a, #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, + Val43 = 0x2b, #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, + Val44 = 0x2c, #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, + Val45 = 0x2d, #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + Val46 = 0x2e, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val47 = 0x2f, #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + Val48 = 0x30, #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + Val49 = 0x31, #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + Val50 = 0x32, #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, + Val51 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + #[doc = "CTimer3_MAT0 input is selected."] + Val56 = 0x38, + #[doc = "CTimer3_MAT1 input is selected."] + Val57 = 0x39, #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, + Val58 = 0x3a, #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, + Val59 = 0x3b, + #[doc = "CTimer4_MAT0 input is selected."] + Val60 = 0x3c, + #[doc = "CTimer4_MAT1 input is selected."] + Val61 = 0x3d, #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, + Val62 = 0x3e, #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, + Val63 = 0x3f, + #[doc = "FlexIO CH0 input is selected."] + Val64 = 0x40, + #[doc = "FlexIO CH1 input is selected."] + Val65 = 0x41, + #[doc = "FlexIO CH2 input is selected."] + Val66 = 0x42, + #[doc = "FlexIO CH3 input is selected."] + Val67 = 0x43, + _RESERVED_44 = 0x44, + _RESERVED_45 = 0x45, _RESERVED_46 = 0x46, _RESERVED_47 = 0x47, _RESERVED_48 = 0x48, @@ -5830,11 +1376,16 @@ pub enum Qdc0phaseaInp { _RESERVED_5e = 0x5e, _RESERVED_5f = 0x5f, _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val97 = 0x61, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val98 = 0x62, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val99 = 0x63, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val100 = 0x64, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val101 = 0x65, _RESERVED_66 = 0x66, _RESERVED_67 = 0x67, _RESERVED_68 = 0x68, @@ -5862,9 +1413,9 @@ pub enum Qdc0phaseaInp { _RESERVED_7e = 0x7e, _RESERVED_7f = 0x7f, } -impl Qdc0phaseaInp { +impl AoiInputInp { #[inline(always)] - pub const fn from_bits(val: u8) -> Qdc0phaseaInp { + pub const fn from_bits(val: u8) -> AoiInputInp { unsafe { core::mem::transmute(val & 0x7f) } } #[inline(always)] @@ -5872,797 +1423,2570 @@ impl Qdc0phaseaInp { unsafe { core::mem::transmute(self) } } } -impl From for Qdc0phaseaInp { +impl From for AoiInputInp { #[inline(always)] - fn from(val: u8) -> Qdc0phaseaInp { - Qdc0phaseaInp::from_bits(val) + fn from(val: u8) -> AoiInputInp { + AoiInputInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Qdc0phaseaInp) -> u8 { - Qdc0phaseaInp::to_bits(val) + fn from(val: AoiInputInp) -> u8 { + AoiInputInp::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Qdc0phasebInp { +pub enum CmpTrigTrigin { _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, + _RESERVED_1 = 0x01, + #[doc = "AOI0_OUT0 input is selected."] + Val2 = 0x02, + #[doc = "AOI0_OUT1 input is selected."] + Val3 = 0x03, + #[doc = "AOI0_OUT2 input is selected."] + Val4 = 0x04, + #[doc = "AOI0_OUT3 input is selected."] + Val5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + #[doc = "CTimer0_MAT0 input is selected."] + Val8 = 0x08, + #[doc = "CTimer0_MAT2 input is selected."] + Val9 = 0x09, + #[doc = "CTimer1_MAT0."] + Val10 = 0x0a, + #[doc = "CTimer1_MAT2 input is selected."] + Val11 = 0x0b, + #[doc = "CTimer2_MAT0 input is selected."] + Val12 = 0x0c, + #[doc = "CTimer2_MAT2 input is selected."] + Val13 = 0x0d, + #[doc = "LPTMR0 input is selected."] + Val14 = 0x0e, + _RESERVED_f = 0x0f, + _RESERVED_10 = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val25 = 0x19, + #[doc = "GPIO1 Pin Event Trig 0 input is selected."] + Val26 = 0x1a, + #[doc = "GPIO2 Pin Event Trig 0 input is selected."] + Val27 = 0x1b, + #[doc = "GPIO3 Pin Event Trig 0 input is selected."] + Val28 = 0x1c, + #[doc = "GPIO4 Pin Event Trig 0 input is selected."] + Val29 = 0x1d, + #[doc = "WUU input is selected."] + Val30 = 0x1e, + _RESERVED_1f = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + _RESERVED_23 = 0x23, + _RESERVED_24 = 0x24, + _RESERVED_25 = 0x25, + _RESERVED_26 = 0x26, + #[doc = "CTimer3_MAT0 input is selected."] + Val39 = 0x27, + #[doc = "CTimer3_MAT1 input is selected."] + Val40 = 0x28, + #[doc = "CTimer4_MAT0 input is selected."] + Val41 = 0x29, + #[doc = "CTimer4_MAT1 input is selected."] + Val42 = 0x2a, + _RESERVED_2b = 0x2b, + _RESERVED_2c = 0x2c, + _RESERVED_2d = 0x2d, + _RESERVED_2e = 0x2e, + _RESERVED_2f = 0x2f, + _RESERVED_30 = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val56 = 0x38, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val57 = 0x39, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val58 = 0x3a, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val59 = 0x3b, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val60 = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, +} +impl CmpTrigTrigin { + #[inline(always)] + pub const fn from_bits(val: u8) -> CmpTrigTrigin { + unsafe { core::mem::transmute(val & 0x3f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for CmpTrigTrigin { + #[inline(always)] + fn from(val: u8) -> CmpTrigTrigin { + CmpTrigTrigin::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: CmpTrigTrigin) -> u8 { + CmpTrigTrigin::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Ctimer0capInp(u8); +impl Ctimer0capInp { + #[doc = "CT_INP0 input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "CT_INP1 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "CT_INP2 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "CT_INP3 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "CT_INP4 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CT_INP5 input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CT_INP6 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "CT_INP7 input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "CT_INP8 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CT_INP9 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CT_INP10 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CT_INP12 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CT_INP13 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "CT_INP14 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "CT_INP15 input is selected."] + pub const Val16: Self = Self(0x10); + #[doc = "CT_INP16 input is selected."] + pub const Val17: Self = Self(0x11); + #[doc = "CT_INP17 input is selected."] + pub const Val18: Self = Self(0x12); + #[doc = "CT_INP18 input is selected."] + pub const Val19: Self = Self(0x13); + #[doc = "CT_INP19 input is selected."] + pub const Val20: Self = Self(0x14); + #[doc = "AOI0_OUT0 input is selected."] + pub const Val22: Self = Self(0x16); + #[doc = "AOI0_OUT1 input is selected."] + pub const Val23: Self = Self(0x17); + #[doc = "AOI0_OUT2 input is selected."] + pub const Val24: Self = Self(0x18); + #[doc = "AOI0_OUT3 input is selected."] + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT is selected."] + pub const Val30: Self = Self(0x1e); + #[doc = "CTimer1_MAT1 input is selected."] + pub const Val33: Self = Self(0x21); + #[doc = "CTimer1_MAT2 input is selected."] + pub const Val34: Self = Self(0x22); + #[doc = "CTimer1_MAT3 input is selected."] + pub const Val35: Self = Self(0x23); + #[doc = "CTimer2_MAT1 input is selected."] + pub const Val36: Self = Self(0x24); + #[doc = "CTimer2_MAT2 input is selected."] + pub const Val37: Self = Self(0x25); + #[doc = "CTimer2_MAT3 input is selected."] + pub const Val38: Self = Self(0x26); + #[doc = "LPI2C0 Master End of Packet input is selected."] + pub const Val48: Self = Self(0x30); + #[doc = "LPI2C0 Slave End of Packet input is selected."] + pub const Val49: Self = Self(0x31); + #[doc = "LPI2C1 Master End of Packet input is selected."] + pub const Val50: Self = Self(0x32); + #[doc = "LPI2C1 Slave End of Packet input is selected."] + pub const Val51: Self = Self(0x33); + #[doc = "LPSPI0 End of Frame input is selected."] + pub const Val52: Self = Self(0x34); + #[doc = "LPSPI0 Received Data Word input is selected."] + pub const Val53: Self = Self(0x35); + #[doc = "LPSPI1 End of Frame input is selected."] + pub const Val54: Self = Self(0x36); + #[doc = "LPSPI1 Received Data Word input is selected."] + pub const Val55: Self = Self(0x37); + #[doc = "LPUART0 Received Data Word input is selected."] + pub const Val56: Self = Self(0x38); + #[doc = "LPUART0 Transmitted Data Word input is selected."] + pub const Val57: Self = Self(0x39); + #[doc = "LPUART0 Receive Line Idle input is selected."] + pub const Val58: Self = Self(0x3a); + #[doc = "LPUART1 Received Data Word input is selected."] + pub const Val59: Self = Self(0x3b); + #[doc = "LPUART1 Transmitted Data Word input is selected."] + pub const Val60: Self = Self(0x3c); + #[doc = "LPUART1 Receive Line Idle input is selected."] + pub const Val61: Self = Self(0x3d); + #[doc = "LPUART2 Received Data Word input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "LPUART2 Transmitted Data Word input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "LPUART2 Receive Line Idle input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "LPUART3 Received Data Word input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "LPUART3 Transmitted Data Word input is selected."] + pub const Val66: Self = Self(0x42); + #[doc = "LPUART3 Receive Line Idle input is selected."] + pub const Val67: Self = Self(0x43); + #[doc = "LPUART4 Received Data Word input is selected."] + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word input is selected."] + pub const Val69: Self = Self(0x45); + #[doc = "LPUART4 Receive Line Idle input is selected."] + pub const Val70: Self = Self(0x46); + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + pub const Val75: Self = Self(0x4b); + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + pub const Val76: Self = Self(0x4c); + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + pub const Val77: Self = Self(0x4d); + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer3_MAT1 input is selected."] + pub const Val79: Self = Self(0x4f); + #[doc = "CTimer3_MAT2 input is selected."] + pub const Val80: Self = Self(0x50); + #[doc = "CTimer3_MAT3 input is selected."] + pub const Val81: Self = Self(0x51); + #[doc = "CTimer4_MAT1 input is selected."] + pub const Val82: Self = Self(0x52); + #[doc = "CTimer4_MAT2 input is selected."] + pub const Val83: Self = Self(0x53); + #[doc = "CTimer4_MAT3 input is selected."] + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet input is selected."] + pub const Val94: Self = Self(0x5e); + #[doc = "LPI2C2 Slave End of Packet input is selected."] + pub const Val95: Self = Self(0x5f); + #[doc = "LPI2C3 Master End of Packet input is selected."] + pub const Val96: Self = Self(0x60); + #[doc = "LPI2C3 Slave End of Packet input is selected."] + pub const Val97: Self = Self(0x61); + #[doc = "LPUART5 Received Data Word input is selected."] + pub const Val98: Self = Self(0x62); + #[doc = "LPUART5 Transmitted Data Word input is selected."] + pub const Val99: Self = Self(0x63); + #[doc = "LPUART5 Receive Line Idle input is selected."] + pub const Val100: Self = Self(0x64); + #[doc = "TRIG_IN0 input is selected."] + pub const Val113: Self = Self(0x71); + #[doc = "TRIG_IN1 input is selected."] + pub const Val114: Self = Self(0x72); + #[doc = "TRIG_IN2 input is selected."] + pub const Val115: Self = Self(0x73); + #[doc = "TRIG_IN3 input is selected."] + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 input is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 input is selected."] + pub const Val118: Self = Self(0x76); + #[doc = "TRIG_IN6 input is selected."] + pub const Val119: Self = Self(0x77); + #[doc = "TRIG_IN7 input is selected."] + pub const Val120: Self = Self(0x78); + #[doc = "TRIG_IN8 input is selected."] + pub const Val121: Self = Self(0x79); + #[doc = "TRIG_IN9 input is selected."] + pub const Val122: Self = Self(0x7a); + #[doc = "TRIG_IN10 input is selected."] + pub const Val123: Self = Self(0x7b); + #[doc = "TRIG_IN11 input is selected."] + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); +} +impl Ctimer0capInp { + pub const fn from_bits(val: u8) -> Ctimer0capInp { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for Ctimer0capInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctimer0capInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Ctimer0capInp { + #[inline(always)] + fn from(val: u8) -> Ctimer0capInp { + Ctimer0capInp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Ctimer0capInp) -> u8 { + Ctimer0capInp::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Ctimer1capInp(u8); +impl Ctimer1capInp { + #[doc = "CT_INP0 input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "CT_INP1 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "CT_INP2 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "CT_INP3 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "CT_INP4 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CT_INP5 input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CT_INP6 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "CT_INP7 input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "CT_INP8 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CT_INP9 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CT_INP10 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CT_INP12 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CT_INP13 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "CT_INP14 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "CT_INP15 input is selected."] + pub const Val16: Self = Self(0x10); + #[doc = "CT_INP16 input is selected."] + pub const Val17: Self = Self(0x11); + #[doc = "CT_INP17 input is selected."] + pub const Val18: Self = Self(0x12); + #[doc = "CT_INP18 input is selected."] + pub const Val19: Self = Self(0x13); + #[doc = "CT_INP19 input is selected."] + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + pub const Val29: Self = Self(0x1d); #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + pub const Val30: Self = Self(0x1e); + #[doc = "CTimer0_MAT1 input is selected."] + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + pub const Val34: Self = Self(0x22); + #[doc = "CTimer0_MAT3 input is selected."] + pub const Val35: Self = Self(0x23); + #[doc = "CTimer2_MAT1 input is selected."] + pub const Val36: Self = Self(0x24); #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, + pub const Val37: Self = Self(0x25); #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + pub const Val38: Self = Self(0x26); + #[doc = "LPI2C0 Master End of Packet input is selected."] + pub const Val48: Self = Self(0x30); + #[doc = "LPI2C0 Slave End of Packet input is selected."] + pub const Val49: Self = Self(0x31); + #[doc = "LPI2C1 Master End of Packet input is selected."] + pub const Val50: Self = Self(0x32); + #[doc = "LPI2C1 Slave End of Packet input is selected."] + pub const Val51: Self = Self(0x33); + #[doc = "LPSPI0 End of Frame input is selected."] + pub const Val52: Self = Self(0x34); + #[doc = "LPSPI0 Received Data Word input is selected."] + pub const Val53: Self = Self(0x35); + #[doc = "LPSPI1 End of Frame input is selected."] + pub const Val54: Self = Self(0x36); + #[doc = "LPSPI1 Received Data Word input is selected."] + pub const Val55: Self = Self(0x37); + #[doc = "LPUART0 Received Data Word input is selected."] + pub const Val56: Self = Self(0x38); + #[doc = "LPUART0 Transmitted Data Word input is selected."] + pub const Val57: Self = Self(0x39); + #[doc = "LPUART0 Receive Line Idle input is selected."] + pub const Val58: Self = Self(0x3a); + #[doc = "LPUART1 Received Data Word input is selected."] + pub const Val59: Self = Self(0x3b); + #[doc = "LPUART1 Transmitted Data Word input is selected."] + pub const Val60: Self = Self(0x3c); + #[doc = "LPUART1 Receive Line Idle input is selected."] + pub const Val61: Self = Self(0x3d); + #[doc = "LPUART2 Received Data Word input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "LPUART2 Transmitted Data Word input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "LPUART2 Receive Line Idle input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "LPUART3 Received Data Word input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "LPUART3 Transmitted Data Word input is selected."] + pub const Val66: Self = Self(0x42); + #[doc = "LPUART3 Receive Line Idle input is selected."] + pub const Val67: Self = Self(0x43); + #[doc = "LPUART4 Received Data Word input is selected."] + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word input is selected."] + pub const Val69: Self = Self(0x45); + #[doc = "LPUART4 Receive Line Idle input is selected."] + pub const Val70: Self = Self(0x46); + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + pub const Val75: Self = Self(0x4b); + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + pub const Val76: Self = Self(0x4c); + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + pub const Val77: Self = Self(0x4d); + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer3_MAT1 is selected."] + pub const Val79: Self = Self(0x4f); + #[doc = "CTimer3_MAT2 input is selected."] + pub const Val80: Self = Self(0x50); + #[doc = "CTimer3_MAT3 input is selected."] + pub const Val81: Self = Self(0x51); + #[doc = "CTimer4_MAT1 input is selected."] + pub const Val82: Self = Self(0x52); + #[doc = "CTimer4_MAT2 input is selected."] + pub const Val83: Self = Self(0x53); + #[doc = "CTimer4_MAT3 input is selected."] + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet input is selected."] + pub const Val94: Self = Self(0x5e); + #[doc = "LPI2C2 Slave End of Packet input is selected."] + pub const Val95: Self = Self(0x5f); + #[doc = "LPI2C3 Master End of Packet input is selected."] + pub const Val96: Self = Self(0x60); + #[doc = "LPI2C3 Slave End of Packet input is selected."] + pub const Val97: Self = Self(0x61); + #[doc = "LPUART5 Received Data Word input is selected."] + pub const Val98: Self = Self(0x62); + #[doc = "LPUART5 Transmitted Data Word input is selected."] + pub const Val99: Self = Self(0x63); + #[doc = "LPUART5 Receive Line Idle input is selected."] + pub const Val100: Self = Self(0x64); #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + pub const Val113: Self = Self(0x71); #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + pub const Val114: Self = Self(0x72); #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + pub const Val115: Self = Self(0x73); #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + pub const Val116: Self = Self(0x74); #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + pub const Val117: Self = Self(0x75); #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + pub const Val118: Self = Self(0x76); #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + pub const Val119: Self = Self(0x77); #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, + pub const Val120: Self = Self(0x78); #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, + pub const Val121: Self = Self(0x79); #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, + pub const Val122: Self = Self(0x7a); #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, + pub const Val123: Self = Self(0x7b); #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); +} +impl Ctimer1capInp { + pub const fn from_bits(val: u8) -> Ctimer1capInp { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for Ctimer1capInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctimer1capInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Ctimer1capInp { + #[inline(always)] + fn from(val: u8) -> Ctimer1capInp { + Ctimer1capInp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Ctimer1capInp) -> u8 { + Ctimer1capInp::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Ctimer2capInp(u8); +impl Ctimer2capInp { + #[doc = "CT_INP0 input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "CT_INP1 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "CT_INP2 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "CT_INP3 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "CT_INP4 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CT_INP5 input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CT_INP6 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "CT_INP7 input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "CT_INP8 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CT_INP9 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CT_INP10 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CT_INP12 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CT_INP13 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "CT_INP14 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "CT_INP15 input is selected."] + pub const Val16: Self = Self(0x10); + #[doc = "CT_INP16 input is selected."] + pub const Val17: Self = Self(0x11); + #[doc = "CT_INP17 input is selected."] + pub const Val18: Self = Self(0x12); + #[doc = "CT_INP18 input is selected."] + pub const Val19: Self = Self(0x13); + #[doc = "CT_INP19 input is selected."] + pub const Val20: Self = Self(0x14); + #[doc = "AOI0_OUT0 input is selected."] + pub const Val22: Self = Self(0x16); + #[doc = "AOI0_OUT1 input is selected."] + pub const Val23: Self = Self(0x17); + #[doc = "AOI0_OUT2 input is selected."] + pub const Val24: Self = Self(0x18); + #[doc = "AOI0_OUT3 input is selected."] + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT is selected."] + pub const Val30: Self = Self(0x1e); + #[doc = "CTimer0_MAT1 input is selected."] + pub const Val33: Self = Self(0x21); + #[doc = "CTimer0_MAT2 input is selected."] + pub const Val34: Self = Self(0x22); + #[doc = "CTimer0_MAT3 input is selected."] + pub const Val35: Self = Self(0x23); + #[doc = "CTimer1_MAT1 input is selected."] + pub const Val36: Self = Self(0x24); + #[doc = "CTimer1_MAT2 input is selected."] + pub const Val37: Self = Self(0x25); + #[doc = "CTimer1_MAT3 input is selected."] + pub const Val38: Self = Self(0x26); + #[doc = "LPI2C0 Master End of Packet input is selected."] + pub const Val48: Self = Self(0x30); + #[doc = "LPI2C0 Slave End of Packet input is selected."] + pub const Val49: Self = Self(0x31); + #[doc = "LPI2C1 Master End of Packet input is selected."] + pub const Val50: Self = Self(0x32); + #[doc = "LPI2C1 Slave End of Packet input is selected."] + pub const Val51: Self = Self(0x33); + #[doc = "LPSPI0 End of Frame input is selected."] + pub const Val52: Self = Self(0x34); + #[doc = "LPSPI0 Received Data Word input is selected."] + pub const Val53: Self = Self(0x35); + #[doc = "LPSPI1 End of Frame input is selected."] + pub const Val54: Self = Self(0x36); + #[doc = "LPSPI1 Received Data Word input is selected."] + pub const Val55: Self = Self(0x37); + #[doc = "LPUART0 Received Data Word input is selected."] + pub const Val56: Self = Self(0x38); + #[doc = "LPUART0 Transmitted Data Word input is selected."] + pub const Val57: Self = Self(0x39); + #[doc = "LPUART0 Receive Line Idle input is selected."] + pub const Val58: Self = Self(0x3a); + #[doc = "LPUART1 Received Data Word input is selected."] + pub const Val59: Self = Self(0x3b); + #[doc = "LPUART1 Transmitted Data Word input is selected."] + pub const Val60: Self = Self(0x3c); + #[doc = "LPUART1 Receive Line Idle input is selected."] + pub const Val61: Self = Self(0x3d); + #[doc = "LPUART2 Received Data Word input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "LPUART2 Transmitted Data Word input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "LPUART2 Receive Line Idle input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "LPUART3 Received Data Word input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "LPUART3 Transmitted Data Word input is selected."] + pub const Val66: Self = Self(0x42); + #[doc = "LPUART3 Receive Line Idle input is selected."] + pub const Val67: Self = Self(0x43); + #[doc = "LPUART4 Received Data Word input is selected."] + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word input is selected."] + pub const Val69: Self = Self(0x45); + #[doc = "LPUART4 Receive Line Idle input is selected."] + pub const Val70: Self = Self(0x46); + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + pub const Val75: Self = Self(0x4b); + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + pub const Val76: Self = Self(0x4c); + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + pub const Val77: Self = Self(0x4d); + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer3_MAT1 input is selected."] + pub const Val79: Self = Self(0x4f); #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, + pub const Val80: Self = Self(0x50); #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, + pub const Val81: Self = Self(0x51); + #[doc = "CTimer4_MAT1 input is selected."] + pub const Val82: Self = Self(0x52); #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, + pub const Val83: Self = Self(0x53); #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet input is selected."] + pub const Val94: Self = Self(0x5e); + #[doc = "LPI2C2 Slave End of Packet input is selected."] + pub const Val95: Self = Self(0x5f); + #[doc = "LPI2C3 Master End of Packet input is selected."] + pub const Val96: Self = Self(0x60); + #[doc = "LPI2C3 Slave End of Packet input is selected."] + pub const Val97: Self = Self(0x61); + #[doc = "LPUART5 Received Data Word input is selected."] + pub const Val98: Self = Self(0x62); + #[doc = "LPUART5 Transmitted Data Word input is selected."] + pub const Val99: Self = Self(0x63); + #[doc = "LPUART5 Receive Line Idle input is selected."] + pub const Val100: Self = Self(0x64); + #[doc = "TRIG_IN0 input is selected."] + pub const Val113: Self = Self(0x71); + #[doc = "TRIG_IN1 input is selected."] + pub const Val114: Self = Self(0x72); + #[doc = "TRIG_IN2 input is selected."] + pub const Val115: Self = Self(0x73); + #[doc = "TRIG_IN3 input is selected."] + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 input is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 input is selected."] + pub const Val118: Self = Self(0x76); + #[doc = "TRIG_IN6 input is selected."] + pub const Val119: Self = Self(0x77); + #[doc = "TRIG_IN7 input is selected."] + pub const Val120: Self = Self(0x78); + #[doc = "TRIG_IN8 input is selected."] + pub const Val121: Self = Self(0x79); + #[doc = "TRIG_IN9 input is selected."] + pub const Val122: Self = Self(0x7a); + #[doc = "TRIG_IN10 input is selected."] + pub const Val123: Self = Self(0x7b); + #[doc = "TRIG_IN11 input is selected."] + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } -impl Qdc0phasebInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Qdc0phasebInp { - unsafe { core::mem::transmute(val & 0x7f) } +impl Ctimer2capInp { + pub const fn from_bits(val: u8) -> Ctimer2capInp { + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 } } -impl From for Qdc0phasebInp { +impl core::fmt::Debug for Ctimer2capInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctimer2capInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Ctimer2capInp { #[inline(always)] - fn from(val: u8) -> Qdc0phasebInp { - Qdc0phasebInp::from_bits(val) + fn from(val: u8) -> Ctimer2capInp { + Ctimer2capInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Qdc0phasebInp) -> u8 { - Qdc0phasebInp::to_bits(val) + fn from(val: Ctimer2capInp) -> u8 { + Ctimer2capInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Qdc1phaseaInp { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Ctimer3capInp(u8); +impl Ctimer3capInp { + #[doc = "CT_INP0 input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "CT_INP1 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "CT_INP2 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "CT_INP3 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "CT_INP4 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CT_INP5 input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CT_INP6 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "CT_INP7 input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "CT_INP8 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CT_INP9 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CT_INP10 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CT_INP12 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CT_INP13 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "CT_INP14 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "CT_INP15 input is selected."] + pub const Val16: Self = Self(0x10); + #[doc = "CT_INP16 input is selected."] + pub const Val17: Self = Self(0x11); + #[doc = "CT_INP17 input is selected."] + pub const Val18: Self = Self(0x12); + #[doc = "CT_INP18 input is selected."] + pub const Val19: Self = Self(0x13); + #[doc = "CT_INP19 input is selected."] + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + pub const Val29: Self = Self(0x1d); #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + pub const Val30: Self = Self(0x1e); + #[doc = "CTimer0_MAT1 input is selected."] + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, + pub const Val34: Self = Self(0x22); + #[doc = "CTimer0_MAT3 input is selected."] + pub const Val35: Self = Self(0x23); + #[doc = "CTimer1_MAT1 input is selected."] + pub const Val36: Self = Self(0x24); #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, + pub const Val37: Self = Self(0x25); #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + pub const Val38: Self = Self(0x26); + #[doc = "LPI2C0 Master End of Packet input is selected."] + pub const Val48: Self = Self(0x30); + #[doc = "LPI2C0 Slave End of Packet input is selected."] + pub const Val49: Self = Self(0x31); + #[doc = "LPI2C1 Master End of Packet input is selected."] + pub const Val50: Self = Self(0x32); + #[doc = "LPI2C1 Slave End of Packet input is selected."] + pub const Val51: Self = Self(0x33); + #[doc = "LPSPI0 End of Frame input is selected."] + pub const Val52: Self = Self(0x34); + #[doc = "LPSPI0 Received Data Word input is selected."] + pub const Val53: Self = Self(0x35); + #[doc = "LPSPI1 End of Frame input is selected."] + pub const Val54: Self = Self(0x36); + #[doc = "LPSPI1 Received Data Word input is selected."] + pub const Val55: Self = Self(0x37); + #[doc = "LPUART0 Received Data Word input is selected."] + pub const Val56: Self = Self(0x38); + #[doc = "LPUART0 Transmitted Data Word input is selected."] + pub const Val57: Self = Self(0x39); + #[doc = "LPUART0 Receive Line Idle input is selected."] + pub const Val58: Self = Self(0x3a); + #[doc = "LPUART1 Received Data Word input is selected."] + pub const Val59: Self = Self(0x3b); + #[doc = "LPUART1 Transmitted Data Word input is selected."] + pub const Val60: Self = Self(0x3c); + #[doc = "LPUART1 Receive Line Idle input is selected."] + pub const Val61: Self = Self(0x3d); + #[doc = "LPUART2 Received Data Word input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "LPUART2 Transmitted Data Word input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "LPUART2 Receive Line Idle input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "LPUART3 Received Data Word input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "LPUART3 Transmitted Data Word input is selected."] + pub const Val66: Self = Self(0x42); + #[doc = "LPUART3 Receive Line Idle input is selected."] + pub const Val67: Self = Self(0x43); + #[doc = "LPUART4 Received Data Word input is selected."] + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word input is selected."] + pub const Val69: Self = Self(0x45); + #[doc = "LPUART4 Receive Line Idle input is selected."] + pub const Val70: Self = Self(0x46); + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + pub const Val75: Self = Self(0x4b); + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + pub const Val76: Self = Self(0x4c); + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + pub const Val77: Self = Self(0x4d); + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer2_MAT1 input is selected."] + pub const Val79: Self = Self(0x4f); #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, + pub const Val80: Self = Self(0x50); #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + pub const Val81: Self = Self(0x51); + #[doc = "CTimer4_MAT1 input is selected."] + pub const Val82: Self = Self(0x52); + #[doc = "CTimer4_MAT2 input is selected."] + pub const Val83: Self = Self(0x53); + #[doc = "CTimer4_MAT3 input is selected."] + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet input is selected."] + pub const Val94: Self = Self(0x5e); + #[doc = "LPI2C2 Slave End of Packet input is selected."] + pub const Val95: Self = Self(0x5f); + #[doc = "LPI2C3 Master End of Packet input is selected."] + pub const Val96: Self = Self(0x60); + #[doc = "LPI2C3 Slave End of Packet input is selected."] + pub const Val97: Self = Self(0x61); + #[doc = "LPUART5 Received Data Word input is selected."] + pub const Val98: Self = Self(0x62); + #[doc = "LPUART5 Transmitted Data Word input is selected."] + pub const Val99: Self = Self(0x63); + #[doc = "LPUART5 Receive Line Idle input is selected."] + pub const Val100: Self = Self(0x64); + #[doc = "TMPR_OUT0 input is selected."] + pub const Val102: Self = Self(0x66); + #[doc = "TMPR_OUT1 input is selected."] + pub const Val103: Self = Self(0x67); #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + pub const Val113: Self = Self(0x71); #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + pub const Val114: Self = Self(0x72); #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + pub const Val115: Self = Self(0x73); #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + pub const Val116: Self = Self(0x74); #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + pub const Val117: Self = Self(0x75); #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + pub const Val118: Self = Self(0x76); #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + pub const Val119: Self = Self(0x77); #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, + pub const Val120: Self = Self(0x78); #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, + pub const Val121: Self = Self(0x79); #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, + pub const Val122: Self = Self(0x7a); #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, + pub const Val123: Self = Self(0x7b); #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, - #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, - #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, - #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, - #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, - #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, - #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, - #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } -impl Qdc1phaseaInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Qdc1phaseaInp { - unsafe { core::mem::transmute(val & 0x7f) } +impl Ctimer3capInp { + pub const fn from_bits(val: u8) -> Ctimer3capInp { + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Ctimer3capInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x66 => f.write_str("Val102"), + 0x67 => f.write_str("Val103"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctimer3capInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x66 => defmt::write!(f, "Val102"), + 0x67 => defmt::write!(f, "Val103"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } -impl From for Qdc1phaseaInp { +impl From for Ctimer3capInp { #[inline(always)] - fn from(val: u8) -> Qdc1phaseaInp { - Qdc1phaseaInp::from_bits(val) + fn from(val: u8) -> Ctimer3capInp { + Ctimer3capInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Qdc1phaseaInp) -> u8 { - Qdc1phaseaInp::to_bits(val) + fn from(val: Ctimer3capInp) -> u8 { + Ctimer3capInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Qdc1phasebInp { - _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Ctimer4capInp(u8); +impl Ctimer4capInp { + #[doc = "CT_INP0 input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "CT_INP1 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "CT_INP2 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "CT_INP3 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "CT_INP4 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CT_INP5 input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CT_INP6 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "CT_INP7 input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "CT_INP8 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CT_INP9 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CT_INP10 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CT_INP12 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CT_INP13 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "CT_INP14 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "CT_INP15 input is selected."] + pub const Val16: Self = Self(0x10); + #[doc = "CT_INP16 input is selected."] + pub const Val17: Self = Self(0x11); + #[doc = "CT_INP17 input is selected."] + pub const Val18: Self = Self(0x12); + #[doc = "CT_INP18 input is selected."] + pub const Val19: Self = Self(0x13); + #[doc = "CT_INP19 input is selected."] + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, - #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT is selected."] + pub const Val30: Self = Self(0x1e); + #[doc = "CTimer0_MAT1 input is selected."] + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, + pub const Val34: Self = Self(0x22); + #[doc = "CTimer0_MAT3 input is selected."] + pub const Val35: Self = Self(0x23); + #[doc = "CTimer1_MAT1 input is selected."] + pub const Val36: Self = Self(0x24); #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, + pub const Val37: Self = Self(0x25); #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + pub const Val38: Self = Self(0x26); + #[doc = "LPI2C0 Master End of Packet input is selected."] + pub const Val48: Self = Self(0x30); + #[doc = "LPI2C0 Slave End of Packet input is selected."] + pub const Val49: Self = Self(0x31); + #[doc = "LPI2C1 Master End of Packet input is selected."] + pub const Val50: Self = Self(0x32); + #[doc = "LPI2C1 Slave End of Packet input is selected."] + pub const Val51: Self = Self(0x33); + #[doc = "LPSPI0 End of Frame input is selected."] + pub const Val52: Self = Self(0x34); + #[doc = "LPSPI0 Received Data Word input is selected."] + pub const Val53: Self = Self(0x35); + #[doc = "LPSPI1 End of Frame input is selected."] + pub const Val54: Self = Self(0x36); + #[doc = "LPSPI1 Received Data Word input is selected."] + pub const Val55: Self = Self(0x37); + #[doc = "LPUART0 Received Data Word input is selected."] + pub const Val56: Self = Self(0x38); + #[doc = "LPUART0 Transmitted Data Word input is selected."] + pub const Val57: Self = Self(0x39); + #[doc = "LPUART0 Receive Line Idle input is selected."] + pub const Val58: Self = Self(0x3a); + #[doc = "LPUART1 Received Data Word input is selected."] + pub const Val59: Self = Self(0x3b); + #[doc = "LPUART1 Transmitted Data Word input is selected."] + pub const Val60: Self = Self(0x3c); + #[doc = "LPUART1 Receive Line Idle input is selected."] + pub const Val61: Self = Self(0x3d); + #[doc = "LPUART2 Received Data Word input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "LPUART2 Transmitted Data Word input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "LPUART2 Receive Line Idle input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "LPUART3 Received Data Word input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "LPUART3 Transmitted Data Word input is selected."] + pub const Val66: Self = Self(0x42); + #[doc = "LPUART3 Receive Line Idle input is selected."] + pub const Val67: Self = Self(0x43); + #[doc = "LPUART4 Received Data Word input is selected."] + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word input is selected."] + pub const Val69: Self = Self(0x45); + #[doc = "LPUART4 Receive Line Idle input is selected."] + pub const Val70: Self = Self(0x46); + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + pub const Val75: Self = Self(0x4b); + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + pub const Val76: Self = Self(0x4c); + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + pub const Val77: Self = Self(0x4d); + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer2_MAT1 input is selected."] + pub const Val79: Self = Self(0x4f); #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, + pub const Val80: Self = Self(0x50); #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + pub const Val81: Self = Self(0x51); + #[doc = "CTimer3_MAT1 input is selected."] + pub const Val82: Self = Self(0x52); + #[doc = "CTimer3_MAT2 input is selected."] + pub const Val83: Self = Self(0x53); + #[doc = "CTimer3_MAT3 input is selected."] + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet input is selected."] + pub const Val94: Self = Self(0x5e); + #[doc = "LPI2C2 Slave End of Packet input is selected."] + pub const Val95: Self = Self(0x5f); + #[doc = "LPI2C3 Master End of Packet input is selected."] + pub const Val96: Self = Self(0x60); + #[doc = "LPI2C3 Slave End of Packet input is selected."] + pub const Val97: Self = Self(0x61); + #[doc = "LPUART5 Received Data Word input is selected."] + pub const Val98: Self = Self(0x62); + #[doc = "LPUART5 Transmitted Data Word input is selected."] + pub const Val99: Self = Self(0x63); + #[doc = "LPUART5 Receive Line Idle input is selected."] + pub const Val100: Self = Self(0x64); + #[doc = "TMPR_OUT0 input is selected."] + pub const Val102: Self = Self(0x66); + #[doc = "TMPR_OUT1 input is selected."] + pub const Val103: Self = Self(0x67); #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + pub const Val113: Self = Self(0x71); #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + pub const Val114: Self = Self(0x72); #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + pub const Val115: Self = Self(0x73); #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + pub const Val116: Self = Self(0x74); #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + pub const Val117: Self = Self(0x75); #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + pub const Val118: Self = Self(0x76); #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + pub const Val119: Self = Self(0x77); #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, + pub const Val120: Self = Self(0x78); #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, + pub const Val121: Self = Self(0x79); #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, + pub const Val122: Self = Self(0x7a); #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, + pub const Val123: Self = Self(0x7b); #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); +} +impl Ctimer4capInp { + pub const fn from_bits(val: u8) -> Ctimer4capInp { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for Ctimer4capInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x66 => f.write_str("Val102"), + 0x67 => f.write_str("Val103"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctimer4capInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x66 => defmt::write!(f, "Val102"), + 0x67 => defmt::write!(f, "Val103"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Ctimer4capInp { + #[inline(always)] + fn from(val: u8) -> Ctimer4capInp { + Ctimer4capInp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Ctimer4capInp) -> u8 { + Ctimer4capInp::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct DacTrigTrigin(u8); +impl DacTrigTrigin { + #[doc = "ARM_TXEV."] + pub const Val1: Self = Self(0x01); + #[doc = "AOI0_OUT0 input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "AOI0_OUT1 input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "AOI0_OUT2 input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "AOI0_OUT3 input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "CMP0_OUT input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "CTimer0_MAT0 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "CTimer0_MAT1 input is selected."] + pub const Val10: Self = Self(0x0a); + #[doc = "CTimer1_MAT0 input is selected."] + pub const Val11: Self = Self(0x0b); + #[doc = "CTimer1_MAT1 input is selected."] + pub const Val12: Self = Self(0x0c); + #[doc = "CTimer2_MAT0 input is selected."] + pub const Val13: Self = Self(0x0d); + #[doc = "CTimer2_MAT1 input is selected."] + pub const Val14: Self = Self(0x0e); + #[doc = "LPTMR0 input is selected."] + pub const Val15: Self = Self(0x0f); + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + pub const Val26: Self = Self(0x1a); #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + pub const Val27: Self = Self(0x1b); #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + pub const Val28: Self = Self(0x1c); #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + pub const Val29: Self = Self(0x1d); #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, - #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, - #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, - #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 inout is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val30: Self = Self(0x1e); + #[doc = "WUU input is selected."] + pub const Val31: Self = Self(0x1f); + #[doc = "CTimer3_MAT0 input is selected."] + pub const Val41: Self = Self(0x29); + #[doc = "CTimer3_MAT1 input is selected."] + pub const Val42: Self = Self(0x2a); + #[doc = "CTimer4_MAT0 input is selected."] + pub const Val43: Self = Self(0x2b); + #[doc = "CTimer4_MAT1 input is selected."] + pub const Val44: Self = Self(0x2c); + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + pub const Val62: Self = Self(0x3e); + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + pub const Val63: Self = Self(0x3f); + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + pub const Val64: Self = Self(0x40); + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + pub const Val65: Self = Self(0x41); + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + pub const Val66: Self = Self(0x42); } -impl Qdc1phasebInp { - #[inline(always)] - pub const fn from_bits(val: u8) -> Qdc1phasebInp { - unsafe { core::mem::transmute(val & 0x7f) } +impl DacTrigTrigin { + pub const fn from_bits(val: u8) -> DacTrigTrigin { + Self(val & 0x7f) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for DacTrigTrigin { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0c => f.write_str("Val12"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x1f => f.write_str("Val31"), + 0x29 => f.write_str("Val41"), + 0x2a => f.write_str("Val42"), + 0x2b => f.write_str("Val43"), + 0x2c => f.write_str("Val44"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for DacTrigTrigin { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0c => defmt::write!(f, "Val12"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x1f => defmt::write!(f, "Val31"), + 0x29 => defmt::write!(f, "Val41"), + 0x2a => defmt::write!(f, "Val42"), + 0x2b => defmt::write!(f, "Val43"), + 0x2c => defmt::write!(f, "Val44"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + other => defmt::write!(f, "0x{:02X}", other), + } } } -impl From for Qdc1phasebInp { +impl From for DacTrigTrigin { #[inline(always)] - fn from(val: u8) -> Qdc1phasebInp { - Qdc1phasebInp::from_bits(val) + fn from(val: u8) -> DacTrigTrigin { + DacTrigTrigin::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Qdc1phasebInp) -> u8 { - Qdc1phasebInp::to_bits(val) + fn from(val: DacTrigTrigin) -> u8 { + DacTrigTrigin::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum QdcHomeInp { +pub enum FlexioTrigInp { _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + Val1 = 0x01, #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + Val2 = 0x02, #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + Val3 = 0x03, #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + Val4 = 0x04, + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + Val5 = 0x05, + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + Val6 = 0x06, + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + Val7 = 0x07, + #[doc = "ADC0_tcomp\\[3\\] input is selected."] + Val8 = 0x08, #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + Val9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + #[doc = "CTimer0_MAT1 input is selected."] + Val12 = 0x0c, #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, + Val13 = 0x0d, + #[doc = "CTimer1_MAT1 input is selected."] + Val14 = 0x0e, #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + Val15 = 0x0f, + _RESERVED_10 = 0x10, #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + Val17 = 0x11, + #[doc = "LPTMR0 input is selected."] + Val18 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + Val24 = 0x18, #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + Val25 = 0x19, #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + Val26 = 0x1a, #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + Val27 = 0x1b, #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + Val28 = 0x1c, #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + Val29 = 0x1d, #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + Val30 = 0x1e, #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, - #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, - #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, - #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, - #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + Val31 = 0x1f, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val32 = 0x20, #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + Val33 = 0x21, #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + Val34 = 0x22, #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + Val35 = 0x23, #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, + Val36 = 0x24, + #[doc = "WUU input is selected."] + Val37 = 0x25, + #[doc = "LPI2C0 Master End of Packet."] + Val38 = 0x26, + #[doc = "LPI2C0 Slave End of Packet."] + Val39 = 0x27, + #[doc = "LPI2C1 Master End of Packet."] + Val40 = 0x28, + #[doc = "LPI2C1 Slave End of Packet."] + Val41 = 0x29, + #[doc = "LPSPI0 End of Frame."] + Val42 = 0x2a, + #[doc = "LPSPI0 Received Data Word."] + Val43 = 0x2b, + #[doc = "LPSPI1 End of Frame."] + Val44 = 0x2c, + #[doc = "LPSPI1 Received Data Word."] + Val45 = 0x2d, + #[doc = "LPUART0 Received Data Word."] + Val46 = 0x2e, + #[doc = "LPUART0 Transmitted Data Word."] + Val47 = 0x2f, + #[doc = "LPUART0 Receive Line Idle."] + Val48 = 0x30, + #[doc = "LPUART1 Received Data Word."] + Val49 = 0x31, + #[doc = "LPUART1 Transmitted Data Word."] + Val50 = 0x32, + #[doc = "LPUART1 Receive Line Idle."] + Val51 = 0x33, + #[doc = "LPUART2 Received Data Word."] + Val52 = 0x34, + #[doc = "LPUART2 Transmitted Data Word."] + Val53 = 0x35, + #[doc = "LPUART2 Receive Line Idle."] + Val54 = 0x36, + #[doc = "LPUART3 Received Data Word."] + Val55 = 0x37, + #[doc = "LPUART3 Transmitted Data Word."] + Val56 = 0x38, + #[doc = "LPUART3 Receive Line Idle."] + Val57 = 0x39, + #[doc = "LPUART4 Received Data Word."] + Val58 = 0x3a, + #[doc = "LPUART4 Transmitted Data Word."] + Val59 = 0x3b, + #[doc = "LPUART4 Receive Line Idle."] + Val60 = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, + _RESERVED_40 = 0x40, + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + Val65 = 0x41, + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + Val66 = 0x42, + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + Val67 = 0x43, + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + Val68 = 0x44, #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, + Val69 = 0x45, #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, + Val70 = 0x46, #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, + Val71 = 0x47, #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, + Val72 = 0x48, _RESERVED_49 = 0x49, _RESERVED_4a = 0x4a, _RESERVED_4b = 0x4b, _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, + #[doc = "LPI2C2 Master End of Packet."] + Val77 = 0x4d, + #[doc = "LPI2C2 Slave End of Packet."] + Val78 = 0x4e, + #[doc = "LPI2C3 Master End of Packet."] + Val79 = 0x4f, + #[doc = "LPI2C3 Slave End of Packet."] + Val80 = 0x50, + #[doc = "LPSPI2 End of Frame input is selected."] + Val81 = 0x51, + #[doc = "LPSPI2 Received Data Word input is selected."] + Val82 = 0x52, + #[doc = "LPSPI3 End of Frame input is selected."] + Val83 = 0x53, + #[doc = "LPSPI3 Received Data Word input is selected."] + Val84 = 0x54, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val85 = 0x55, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val86 = 0x56, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val87 = 0x57, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val88 = 0x58, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val89 = 0x59, _RESERVED_5a = 0x5a, _RESERVED_5b = 0x5b, _RESERVED_5c = 0x5c, @@ -6702,9 +4026,9 @@ pub enum QdcHomeInp { _RESERVED_7e = 0x7e, _RESERVED_7f = 0x7f, } -impl QdcHomeInp { +impl FlexioTrigInp { #[inline(always)] - pub const fn from_bits(val: u8) -> QdcHomeInp { + pub const fn from_bits(val: u8) -> FlexioTrigInp { unsafe { core::mem::transmute(val & 0x7f) } } #[inline(always)] @@ -6712,332 +4036,412 @@ impl QdcHomeInp { unsafe { core::mem::transmute(self) } } } -impl From for QdcHomeInp { +impl From for FlexioTrigInp { + #[inline(always)] + fn from(val: u8) -> FlexioTrigInp { + FlexioTrigInp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FlexioTrigInp) -> u8 { + FlexioTrigInp::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct FreqmeasRefInp(u8); +impl FreqmeasRefInp { + #[doc = "clk_in input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "FRO_OSC_12M input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "fro_hf_div input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "OSC32K\\[1\\] input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "clk_16k\\[1\\] input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "SLOW_CLK input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "FREQME_CLK_IN0 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "FREQME_CLK_IN1 input is selected input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "AOI0_OUT0 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "AOI0_OUT1."] + pub const Val10: Self = Self(0x0a); + #[doc = "pll1_clk_div input is selected."] + pub const Val31: Self = Self(0x1f); +} +impl FreqmeasRefInp { + pub const fn from_bits(val: u8) -> FreqmeasRefInp { + Self(val & 0x7f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for FreqmeasRefInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x1f => f.write_str("Val31"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for FreqmeasRefInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x1f => defmt::write!(f, "Val31"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for FreqmeasRefInp { + #[inline(always)] + fn from(val: u8) -> FreqmeasRefInp { + FreqmeasRefInp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FreqmeasRefInp) -> u8 { + FreqmeasRefInp::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct FreqmeasTarInp(u8); +impl FreqmeasTarInp { + #[doc = "clk_in input is selected."] + pub const Val1: Self = Self(0x01); + #[doc = "FRO_OSC_12M input is selected."] + pub const Val2: Self = Self(0x02); + #[doc = "fro_hf_div input is selected."] + pub const Val3: Self = Self(0x03); + #[doc = "OSC32K\\[1\\] input is selected."] + pub const Val4: Self = Self(0x04); + #[doc = "clk_16k\\[1\\] input is selected."] + pub const Val5: Self = Self(0x05); + #[doc = "SLOW_CLK input is selected."] + pub const Val6: Self = Self(0x06); + #[doc = "FREQME_CLK_IN0 input is selected."] + pub const Val7: Self = Self(0x07); + #[doc = "FREQME_CLK_IN1 input is selected input is selected."] + pub const Val8: Self = Self(0x08); + #[doc = "AOI0_OUT0 input is selected."] + pub const Val9: Self = Self(0x09); + #[doc = "AOI0_OUT1."] + pub const Val10: Self = Self(0x0a); + #[doc = "pll1_clk_div input is selected."] + pub const Val31: Self = Self(0x1f); +} +impl FreqmeasTarInp { + pub const fn from_bits(val: u8) -> FreqmeasTarInp { + Self(val & 0x7f) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for FreqmeasTarInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x1f => f.write_str("Val31"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for FreqmeasTarInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x1f => defmt::write!(f, "Val31"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for FreqmeasTarInp { #[inline(always)] - fn from(val: u8) -> QdcHomeInp { - QdcHomeInp::from_bits(val) + fn from(val: u8) -> FreqmeasTarInp { + FreqmeasTarInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: QdcHomeInp) -> u8 { - QdcHomeInp::to_bits(val) + fn from(val: FreqmeasTarInp) -> u8 { + FreqmeasTarInp::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum QdcIcapInp { +pub enum Lpi2cTrigInp { _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, + _RESERVED_1 = 0x01, #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + Val2 = 0x02, #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + Val3 = 0x03, #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + Val4 = 0x04, #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + Val5 = 0x05, #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, - #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, - #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, - #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + Val6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + #[doc = "CTimer0_MAT0 input is selected."] + Val9 = 0x09, + #[doc = "CTimer0_MAT1 input is selected."] + Val10 = 0x0a, + #[doc = "CTimer1_MAT0 input is selected."] + Val11 = 0x0b, + #[doc = "CTimer1_MAT1 input is selected."] + Val12 = 0x0c, + #[doc = "CTimer2_MAT0 input is selected."] + Val13 = 0x0d, + #[doc = "CTimer2_MAT1 input is selected."] + Val14 = 0x0e, + #[doc = "LPTMR0 input is selected."] + Val15 = 0x0f, + _RESERVED_10 = 0x10, #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + Val17 = 0x11, #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + Val18 = 0x12, #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + Val19 = 0x13, #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + Val20 = 0x14, #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + Val21 = 0x15, #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + Val22 = 0x16, #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + Val23 = 0x17, #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, - #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, - #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, - #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, - #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + Val24 = 0x18, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val25 = 0x19, #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + Val26 = 0x1a, #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + Val27 = 0x1b, #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + Val28 = 0x1c, #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, - #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, - #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, - #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, - _RESERVED_35 = 0x35, - _RESERVED_36 = 0x36, - _RESERVED_37 = 0x37, - _RESERVED_38 = 0x38, - _RESERVED_39 = 0x39, - _RESERVED_3a = 0x3a, - _RESERVED_3b = 0x3b, - _RESERVED_3c = 0x3c, - _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + Val29 = 0x1d, + #[doc = "WUU input is selected."] + Val30 = 0x1e, + _RESERVED_1f = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + #[doc = "CTimer3_MAT2 input is selected."] + Val35 = 0x23, + #[doc = "CTimer3_MAT3 input is selected."] + Val36 = 0x24, + #[doc = "CTimer4_MAT2 input is selected."] + Val37 = 0x25, + #[doc = "CTimer4_MAT3 input is selected."] + Val38 = 0x26, + #[doc = "FlexIO0 CH0 input is selected."] + Val39 = 0x27, + #[doc = "FlexIO0 CH1 input is selected."] + Val40 = 0x28, + #[doc = "FlexIO0 CH2 input is selected."] + Val41 = 0x29, + #[doc = "FlexIO0 CH3 input is selected."] + Val42 = 0x2a, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val43 = 0x2b, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val44 = 0x2c, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val45 = 0x2d, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val46 = 0x2e, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val47 = 0x2f, + _RESERVED_30 = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + _RESERVED_38 = 0x38, + _RESERVED_39 = 0x39, + _RESERVED_3a = 0x3a, + _RESERVED_3b = 0x3b, + _RESERVED_3c = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, } -impl QdcIcapInp { +impl Lpi2cTrigInp { #[inline(always)] - pub const fn from_bits(val: u8) -> QdcIcapInp { - unsafe { core::mem::transmute(val & 0x7f) } + pub const fn from_bits(val: u8) -> Lpi2cTrigInp { + unsafe { core::mem::transmute(val & 0x3f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for QdcIcapInp { +impl From for Lpi2cTrigInp { #[inline(always)] - fn from(val: u8) -> QdcIcapInp { - QdcIcapInp::from_bits(val) + fn from(val: u8) -> Lpi2cTrigInp { + Lpi2cTrigInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: QdcIcapInp) -> u8 { - QdcIcapInp::to_bits(val) + fn from(val: Lpi2cTrigInp) -> u8 { + Lpi2cTrigInp::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum QdcIndexInp { +pub enum LpspiTrigInp { _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, + _RESERVED_1 = 0x01, #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + Val2 = 0x02, #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + Val3 = 0x03, #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + Val4 = 0x04, #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + Val5 = 0x05, #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + Val6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + #[doc = "CTimer0_MAT1 input is selected."] + Val9 = 0x09, #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, + Val10 = 0x0a, + #[doc = "CTimer1_MAT1 input is selected."] + Val11 = 0x0b, #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, - #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + Val12 = 0x0c, + #[doc = "CTimer2_MAT1 input is selected."] + Val13 = 0x0d, #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, - #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + Val14 = 0x0e, + #[doc = "LPTMR0 input is selected."] + Val15 = 0x0f, + _RESERVED_10 = 0x10, #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + Val17 = 0x11, #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + Val18 = 0x12, #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + Val19 = 0x13, #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + Val20 = 0x14, #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + Val21 = 0x15, #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + Val22 = 0x16, #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + Val23 = 0x17, #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, - #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, - #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, - #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, - #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + Val24 = 0x18, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val25 = 0x19, #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + Val26 = 0x1a, #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + Val27 = 0x1b, #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + Val28 = 0x1c, #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, - #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, + Val29 = 0x1d, + #[doc = "WUU input is selected."] + Val30 = 0x1e, + _RESERVED_1f = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + #[doc = "CTimer3_MAT2 inputs is selected."] + Val35 = 0x23, #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, + Val36 = 0x24, #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, + Val37 = 0x25, #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, + Val38 = 0x26, + #[doc = "FlexIO0 CH0 input is selected."] + Val39 = 0x27, + #[doc = "FlexIO0 CH1 input is selected."] + Val40 = 0x28, + #[doc = "FlexIO0 CH2 input is selected."] + Val41 = 0x29, + #[doc = "FlexIO0 CH3 input is selected."] + Val42 = 0x2a, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val43 = 0x2b, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val44 = 0x2c, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val45 = 0x2d, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val46 = 0x2e, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val47 = 0x2f, + _RESERVED_30 = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, _RESERVED_35 = 0x35, _RESERVED_36 = 0x36, _RESERVED_37 = 0x37, @@ -7047,207 +4451,131 @@ pub enum QdcIndexInp { _RESERVED_3b = 0x3b, _RESERVED_3c = 0x3c, _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, } -impl QdcIndexInp { +impl LpspiTrigInp { #[inline(always)] - pub const fn from_bits(val: u8) -> QdcIndexInp { - unsafe { core::mem::transmute(val & 0x7f) } + pub const fn from_bits(val: u8) -> LpspiTrigInp { + unsafe { core::mem::transmute(val & 0x3f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for QdcIndexInp { +impl From for LpspiTrigInp { #[inline(always)] - fn from(val: u8) -> QdcIndexInp { - QdcIndexInp::from_bits(val) + fn from(val: u8) -> LpspiTrigInp { + LpspiTrigInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: QdcIndexInp) -> u8 { - QdcIndexInp::to_bits(val) + fn from(val: LpspiTrigInp) -> u8 { + LpspiTrigInp::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum QdcTrigInp { +pub enum LpuartInp { _RESERVED_0 = 0x0, - #[doc = "ARM_TXEV input is selected."] - VAL1 = 0x01, + _RESERVED_1 = 0x01, #[doc = "AOI0_OUT0 input is selected."] - VAL2 = 0x02, + Val2 = 0x02, #[doc = "AOI0_OUT1 input is selected."] - VAL3 = 0x03, + Val3 = 0x03, #[doc = "AOI0_OUT2 input is selected."] - VAL4 = 0x04, + Val4 = 0x04, #[doc = "AOI0_OUT3 input is selected."] - VAL5 = 0x05, + Val5 = 0x05, #[doc = "CMP0_OUT input is selected."] - VAL6 = 0x06, - #[doc = "CMP1_OUT input is selected."] - VAL7 = 0x07, - #[doc = "CMP2_OUT input is selected."] - VAL8 = 0x08, + Val6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, #[doc = "CTimer0_MAT2 input is selected."] - VAL9 = 0x09, - #[doc = "CTimer0_MAT3."] - VAL10 = 0x0a, + Val9 = 0x09, + #[doc = "CTimer0_MAT3 input is selected."] + Val10 = 0x0a, #[doc = "CTimer1_MAT2 input is selected."] - VAL11 = 0x0b, + Val11 = 0x0b, #[doc = "CTimer1_MAT3 input is selected."] - VAL12 = 0x0c, + Val12 = 0x0c, #[doc = "CTimer2_MAT2 input is selected."] - VAL13 = 0x0d, + Val13 = 0x0d, #[doc = "CTimer2_MAT3 input is selected."] - VAL14 = 0x0e, - _RESERVED_f = 0x0f, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL16 = 0x10, - #[doc = "PWM0_SM0_MUX_TRIG1 input is selected."] - VAL17 = 0x11, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL18 = 0x12, - #[doc = "PWM0_SM1_MUX_TRIG1 input is selected."] - VAL19 = 0x13, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL20 = 0x14, - #[doc = "PWM0_SM2_MUX_TRIG1 input is selected."] - VAL21 = 0x15, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL22 = 0x16, - #[doc = "PWM0_SM3_MUX_TRIG1 input is selected."] - VAL23 = 0x17, + Val14 = 0x0e, + #[doc = "LPTMR0 input is selected."] + Val15 = 0x0f, + _RESERVED_10 = 0x10, #[doc = "TRIG_IN0 input is selected."] - VAL24 = 0x18, + Val17 = 0x11, #[doc = "TRIG_IN1 input is selected."] - VAL25 = 0x19, + Val18 = 0x12, #[doc = "TRIG_IN2 input is selected."] - VAL26 = 0x1a, + Val19 = 0x13, #[doc = "TRIG_IN3 input is selected."] - VAL27 = 0x1b, + Val20 = 0x14, #[doc = "TRIG_IN4 input is selected."] - VAL28 = 0x1c, + Val21 = 0x15, #[doc = "TRIG_IN5 input is selected."] - VAL29 = 0x1d, + Val22 = 0x16, #[doc = "TRIG_IN6 input is selected."] - VAL30 = 0x1e, + Val23 = 0x17, #[doc = "TRIG_IN7 input is selected."] - VAL31 = 0x1f, + Val24 = 0x18, #[doc = "TRIG_IN8 input is selected."] - VAL32 = 0x20, + Val25 = 0x19, #[doc = "TRIG_IN9 input is selected."] - VAL33 = 0x21, + Val26 = 0x1a, #[doc = "TRIG_IN10 input is selected."] - VAL34 = 0x22, + Val27 = 0x1b, #[doc = "TRIG_IN11 input is selected."] - VAL35 = 0x23, - #[doc = "GPIO0 Pin Event Trig 0 is selected."] - VAL36 = 0x24, + Val28 = 0x1c, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val29 = 0x1d, #[doc = "GPIO1 Pin Event Trig 0 input is selected."] - VAL37 = 0x25, + Val30 = 0x1e, #[doc = "GPIO2 Pin Event Trig 0 input is selected."] - VAL38 = 0x26, + Val31 = 0x1f, #[doc = "GPIO3 Pin Event Trig 0 input is selected."] - VAL39 = 0x27, + Val32 = 0x20, #[doc = "GPIO4 Pin Event Trig 0 input is selected."] - VAL40 = 0x28, - #[doc = "AOI1_OUT0 input is selected."] - VAL41 = 0x29, - #[doc = "AOI1_OUT1 input is selected."] - VAL42 = 0x2a, - #[doc = "AOI1_OUT2 input is selected."] - VAL43 = 0x2b, - #[doc = "AOI1_OUT3 input is selected."] - VAL44 = 0x2c, - _RESERVED_2d = 0x2d, - _RESERVED_2e = 0x2e, - _RESERVED_2f = 0x2f, - _RESERVED_30 = 0x30, + Val33 = 0x21, + #[doc = "WUU selected."] + Val34 = 0x22, + _RESERVED_23 = 0x23, + _RESERVED_24 = 0x24, + _RESERVED_25 = 0x25, + _RESERVED_26 = 0x26, + _RESERVED_27 = 0x27, #[doc = "CTimer3_MAT2 input is selected."] - VAL49 = 0x31, + Val40 = 0x28, #[doc = "CTimer3_MAT3 input is selected."] - VAL50 = 0x32, + Val41 = 0x29, #[doc = "CTimer4_MAT2 input is selected."] - VAL51 = 0x33, + Val42 = 0x2a, #[doc = "CTimer4_MAT3 input is selected."] - VAL52 = 0x34, + Val43 = 0x2b, + #[doc = "FlexIO0 CH0 input is selected."] + Val44 = 0x2c, + #[doc = "FlexIO0 CH1 input is selected."] + Val45 = 0x2d, + #[doc = "FlexIO0 CH2 input is selected."] + Val46 = 0x2e, + #[doc = "FlexIO0 CH3 input is selected."] + Val47 = 0x2f, + #[doc = "GPIO0 Pin Event Trig 1 input is selected."] + Val48 = 0x30, + #[doc = "GPIO1 Pin Event Trig 1 input is selected."] + Val49 = 0x31, + #[doc = "GPIO2 Pin Event Trig 1 input is selected."] + Val50 = 0x32, + #[doc = "GPIO3 Pin Event Trig 1 input is selected."] + Val51 = 0x33, + #[doc = "GPIO4 Pin Event Trig 1 input is selected."] + Val52 = 0x34, _RESERVED_35 = 0x35, _RESERVED_36 = 0x36, _RESERVED_37 = 0x37, @@ -7257,101 +4585,29 @@ pub enum QdcTrigInp { _RESERVED_3b = 0x3b, _RESERVED_3c = 0x3c, _RESERVED_3d = 0x3d, - #[doc = "PWM1_SM0_OUT_TRIG0 input is selected."] - VAL62 = 0x3e, - #[doc = "PWM1_SM0_OUT_TRIG1 input is selected."] - VAL63 = 0x3f, - #[doc = "PWM1_SM1_OUT_TRIG0 input is selected."] - VAL64 = 0x40, - #[doc = "PWM1_SM1_OUT_TRIG1 input is selected."] - VAL65 = 0x41, - #[doc = "PWM1_SM2_OUT_TRIG0 input is selected."] - VAL66 = 0x42, - #[doc = "PWM1_SM2_OUT_TRIG1 input is selected."] - VAL67 = 0x43, - #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] - VAL68 = 0x44, - #[doc = "PWM1_SM3_MUX_TRIG1 input is selected."] - VAL69 = 0x45, - _RESERVED_46 = 0x46, - _RESERVED_47 = 0x47, - _RESERVED_48 = 0x48, - _RESERVED_49 = 0x49, - _RESERVED_4a = 0x4a, - _RESERVED_4b = 0x4b, - _RESERVED_4c = 0x4c, - _RESERVED_4d = 0x4d, - _RESERVED_4e = 0x4e, - _RESERVED_4f = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, - _RESERVED_59 = 0x59, - _RESERVED_5a = 0x5a, - _RESERVED_5b = 0x5b, - _RESERVED_5c = 0x5c, - _RESERVED_5d = 0x5d, - _RESERVED_5e = 0x5e, - _RESERVED_5f = 0x5f, - _RESERVED_60 = 0x60, - _RESERVED_61 = 0x61, - _RESERVED_62 = 0x62, - _RESERVED_63 = 0x63, - _RESERVED_64 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - _RESERVED_69 = 0x69, - _RESERVED_6a = 0x6a, - _RESERVED_6b = 0x6b, - _RESERVED_6c = 0x6c, - _RESERVED_6d = 0x6d, - _RESERVED_6e = 0x6e, - _RESERVED_6f = 0x6f, - _RESERVED_70 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, } -impl QdcTrigInp { +impl LpuartInp { #[inline(always)] - pub const fn from_bits(val: u8) -> QdcTrigInp { - unsafe { core::mem::transmute(val & 0x7f) } + pub const fn from_bits(val: u8) -> LpuartInp { + unsafe { core::mem::transmute(val & 0x3f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for QdcTrigInp { +impl From for LpuartInp { #[inline(always)] - fn from(val: u8) -> QdcTrigInp { - QdcTrigInp::from_bits(val) + fn from(val: u8) -> LpuartInp { + LpuartInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: QdcTrigInp) -> u8 { - QdcTrigInp::to_bits(val) + fn from(val: LpuartInp) -> u8 { + LpuartInp::to_bits(val) } } #[repr(u8)] @@ -7360,171 +4616,167 @@ impl From for u8 { pub enum SmartDmaTrigInp { _RESERVED_0 = 0x0, #[doc = "GPIO P0_16 input is selected."] - VAL1 = 0x01, + Val1 = 0x01, #[doc = "GPIO P0_17 input is selected."] - VAL2 = 0x02, + Val2 = 0x02, #[doc = "GPIO P1_8 input is selected."] - VAL3 = 0x03, + Val3 = 0x03, #[doc = "GPIO P1_9 input is selected."] - VAL4 = 0x04, + Val4 = 0x04, #[doc = "GPIO P1_10 input is selected."] - VAL5 = 0x05, + Val5 = 0x05, #[doc = "GPIO P1_11 input is selected."] - VAL6 = 0x06, + Val6 = 0x06, #[doc = "GPIO P1_12 input is selected."] - VAL7 = 0x07, + Val7 = 0x07, #[doc = "GPIO P1_13 input is selected."] - VAL8 = 0x08, + Val8 = 0x08, #[doc = "GPIO P2_0 input is selected."] - VAL9 = 0x09, + Val9 = 0x09, #[doc = "GPIO P2_1 input is selected."] - VAL10 = 0x0a, + Val10 = 0x0a, #[doc = "GPIO P2_2 input is selected."] - VAL11 = 0x0b, + Val11 = 0x0b, #[doc = "GPIO P2_3 input is selected."] - VAL12 = 0x0c, + Val12 = 0x0c, #[doc = "GPIO P2_6 input is selected."] - VAL13 = 0x0d, + Val13 = 0x0d, #[doc = "GPIO P3_8 input is selected."] - VAL14 = 0x0e, + Val14 = 0x0e, #[doc = "GPIO P3_9 input is selected."] - VAL15 = 0x0f, + Val15 = 0x0f, #[doc = "GPIO P3_10 input is selected."] - VAL16 = 0x10, + Val16 = 0x10, #[doc = "GPIO P3_11 input is selected."] - VAL17 = 0x11, + Val17 = 0x11, #[doc = "GPIO P3_12 input is seclected."] - VAL18 = 0x12, + Val18 = 0x12, #[doc = "GPIO0 Pin Event Trig input is selected."] - VAL19 = 0x13, + Val19 = 0x13, #[doc = "GPIO1 Pin Event Trig input is selected."] - VAL20 = 0x14, + Val20 = 0x14, #[doc = "GPIO2 Pin Event Trig input is selected."] - VAL21 = 0x15, + Val21 = 0x15, #[doc = "GPIO3 Pin Event Trig input is selected."] - VAL22 = 0x16, + Val22 = 0x16, #[doc = "GPIO4 Pin Event Trig input is selected."] - VAL23 = 0x17, + Val23 = 0x17, #[doc = "ARM_TXEV input is selected."] - VAL24 = 0x18, + Val24 = 0x18, #[doc = "AOI0_OUT0 input is selected."] - VAL25 = 0x19, - #[doc = "AOI1_OUT1 input is selected."] - VAL26 = 0x1a, + Val25 = 0x19, + _RESERVED_1a = 0x1a, #[doc = "DMA_IRQ input is selected."] - VAL27 = 0x1b, - #[doc = "MAU_IRQ input is selected."] - VAL28 = 0x1c, + Val27 = 0x1b, + _RESERVED_1c = 0x1c, #[doc = "WUU_IRQ input is selected."] - VAL29 = 0x1d, + Val29 = 0x1d, #[doc = "CTimer0_MAT2 input is selected."] - VAL30 = 0x1e, + Val30 = 0x1e, #[doc = "CTimer0_MAT3 input is selected."] - VAL31 = 0x1f, + Val31 = 0x1f, #[doc = "CTimer1_MAT2 input is selected."] - VAL32 = 0x20, + Val32 = 0x20, #[doc = "CTimer1_MAT3 input is selected."] - VAL33 = 0x21, + Val33 = 0x21, #[doc = "CTimer2_MAT2 input is selected."] - VAL34 = 0x22, + Val34 = 0x22, #[doc = "CTimer2_MAT3 input is selected."] - VAL35 = 0x23, + Val35 = 0x23, #[doc = "CTimer3_MAT2 input is selected."] - VAL36 = 0x24, + Val36 = 0x24, #[doc = "CTimer3_MAT3 input is selected."] - VAL37 = 0x25, + Val37 = 0x25, #[doc = "CTimer4_MAT2 input is selected."] - VAL38 = 0x26, + Val38 = 0x26, #[doc = "CTimer4_MAT3 input is selected."] - VAL39 = 0x27, + Val39 = 0x27, #[doc = "OSTIMER_IRQ input is selected."] - VAL40 = 0x28, - #[doc = "PWM0_IRQ input is selected."] - VAL41 = 0x29, - #[doc = "PWM1_IRQ input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_IRQ input is selected."] - VAL43 = 0x2b, - #[doc = "QDC1_IRQ input is selected."] - VAL44 = 0x2c, + Val40 = 0x28, + _RESERVED_29 = 0x29, + _RESERVED_2a = 0x2a, + _RESERVED_2b = 0x2b, + _RESERVED_2c = 0x2c, #[doc = "RTC_Alarm_IRQ input is selected."] - VAL45 = 0x2d, + Val45 = 0x2d, #[doc = "RTC_1Hz_IRQ input is selected."] - VAL46 = 0x2e, + Val46 = 0x2e, #[doc = "uTICK_IRQ input is selected."] - VAL47 = 0x2f, + Val47 = 0x2f, #[doc = "WDT_IRQ input is selected."] - VAL48 = 0x30, + Val48 = 0x30, #[doc = "Wakeup_Timer_IRQ input is selected."] - VAL49 = 0x31, + Val49 = 0x31, #[doc = "CAN0_IRQ input is selected."] - VAL50 = 0x32, + Val50 = 0x32, #[doc = "CAN1_IRQ input is selected."] - VAL51 = 0x33, - #[doc = "FlexIO_IRQ input is selected."] - VAL52 = 0x34, - #[doc = "FlexIO_Shifer0_DMA_Req input is selected."] - VAL53 = 0x35, - #[doc = "FlexIO_Shifer1_DMA_Req input is selected."] - VAL54 = 0x36, - #[doc = "FlexIO_Shifer2_DMA_Req input is selected."] - VAL55 = 0x37, - #[doc = "FlexIO_Shifer3_DMA_Req input is selected."] - VAL56 = 0x38, + Val51 = 0x33, + #[doc = "FlexIO0_IRQ input is selected."] + Val52 = 0x34, + #[doc = "FlexIO0_Shifer0_DMA_Req input is selected."] + Val53 = 0x35, + #[doc = "FlexIO0_Shifer1_DMA_Req input is selected."] + Val54 = 0x36, + #[doc = "FlexIO0_Shifer2_DMA_Req input is selected."] + Val55 = 0x37, + #[doc = "FlexIO0_Shifer3_DMA_Req input is selected."] + Val56 = 0x38, #[doc = "I3C0_IRQ input is selected."] - VAL57 = 0x39, + Val57 = 0x39, #[doc = "LPI2C0_IRQ input is selected."] - VAL58 = 0x3a, + Val58 = 0x3a, #[doc = "LPI2C1_IRQ input is selected."] - VAL59 = 0x3b, + Val59 = 0x3b, #[doc = "LPSPI0_IRQ input is selected."] - VAL60 = 0x3c, + Val60 = 0x3c, #[doc = "LPSPI1_IRQ input is selected."] - VAL61 = 0x3d, + Val61 = 0x3d, #[doc = "LPUART0_IRQ input is selected."] - VAL62 = 0x3e, + Val62 = 0x3e, #[doc = "LPUART1_IRQ input is selected."] - VAL63 = 0x3f, + Val63 = 0x3f, #[doc = "LPUART2_IRQ input is selected."] - VAL64 = 0x40, + Val64 = 0x40, #[doc = "LPUART3_IRQ input is selected."] - VAL65 = 0x41, - #[doc = "USB0_SOF input is selected."] - VAL66 = 0x42, - _RESERVED_43 = 0x43, + Val65 = 0x41, + _RESERVED_42 = 0x42, + #[doc = "USB1 Start of Frame input is selected."] + Val67 = 0x43, #[doc = "ADC0_IRQ input is selected."] - VAL68 = 0x44, + Val68 = 0x44, #[doc = "ADC1_IRQ input is selected."] - VAL69 = 0x45, - #[doc = "ADC2_IRQ input is selected."] - VAL70 = 0x46, - #[doc = "ADC3_IRQ input is selected."] - VAL71 = 0x47, + Val69 = 0x45, + _RESERVED_46 = 0x46, + _RESERVED_47 = 0x47, #[doc = "CMP0_IRQ input is selected."] - VAL72 = 0x48, - #[doc = "CMP1_IRQ input is selected."] - VAL73 = 0x49, - #[doc = "CMP2_IRQ input is selected."] - VAL74 = 0x4a, - #[doc = "CMP0_OUT input is selected."] - VAL75 = 0x4b, - #[doc = "CMP1_OUT input is selected."] - VAL76 = 0x4c, - #[doc = "CMP2_OUT input is selected."] - VAL77 = 0x4d, - #[doc = "DAC0_IRQ input is selected."] - VAL78 = 0x4e, - #[doc = "SLCD_IRQ input is selected."] - VAL79 = 0x4f, - _RESERVED_50 = 0x50, - _RESERVED_51 = 0x51, - _RESERVED_52 = 0x52, - _RESERVED_53 = 0x53, - _RESERVED_54 = 0x54, - _RESERVED_55 = 0x55, - _RESERVED_56 = 0x56, - _RESERVED_57 = 0x57, - _RESERVED_58 = 0x58, + Val72 = 0x48, + _RESERVED_49 = 0x49, + _RESERVED_4a = 0x4a, + #[doc = "CMP0_OUT input is selected."] + Val75 = 0x4b, + _RESERVED_4c = 0x4c, + _RESERVED_4d = 0x4d, + #[doc = "DAC0_IRQ input is selected."] + Val78 = 0x4e, + _RESERVED_4f = 0x4f, + #[doc = "DMA1_IRQ input is selected."] + Val80 = 0x50, + #[doc = "DAC1_IRQ input is selected."] + Val81 = 0x51, + #[doc = "TSI0_End_of_Scan_IRQ input is selected."] + Val82 = 0x52, + #[doc = "TSI0_Out_of_Range_IRQ input is selected."] + Val83 = 0x53, + #[doc = "ENET QOS IRQ input is selected."] + Val84 = 0x54, + #[doc = "10BASE_T1S IRQ input is selected."] + Val85 = 0x55, + #[doc = "ERM Interrupt input is selected."] + Val86 = 0x56, + #[doc = "TMPR_OUT0 input is selected."] + Val87 = 0x57, + #[doc = "TMPR_OUT1 input is selected."] + Val88 = 0x58, _RESERVED_59 = 0x59, _RESERVED_5a = 0x5a, _RESERVED_5b = 0x5b, @@ -7587,255 +4839,412 @@ impl From for u8 { SmartDmaTrigInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timer0trigInp { - _RESERVED_0 = 0x0, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Timer0trigInp(u8); +impl Timer0trigInp { #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, + pub const Val1: Self = Self(0x01); #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, + pub const Val2: Self = Self(0x02); #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, + pub const Val3: Self = Self(0x03); #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, + pub const Val4: Self = Self(0x04); #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, + pub const Val5: Self = Self(0x05); #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, + pub const Val6: Self = Self(0x06); #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, + pub const Val7: Self = Self(0x07); #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, + pub const Val8: Self = Self(0x08); #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, + pub const Val9: Self = Self(0x09); #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, + pub const Val10: Self = Self(0x0a); #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, + pub const Val11: Self = Self(0x0b); #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, + pub const Val13: Self = Self(0x0d); #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, + pub const Val14: Self = Self(0x0e); #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, + pub const Val15: Self = Self(0x0f); #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, + pub const Val16: Self = Self(0x10); #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, + pub const Val17: Self = Self(0x11); #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, + pub const Val18: Self = Self(0x12); #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, + pub const Val19: Self = Self(0x13); #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, + pub const Val29: Self = Self(0x1d); #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, + pub const Val30: Self = Self(0x1e); #[doc = "CTimer1_MAT1 input is selected."] - VAL33 = 0x21, + pub const Val33: Self = Self(0x21); #[doc = "CTimer1_MAT2 input is selected."] - VAL34 = 0x22, + pub const Val34: Self = Self(0x22); #[doc = "CTimer1_MAT3 input is selected."] - VAL35 = 0x23, + pub const Val35: Self = Self(0x23); #[doc = "CTimer2_MAT1 input is selected."] - VAL36 = 0x24, + pub const Val36: Self = Self(0x24); #[doc = "CTimer2_MAT2 input is selected."] - VAL37 = 0x25, + pub const Val37: Self = Self(0x25); #[doc = "CTimer2_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, + pub const Val38: Self = Self(0x26); #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, + pub const Val48: Self = Self(0x30); #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, + pub const Val49: Self = Self(0x31); #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, + pub const Val50: Self = Self(0x32); #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, + pub const Val51: Self = Self(0x33); #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, + pub const Val52: Self = Self(0x34); #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, + pub const Val53: Self = Self(0x35); #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, + pub const Val54: Self = Self(0x36); #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, + pub const Val55: Self = Self(0x37); #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, + pub const Val56: Self = Self(0x38); #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, + pub const Val57: Self = Self(0x39); #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, + pub const Val58: Self = Self(0x3a); #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, + pub const Val59: Self = Self(0x3b); #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, + pub const Val60: Self = Self(0x3c); #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, + pub const Val61: Self = Self(0x3d); #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, + pub const Val62: Self = Self(0x3e); #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, + pub const Val63: Self = Self(0x3f); #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, + pub const Val64: Self = Self(0x40); #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, + pub const Val65: Self = Self(0x41); #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, + pub const Val66: Self = Self(0x42); #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, + pub const Val67: Self = Self(0x43); #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, + pub const Val68: Self = Self(0x44); #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, + pub const Val69: Self = Self(0x45); #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, + pub const Val70: Self = Self(0x46); #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, + pub const Val75: Self = Self(0x4b); #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, + pub const Val76: Self = Self(0x4c); #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, + pub const Val77: Self = Self(0x4d); #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, + pub const Val78: Self = Self(0x4e); #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, + pub const Val79: Self = Self(0x4f); #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, + pub const Val80: Self = Self(0x50); #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, + pub const Val81: Self = Self(0x51); #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, + pub const Val82: Self = Self(0x52); #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, + pub const Val83: Self = Self(0x53); #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, + pub const Val84: Self = Self(0x54); #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, + pub const Val94: Self = Self(0x5e); #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, + pub const Val95: Self = Self(0x5f); #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, + pub const Val96: Self = Self(0x60); #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, + pub const Val97: Self = Self(0x61); #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, + pub const Val98: Self = Self(0x62); #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, + pub const Val99: Self = Self(0x63); #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val100: Self = Self(0x64); + #[doc = "TRIG_IN0 input is selected."] + pub const Val113: Self = Self(0x71); + #[doc = "TRIG_IN1 input is selected."] + pub const Val114: Self = Self(0x72); + #[doc = "TRIG_IN2 input is selected."] + pub const Val115: Self = Self(0x73); + #[doc = "TRIG_IN3 input is selected."] + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 input is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 input is selected."] + pub const Val118: Self = Self(0x76); + #[doc = "TRIG_IN6 input is selected."] + pub const Val119: Self = Self(0x77); + #[doc = "TRIG_IN7 input is selected."] + pub const Val120: Self = Self(0x78); + #[doc = "TRIG_IN8 input is selected."] + pub const Val121: Self = Self(0x79); + #[doc = "TRIG_IN9 input is selected."] + pub const Val122: Self = Self(0x7a); + #[doc = "TRIG_IN10 input is selected."] + pub const Val123: Self = Self(0x7b); + #[doc = "TRIG_IN11 input is selected."] + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } impl Timer0trigInp { - #[inline(always)] pub const fn from_bits(val: u8) -> Timer0trigInp { - unsafe { core::mem::transmute(val & 0x7f) } + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Timer0trigInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Timer0trigInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } impl From for Timer0trigInp { @@ -7850,255 +5259,412 @@ impl From for u8 { Timer0trigInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timer1trigInp { - _RESERVED_0 = 0x0, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Timer1trigInp(u8); +impl Timer1trigInp { #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, + pub const Val1: Self = Self(0x01); #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, + pub const Val2: Self = Self(0x02); #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, + pub const Val3: Self = Self(0x03); #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, + pub const Val4: Self = Self(0x04); #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, + pub const Val5: Self = Self(0x05); #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, + pub const Val6: Self = Self(0x06); #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, + pub const Val7: Self = Self(0x07); #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, + pub const Val8: Self = Self(0x08); #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, + pub const Val9: Self = Self(0x09); #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, + pub const Val10: Self = Self(0x0a); #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, + pub const Val11: Self = Self(0x0b); #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, + pub const Val13: Self = Self(0x0d); #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, + pub const Val14: Self = Self(0x0e); #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, + pub const Val15: Self = Self(0x0f); #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, + pub const Val16: Self = Self(0x10); #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, + pub const Val17: Self = Self(0x11); #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, + pub const Val18: Self = Self(0x12); #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, + pub const Val19: Self = Self(0x13); #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT input is selected."] + pub const Val30: Self = Self(0x1e); #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, + pub const Val34: Self = Self(0x22); #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, + pub const Val35: Self = Self(0x23); #[doc = "CTimer2_MAT1 input is selected."] - VAL36 = 0x24, + pub const Val36: Self = Self(0x24); #[doc = "CTimer2_MAT2 input is selected."] - VAL37 = 0x25, + pub const Val37: Self = Self(0x25); #[doc = "CTimer2_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, + pub const Val38: Self = Self(0x26); #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, + pub const Val48: Self = Self(0x30); #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, + pub const Val49: Self = Self(0x31); #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, + pub const Val50: Self = Self(0x32); #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, + pub const Val51: Self = Self(0x33); #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, + pub const Val52: Self = Self(0x34); #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, + pub const Val53: Self = Self(0x35); #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, + pub const Val54: Self = Self(0x36); #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, + pub const Val55: Self = Self(0x37); #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, + pub const Val56: Self = Self(0x38); #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, + pub const Val57: Self = Self(0x39); #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, + pub const Val58: Self = Self(0x3a); #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, + pub const Val59: Self = Self(0x3b); #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, + pub const Val60: Self = Self(0x3c); #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, + pub const Val61: Self = Self(0x3d); #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, + pub const Val62: Self = Self(0x3e); #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, + pub const Val63: Self = Self(0x3f); #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, + pub const Val64: Self = Self(0x40); #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, + pub const Val65: Self = Self(0x41); #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, + pub const Val66: Self = Self(0x42); #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, + pub const Val67: Self = Self(0x43); #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, + pub const Val68: Self = Self(0x44); #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, + pub const Val69: Self = Self(0x45); #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, + pub const Val70: Self = Self(0x46); #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, + pub const Val75: Self = Self(0x4b); #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, + pub const Val76: Self = Self(0x4c); #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, + pub const Val77: Self = Self(0x4d); #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, - #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, + pub const Val78: Self = Self(0x4e); + #[doc = "CTimer3_MAT1 is selected."] + pub const Val79: Self = Self(0x4f); #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, + pub const Val80: Self = Self(0x50); #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, + pub const Val81: Self = Self(0x51); #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, + pub const Val82: Self = Self(0x52); #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, + pub const Val83: Self = Self(0x53); #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, - #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, + pub const Val84: Self = Self(0x54); + #[doc = "LPI2C2 Master End of Packet is selected."] + pub const Val94: Self = Self(0x5e); #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, + pub const Val95: Self = Self(0x5f); #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, + pub const Val96: Self = Self(0x60); #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, + pub const Val97: Self = Self(0x61); #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, + pub const Val98: Self = Self(0x62); #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, + pub const Val99: Self = Self(0x63); #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val100: Self = Self(0x64); + #[doc = "TRIG_IN0 input is selected."] + pub const Val113: Self = Self(0x71); + #[doc = "TRIG_IN1 input is selected."] + pub const Val114: Self = Self(0x72); + #[doc = "TRIG_IN2 input is selected."] + pub const Val115: Self = Self(0x73); + #[doc = "TRIG_IN3 input is selected."] + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 input is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 input is selected."] + pub const Val118: Self = Self(0x76); + #[doc = "TRIG_IN6 input is selected."] + pub const Val119: Self = Self(0x77); + #[doc = "TRIG_IN7 input is selected."] + pub const Val120: Self = Self(0x78); + #[doc = "TRIG_IN8 input is selected."] + pub const Val121: Self = Self(0x79); + #[doc = "TRIG_IN9 input is selected."] + pub const Val122: Self = Self(0x7a); + #[doc = "TRIG_IN10 input is selected."] + pub const Val123: Self = Self(0x7b); + #[doc = "TRIG_IN11 input is selected."] + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } impl Timer1trigInp { - #[inline(always)] pub const fn from_bits(val: u8) -> Timer1trigInp { - unsafe { core::mem::transmute(val & 0x7f) } + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Timer1trigInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Timer1trigInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } impl From for Timer1trigInp { @@ -8113,255 +5679,412 @@ impl From for u8 { Timer1trigInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timer2trigInp { - _RESERVED_0 = 0x0, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Timer2trigInp(u8); +impl Timer2trigInp { #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, + pub const Val1: Self = Self(0x01); #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, + pub const Val2: Self = Self(0x02); #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, + pub const Val3: Self = Self(0x03); #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, + pub const Val4: Self = Self(0x04); #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, + pub const Val5: Self = Self(0x05); #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, + pub const Val6: Self = Self(0x06); #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, + pub const Val7: Self = Self(0x07); #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, + pub const Val8: Self = Self(0x08); #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, + pub const Val9: Self = Self(0x09); #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, + pub const Val10: Self = Self(0x0a); #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, + pub const Val11: Self = Self(0x0b); #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, + pub const Val13: Self = Self(0x0d); #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, + pub const Val14: Self = Self(0x0e); #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, + pub const Val15: Self = Self(0x0f); #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, + pub const Val16: Self = Self(0x10); #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, + pub const Val17: Self = Self(0x11); #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, + pub const Val18: Self = Self(0x12); #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, + pub const Val19: Self = Self(0x13); #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, + pub const Val25: Self = Self(0x19); #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, + pub const Val26: Self = Self(0x1a); #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, + pub const Val27: Self = Self(0x1b); #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, + pub const Val28: Self = Self(0x1c); #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, + pub const Val29: Self = Self(0x1d); #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, + pub const Val30: Self = Self(0x1e); #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, + pub const Val34: Self = Self(0x22); #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, + pub const Val35: Self = Self(0x23); #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, + pub const Val36: Self = Self(0x24); #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, + pub const Val37: Self = Self(0x25); #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, + pub const Val38: Self = Self(0x26); #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, + pub const Val48: Self = Self(0x30); #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, + pub const Val49: Self = Self(0x31); #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, + pub const Val50: Self = Self(0x32); #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, + pub const Val51: Self = Self(0x33); #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, + pub const Val52: Self = Self(0x34); #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, + pub const Val53: Self = Self(0x35); #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, + pub const Val54: Self = Self(0x36); #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, + pub const Val55: Self = Self(0x37); #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, + pub const Val56: Self = Self(0x38); #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, + pub const Val57: Self = Self(0x39); #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, + pub const Val58: Self = Self(0x3a); #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, + pub const Val59: Self = Self(0x3b); #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, + pub const Val60: Self = Self(0x3c); #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, + pub const Val61: Self = Self(0x3d); #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, + pub const Val62: Self = Self(0x3e); #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, + pub const Val63: Self = Self(0x3f); #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, + pub const Val64: Self = Self(0x40); #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, + pub const Val65: Self = Self(0x41); #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, + pub const Val66: Self = Self(0x42); #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, + pub const Val67: Self = Self(0x43); #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, + pub const Val68: Self = Self(0x44); #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, + pub const Val69: Self = Self(0x45); #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, + pub const Val70: Self = Self(0x46); #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, + pub const Val75: Self = Self(0x4b); #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, + pub const Val76: Self = Self(0x4c); #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, + pub const Val77: Self = Self(0x4d); #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, + pub const Val78: Self = Self(0x4e); #[doc = "CTimer3_MAT1 input is selected."] - VAL79 = 0x4f, - #[doc = "CTimer3_MAT2 input is selected."] - VAL80 = 0x50, + pub const Val79: Self = Self(0x4f); + #[doc = "CTimer3_MAT2 is selected."] + pub const Val80: Self = Self(0x50); #[doc = "CTimer3_MAT3 input is selected."] - VAL81 = 0x51, + pub const Val81: Self = Self(0x51); #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, + pub const Val82: Self = Self(0x52); #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, + pub const Val83: Self = Self(0x53); #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, + pub const Val84: Self = Self(0x54); #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, + pub const Val94: Self = Self(0x5e); #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, + pub const Val95: Self = Self(0x5f); #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, + pub const Val96: Self = Self(0x60); #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, + pub const Val97: Self = Self(0x61); #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, + pub const Val98: Self = Self(0x62); #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, + pub const Val99: Self = Self(0x63); #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, - _RESERVED_71 = 0x71, - _RESERVED_72 = 0x72, - _RESERVED_73 = 0x73, - _RESERVED_74 = 0x74, - _RESERVED_75 = 0x75, - _RESERVED_76 = 0x76, - _RESERVED_77 = 0x77, - _RESERVED_78 = 0x78, - _RESERVED_79 = 0x79, - _RESERVED_7a = 0x7a, - _RESERVED_7b = 0x7b, - _RESERVED_7c = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val100: Self = Self(0x64); + #[doc = "TRIG_IN0 input is selected."] + pub const Val113: Self = Self(0x71); + #[doc = "TRIG_IN1 input is selected."] + pub const Val114: Self = Self(0x72); + #[doc = "TRIG_IN2 input is selected."] + pub const Val115: Self = Self(0x73); + #[doc = "TRIG_IN3 input is selected."] + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 input is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 input is selected."] + pub const Val118: Self = Self(0x76); + #[doc = "TRIG_IN6 input is selected."] + pub const Val119: Self = Self(0x77); + #[doc = "TRIG_IN7 input is selected."] + pub const Val120: Self = Self(0x78); + #[doc = "TRIG_IN8 input is selected."] + pub const Val121: Self = Self(0x79); + #[doc = "TRIG_IN9 input is selected."] + pub const Val122: Self = Self(0x7a); + #[doc = "TRIG_IN10 input is selected."] + pub const Val123: Self = Self(0x7b); + #[doc = "TRIG_IN11 input is selected."] + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } impl Timer2trigInp { - #[inline(always)] pub const fn from_bits(val: u8) -> Timer2trigInp { - unsafe { core::mem::transmute(val & 0x7f) } + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Timer2trigInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Timer2trigInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } impl From for Timer2trigInp { @@ -8376,267 +6099,420 @@ impl From for u8 { Timer2trigInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timer3trigInp { - _RESERVED_0 = 0x0, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Timer3trigInp(u8); +impl Timer3trigInp { #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, + pub const Val1: Self = Self(0x01); #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, + pub const Val2: Self = Self(0x02); #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, + pub const Val3: Self = Self(0x03); #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, + pub const Val4: Self = Self(0x04); #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, + pub const Val5: Self = Self(0x05); #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, + pub const Val6: Self = Self(0x06); #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, + pub const Val7: Self = Self(0x07); #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, + pub const Val8: Self = Self(0x08); #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, + pub const Val9: Self = Self(0x09); #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, + pub const Val10: Self = Self(0x0a); #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, + pub const Val11: Self = Self(0x0b); #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, + pub const Val13: Self = Self(0x0d); #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, + pub const Val14: Self = Self(0x0e); #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, + pub const Val15: Self = Self(0x0f); #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, + pub const Val16: Self = Self(0x10); #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, + pub const Val17: Self = Self(0x11); #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, + pub const Val18: Self = Self(0x12); #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, + pub const Val19: Self = Self(0x13); #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT input is selected."] + pub const Val30: Self = Self(0x1e); #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, + pub const Val34: Self = Self(0x22); #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, + pub const Val35: Self = Self(0x23); #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, + pub const Val36: Self = Self(0x24); #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, + pub const Val37: Self = Self(0x25); #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, + pub const Val38: Self = Self(0x26); #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, + pub const Val48: Self = Self(0x30); #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, + pub const Val49: Self = Self(0x31); #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, + pub const Val50: Self = Self(0x32); #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, + pub const Val51: Self = Self(0x33); #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, + pub const Val52: Self = Self(0x34); #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, + pub const Val53: Self = Self(0x35); #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, + pub const Val54: Self = Self(0x36); #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, + pub const Val55: Self = Self(0x37); #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, + pub const Val56: Self = Self(0x38); #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, + pub const Val57: Self = Self(0x39); #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, + pub const Val58: Self = Self(0x3a); #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, + pub const Val59: Self = Self(0x3b); #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, + pub const Val60: Self = Self(0x3c); #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, + pub const Val61: Self = Self(0x3d); #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, + pub const Val62: Self = Self(0x3e); #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, + pub const Val63: Self = Self(0x3f); #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, + pub const Val64: Self = Self(0x40); #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, + pub const Val65: Self = Self(0x41); #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, + pub const Val66: Self = Self(0x42); #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, + pub const Val67: Self = Self(0x43); #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, - #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, + pub const Val68: Self = Self(0x44); + #[doc = "LPUART4 Transmitted Data Word is selected."] + pub const Val69: Self = Self(0x45); #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, + pub const Val70: Self = Self(0x46); #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, + pub const Val75: Self = Self(0x4b); #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, + pub const Val76: Self = Self(0x4c); #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, + pub const Val77: Self = Self(0x4d); #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, + pub const Val78: Self = Self(0x4e); #[doc = "CTimer2_MAT1 input is selected."] - VAL79 = 0x4f, + pub const Val79: Self = Self(0x4f); #[doc = "CTimer2_MAT2 input is selected."] - VAL80 = 0x50, + pub const Val80: Self = Self(0x50); #[doc = "CTimer2_MAT3 input is selected."] - VAL81 = 0x51, + pub const Val81: Self = Self(0x51); #[doc = "CTimer4_MAT1 input is selected."] - VAL82 = 0x52, + pub const Val82: Self = Self(0x52); #[doc = "CTimer4_MAT2 input is selected."] - VAL83 = 0x53, + pub const Val83: Self = Self(0x53); #[doc = "CTimer4_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, + pub const Val84: Self = Self(0x54); #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, + pub const Val94: Self = Self(0x5e); #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, + pub const Val95: Self = Self(0x5f); #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, + pub const Val96: Self = Self(0x60); #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, + pub const Val97: Self = Self(0x61); #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, + pub const Val98: Self = Self(0x62); #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, + pub const Val99: Self = Self(0x63); #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, + pub const Val100: Self = Self(0x64); + #[doc = "TMPR_OUT0 input is selected."] + pub const Val102: Self = Self(0x66); + #[doc = "TMPR_OUT1 input is selected."] + pub const Val103: Self = Self(0x67); #[doc = "TRIG_IN0 input is selected."] - VAL113 = 0x71, + pub const Val113: Self = Self(0x71); #[doc = "TRIG_IN1 input is selected."] - VAL114 = 0x72, + pub const Val114: Self = Self(0x72); #[doc = "TRIG_IN2 input is selected."] - VAL115 = 0x73, + pub const Val115: Self = Self(0x73); #[doc = "TRIG_IN3 input is selected."] - VAL116 = 0x74, + pub const Val116: Self = Self(0x74); #[doc = "TRIG_IN4 input is selected."] - VAL117 = 0x75, + pub const Val117: Self = Self(0x75); #[doc = "TRIG_IN5 input is selected."] - VAL118 = 0x76, + pub const Val118: Self = Self(0x76); #[doc = "TRIG_IN6 input is selected."] - VAL119 = 0x77, + pub const Val119: Self = Self(0x77); #[doc = "TRIG_IN7 input is selected."] - VAL120 = 0x78, + pub const Val120: Self = Self(0x78); #[doc = "TRIG_IN8 input is selected."] - VAL121 = 0x79, + pub const Val121: Self = Self(0x79); #[doc = "TRIG_IN9 input is selected."] - VAL122 = 0x7a, + pub const Val122: Self = Self(0x7a); #[doc = "TRIG_IN10 input is selected."] - VAL123 = 0x7b, + pub const Val123: Self = Self(0x7b); #[doc = "TRIG_IN11 input is selected."] - VAL124 = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } impl Timer3trigInp { - #[inline(always)] pub const fn from_bits(val: u8) -> Timer3trigInp { - unsafe { core::mem::transmute(val & 0x7f) } + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Timer3trigInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x66 => f.write_str("Val102"), + 0x67 => f.write_str("Val103"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Timer3trigInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x66 => defmt::write!(f, "Val102"), + 0x67 => defmt::write!(f, "Val103"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } impl From for Timer3trigInp { @@ -8651,267 +6527,420 @@ impl From for u8 { Timer3trigInp::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timer4trigInp { - _RESERVED_0 = 0x0, +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Timer4trigInp(u8); +impl Timer4trigInp { #[doc = "CT_INP0 input is selected."] - VAL1 = 0x01, + pub const Val1: Self = Self(0x01); #[doc = "CT_INP1 input is selected."] - VAL2 = 0x02, + pub const Val2: Self = Self(0x02); #[doc = "CT_INP2 input is selected."] - VAL3 = 0x03, + pub const Val3: Self = Self(0x03); #[doc = "CT_INP3 input is selected."] - VAL4 = 0x04, + pub const Val4: Self = Self(0x04); #[doc = "CT_INP4 input is selected."] - VAL5 = 0x05, + pub const Val5: Self = Self(0x05); #[doc = "CT_INP5 input is selected."] - VAL6 = 0x06, + pub const Val6: Self = Self(0x06); #[doc = "CT_INP6 input is selected."] - VAL7 = 0x07, + pub const Val7: Self = Self(0x07); #[doc = "CT_INP7 input is selected."] - VAL8 = 0x08, + pub const Val8: Self = Self(0x08); #[doc = "CT_INP8 input is selected."] - VAL9 = 0x09, + pub const Val9: Self = Self(0x09); #[doc = "CT_INP9 input is selected."] - VAL10 = 0x0a, + pub const Val10: Self = Self(0x0a); #[doc = "CT_INP10 input is selected."] - VAL11 = 0x0b, - #[doc = "CT_INP11 input is selected."] - VAL12 = 0x0c, + pub const Val11: Self = Self(0x0b); #[doc = "CT_INP12 input is selected."] - VAL13 = 0x0d, + pub const Val13: Self = Self(0x0d); #[doc = "CT_INP13 input is selected."] - VAL14 = 0x0e, + pub const Val14: Self = Self(0x0e); #[doc = "CT_INP14 input is selected."] - VAL15 = 0x0f, + pub const Val15: Self = Self(0x0f); #[doc = "CT_INP15 input is selected."] - VAL16 = 0x10, + pub const Val16: Self = Self(0x10); #[doc = "CT_INP16 input is selected."] - VAL17 = 0x11, + pub const Val17: Self = Self(0x11); #[doc = "CT_INP17 input is selected."] - VAL18 = 0x12, + pub const Val18: Self = Self(0x12); #[doc = "CT_INP18 input is selected."] - VAL19 = 0x13, + pub const Val19: Self = Self(0x13); #[doc = "CT_INP19 input is selected."] - VAL20 = 0x14, - #[doc = "USB0 usb0 start of frame input is selected."] - VAL21 = 0x15, + pub const Val20: Self = Self(0x14); #[doc = "AOI0_OUT0 input is selected."] - VAL22 = 0x16, + pub const Val22: Self = Self(0x16); #[doc = "AOI0_OUT1 input is selected."] - VAL23 = 0x17, + pub const Val23: Self = Self(0x17); #[doc = "AOI0_OUT2 input is selected."] - VAL24 = 0x18, + pub const Val24: Self = Self(0x18); #[doc = "AOI0_OUT3 input is selected."] - VAL25 = 0x19, - #[doc = "ADC0_tcomp\\[0\\]."] - VAL26 = 0x1a, - #[doc = "ADC0_tcomp\\[1\\]."] - VAL27 = 0x1b, - #[doc = "ADC0_tcomp\\[2\\]."] - VAL28 = 0x1c, + pub const Val25: Self = Self(0x19); + #[doc = "ADC0_tcomp\\[0\\] input is selected."] + pub const Val26: Self = Self(0x1a); + #[doc = "ADC0_tcomp\\[1\\] input is selected."] + pub const Val27: Self = Self(0x1b); + #[doc = "ADC0_tcomp\\[2\\] input is selected."] + pub const Val28: Self = Self(0x1c); #[doc = "ADC0_tcomp\\[3\\] input is selected."] - VAL29 = 0x1d, - #[doc = "CMP0_OUT is selected."] - VAL30 = 0x1e, - #[doc = "CMP1_OUT is selected."] - VAL31 = 0x1f, - #[doc = "CMP2_OUT is selected."] - VAL32 = 0x20, + pub const Val29: Self = Self(0x1d); + #[doc = "CMP0_OUT input is selected."] + pub const Val30: Self = Self(0x1e); #[doc = "CTimer0_MAT1 input is selected."] - VAL33 = 0x21, + pub const Val33: Self = Self(0x21); #[doc = "CTimer0_MAT2 input is selected."] - VAL34 = 0x22, + pub const Val34: Self = Self(0x22); #[doc = "CTimer0_MAT3 input is selected."] - VAL35 = 0x23, + pub const Val35: Self = Self(0x23); #[doc = "CTimer1_MAT1 input is selected."] - VAL36 = 0x24, + pub const Val36: Self = Self(0x24); #[doc = "CTimer1_MAT2 input is selected."] - VAL37 = 0x25, + pub const Val37: Self = Self(0x25); #[doc = "CTimer1_MAT3 input is selected."] - VAL38 = 0x26, - #[doc = "QDC0_CMP_FLAG0 is selected."] - VAL39 = 0x27, - #[doc = "QDC0_CMP_FLAG1 input is selected."] - VAL40 = 0x28, - #[doc = "QDC0_CMP_FLAG2 input is selected."] - VAL41 = 0x29, - #[doc = "QDC0_CMP_FLAG3 input is selected."] - VAL42 = 0x2a, - #[doc = "QDC0_POS_MATCH0 input is selected."] - VAL43 = 0x2b, - #[doc = "PWM0_SM0_MUX_TRIG0 input is selected."] - VAL44 = 0x2c, - #[doc = "PWM0_SM1_MUX_TRIG0 input is selected."] - VAL45 = 0x2d, - #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] - VAL46 = 0x2e, - #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] - VAL47 = 0x2f, + pub const Val38: Self = Self(0x26); #[doc = "LPI2C0 Master End of Packet input is selected."] - VAL48 = 0x30, + pub const Val48: Self = Self(0x30); #[doc = "LPI2C0 Slave End of Packet input is selected."] - VAL49 = 0x31, + pub const Val49: Self = Self(0x31); #[doc = "LPI2C1 Master End of Packet input is selected."] - VAL50 = 0x32, + pub const Val50: Self = Self(0x32); #[doc = "LPI2C1 Slave End of Packet input is selected."] - VAL51 = 0x33, + pub const Val51: Self = Self(0x33); #[doc = "LPSPI0 End of Frame input is selected."] - VAL52 = 0x34, + pub const Val52: Self = Self(0x34); #[doc = "LPSPI0 Received Data Word input is selected."] - VAL53 = 0x35, + pub const Val53: Self = Self(0x35); #[doc = "LPSPI1 End of Frame input is selected."] - VAL54 = 0x36, + pub const Val54: Self = Self(0x36); #[doc = "LPSPI1 Received Data Word input is selected."] - VAL55 = 0x37, + pub const Val55: Self = Self(0x37); #[doc = "LPUART0 Received Data Word input is selected."] - VAL56 = 0x38, + pub const Val56: Self = Self(0x38); #[doc = "LPUART0 Transmitted Data Word input is selected."] - VAL57 = 0x39, + pub const Val57: Self = Self(0x39); #[doc = "LPUART0 Receive Line Idle input is selected."] - VAL58 = 0x3a, + pub const Val58: Self = Self(0x3a); #[doc = "LPUART1 Received Data Word input is selected."] - VAL59 = 0x3b, + pub const Val59: Self = Self(0x3b); #[doc = "LPUART1 Transmitted Data Word input is selected."] - VAL60 = 0x3c, + pub const Val60: Self = Self(0x3c); #[doc = "LPUART1 Receive Line Idle input is selected."] - VAL61 = 0x3d, + pub const Val61: Self = Self(0x3d); #[doc = "LPUART2 Received Data Word input is selected."] - VAL62 = 0x3e, + pub const Val62: Self = Self(0x3e); #[doc = "LPUART2 Transmitted Data Word input is selected."] - VAL63 = 0x3f, + pub const Val63: Self = Self(0x3f); #[doc = "LPUART2 Receive Line Idle input is selected."] - VAL64 = 0x40, + pub const Val64: Self = Self(0x40); #[doc = "LPUART3 Received Data Word input is selected."] - VAL65 = 0x41, + pub const Val65: Self = Self(0x41); #[doc = "LPUART3 Transmitted Data Word input is selected."] - VAL66 = 0x42, + pub const Val66: Self = Self(0x42); #[doc = "LPUART3 Receive Line Idle input is selected."] - VAL67 = 0x43, + pub const Val67: Self = Self(0x43); #[doc = "LPUART4 Received Data Word input is selected."] - VAL68 = 0x44, + pub const Val68: Self = Self(0x44); #[doc = "LPUART4 Transmitted Data Word input is selected."] - VAL69 = 0x45, + pub const Val69: Self = Self(0x45); #[doc = "LPUART4 Receive Line Idle input is selected."] - VAL70 = 0x46, - #[doc = "AOI1_OUT0 input is selected."] - VAL71 = 0x47, - #[doc = "AOI1_OUT1 input is selected."] - VAL72 = 0x48, - #[doc = "AOI1_OUT2 input is selected."] - VAL73 = 0x49, - #[doc = "AOI1_OUT3 input is selected."] - VAL74 = 0x4a, + pub const Val70: Self = Self(0x46); #[doc = "ADC1_tcomp\\[0\\] input is selected."] - VAL75 = 0x4b, + pub const Val75: Self = Self(0x4b); #[doc = "ADC1_tcomp\\[1\\] input is selected."] - VAL76 = 0x4c, + pub const Val76: Self = Self(0x4c); #[doc = "ADC1_tcomp\\[2\\] input is selected."] - VAL77 = 0x4d, + pub const Val77: Self = Self(0x4d); #[doc = "ADC1_tcomp\\[3\\] input is selected."] - VAL78 = 0x4e, + pub const Val78: Self = Self(0x4e); #[doc = "CTimer2_MAT1 input is selected."] - VAL79 = 0x4f, + pub const Val79: Self = Self(0x4f); #[doc = "CTimer2_MAT2 input is selected."] - VAL80 = 0x50, + pub const Val80: Self = Self(0x50); #[doc = "CTimer2_MAT3 input is selected."] - VAL81 = 0x51, + pub const Val81: Self = Self(0x51); #[doc = "CTimer3_MAT1 input is selected."] - VAL82 = 0x52, + pub const Val82: Self = Self(0x52); #[doc = "CTimer3_MAT2 input is selected."] - VAL83 = 0x53, + pub const Val83: Self = Self(0x53); #[doc = "CTimer3_MAT3 input is selected."] - VAL84 = 0x54, - #[doc = "QDC1_CMP_FLAG0 input is selected."] - VAL85 = 0x55, - #[doc = "QDC1_CMP_FLAG1 input is selected."] - VAL86 = 0x56, - #[doc = "QDC1_CMP_FLAG2 input is selected."] - VAL87 = 0x57, - #[doc = "QDC1_CMP_FLAG3 input is selected."] - VAL88 = 0x58, - #[doc = "QDC1_POS_MATCH0 input is selected."] - VAL89 = 0x59, - #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] - VAL90 = 0x5a, - #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] - VAL91 = 0x5b, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL92 = 0x5c, - #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] - VAL93 = 0x5d, + pub const Val84: Self = Self(0x54); #[doc = "LPI2C2 Master End of Packet input is selected."] - VAL94 = 0x5e, + pub const Val94: Self = Self(0x5e); #[doc = "LPI2C2 Slave End of Packet input is selected."] - VAL95 = 0x5f, + pub const Val95: Self = Self(0x5f); #[doc = "LPI2C3 Master End of Packet input is selected."] - VAL96 = 0x60, + pub const Val96: Self = Self(0x60); #[doc = "LPI2C3 Slave End of Packet input is selected."] - VAL97 = 0x61, + pub const Val97: Self = Self(0x61); #[doc = "LPUART5 Received Data Word input is selected."] - VAL98 = 0x62, + pub const Val98: Self = Self(0x62); #[doc = "LPUART5 Transmitted Data Word input is selected."] - VAL99 = 0x63, + pub const Val99: Self = Self(0x63); #[doc = "LPUART5 Receive Line Idle input is selected."] - VAL100 = 0x64, - _RESERVED_65 = 0x65, - _RESERVED_66 = 0x66, - _RESERVED_67 = 0x67, - _RESERVED_68 = 0x68, - #[doc = "ADC2_tcomp\\[0\\] input is selected."] - VAL105 = 0x69, - #[doc = "ADC2_tcomp\\[1\\] input is selected."] - VAL106 = 0x6a, - #[doc = "ADC2_tcomp\\[2\\] input is selected."] - VAL107 = 0x6b, - #[doc = "ADC2_tcomp\\[3\\] input is selected."] - VAL108 = 0x6c, - #[doc = "ADC3_tcomp\\[0\\] input is selected."] - VAL109 = 0x6d, - #[doc = "ADC3_tcomp\\[1\\] input is selected."] - VAL110 = 0x6e, - #[doc = "ADC3_tcomp\\[2\\] input is selected."] - VAL111 = 0x6f, - #[doc = "ADC3_tcomp\\[3\\] input is selected."] - VAL112 = 0x70, + pub const Val100: Self = Self(0x64); + #[doc = "TMPR_OUT0 input is selected."] + pub const Val102: Self = Self(0x66); + #[doc = "TMPR_OUT1 input is selected."] + pub const Val103: Self = Self(0x67); #[doc = "TRIG_IN0 input is selected."] - VAL113 = 0x71, + pub const Val113: Self = Self(0x71); #[doc = "TRIG_IN1 input is selected."] - VAL114 = 0x72, + pub const Val114: Self = Self(0x72); #[doc = "TRIG_IN2 input is selected."] - VAL115 = 0x73, + pub const Val115: Self = Self(0x73); #[doc = "TRIG_IN3 input is selected."] - VAL116 = 0x74, - #[doc = "TRIG_IN4 input is selected."] - VAL117 = 0x75, - #[doc = "TRIG_IN5 input is selected."] - VAL118 = 0x76, + pub const Val116: Self = Self(0x74); + #[doc = "TRIG_IN4 is selected."] + pub const Val117: Self = Self(0x75); + #[doc = "TRIG_IN5 is selected."] + pub const Val118: Self = Self(0x76); #[doc = "TRIG_IN6 input is selected."] - VAL119 = 0x77, + pub const Val119: Self = Self(0x77); #[doc = "TRIG_IN7 input is selected."] - VAL120 = 0x78, + pub const Val120: Self = Self(0x78); #[doc = "TRIG_IN8 input is selected."] - VAL121 = 0x79, + pub const Val121: Self = Self(0x79); #[doc = "TRIG_IN9 input is selected."] - VAL122 = 0x7a, + pub const Val122: Self = Self(0x7a); #[doc = "TRIG_IN10 input is selected."] - VAL123 = 0x7b, + pub const Val123: Self = Self(0x7b); #[doc = "TRIG_IN11 input is selected."] - VAL124 = 0x7c, - _RESERVED_7d = 0x7d, - _RESERVED_7e = 0x7e, - _RESERVED_7f = 0x7f, + pub const Val124: Self = Self(0x7c); + #[doc = "USB1 Start of Frame input is selected."] + pub const Val125: Self = Self(0x7d); + #[doc = "LPSPI2 End of Frame input is selected."] + pub const Val126: Self = Self(0x7e); + #[doc = "LPSPI2 Received Data Word input is selected."] + pub const Val127: Self = Self(0x7f); + #[doc = "LPSPI3 End of Frame input is selected."] + pub const Val128: Self = Self(0x80); + #[doc = "LPSPI3 Received Data Word input is selected."] + pub const Val129: Self = Self(0x81); + #[doc = "LPSPI4 End of Frame input is selected."] + pub const Val130: Self = Self(0x82); + #[doc = "LPSPI4 Received Data Word input is selected."] + pub const Val131: Self = Self(0x83); + #[doc = "LPSPI5 End of Frame input is selected."] + pub const Val132: Self = Self(0x84); + #[doc = "LPSPI5 Received Data Word input is selected."] + pub const Val133: Self = Self(0x85); } impl Timer4trigInp { - #[inline(always)] pub const fn from_bits(val: u8) -> Timer4trigInp { - unsafe { core::mem::transmute(val & 0x7f) } + Self(val & 0xff) } - #[inline(always)] pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } + self.0 + } +} +impl core::fmt::Debug for Timer4trigInp { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x01 => f.write_str("Val1"), + 0x02 => f.write_str("Val2"), + 0x03 => f.write_str("Val3"), + 0x04 => f.write_str("Val4"), + 0x05 => f.write_str("Val5"), + 0x06 => f.write_str("Val6"), + 0x07 => f.write_str("Val7"), + 0x08 => f.write_str("Val8"), + 0x09 => f.write_str("Val9"), + 0x0a => f.write_str("Val10"), + 0x0b => f.write_str("Val11"), + 0x0d => f.write_str("Val13"), + 0x0e => f.write_str("Val14"), + 0x0f => f.write_str("Val15"), + 0x10 => f.write_str("Val16"), + 0x11 => f.write_str("Val17"), + 0x12 => f.write_str("Val18"), + 0x13 => f.write_str("Val19"), + 0x14 => f.write_str("Val20"), + 0x16 => f.write_str("Val22"), + 0x17 => f.write_str("Val23"), + 0x18 => f.write_str("Val24"), + 0x19 => f.write_str("Val25"), + 0x1a => f.write_str("Val26"), + 0x1b => f.write_str("Val27"), + 0x1c => f.write_str("Val28"), + 0x1d => f.write_str("Val29"), + 0x1e => f.write_str("Val30"), + 0x21 => f.write_str("Val33"), + 0x22 => f.write_str("Val34"), + 0x23 => f.write_str("Val35"), + 0x24 => f.write_str("Val36"), + 0x25 => f.write_str("Val37"), + 0x26 => f.write_str("Val38"), + 0x30 => f.write_str("Val48"), + 0x31 => f.write_str("Val49"), + 0x32 => f.write_str("Val50"), + 0x33 => f.write_str("Val51"), + 0x34 => f.write_str("Val52"), + 0x35 => f.write_str("Val53"), + 0x36 => f.write_str("Val54"), + 0x37 => f.write_str("Val55"), + 0x38 => f.write_str("Val56"), + 0x39 => f.write_str("Val57"), + 0x3a => f.write_str("Val58"), + 0x3b => f.write_str("Val59"), + 0x3c => f.write_str("Val60"), + 0x3d => f.write_str("Val61"), + 0x3e => f.write_str("Val62"), + 0x3f => f.write_str("Val63"), + 0x40 => f.write_str("Val64"), + 0x41 => f.write_str("Val65"), + 0x42 => f.write_str("Val66"), + 0x43 => f.write_str("Val67"), + 0x44 => f.write_str("Val68"), + 0x45 => f.write_str("Val69"), + 0x46 => f.write_str("Val70"), + 0x4b => f.write_str("Val75"), + 0x4c => f.write_str("Val76"), + 0x4d => f.write_str("Val77"), + 0x4e => f.write_str("Val78"), + 0x4f => f.write_str("Val79"), + 0x50 => f.write_str("Val80"), + 0x51 => f.write_str("Val81"), + 0x52 => f.write_str("Val82"), + 0x53 => f.write_str("Val83"), + 0x54 => f.write_str("Val84"), + 0x5e => f.write_str("Val94"), + 0x5f => f.write_str("Val95"), + 0x60 => f.write_str("Val96"), + 0x61 => f.write_str("Val97"), + 0x62 => f.write_str("Val98"), + 0x63 => f.write_str("Val99"), + 0x64 => f.write_str("Val100"), + 0x66 => f.write_str("Val102"), + 0x67 => f.write_str("Val103"), + 0x71 => f.write_str("Val113"), + 0x72 => f.write_str("Val114"), + 0x73 => f.write_str("Val115"), + 0x74 => f.write_str("Val116"), + 0x75 => f.write_str("Val117"), + 0x76 => f.write_str("Val118"), + 0x77 => f.write_str("Val119"), + 0x78 => f.write_str("Val120"), + 0x79 => f.write_str("Val121"), + 0x7a => f.write_str("Val122"), + 0x7b => f.write_str("Val123"), + 0x7c => f.write_str("Val124"), + 0x7d => f.write_str("Val125"), + 0x7e => f.write_str("Val126"), + 0x7f => f.write_str("Val127"), + 0x80 => f.write_str("Val128"), + 0x81 => f.write_str("Val129"), + 0x82 => f.write_str("Val130"), + 0x83 => f.write_str("Val131"), + 0x84 => f.write_str("Val132"), + 0x85 => f.write_str("Val133"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Timer4trigInp { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x01 => defmt::write!(f, "Val1"), + 0x02 => defmt::write!(f, "Val2"), + 0x03 => defmt::write!(f, "Val3"), + 0x04 => defmt::write!(f, "Val4"), + 0x05 => defmt::write!(f, "Val5"), + 0x06 => defmt::write!(f, "Val6"), + 0x07 => defmt::write!(f, "Val7"), + 0x08 => defmt::write!(f, "Val8"), + 0x09 => defmt::write!(f, "Val9"), + 0x0a => defmt::write!(f, "Val10"), + 0x0b => defmt::write!(f, "Val11"), + 0x0d => defmt::write!(f, "Val13"), + 0x0e => defmt::write!(f, "Val14"), + 0x0f => defmt::write!(f, "Val15"), + 0x10 => defmt::write!(f, "Val16"), + 0x11 => defmt::write!(f, "Val17"), + 0x12 => defmt::write!(f, "Val18"), + 0x13 => defmt::write!(f, "Val19"), + 0x14 => defmt::write!(f, "Val20"), + 0x16 => defmt::write!(f, "Val22"), + 0x17 => defmt::write!(f, "Val23"), + 0x18 => defmt::write!(f, "Val24"), + 0x19 => defmt::write!(f, "Val25"), + 0x1a => defmt::write!(f, "Val26"), + 0x1b => defmt::write!(f, "Val27"), + 0x1c => defmt::write!(f, "Val28"), + 0x1d => defmt::write!(f, "Val29"), + 0x1e => defmt::write!(f, "Val30"), + 0x21 => defmt::write!(f, "Val33"), + 0x22 => defmt::write!(f, "Val34"), + 0x23 => defmt::write!(f, "Val35"), + 0x24 => defmt::write!(f, "Val36"), + 0x25 => defmt::write!(f, "Val37"), + 0x26 => defmt::write!(f, "Val38"), + 0x30 => defmt::write!(f, "Val48"), + 0x31 => defmt::write!(f, "Val49"), + 0x32 => defmt::write!(f, "Val50"), + 0x33 => defmt::write!(f, "Val51"), + 0x34 => defmt::write!(f, "Val52"), + 0x35 => defmt::write!(f, "Val53"), + 0x36 => defmt::write!(f, "Val54"), + 0x37 => defmt::write!(f, "Val55"), + 0x38 => defmt::write!(f, "Val56"), + 0x39 => defmt::write!(f, "Val57"), + 0x3a => defmt::write!(f, "Val58"), + 0x3b => defmt::write!(f, "Val59"), + 0x3c => defmt::write!(f, "Val60"), + 0x3d => defmt::write!(f, "Val61"), + 0x3e => defmt::write!(f, "Val62"), + 0x3f => defmt::write!(f, "Val63"), + 0x40 => defmt::write!(f, "Val64"), + 0x41 => defmt::write!(f, "Val65"), + 0x42 => defmt::write!(f, "Val66"), + 0x43 => defmt::write!(f, "Val67"), + 0x44 => defmt::write!(f, "Val68"), + 0x45 => defmt::write!(f, "Val69"), + 0x46 => defmt::write!(f, "Val70"), + 0x4b => defmt::write!(f, "Val75"), + 0x4c => defmt::write!(f, "Val76"), + 0x4d => defmt::write!(f, "Val77"), + 0x4e => defmt::write!(f, "Val78"), + 0x4f => defmt::write!(f, "Val79"), + 0x50 => defmt::write!(f, "Val80"), + 0x51 => defmt::write!(f, "Val81"), + 0x52 => defmt::write!(f, "Val82"), + 0x53 => defmt::write!(f, "Val83"), + 0x54 => defmt::write!(f, "Val84"), + 0x5e => defmt::write!(f, "Val94"), + 0x5f => defmt::write!(f, "Val95"), + 0x60 => defmt::write!(f, "Val96"), + 0x61 => defmt::write!(f, "Val97"), + 0x62 => defmt::write!(f, "Val98"), + 0x63 => defmt::write!(f, "Val99"), + 0x64 => defmt::write!(f, "Val100"), + 0x66 => defmt::write!(f, "Val102"), + 0x67 => defmt::write!(f, "Val103"), + 0x71 => defmt::write!(f, "Val113"), + 0x72 => defmt::write!(f, "Val114"), + 0x73 => defmt::write!(f, "Val115"), + 0x74 => defmt::write!(f, "Val116"), + 0x75 => defmt::write!(f, "Val117"), + 0x76 => defmt::write!(f, "Val118"), + 0x77 => defmt::write!(f, "Val119"), + 0x78 => defmt::write!(f, "Val120"), + 0x79 => defmt::write!(f, "Val121"), + 0x7a => defmt::write!(f, "Val122"), + 0x7b => defmt::write!(f, "Val123"), + 0x7c => defmt::write!(f, "Val124"), + 0x7d => defmt::write!(f, "Val125"), + 0x7e => defmt::write!(f, "Val126"), + 0x7f => defmt::write!(f, "Val127"), + 0x80 => defmt::write!(f, "Val128"), + 0x81 => defmt::write!(f, "Val129"), + 0x82 => defmt::write!(f, "Val130"), + 0x83 => defmt::write!(f, "Val131"), + 0x84 => defmt::write!(f, "Val132"), + 0x85 => defmt::write!(f, "Val133"), + other => defmt::write!(f, "0x{:02X}", other), + } } } impl From for Timer4trigInp { @@ -8929,80 +6958,331 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum TrigInVal { - #[doc = "TRIG_IN0 is 0."] - VAL0 = 0x0, - #[doc = "TRIG_IN0 is 1."] - VAL1 = 0x01, +pub enum TrigOutInp { + _RESERVED_0 = 0x0, + _RESERVED_1 = 0x01, + #[doc = "AOI0_OUT0 input is selected."] + Val2 = 0x02, + #[doc = "AOI0_OUT1 input is selected."] + Val3 = 0x03, + #[doc = "AOI0_OUT2 input is selected."] + Val4 = 0x04, + #[doc = "AOI0_OUT3 input is selected."] + Val5 = 0x05, + #[doc = "CMP0_OUT input is selected."] + Val6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + #[doc = "LPUART0 ipp_do_lpuart_txd input is selected."] + Val9 = 0x09, + #[doc = "LPUART1 ipp_do_lpuart_txd input is selected."] + Val10 = 0x0a, + #[doc = "LPUART2 ipp_do_lpuart_txd input is selected."] + Val11 = 0x0b, + #[doc = "LPUART3 ipp_do_lpuart_txd input is selected."] + Val12 = 0x0c, + #[doc = "LPUART4 ipp_do_lpuart_txd input is selected."] + Val13 = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, + #[doc = "ARM_TXEV input is selected."] + Val16 = 0x10, + _RESERVED_11 = 0x11, + #[doc = "LPUART5 ipp_do_lpuart_txd input is selected."] + Val18 = 0x12, + #[doc = "RTC_1Hz_CLK input is selected."] + Val19 = 0x13, + _RESERVED_14 = 0x14, + #[doc = "USB1 Start of Frame input is selected."] + Val21 = 0x15, + #[doc = "PWM0_SM2_MUX_TRIG0 input is selected."] + Val22 = 0x16, + #[doc = "PWM0_SM3_MUX_TRIG0 input is selected."] + Val23 = 0x17, + #[doc = "TRIG_IN0 input is selected."] + Val24 = 0x18, + #[doc = "TRIG_IN1 input is selected."] + Val25 = 0x19, + #[doc = "TRIG_IN2 input is selected."] + Val26 = 0x1a, + #[doc = "TRIG_IN3 input is selected."] + Val27 = 0x1b, + #[doc = "TRIG_IN4 input is selected."] + Val28 = 0x1c, + #[doc = "TRIG_IN5 input is selected."] + Val29 = 0x1d, + #[doc = "TRIG_IN6 input is selected."] + Val30 = 0x1e, + #[doc = "TRIG_IN7 input is selected."] + Val31 = 0x1f, + #[doc = "GPIO0 Pin Event Trig 0 input is selected."] + Val32 = 0x20, + #[doc = "GPIO2 Pin Event Trig 0 input is selected."] + Val33 = 0x21, + #[doc = "GPIO3 Pin Event Trig 0 input is selected."] + Val34 = 0x22, + #[doc = "GPIO4 Pin Event Trig 0 input is selected."] + Val35 = 0x23, + #[doc = "WUU input is selected."] + Val36 = 0x24, + #[doc = "PWM1_A0_TRIG0 input is selected."] + Val37 = 0x25, + #[doc = "LPI2C0 Master End of Packet."] + Val38 = 0x26, + #[doc = "LPI2C0 Slave End of Packet."] + Val39 = 0x27, + #[doc = "LPI2C1 Master End of Packet."] + Val40 = 0x28, + #[doc = "LPI2C1 Slave End of Packet."] + Val41 = 0x29, + #[doc = "LPSPI0 End of Frame."] + Val42 = 0x2a, + #[doc = "LPSPI0 Received Data Word."] + Val43 = 0x2b, + #[doc = "LPSPI1 End of Frame."] + Val44 = 0x2c, + #[doc = "LPSPI1 Received Data Word."] + Val45 = 0x2d, + #[doc = "LPUART0 Received Data Word."] + Val46 = 0x2e, + #[doc = "LPUART0 Transmitted Data Word."] + Val47 = 0x2f, + #[doc = "LPUART0 Receive Line Idle."] + Val48 = 0x30, + #[doc = "LPUART1 Received Data Word."] + Val49 = 0x31, + #[doc = "LPUART1 Transmitted Data Word."] + Val50 = 0x32, + #[doc = "LPUART1 Receive Line Idle."] + Val51 = 0x33, + #[doc = "LPUART2 Received Data Word."] + Val52 = 0x34, + #[doc = "LPUART2 Transmitted Data Word."] + Val53 = 0x35, + #[doc = "LPUART2 Receive Line Idle."] + Val54 = 0x36, + #[doc = "LPUART3 Received Data Word."] + Val55 = 0x37, + #[doc = "LPUART3 Transmitted Data Word."] + Val56 = 0x38, + #[doc = "LPUART3 Receive Line Idle."] + Val57 = 0x39, + #[doc = "LPUART4 Received Data Word."] + Val58 = 0x3a, + #[doc = "LPUART4 Transmitted Data Word."] + Val59 = 0x3b, + #[doc = "LPUART4 Receive Line Idle."] + Val60 = 0x3c, + #[doc = "AOI1_OUT0 input is selected."] + Val61 = 0x3d, + #[doc = "AOI1_OUT1 input is selected."] + Val62 = 0x3e, + #[doc = "AOI1_OUT2 input is selected."] + Val63 = 0x3f, + #[doc = "AOI1_OUT3 input is selected."] + Val64 = 0x40, + #[doc = "ADC1_tcomp\\[0\\] input is selected."] + Val65 = 0x41, + #[doc = "ADC1_tcomp\\[1\\] input is selected."] + Val66 = 0x42, + #[doc = "ADC1_tcomp\\[2\\] input is selected."] + Val67 = 0x43, + #[doc = "ADC1_tcomp\\[3\\] input is selected."] + Val68 = 0x44, + #[doc = "CTimer3_MAT2 input is selected."] + Val69 = 0x45, + #[doc = "CTimer3_MAT3 input is selected."] + Val70 = 0x46, + #[doc = "CTimer4_MAT2 input is selected."] + Val71 = 0x47, + #[doc = "CTimer4_MAT3 input is selected."] + Val72 = 0x48, + #[doc = "PWM1_SM0_MUX_TRIG0 input is selected."] + Val73 = 0x49, + #[doc = "PWM1_SM1_MUX_TRIG0 input is selected."] + Val74 = 0x4a, + #[doc = "PWM1_SM2_MUX_TRIG0 input is selected."] + Val75 = 0x4b, + #[doc = "PWM1_SM3_MUX_TRIG0 input is selected."] + Val76 = 0x4c, + #[doc = "LPI2C2 Master End of Packet."] + Val77 = 0x4d, + #[doc = "LPI2C2 Slave End of Packet."] + Val78 = 0x4e, + #[doc = "LPI2C3 Master End of Packet."] + Val79 = 0x4f, + #[doc = "LPI2C3 Slave End of Packet."] + Val80 = 0x50, + _RESERVED_51 = 0x51, + _RESERVED_52 = 0x52, + _RESERVED_53 = 0x53, + _RESERVED_54 = 0x54, + _RESERVED_55 = 0x55, + _RESERVED_56 = 0x56, + _RESERVED_57 = 0x57, + _RESERVED_58 = 0x58, + _RESERVED_59 = 0x59, + _RESERVED_5a = 0x5a, + _RESERVED_5b = 0x5b, + _RESERVED_5c = 0x5c, + _RESERVED_5d = 0x5d, + _RESERVED_5e = 0x5e, + _RESERVED_5f = 0x5f, + _RESERVED_60 = 0x60, + _RESERVED_61 = 0x61, + _RESERVED_62 = 0x62, + _RESERVED_63 = 0x63, + _RESERVED_64 = 0x64, + _RESERVED_65 = 0x65, + _RESERVED_66 = 0x66, + _RESERVED_67 = 0x67, + _RESERVED_68 = 0x68, + _RESERVED_69 = 0x69, + _RESERVED_6a = 0x6a, + _RESERVED_6b = 0x6b, + _RESERVED_6c = 0x6c, + _RESERVED_6d = 0x6d, + _RESERVED_6e = 0x6e, + _RESERVED_6f = 0x6f, + _RESERVED_70 = 0x70, + _RESERVED_71 = 0x71, + _RESERVED_72 = 0x72, + _RESERVED_73 = 0x73, + _RESERVED_74 = 0x74, + _RESERVED_75 = 0x75, + _RESERVED_76 = 0x76, + _RESERVED_77 = 0x77, + _RESERVED_78 = 0x78, + _RESERVED_79 = 0x79, + _RESERVED_7a = 0x7a, + _RESERVED_7b = 0x7b, + _RESERVED_7c = 0x7c, + _RESERVED_7d = 0x7d, + _RESERVED_7e = 0x7e, + _RESERVED_7f = 0x7f, } -impl TrigInVal { +impl TrigOutInp { #[inline(always)] - pub const fn from_bits(val: u8) -> TrigInVal { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> TrigOutInp { + unsafe { core::mem::transmute(val & 0x7f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for TrigInVal { +impl From for TrigOutInp { #[inline(always)] - fn from(val: u8) -> TrigInVal { - TrigInVal::from_bits(val) + fn from(val: u8) -> TrigOutInp { + TrigOutInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: TrigInVal) -> u8 { - TrigInVal::to_bits(val) + fn from(val: TrigOutInp) -> u8 { + TrigOutInp::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum UsbfsTrigInp { +pub enum Tsi0TrigInputInp { _RESERVED_0 = 0x0, - #[doc = "LPUART0 lpuart_trg_txdata input is selected."] - VAL1 = 0x01, - #[doc = "LPUART1 lpuart_trg_txdata input is selected."] - VAL2 = 0x02, - #[doc = "LPUART2 lpuart_trg_txdata input is selected."] - VAL3 = 0x03, - #[doc = "LPUART3 lpuart_trg_txdata input is selected."] - VAL4 = 0x04, - #[doc = "LPUART4 lpuart_trg_txdata input is selected."] - VAL5 = 0x05, - #[doc = "LPUART5 lpuart_trg_txdata input is selected."] - VAL6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, + #[doc = "CTimer0_MAT2 input is selected."] + Val1 = 0x01, + #[doc = "CTimer0_MAT3 input is selected."] + Val2 = 0x02, + #[doc = "CTimer1_MAT2 input is selected."] + Val3 = 0x03, + #[doc = "CTimer1_MAT3 input is selected."] + Val4 = 0x04, + #[doc = "CTimer2_MAT2 input is selected."] + Val5 = 0x05, + #[doc = "CTimer2_MAT3 input is selected."] + Val6 = 0x06, + #[doc = "CTimer3_MAT2 input is selected."] + Val7 = 0x07, + #[doc = "CTimer3_MAT3 input is selected."] + Val8 = 0x08, + #[doc = "CTimer4_MAT2 input is selected."] + Val9 = 0x09, + #[doc = "CTimer4_MAT3 input is selected."] + Val10 = 0x0a, + #[doc = "LPTMR0 input is selected."] + Val11 = 0x0b, + #[doc = "WUU input is selected."] + Val12 = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, _RESERVED_f = 0x0f, + _RESERVED_10 = 0x10, + _RESERVED_11 = 0x11, + _RESERVED_12 = 0x12, + _RESERVED_13 = 0x13, + _RESERVED_14 = 0x14, + _RESERVED_15 = 0x15, + _RESERVED_16 = 0x16, + _RESERVED_17 = 0x17, + _RESERVED_18 = 0x18, + _RESERVED_19 = 0x19, + _RESERVED_1a = 0x1a, + _RESERVED_1b = 0x1b, + _RESERVED_1c = 0x1c, + _RESERVED_1d = 0x1d, + _RESERVED_1e = 0x1e, + _RESERVED_1f = 0x1f, + _RESERVED_20 = 0x20, + _RESERVED_21 = 0x21, + _RESERVED_22 = 0x22, + _RESERVED_23 = 0x23, + _RESERVED_24 = 0x24, + _RESERVED_25 = 0x25, + _RESERVED_26 = 0x26, + _RESERVED_27 = 0x27, + _RESERVED_28 = 0x28, + _RESERVED_29 = 0x29, + _RESERVED_2a = 0x2a, + _RESERVED_2b = 0x2b, + _RESERVED_2c = 0x2c, + _RESERVED_2d = 0x2d, + _RESERVED_2e = 0x2e, + _RESERVED_2f = 0x2f, + _RESERVED_30 = 0x30, + _RESERVED_31 = 0x31, + _RESERVED_32 = 0x32, + _RESERVED_33 = 0x33, + _RESERVED_34 = 0x34, + _RESERVED_35 = 0x35, + _RESERVED_36 = 0x36, + _RESERVED_37 = 0x37, + _RESERVED_38 = 0x38, + _RESERVED_39 = 0x39, + _RESERVED_3a = 0x3a, + _RESERVED_3b = 0x3b, + _RESERVED_3c = 0x3c, + _RESERVED_3d = 0x3d, + _RESERVED_3e = 0x3e, + _RESERVED_3f = 0x3f, } -impl UsbfsTrigInp { +impl Tsi0TrigInputInp { #[inline(always)] - pub const fn from_bits(val: u8) -> UsbfsTrigInp { - unsafe { core::mem::transmute(val & 0x0f) } + pub const fn from_bits(val: u8) -> Tsi0TrigInputInp { + unsafe { core::mem::transmute(val & 0x3f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for UsbfsTrigInp { +impl From for Tsi0TrigInputInp { #[inline(always)] - fn from(val: u8) -> UsbfsTrigInp { - UsbfsTrigInp::from_bits(val) + fn from(val: u8) -> Tsi0TrigInputInp { + Tsi0TrigInputInp::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: UsbfsTrigInp) -> u8 { - UsbfsTrigInp::to_bits(val) + fn from(val: Tsi0TrigInputInp) -> u8 { + Tsi0TrigInputInp::to_bits(val) } } diff --git a/nxp-pac/src/meta_peripherals/mcxa/LPI2C.rs b/nxp-pac/src/meta_peripherals/mcxa/LPI2C.rs index 038a0f6..cbeacae 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/LPI2C.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/LPI2C.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Low-Power Inter-Integrated Circuit."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Lpi2c { @@ -579,6 +580,18 @@ impl Mcfgr1 { pub const fn set_pincfg(&mut self, val: Pincfg) { self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); } + #[doc = "Force HS Mode."] + #[must_use] + #[inline(always)] + pub const fn frchs(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "Force HS Mode."] + #[inline(always)] + pub const fn set_frchs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } } impl Default for Mcfgr1 { #[inline(always)] @@ -597,6 +610,7 @@ impl core::fmt::Debug for Mcfgr1 { .field("startcfg", &self.startcfg()) .field("matcfg", &self.matcfg()) .field("pincfg", &self.pincfg()) + .field("frchs", &self.frchs()) .finish() } } @@ -605,7 +619,7 @@ impl defmt::Format for Mcfgr1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mcfgr1 {{ prescale: {:?}, autostop: {=bool:?}, ignack: {=bool:?}, timecfg: {:?}, stopcfg: {:?}, startcfg: {:?}, matcfg: {:?}, pincfg: {:?} }}", + "Mcfgr1 {{ prescale: {:?}, autostop: {=bool:?}, ignack: {=bool:?}, timecfg: {:?}, stopcfg: {:?}, startcfg: {:?}, matcfg: {:?}, pincfg: {:?}, frchs: {=bool:?} }}", self.prescale(), self.autostop(), self.ignack(), @@ -613,7 +627,8 @@ impl defmt::Format for Mcfgr1 { self.stopcfg(), self.startcfg(), self.matcfg(), - self.pincfg() + self.pincfg(), + self.frchs() ) } } @@ -1917,13 +1932,13 @@ impl Scfgr1 { #[doc = "Ignore NACK."] #[must_use] #[inline(always)] - pub const fn ignack(&self) -> Scfgr1ignack { + pub const fn ignack(&self) -> Scfgr1Ignack { let val = (self.0 >> 12usize) & 0x01; - Scfgr1ignack::from_bits(val as u8) + Scfgr1Ignack::from_bits(val as u8) } #[doc = "Ignore NACK."] #[inline(always)] - pub const fn set_ignack(&mut self, val: Scfgr1ignack) { + pub const fn set_ignack(&mut self, val: Scfgr1Ignack) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); } #[doc = "HS Mode Enable."] @@ -3059,21 +3074,21 @@ impl defmt::Format for Verid { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Addrcfg { #[doc = "Address match 0 (7-bit)."] - ADDRESS_MATCH0_7_BIT = 0x0, + AddressMatch07Bit = 0x0, #[doc = "Address match 0 (10-bit)."] - ADDRESS_MATCH0_10_BIT = 0x01, + AddressMatch010Bit = 0x01, #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)."] - ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_7_BIT = 0x02, + AddressMatch07BitOrAddressMatch17Bit = 0x02, #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)."] - ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_10_BIT = 0x03, + AddressMatch010BitOrAddressMatch110Bit = 0x03, #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)."] - ADDRESS_MATCH0_7_BIT_OR_ADDRESS_MATCH1_10_BIT = 0x04, + AddressMatch07BitOrAddressMatch110Bit = 0x04, #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)."] - ADDRESS_MATCH0_10_BIT_OR_ADDRESS_MATCH1_7_BIT = 0x05, + AddressMatch010BitOrAddressMatch17Bit = 0x05, #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)."] - FROM_ADDRESS_MATCH0_7_BIT_TO_ADDRESS_MATCH1_7_BIT = 0x06, + FromAddressMatch07BitToAddressMatch17Bit = 0x06, #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)."] - FROM_ADDRESS_MATCH0_10_BIT_TO_ADDRESS_MATCH1_10_BIT = 0x07, + FromAddressMatch010BitToAddressMatch110Bit = 0x07, } impl Addrcfg { #[inline(always)] @@ -3102,9 +3117,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Alf { #[doc = "Controller did not lose arbitration."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Controller lost arbitration."] - INT_YES = 0x01, + IntYes = 0x01, } impl Alf { #[inline(always)] @@ -3133,9 +3148,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Anv { #[doc = "Valid."] - VALID = 0x0, + Valid = 0x0, #[doc = "Not valid."] - NOT_VALID = 0x01, + NotValid = 0x01, } impl Anv { #[inline(always)] @@ -3207,9 +3222,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dmf { #[doc = "Matching data not received."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Matching data received."] - INT_YES = 0x01, + IntYes = 0x01, } impl Dmf { #[inline(always)] @@ -3238,9 +3253,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dozen { #[doc = "Enable."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "Disable."] - DISABLED = 0x01, + Disabled = 0x01, } impl Dozen { #[inline(always)] @@ -3269,9 +3284,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Epf { #[doc = "No Stop or repeated Start generated."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Stop or repeated Start generated."] - INT_YES = 0x01, + IntYes = 0x01, } impl Epf { #[inline(always)] @@ -3300,9 +3315,9 @@ impl From for u8 { pub struct Feature(u16); impl Feature { #[doc = "Controller only, with standard feature set."] - pub const MASTER_ONLY: Self = Self(0x02); + pub const MasterOnly: Self = Self(0x02); #[doc = "Controller and target, with standard feature set."] - pub const MASTER_AND_SLAVE: Self = Self(0x03); + pub const MasterAndSlave: Self = Self(0x03); } impl Feature { pub const fn from_bits(val: u16) -> Feature { @@ -3315,8 +3330,8 @@ impl Feature { impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x02 => f.write_str("MASTER_ONLY"), - 0x03 => f.write_str("MASTER_AND_SLAVE"), + 0x02 => f.write_str("MasterOnly"), + 0x03 => f.write_str("MasterAndSlave"), other => core::write!(f, "0x{:02X}", other), } } @@ -3325,8 +3340,8 @@ impl core::fmt::Debug for Feature { impl defmt::Format for Feature { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x02 => defmt::write!(f, "MASTER_ONLY"), - 0x03 => defmt::write!(f, "MASTER_AND_SLAVE"), + 0x02 => defmt::write!(f, "MasterOnly"), + 0x03 => defmt::write!(f, "MasterAndSlave"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3348,9 +3363,9 @@ impl From for u16 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Filtdz { #[doc = "Enable."] - FILTER_ENABLED = 0x0, + FilterEnabled = 0x0, #[doc = "Disable."] - FILTER_DISABLED = 0x01, + FilterDisabled = 0x01, } impl Filtdz { #[inline(always)] @@ -3379,9 +3394,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hrdir { #[doc = "HREQ pin is input (for LPI2C controller)."] - INPUT = 0x0, + Input = 0x0, #[doc = "HREQ pin is output (for LPI2C target)."] - OUTPUT = 0x01, + Output = 0x01, } impl Hrdir { #[inline(always)] @@ -3410,9 +3425,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hrpol { #[doc = "Active low."] - ACTIVE_LOW = 0x0, + ActiveLow = 0x0, #[doc = "Active high."] - ACTIVE_HIGH = 0x01, + ActiveHigh = 0x01, } impl Hrpol { #[inline(always)] @@ -3441,20 +3456,20 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Matcfg { #[doc = "Match is disabled."] - DISABLED = 0x0, + Disabled = 0x0, _RESERVED_1 = 0x01, #[doc = "Match is enabled: first data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]."] - FIRST_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 = 0x02, + FirstDataWordEqualsMatch0OrMatch1 = 0x02, #[doc = "Match is enabled: any data word equals MDMR\\[MATCH0\\] OR MDMR\\[MATCH1\\]."] - ANY_DATA_WORD_EQUALS_MATCH0_OR_MATCH1 = 0x03, + AnyDataWordEqualsMatch0OrMatch1 = 0x03, #[doc = "Match is enabled: (first data word equals MDMR\\[MATCH0\\]) AND (second data word equals MDMR\\[MATCH1)."] - FIRST_DATA_WORD_MATCH0_AND_SECOND_DATA_WORD_MATCH1 = 0x04, + FirstDataWordMatch0AndSecondDataWordMatch1 = 0x04, #[doc = "Match is enabled: (any data word equals MDMR\\[MATCH0\\]) AND (next data word equals MDMR\\[MATCH1)."] - ANY_DATA_WORD_MATCH0_NEXT_DATA_WORD_MATCH1 = 0x05, + AnyDataWordMatch0NextDataWordMatch1 = 0x05, #[doc = "Match is enabled: (first data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])."] - FIRST_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 = 0x06, + FirstDataWordAndMatch1EqualsMatch0AndMatch1 = 0x06, #[doc = "Match is enabled: (any data word AND MDMR\\[MATCH1\\]) equals (MDMR\\[MATCH0\\] AND MDMR\\[MATCH1\\])."] - ANY_DATA_WORD_AND_MATCH1_EQUALS_MATCH0_AND_MATCH1 = 0x07, + AnyDataWordAndMatch1EqualsMatch0AndMatch1 = 0x07, } impl Matcfg { #[inline(always)] @@ -3483,9 +3498,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mbf { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl Mbf { #[inline(always)] @@ -3514,9 +3529,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum McrRrf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Reset receive FIFO."] - RESET = 0x01, + Reset = 0x01, } impl McrRrf { #[inline(always)] @@ -3545,9 +3560,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum McrRtf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Reset transmit FIFO."] - RESET = 0x01, + Reset = 0x01, } impl McrRtf { #[inline(always)] @@ -3576,9 +3591,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MsrBbf { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl MsrBbf { #[inline(always)] @@ -3607,9 +3622,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MsrFef { #[doc = "No FIFO error."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "FIFO error."] - INT_YES = 0x01, + IntYes = 0x01, } impl MsrFef { #[inline(always)] @@ -3638,9 +3653,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MsrSdf { #[doc = "No Stop condition generated."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Stop condition generated."] - INT_YES = 0x01, + IntYes = 0x01, } impl MsrSdf { #[inline(always)] @@ -3669,9 +3684,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ndf { #[doc = "No unexpected NACK detected."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Unexpected NACK detected."] - INT_YES = 0x01, + IntYes = 0x01, } impl Ndf { #[inline(always)] @@ -3700,21 +3715,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pincfg { #[doc = "Two-pin open drain mode."] - OPEN_DRAIN_2_PIN = 0x0, + OpenDrain2Pin = 0x0, #[doc = "Two-pin output only mode (Ultra-Fast mode)."] - OUTPUT_2_PIN_ONLY = 0x01, + Output2PinOnly = 0x01, #[doc = "Two-pin push-pull mode."] - PUSH_PULL_2_PIN = 0x02, + PushPull2Pin = 0x02, #[doc = "Four-pin push-pull mode."] - PUSH_PULL_4_PIN = 0x03, + PushPull4Pin = 0x03, #[doc = "Two-pin open-drain mode with separate LPI2C target."] - OPEN_DRAIN_2_PIN_W_LPI2C_SLAVE = 0x04, + OpenDrain2PinWLpi2cSlave = 0x04, #[doc = "Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target."] - OUTPUT_2_PIN_ONLY_W_LPI2C_SLAVE = 0x05, + Output2PinOnlyWLpi2cSlave = 0x05, #[doc = "Two-pin push-pull mode with separate LPI2C target."] - PUSH_PULL_2_PIN_W_LPI2C_SLAVE = 0x06, + PushPull2PinWLpi2cSlave = 0x06, #[doc = "Four-pin push-pull mode (inverted outputs)."] - PUSH_PULL_4_PIN_W_LPI2C_SLAVE = 0x07, + PushPull4PinWLpi2cSlave = 0x07, } impl Pincfg { #[inline(always)] @@ -3743,9 +3758,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pltf { #[doc = "Pin low timeout did not occur."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Pin low timeout occurred."] - INT_YES = 0x01, + IntYes = 0x01, } impl Pltf { #[inline(always)] @@ -3774,21 +3789,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Prescale { #[doc = "Divide by 1."] - DIVIDE_BY_1 = 0x0, + DivideBy1 = 0x0, #[doc = "Divide by 2."] - DIVIDE_BY_2 = 0x01, + DivideBy2 = 0x01, #[doc = "Divide by 4."] - DIVIDE_BY_4 = 0x02, + DivideBy4 = 0x02, #[doc = "Divide by 8."] - DIVIDE_BY_8 = 0x03, + DivideBy8 = 0x03, #[doc = "Divide by 16."] - DIVIDE_BY_16 = 0x04, + DivideBy16 = 0x04, #[doc = "Divide by 32."] - DIVIDE_BY_32 = 0x05, + DivideBy32 = 0x05, #[doc = "Divide by 64."] - DIVIDE_BY_64 = 0x06, + DivideBy64 = 0x06, #[doc = "Divide by 128."] - DIVIDE_BY_128 = 0x07, + DivideBy128 = 0x07, } impl Prescale { #[inline(always)] @@ -3817,9 +3832,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Relax { #[doc = "Normal transfer."] - NORMAL_TRANSFER = 0x0, + NormalTransfer = 0x0, #[doc = "Relaxed transfer."] - RELAXED_TRANSFER = 0x01, + RelaxedTransfer = 0x01, } impl Relax { #[inline(always)] @@ -3848,9 +3863,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rscfg { #[doc = "Any repeated Start condition following an address match."] - ANY_REPEATED_START_AFTER_ADDRESS_MATCH = 0x0, + AnyRepeatedStartAfterAddressMatch = 0x0, #[doc = "Any repeated Start condition."] - ANY_REPEATED_START = 0x01, + AnyRepeatedStart = 0x01, } impl Rscfg { #[inline(always)] @@ -3878,10 +3893,10 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxcfg { - #[doc = "Return received data, clear MSR\\[RDF\\]."] - RETURNS_RECEIVED_DATA_AND_CLEARS_RX_DATA_FLAG = 0x0, - #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set."] - WHEN_ADDRESS_VALID_FLAG_SET_RETURNS_ADDRESS_STATUS_AND_CLEARS_ADDRESS_VALID_FLAG = 0x01, + #[doc = "Return received data, clear SSR\\[RDF\\]."] + ReturnsReceivedDataAndClearsRxDataFlag = 0x0, + #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear SSR\\[RDF\\] when SSR\\[AFV\\] is not set."] + WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag = 0x01, } impl Rxcfg { #[inline(always)] @@ -3910,9 +3925,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxnack { #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]."] - SET_BY_TXNACK = 0x0, + SetByTxnack = 0x0, #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]."] - ALWAYS_GENERATED_ON_ADDRESS_OR_RECEIVE_DATA_OVERRUN = 0x01, + AlwaysGeneratedOnAddressOrReceiveDataOverrun = 0x01, } impl Rxnack { #[inline(always)] @@ -3941,9 +3956,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sbf { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl Sbf { #[inline(always)] @@ -3970,15 +3985,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Scfgr1ignack { +pub enum Scfgr1Ignack { #[doc = "End transfer on NACK."] - ENDS_TRANSFER_ON_NACK = 0x0, + EndsTransferOnNack = 0x0, #[doc = "Do not end transfer on NACK."] - DOES_NOT_END_TRANSFER_ON_NACK = 0x01, + DoesNotEndTransferOnNack = 0x01, } -impl Scfgr1ignack { +impl Scfgr1Ignack { #[inline(always)] - pub const fn from_bits(val: u8) -> Scfgr1ignack { + pub const fn from_bits(val: u8) -> Scfgr1Ignack { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -3986,16 +4001,16 @@ impl Scfgr1ignack { unsafe { core::mem::transmute(self) } } } -impl From for Scfgr1ignack { +impl From for Scfgr1Ignack { #[inline(always)] - fn from(val: u8) -> Scfgr1ignack { - Scfgr1ignack::from_bits(val) + fn from(val: u8) -> Scfgr1Ignack { + Scfgr1Ignack::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Scfgr1ignack) -> u8 { - Scfgr1ignack::to_bits(val) + fn from(val: Scfgr1Ignack) -> u8 { + Scfgr1Ignack::to_bits(val) } } #[repr(u8)] @@ -4003,9 +4018,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ScrRrf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "SRDR is now empty."] - NOW_EMPTY = 0x01, + NowEmpty = 0x01, } impl ScrRrf { #[inline(always)] @@ -4034,9 +4049,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ScrRtf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "STDR is now empty."] - NOW_EMPTY = 0x01, + NowEmpty = 0x01, } impl ScrRtf { #[inline(always)] @@ -4065,9 +4080,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sdcfg { #[doc = "Any Stop condition following an address match."] - ANY_STOP_AFTER_ADDRESS_MATCH = 0x0, + AnyStopAfterAddressMatch = 0x0, #[doc = "Any Stop condition."] - ANY_STOP = 0x01, + AnyStop = 0x01, } impl Sdcfg { #[inline(always)] @@ -4096,9 +4111,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SsrBbf { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Busy."] - BUSY = 0x01, + Busy = 0x01, } impl SsrBbf { #[inline(always)] @@ -4127,9 +4142,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Startcfg { #[doc = "Sets when both I2C bus and LPI2C controller are idle."] - BOTH_I2C_AND_LPI2C_IDLE = 0x0, + BothI2cAndLpi2cIdle = 0x0, #[doc = "Sets when I2C bus is idle."] - I2C_IDLE = 0x01, + I2cIdle = 0x01, } impl Startcfg { #[inline(always)] @@ -4158,9 +4173,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Stf { #[doc = "Start condition not detected."] - INT_NO = 0x0, + IntNo = 0x0, #[doc = "Start condition detected."] - INT_YES = 0x01, + IntYes = 0x01, } impl Stf { #[inline(always)] @@ -4189,9 +4204,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Stopcfg { #[doc = "Any Stop condition."] - ANY_STOP = 0x0, + AnyStop = 0x0, #[doc = "Last Stop condition."] - LAST_STOP = 0x01, + LastStop = 0x01, } impl Stopcfg { #[inline(always)] @@ -4220,9 +4235,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Timecfg { #[doc = "SCL."] - IF_SCL_LOW = 0x0, + IfSclLow = 0x0, #[doc = "SCL or SDA."] - IF_SCL_OR_SDA_LOW = 0x01, + IfSclOrSdaLow = 0x01, } impl Timecfg { #[inline(always)] @@ -4250,10 +4265,10 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txcfg { - #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty."] - ASSERTS_DURING_SLAVE_TRANSMIT_TRANSFER_WHEN_TX_DATA_EMPTY = 0x0, - #[doc = "MSR\\[TDF\\] is set whenever STDR is empty."] - ASSERTS_WHEN_TX_DATA_EMPTY = 0x01, + #[doc = "SSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty."] + AssertsDuringSlaveTransmitTransferWhenTxDataEmpty = 0x0, + #[doc = "SSR\\[TDF\\] is set whenever STDR is empty."] + AssertsWhenTxDataEmpty = 0x01, } impl Txcfg { #[inline(always)] @@ -4282,9 +4297,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txnack { #[doc = "Transmit ACK."] - TRANSMIT_ACK = 0x0, + TransmitAck = 0x0, #[doc = "Transmit NACK."] - TRANSMIT_NACK = 0x01, + TransmitNack = 0x01, } impl Txnack { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/LPSPI.rs b/nxp-pac/src/meta_peripherals/mcxa/LPSPI.rs index 2d0dcb7..5c29154 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/LPSPI.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/LPSPI.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Low-Power Serial Peripheral Interface."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Lpspi { @@ -607,6 +608,18 @@ impl Cr { pub const fn set_rst(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } + #[doc = "Doze Mode Enable."] + #[must_use] + #[inline(always)] + pub const fn dozen(&self) -> Dozen { + let val = (self.0 >> 2usize) & 0x01; + Dozen::from_bits(val as u8) + } + #[doc = "Doze Mode Enable."] + #[inline(always)] + pub const fn set_dozen(&mut self, val: Dozen) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } #[doc = "Debug Enable."] #[must_use] #[inline(always)] @@ -655,6 +668,7 @@ impl core::fmt::Debug for Cr { f.debug_struct("Cr") .field("men", &self.men()) .field("rst", &self.rst()) + .field("dozen", &self.dozen()) .field("dbgen", &self.dbgen()) .field("rtf", &self.rtf()) .field("rrf", &self.rrf()) @@ -666,9 +680,10 @@ impl defmt::Format for Cr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Cr {{ men: {=bool:?}, rst: {=bool:?}, dbgen: {=bool:?}, rtf: {:?}, rrf: {:?} }}", + "Cr {{ men: {=bool:?}, rst: {=bool:?}, dozen: {:?}, dbgen: {=bool:?}, rtf: {:?}, rrf: {:?} }}", self.men(), self.rst(), + self.dozen(), self.dbgen(), self.rtf(), self.rrf() @@ -1823,9 +1838,9 @@ impl defmt::Format for Verid { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Contc { #[doc = "Command word for start of new transfer."] - START = 0x0, + Start = 0x0, #[doc = "Command word for continuing transfer."] - CONTINUE = 0x01, + Continue = 0x01, } impl Contc { #[inline(always)] @@ -1854,9 +1869,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpha { #[doc = "Captured."] - CAPTURED = 0x0, + Captured = 0x0, #[doc = "Changed."] - CHANGED = 0x01, + Changed = 0x01, } impl Cpha { #[inline(always)] @@ -1885,9 +1900,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpol { #[doc = "Inactive low."] - INACTIVE_LOW = 0x0, + InactiveLow = 0x0, #[doc = "Inactive high."] - INACTIVE_HIGH = 0x01, + InactiveHigh = 0x01, } impl Cpol { #[inline(always)] @@ -1911,12 +1926,43 @@ impl From for u8 { Cpol::to_bits(val) } } +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Dozen { + #[doc = "Enable."] + Enabled = 0x0, + #[doc = "Disable."] + Disabled = 0x01, +} +impl Dozen { + #[inline(always)] + pub const fn from_bits(val: u8) -> Dozen { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Dozen { + #[inline(always)] + fn from(val: u8) -> Dozen { + Dozen::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Dozen) -> u8 { + Dozen::to_bits(val) + } +} #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Feature(u16); impl Feature { #[doc = "Standard feature set supporting a 32-bit shift register."] - pub const STANDARD: Self = Self(0x04); + pub const Standard: Self = Self(0x04); } impl Feature { pub const fn from_bits(val: u16) -> Feature { @@ -1929,7 +1975,7 @@ impl Feature { impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x04 => f.write_str("STANDARD"), + 0x04 => f.write_str("Standard"), other => core::write!(f, "0x{:02X}", other), } } @@ -1938,7 +1984,7 @@ impl core::fmt::Debug for Feature { impl defmt::Format for Feature { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x04 => defmt::write!(f, "STANDARD"), + 0x04 => defmt::write!(f, "Standard"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -1960,9 +2006,9 @@ impl From for u16 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hrdir { #[doc = "Input."] - INPUT = 0x0, + Input = 0x0, #[doc = "Output."] - OUTPUT = 0x01, + Output = 0x01, } impl Hrdir { #[inline(always)] @@ -1991,9 +2037,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Hrsel { #[doc = "HREQ pin."] - HREQPIN = 0x0, + Hreqpin = 0x0, #[doc = "Input trigger."] - INPUT_TRIGGER = 0x01, + InputTrigger = 0x01, } impl Hrsel { #[inline(always)] @@ -2022,9 +2068,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lsbf { #[doc = "MSB first."] - MSB_FIRST = 0x0, + MsbFirst = 0x0, #[doc = "LSB first."] - LSB_FIRST = 0x01, + LsbFirst = 0x01, } impl Lsbf { #[inline(always)] @@ -2053,9 +2099,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Master { #[doc = "Peripheral mode."] - SLAVE_MODE = 0x0, + SlaveMode = 0x0, #[doc = "Controller mode."] - MASTER_MODE = 0x01, + MasterMode = 0x01, } impl Master { #[inline(always)] @@ -2084,20 +2130,20 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Matcfg { #[doc = "Match is disabled."] - DISABLED = 0x0, + Disabled = 0x0, _RESERVED_1 = 0x01, #[doc = "Match first data word with compare word."] - ENABLED_FIRSTDATAMATCH = 0x02, + EnabledFirstdatamatch = 0x02, #[doc = "Match any data word with compare word."] - ENABLED_ANYDATAMATCH = 0x03, + EnabledAnydatamatch = 0x03, #[doc = "Sequential match, first data word."] - ENABLED_DATAMATCH_100 = 0x04, + EnabledDatamatch100 = 0x04, #[doc = "Sequential match, any data word."] - ENABLED_DATAMATCH_101 = 0x05, + EnabledDatamatch101 = 0x05, #[doc = "Match first data word (masked) with compare word (masked)."] - ENABLED_DATAMATCH_110 = 0x06, + EnabledDatamatch110 = 0x06, #[doc = "Match any data word (masked) with compare word (masked)."] - ENABLED_DATAMATCH_111 = 0x07, + EnabledDatamatch111 = 0x07, } impl Matcfg { #[inline(always)] @@ -2126,9 +2172,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mbf { #[doc = "LPSPI is idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "LPSPI is busy."] - BUSY = 0x01, + Busy = 0x01, } impl Mbf { #[inline(always)] @@ -2157,9 +2203,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Outcfg { #[doc = "Retain last value."] - RETAIN_LASTVALUE = 0x0, + RetainLastvalue = 0x0, #[doc = "3-stated."] - TRISTATED = 0x01, + Tristated = 0x01, } impl Outcfg { #[inline(always)] @@ -2188,9 +2234,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Partial { #[doc = "Discard."] - DISCARDED = 0x0, + Discarded = 0x0, #[doc = "Store."] - STORED = 0x01, + Stored = 0x01, } impl Partial { #[inline(always)] @@ -2219,13 +2265,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pcs { #[doc = "Transfer using PCS\\[0\\]."] - TX_PCS0 = 0x0, + TxPcs0 = 0x0, #[doc = "Transfer using PCS\\[1\\]."] - TX_PCS1 = 0x01, + TxPcs1 = 0x01, #[doc = "Transfer using PCS\\[2\\]."] - TX_PCS2 = 0x02, + TxPcs2 = 0x02, #[doc = "Transfer using PCS\\[3\\]."] - TX_PCS3 = 0x03, + TxPcs3 = 0x03, } impl Pcs { #[inline(always)] @@ -2254,9 +2300,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pcscfg { #[doc = "PCS\\[3:2\\] configured for chip select function."] - CHIP_SELECT = 0x0, + ChipSelect = 0x0, #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])."] - HALFDUPLEX4BIT = 0x01, + Halfduplex4bit = 0x01, } impl Pcscfg { #[inline(always)] @@ -2285,9 +2331,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pcspol { #[doc = "Active low."] - DISCARDED = 0x0, + Discarded = 0x0, #[doc = "Active high."] - STORED = 0x01, + Stored = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -2330,13 +2376,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pincfg { #[doc = "SIN is used for input data; SOUT is used for output data."] - SIN_IN_SOUT_OUT = 0x0, + SinInSoutOut = 0x0, #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported."] - SIN_BOTH_IN_OUT = 0x01, + SinBothInOut = 0x01, #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported."] - SOUT_BOTH_IN_OUT = 0x02, + SoutBothInOut = 0x02, #[doc = "SOUT is used for input data; SIN is used for output data."] - SOUT_IN_SIN_OUT = 0x03, + SoutInSinOut = 0x03, } impl Pincfg { #[inline(always)] @@ -2365,21 +2411,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Prescale { #[doc = "Divide by 1."] - DIVIDEBY1 = 0x0, + Divideby1 = 0x0, #[doc = "Divide by 2."] - DIVIDEBY2 = 0x01, + Divideby2 = 0x01, #[doc = "Divide by 4."] - DIVIDEBY4 = 0x02, + Divideby4 = 0x02, #[doc = "Divide by 8."] - DIVIDEBY8 = 0x03, + Divideby8 = 0x03, #[doc = "Divide by 16."] - DIVIDEBY16 = 0x04, + Divideby16 = 0x04, #[doc = "Divide by 32."] - DIVIDEBY32 = 0x05, + Divideby32 = 0x05, #[doc = "Divide by 64."] - DIVIDEBY64 = 0x06, + Divideby64 = 0x06, #[doc = "Divide by 128."] - DIVIDEBY128 = 0x07, + Divideby128 = 0x07, } impl Prescale { #[inline(always)] @@ -2408,9 +2454,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rdmo { #[doc = "Disable."] - STORED = 0x0, + Stored = 0x0, #[doc = "Enable."] - DISCARDED = 0x01, + Discarded = 0x01, } impl Rdmo { #[inline(always)] @@ -2439,9 +2485,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rrf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Reset."] - RXFIFO_RST = 0x01, + RxfifoRst = 0x01, } impl Rrf { #[inline(always)] @@ -2470,9 +2516,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rtf { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Reset."] - TXFIFO_RST = 0x01, + TxfifoRst = 0x01, } impl Rtf { #[inline(always)] @@ -2501,9 +2547,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxmsk { #[doc = "Normal transfer."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "Mask receive data."] - MASK = 0x01, + Mask = 0x01, } impl Rxmsk { #[inline(always)] @@ -2532,9 +2578,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sample { #[doc = "SCK edge."] - ON_SCK_EDGE = 0x0, + OnSckEdge = 0x0, #[doc = "Delayed SCK edge."] - ON_DELAYED_SCK_EDGE = 0x01, + OnDelayedSckEdge = 0x01, } impl Sample { #[inline(always)] @@ -2563,9 +2609,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sof { #[doc = "Subsequent data word or RX FIFO is empty (RXEMPTY=1)."] - NEXT_DATAWORD = 0x0, + NextDataword = 0x0, #[doc = "First data word."] - FIRST_DATAWORD = 0x01, + FirstDataword = 0x01, } impl Sof { #[inline(always)] @@ -2594,9 +2640,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tdf { #[doc = "Transmit data not requested."] - TXDATA_NOT_REQST = 0x0, + TxdataNotReqst = 0x0, #[doc = "Transmit data requested."] - TXDATA_REQST = 0x01, + TxdataReqst = 0x01, } impl Tdf { #[inline(always)] @@ -2625,9 +2671,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txmsk { #[doc = "Normal transfer."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "Mask transmit data."] - MASK = 0x01, + Mask = 0x01, } impl Txmsk { #[inline(always)] @@ -2656,11 +2702,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Width { #[doc = "1-bit transfer."] - ONEBIT = 0x0, + Onebit = 0x0, #[doc = "2-bit transfer."] - TWOBIT = 0x01, + Twobit = 0x01, #[doc = "4-bit transfer."] - FOURBIT = 0x02, + Fourbit = 0x02, _RESERVED_3 = 0x03, } impl Width { diff --git a/nxp-pac/src/meta_peripherals/mcxa/LPUART.rs b/nxp-pac/src/meta_peripherals/mcxa/LPUART.rs index 75f83a4..d3ece74 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/LPUART.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/LPUART.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "LPUART."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Lpuart { @@ -196,6 +197,18 @@ impl Baud { pub const fn set_rdmae(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } + #[doc = "Reduced Oversample Mode Selection."] + #[must_use] + #[inline(always)] + pub const fn hlfm(&self) -> Hlfm { + let val = (self.0 >> 22usize) & 0x01; + Hlfm::from_bits(val as u8) + } + #[doc = "Reduced Oversample Mode Selection."] + #[inline(always)] + pub const fn set_hlfm(&mut self, val: Hlfm) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val.to_bits() as u32) & 0x01) << 22usize); + } #[doc = "Transmitter DMA Enable."] #[must_use] #[inline(always)] @@ -275,6 +288,7 @@ impl core::fmt::Debug for Baud { .field("matcfg", &self.matcfg()) .field("ridmae", &self.ridmae()) .field("rdmae", &self.rdmae()) + .field("hlfm", &self.hlfm()) .field("tdmae", &self.tdmae()) .field("osr", &self.osr()) .field("m10", &self.m10()) @@ -288,7 +302,7 @@ impl defmt::Format for Baud { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Baud {{ sbr: {=u16:?}, sbns: {:?}, rxedgie: {=bool:?}, lbkdie: {=bool:?}, resyncdis: {:?}, bothedge: {=bool:?}, matcfg: {:?}, ridmae: {=bool:?}, rdmae: {=bool:?}, tdmae: {=bool:?}, osr: {=u8:?}, m10: {=bool:?}, maen2: {=bool:?}, maen1: {=bool:?} }}", + "Baud {{ sbr: {=u16:?}, sbns: {:?}, rxedgie: {=bool:?}, lbkdie: {=bool:?}, resyncdis: {:?}, bothedge: {=bool:?}, matcfg: {:?}, ridmae: {=bool:?}, rdmae: {=bool:?}, hlfm: {:?}, tdmae: {=bool:?}, osr: {=u8:?}, m10: {=bool:?}, maen2: {=bool:?}, maen1: {=bool:?} }}", self.sbr(), self.sbns(), self.rxedgie(), @@ -298,6 +312,7 @@ impl defmt::Format for Baud { self.matcfg(), self.ridmae(), self.rdmae(), + self.hlfm(), self.tdmae(), self.osr(), self.m10(), @@ -443,6 +458,18 @@ impl Ctrl { pub const fn set_swap(&mut self, val: Swap) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val.to_bits() as u32) & 0x01) << 12usize); } + #[doc = "Early Sample Selection."] + #[must_use] + #[inline(always)] + pub const fn erlsmp(&self) -> Erlsmp { + let val = (self.0 >> 13usize) & 0x01; + Erlsmp::from_bits(val as u8) + } + #[doc = "Early Sample Selection."] + #[inline(always)] + pub const fn set_erlsmp(&mut self, val: Erlsmp) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val.to_bits() as u32) & 0x01) << 13usize); + } #[doc = "Match 2 (MA2F) Interrupt Enable."] #[must_use] #[inline(always)] @@ -680,6 +707,7 @@ impl core::fmt::Debug for Ctrl { .field("idlecfg", &self.idlecfg()) .field("m7", &self.m7()) .field("swap", &self.swap()) + .field("erlsmp", &self.erlsmp()) .field("ma2ie", &self.ma2ie()) .field("ma1ie", &self.ma1ie()) .field("sbk", &self.sbk()) @@ -706,7 +734,7 @@ impl defmt::Format for Ctrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ctrl {{ pt: {:?}, pe: {=bool:?}, ilt: {:?}, wake: {:?}, m: {:?}, rsrc: {:?}, dozeen: {:?}, loops: {:?}, idlecfg: {:?}, m7: {:?}, swap: {:?}, ma2ie: {=bool:?}, ma1ie: {=bool:?}, sbk: {:?}, rwu: {:?}, re: {=bool:?}, te: {=bool:?}, ilie: {=bool:?}, rie: {=bool:?}, tcie: {=bool:?}, tie: {=bool:?}, peie: {=bool:?}, feie: {=bool:?}, neie: {=bool:?}, orie: {=bool:?}, txinv: {=bool:?}, txdir: {:?}, r9t8: {=bool:?}, r8t9: {=bool:?} }}", + "Ctrl {{ pt: {:?}, pe: {=bool:?}, ilt: {:?}, wake: {:?}, m: {:?}, rsrc: {:?}, dozeen: {:?}, loops: {:?}, idlecfg: {:?}, m7: {:?}, swap: {:?}, erlsmp: {:?}, ma2ie: {=bool:?}, ma1ie: {=bool:?}, sbk: {:?}, rwu: {:?}, re: {=bool:?}, te: {=bool:?}, ilie: {=bool:?}, rie: {=bool:?}, tcie: {=bool:?}, tie: {=bool:?}, peie: {=bool:?}, feie: {=bool:?}, neie: {=bool:?}, orie: {=bool:?}, txinv: {=bool:?}, txdir: {:?}, r9t8: {=bool:?}, r8t9: {=bool:?} }}", self.pt(), self.pe(), self.ilt(), @@ -718,6 +746,7 @@ impl defmt::Format for Ctrl { self.idlecfg(), self.m7(), self.swap(), + self.erlsmp(), self.ma2ie(), self.ma1ie(), self.sbk(), @@ -2035,9 +2064,9 @@ impl defmt::Format for Water { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Brk13 { #[doc = "9 to 13 bit times."] - SHORT = 0x0, + Short = 0x0, #[doc = "12 to 15 bit times."] - LONG = 0x01, + Long = 0x01, } impl Brk13 { #[inline(always)] @@ -2066,9 +2095,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dozeen { #[doc = "Enable."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "Disable."] - DISABLED = 0x01, + Disabled = 0x01, } impl Dozeen { #[inline(always)] @@ -2092,14 +2121,45 @@ impl From for u8 { Dozeen::to_bits(val) } } +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Erlsmp { + #[doc = "Regular midpoint bit sampling."] + Midpoint = 0x0, + #[doc = "Early bit sampling at 1/2 duration of bit timing."] + Reduced = 0x01, +} +impl Erlsmp { + #[inline(always)] + pub const fn from_bits(val: u8) -> Erlsmp { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Erlsmp { + #[inline(always)] + fn from(val: u8) -> Erlsmp { + Erlsmp::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Erlsmp) -> u8 { + Erlsmp::to_bits(val) + } +} #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct Feature(u16); impl Feature { #[doc = "Standard feature set."] - pub const STANDARD: Self = Self(0x01); + pub const Standard: Self = Self(0x01); #[doc = "Standard feature set with MODEM and IrDA support."] - pub const MODEM: Self = Self(0x03); + pub const Modem: Self = Self(0x03); } impl Feature { pub const fn from_bits(val: u16) -> Feature { @@ -2112,8 +2172,8 @@ impl Feature { impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x01 => f.write_str("STANDARD"), - 0x03 => f.write_str("MODEM"), + 0x01 => f.write_str("Standard"), + 0x03 => f.write_str("Modem"), other => core::write!(f, "0x{:02X}", other), } } @@ -2122,8 +2182,8 @@ impl core::fmt::Debug for Feature { impl defmt::Format for Feature { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x01 => defmt::write!(f, "STANDARD"), - 0x03 => defmt::write!(f, "MODEM"), + 0x01 => defmt::write!(f, "Standard"), + 0x03 => defmt::write!(f, "Modem"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -2143,23 +2203,54 @@ impl From for u16 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Hlfm { + #[doc = "Regular Oversampling."] + Regular = 0x0, + #[doc = "Reduced Oversampling by 0.5."] + Reduced = 0x01, +} +impl Hlfm { + #[inline(always)] + pub const fn from_bits(val: u8) -> Hlfm { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Hlfm { + #[inline(always)] + fn from(val: u8) -> Hlfm { + Hlfm::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Hlfm) -> u8 { + Hlfm::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Idlecfg { #[doc = "1."] - IDLE_1 = 0x0, + Idle1 = 0x0, #[doc = "2."] - IDLE_2 = 0x01, + Idle2 = 0x01, #[doc = "4."] - IDLE_4 = 0x02, + Idle4 = 0x02, #[doc = "8."] - IDLE_8 = 0x03, + Idle8 = 0x03, #[doc = "16."] - IDLE_16 = 0x04, + Idle16 = 0x04, #[doc = "32."] - IDLE_32 = 0x05, + Idle32 = 0x05, #[doc = "64."] - IDLE_64 = 0x06, + Idle64 = 0x06, #[doc = "128."] - IDLE_128 = 0x07, + Idle128 = 0x07, } impl Idlecfg { #[inline(always)] @@ -2188,9 +2279,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ilt { #[doc = "After the start bit."] - FROM_START = 0x0, + FromStart = 0x0, #[doc = "After the stop bit."] - FROM_STOP = 0x01, + FromStop = 0x01, } impl Ilt { #[inline(always)] @@ -2219,9 +2310,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Loops { #[doc = "Normal operation: RXD and TXD use separate pins."] - NOFFECT = 0x0, + Noffect = 0x0, #[doc = "Loop mode or Single-Wire mode."] - LOOPBACK = 0x01, + Loopback = 0x01, } impl Loops { #[inline(always)] @@ -2250,9 +2341,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum M { #[doc = "8-bit."] - DATA8 = 0x0, + Data8 = 0x0, #[doc = "9-bit."] - DATA9 = 0x01, + Data9 = 0x01, } impl M { #[inline(always)] @@ -2281,9 +2372,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum M7 { #[doc = "8-bit to 10-bit."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "7-bit."] - DATA7 = 0x01, + Data7 = 0x01, } impl M7 { #[inline(always)] @@ -2312,13 +2403,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Matcfg { #[doc = "Address match wake-up."] - ADDR_MATCH = 0x0, + AddrMatch = 0x0, #[doc = "Idle match wake-up."] - IDLE_MATCH = 0x01, + IdleMatch = 0x01, #[doc = "Match on and match off."] - ONOFF_MATCH = 0x02, + OnoffMatch = 0x02, #[doc = "Enables RWU on data match and match on or off for the transmitter CTS input."] - RWU_MATCH = 0x03, + RwuMatch = 0x03, } impl Matcfg { #[inline(always)] @@ -2347,9 +2438,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Msbf { #[doc = "LSB."] - LSB_FIRST = 0x0, + LsbFirst = 0x0, #[doc = "MSB."] - MSB_FIRST = 0x01, + MsbFirst = 0x01, } impl Msbf { #[inline(always)] @@ -2378,9 +2469,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pt { #[doc = "Even parity."] - EVEN = 0x0, + Even = 0x0, #[doc = "Odd parity."] - ODD = 0x01, + Odd = 0x01, } impl Pt { #[inline(always)] @@ -2409,9 +2500,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Raf { #[doc = "Idle, waiting for a start bit."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Receiver active (RXD pin input not idle)."] - ACTIVE = 0x01, + Active = 0x01, } impl Raf { #[inline(always)] @@ -2440,9 +2531,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Resyncdis { #[doc = "Enable."] - RESYNC = 0x0, + Resync = 0x0, #[doc = "Disable."] - NO_RESYNC = 0x01, + NoResync = 0x01, } impl Resyncdis { #[inline(always)] @@ -2471,9 +2562,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rsrc { #[doc = "Internal Loopback mode."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Single-wire mode."] - ONEWIRE = 0x01, + Onewire = 0x01, } impl Rsrc { #[inline(always)] @@ -2502,9 +2593,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rst { #[doc = "Not reset."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Reset."] - RESET = 0x01, + Reset = 0x01, } impl Rst { #[inline(always)] @@ -2533,9 +2624,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rwu { #[doc = "Normal receiver operation."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "LPUART receiver in standby, waiting for a wake-up condition."] - RX_WAKEUP = 0x01, + RxWakeup = 0x01, } impl Rwu { #[inline(always)] @@ -2564,9 +2655,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rwuid { #[doc = "STAT\\[IDLE\\] does not become 1."] - IDLE_NOTSET = 0x0, + IdleNotset = 0x0, #[doc = "STAT\\[IDLE\\] becomes 1."] - IDLE_SET = 0x01, + IdleSet = 0x01, } impl Rwuid { #[inline(always)] @@ -2595,21 +2686,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxfifosize { #[doc = "1."] - FIFO_1 = 0x0, + Fifo1 = 0x0, #[doc = "4."] - FIFO_4 = 0x01, + Fifo4 = 0x01, #[doc = "8."] - FIFO_8 = 0x02, + Fifo8 = 0x02, #[doc = "16."] - FIFO_16 = 0x03, + Fifo16 = 0x03, #[doc = "32."] - FIFO_32 = 0x04, + Fifo32 = 0x04, #[doc = "64."] - FIFO_64 = 0x05, + Fifo64 = 0x05, #[doc = "128."] - FIFO_128 = 0x06, + Fifo128 = 0x06, #[doc = "256."] - FIFO_256 = 0x07, + Fifo256 = 0x07, } impl Rxfifosize { #[inline(always)] @@ -2638,9 +2729,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxflush { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "All data flushed out."] - RXFIFO_RST = 0x01, + RxfifoRst = 0x01, } impl Rxflush { #[inline(always)] @@ -2669,21 +2760,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rxiden { #[doc = "Disable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for one character."] - IDLE_1 = 0x01, + Idle1 = 0x01, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for two characters."] - IDLE_2 = 0x02, + Idle2 = 0x02, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for four characters."] - IDLE_4 = 0x03, + Idle4 = 0x03, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for eight characters."] - IDLE_8 = 0x04, + Idle8 = 0x04, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters."] - IDLE_16 = 0x05, + Idle16 = 0x05, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters."] - IDLE_32 = 0x06, + Idle32 = 0x06, #[doc = "Enable STAT\\[RDRF\\] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters."] - IDLE_64 = 0x07, + Idle64 = 0x07, } impl Rxiden { #[inline(always)] @@ -2712,9 +2803,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sbk { #[doc = "Normal transmitter operation."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Queue break character(s) to be sent."] - TX_BREAK = 0x01, + TxBreak = 0x01, } impl Sbk { #[inline(always)] @@ -2743,9 +2834,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sbns { #[doc = "One stop bit."] - ONE = 0x0, + One = 0x0, #[doc = "Two stop bits."] - TWO = 0x01, + Two = 0x01, } impl Sbns { #[inline(always)] @@ -2774,9 +2865,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Swap { #[doc = "Use the standard way."] - STANDARD = 0x0, + Standard = 0x0, #[doc = "Swap."] - SWAP = 0x01, + Swap = 0x01, } impl Swap { #[inline(always)] @@ -2805,9 +2896,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tc { #[doc = "Transmitter active."] - ACTIVE = 0x0, + Active = 0x0, #[doc = "Transmitter idle."] - COMPLETE = 0x01, + Complete = 0x01, } impl Tc { #[inline(always)] @@ -2836,9 +2927,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tdre { #[doc = "Greater than watermark."] - TXDATA = 0x0, + Txdata = 0x0, #[doc = "Equal to or less than watermark."] - NO_TXDATA = 0x01, + NoTxdata = 0x01, } impl Tdre { #[inline(always)] @@ -2867,13 +2958,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tnp { #[doc = "1 / OSR."] - ONE_SAMPLE = 0x0, + OneSample = 0x0, #[doc = "2 / OSR."] - TWO_SAMPLE = 0x01, + TwoSample = 0x01, #[doc = "3 / OSR."] - THREE_SAMPLE = 0x02, + ThreeSample = 0x02, #[doc = "4 / OSR."] - FOUR_SAMPLE = 0x03, + FourSample = 0x03, } impl Tnp { #[inline(always)] @@ -2902,13 +2993,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Trgsel { #[doc = "Input trigger disabled."] - DISABLED = 0x0, + Disabled = 0x0, #[doc = "Input trigger used instead of the RXD pin input."] - TRG_RXD = 0x01, + TrgRxd = 0x01, #[doc = "Input trigger used instead of the CTS_B pin input."] - TRG_CTS = 0x02, + TrgCts = 0x02, #[doc = "Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger."] - TRG_TXD = 0x03, + TrgTxd = 0x03, } impl Trgsel { #[inline(always)] @@ -2937,9 +3028,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txctsc { #[doc = "Sampled at the start of each character."] - START = 0x0, + Start = 0x0, #[doc = "Sampled when the transmitter is idle."] - IDLE = 0x01, + Idle = 0x01, } impl Txctsc { #[inline(always)] @@ -2968,9 +3059,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txctssrc { #[doc = "The CTS_B pin."] - CTS = 0x0, + Cts = 0x0, #[doc = "An internal connection to the receiver address match result."] - MATCH = 0x01, + Match = 0x01, } impl Txctssrc { #[inline(always)] @@ -2999,9 +3090,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txdir { #[doc = "Input."] - TX_INPUT = 0x0, + TxInput = 0x0, #[doc = "Output."] - TX_OUTPUT = 0x01, + TxOutput = 0x01, } impl Txdir { #[inline(always)] @@ -3030,21 +3121,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txfifosize { #[doc = "1."] - FIFO_1 = 0x0, + Fifo1 = 0x0, #[doc = "4."] - FIFO_4 = 0x01, + Fifo4 = 0x01, #[doc = "8."] - FIFO_8 = 0x02, + Fifo8 = 0x02, #[doc = "16."] - FIFO_16 = 0x03, + Fifo16 = 0x03, #[doc = "32."] - FIFO_32 = 0x04, + Fifo32 = 0x04, #[doc = "64."] - FIFO_64 = 0x05, + Fifo64 = 0x05, #[doc = "128."] - FIFO_128 = 0x06, + Fifo128 = 0x06, #[doc = "256."] - FIFO_256 = 0x07, + Fifo256 = 0x07, } impl Txfifosize { #[inline(always)] @@ -3073,9 +3164,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txflush { #[doc = "No effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "All data flushed out."] - TXFIFO_RST = 0x01, + TxfifoRst = 0x01, } impl Txflush { #[inline(always)] @@ -3104,9 +3195,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Txrtspol { #[doc = "Active low."] - LOW = 0x0, + Low = 0x0, #[doc = "Active high."] - HIGH = 0x01, + High = 0x01, } impl Txrtspol { #[inline(always)] @@ -3135,9 +3226,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Wake { #[doc = "Idle."] - IDLE = 0x0, + Idle = 0x0, #[doc = "Mark."] - MARK = 0x01, + Mark = 0x01, } impl Wake { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/MBC.rs b/nxp-pac/src/meta_peripherals/mcxa/MBC.rs index fd6071e..4bad174 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/MBC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/MBC.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "TRDC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mbc { @@ -21,28 +22,28 @@ impl Mbc { #[inline(always)] pub const fn mbc0_mem0_glbcfg( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize) as _) } } #[doc = "MBC Global Configuration Register."] #[inline(always)] pub const fn mbc0_mem1_glbcfg( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x04usize) as _) } } #[doc = "MBC Global Configuration Register."] #[inline(always)] pub const fn mbc0_mem2_glbcfg( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x08usize) as _) } } #[doc = "MBC Global Configuration Register."] #[inline(always)] pub const fn mbc0_mem3_glbcfg( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0cusize) as _) } } #[doc = "MBC Global Access Control."] @@ -137,8 +138,8 @@ impl Mbc { #[doc = "MBC Global Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mem0glbcfg(pub u32); -impl Mem0glbcfg { +pub struct Mem0Glbcfg(pub u32); +impl Mem0Glbcfg { #[doc = "Number of blocks in this memory."] #[must_use] #[inline(always)] @@ -164,26 +165,26 @@ impl Mem0glbcfg { self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); } } -impl Default for Mem0glbcfg { +impl Default for Mem0Glbcfg { #[inline(always)] - fn default() -> Mem0glbcfg { - Mem0glbcfg(0) + fn default() -> Mem0Glbcfg { + Mem0Glbcfg(0) } } -impl core::fmt::Debug for Mem0glbcfg { +impl core::fmt::Debug for Mem0Glbcfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mem0glbcfg") + f.debug_struct("Mem0Glbcfg") .field("nblks", &self.nblks()) .field("size_log2", &self.size_log2()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Mem0glbcfg { +impl defmt::Format for Mem0Glbcfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mem0glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", + "Mem0Glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", self.nblks(), self.size_log2() ) @@ -192,8 +193,8 @@ impl defmt::Format for Mem0glbcfg { #[doc = "MBC Global Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mem1glbcfg(pub u32); -impl Mem1glbcfg { +pub struct Mem1Glbcfg(pub u32); +impl Mem1Glbcfg { #[doc = "Number of blocks in this memory."] #[must_use] #[inline(always)] @@ -219,26 +220,26 @@ impl Mem1glbcfg { self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); } } -impl Default for Mem1glbcfg { +impl Default for Mem1Glbcfg { #[inline(always)] - fn default() -> Mem1glbcfg { - Mem1glbcfg(0) + fn default() -> Mem1Glbcfg { + Mem1Glbcfg(0) } } -impl core::fmt::Debug for Mem1glbcfg { +impl core::fmt::Debug for Mem1Glbcfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mem1glbcfg") + f.debug_struct("Mem1Glbcfg") .field("nblks", &self.nblks()) .field("size_log2", &self.size_log2()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Mem1glbcfg { +impl defmt::Format for Mem1Glbcfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mem1glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", + "Mem1Glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", self.nblks(), self.size_log2() ) @@ -247,8 +248,8 @@ impl defmt::Format for Mem1glbcfg { #[doc = "MBC Global Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mem2glbcfg(pub u32); -impl Mem2glbcfg { +pub struct Mem2Glbcfg(pub u32); +impl Mem2Glbcfg { #[doc = "Number of blocks in this memory."] #[must_use] #[inline(always)] @@ -274,26 +275,26 @@ impl Mem2glbcfg { self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); } } -impl Default for Mem2glbcfg { +impl Default for Mem2Glbcfg { #[inline(always)] - fn default() -> Mem2glbcfg { - Mem2glbcfg(0) + fn default() -> Mem2Glbcfg { + Mem2Glbcfg(0) } } -impl core::fmt::Debug for Mem2glbcfg { +impl core::fmt::Debug for Mem2Glbcfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mem2glbcfg") + f.debug_struct("Mem2Glbcfg") .field("nblks", &self.nblks()) .field("size_log2", &self.size_log2()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Mem2glbcfg { +impl defmt::Format for Mem2Glbcfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mem2glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", + "Mem2Glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?} }}", self.nblks(), self.size_log2() ) @@ -302,8 +303,8 @@ impl defmt::Format for Mem2glbcfg { #[doc = "MBC Global Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Mem3glbcfg(pub u32); -impl Mem3glbcfg { +pub struct Mem3Glbcfg(pub u32); +impl Mem3Glbcfg { #[doc = "Number of blocks in this memory."] #[must_use] #[inline(always)] @@ -341,15 +342,15 @@ impl Mem3glbcfg { self.0 = (self.0 & !(0x03 << 30usize)) | (((val as u32) & 0x03) << 30usize); } } -impl Default for Mem3glbcfg { +impl Default for Mem3Glbcfg { #[inline(always)] - fn default() -> Mem3glbcfg { - Mem3glbcfg(0) + fn default() -> Mem3Glbcfg { + Mem3Glbcfg(0) } } -impl core::fmt::Debug for Mem3glbcfg { +impl core::fmt::Debug for Mem3Glbcfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Mem3glbcfg") + f.debug_struct("Mem3Glbcfg") .field("nblks", &self.nblks()) .field("size_log2", &self.size_log2()) .field("clre", &self.clre()) @@ -357,11 +358,11 @@ impl core::fmt::Debug for Mem3glbcfg { } } #[cfg(feature = "defmt")] -impl defmt::Format for Mem3glbcfg { +impl defmt::Format for Mem3Glbcfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mem3glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?}, clre: {=u8:?} }}", + "Mem3Glbcfg {{ nblks: {=u16:?}, size_log2: {=u8:?}, clre: {=u8:?} }}", self.nblks(), self.size_log2(), self.clre() @@ -2282,21 +2283,21 @@ impl defmt::Format for MemnGlbac7 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mbacsel { #[doc = "select MBC_MEMN_GLBAC0 access control policy for block B."] - GLBAC0 = 0x0, + Glbac0 = 0x0, #[doc = "select MBC_MEMN_GLBAC1 access control policy for block B."] - GLBAC1 = 0x01, + Glbac1 = 0x01, #[doc = "select MBC_MEMN_GLBAC2 access control policy for block B."] - GLBAC2 = 0x02, + Glbac2 = 0x02, #[doc = "select MBC_MEMN_GLBAC3 access control policy for block B."] - GLBAC3 = 0x03, + Glbac3 = 0x03, #[doc = "select MBC_MEMN_GLBAC4 access control policy for block B."] - GLBAC4 = 0x04, + Glbac4 = 0x04, #[doc = "select MBC_MEMN_GLBAC5 access control policy for block B."] - GLBAC5 = 0x05, + Glbac5 = 0x05, #[doc = "select MBC_MEMN_GLBAC6 access control policy for block B."] - GLBAC6 = 0x06, + Glbac6 = 0x06, #[doc = "select MBC_MEMN_GLBAC7 access control policy for block B."] - GLBAC7 = 0x07, + Glbac7 = 0x07, } impl Mbacsel { #[inline(always)] @@ -2325,9 +2326,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Nse { #[doc = "Secure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\]), nonsecure accesses to block B are not allowed."] - ALLOWED = 0x0, + Allowed = 0x0, #[doc = "Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww\\[MBACSEL\\])."] - NOTALLOWED = 0x01, + Notallowed = 0x01, } impl Nse { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/MRCC2xx.rs b/nxp-pac/src/meta_peripherals/mcxa/MRCC2xx.rs index f24521d..364f9c7 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/MRCC2xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/MRCC2xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "MRCC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mrcc { @@ -19,9 +20,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 0."] #[inline(always)] - pub const fn mrcc_glb_rst0( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize) as _) } } #[doc = "Peripheral Reset Control Set 0."] @@ -40,9 +39,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 1."] #[inline(always)] - pub const fn mrcc_glb_rst1( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize) as _) } } #[doc = "Peripheral Reset Control Set 1."] @@ -61,9 +58,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 2."] #[inline(always)] - pub const fn mrcc_glb_rst2( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } } #[doc = "Peripheral Reset Control Set 2."] @@ -82,7 +77,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 0."] #[inline(always)] - pub const fn mrcc_glb_cc0(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize) as _) } } #[doc = "AHB Clock Control Set 0."] @@ -101,7 +96,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 1."] #[inline(always)] - pub const fn mrcc_glb_cc1(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x50usize) as _) } } #[doc = "AHB Clock Control Set 1."] @@ -120,7 +115,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 2."] #[inline(always)] - pub const fn mrcc_glb_cc2(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x60usize) as _) } } #[doc = "AHB Clock Control Set 2."] @@ -139,23 +134,17 @@ impl Mrcc { } #[doc = "Control Automatic Clock Gating 0."] #[inline(always)] - pub const fn mrcc_glb_acc0( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x80usize) as _) } } #[doc = "Control Automatic Clock Gating 1."] #[inline(always)] - pub const fn mrcc_glb_acc1( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x84usize) as _) } } #[doc = "Control Automatic Clock Gating 2."] #[inline(always)] - pub const fn mrcc_glb_acc2( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x88usize) as _) } } #[doc = "I3C0_FCLK clock selection control."] @@ -169,7 +158,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_i3c0_fclk_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa4usize) as _) } } #[doc = "CTIMER0 clock selection control."] @@ -183,7 +172,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xacusize) as _) } } #[doc = "CTIMER1 clock selection control."] @@ -197,7 +186,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xb4usize) as _) } } #[doc = "CTIMER2 clock selection control."] @@ -211,7 +200,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xbcusize) as _) } } #[doc = "CTIMER3 clock selection control."] @@ -225,7 +214,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc4usize) as _) } } #[doc = "CTIMER4 clock selection control."] @@ -239,14 +228,14 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xccusize) as _) } } #[doc = "WWDT0 clock divider control."] #[inline(always)] pub const fn mrcc_wwdt0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd4usize) as _) } } #[doc = "FLEXIO0 clock selection control."] @@ -260,7 +249,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexio0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xdcusize) as _) } } #[doc = "LPI2C0 clock selection control."] @@ -274,7 +263,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe4usize) as _) } } #[doc = "LPI2C1 clock selection control."] @@ -288,7 +277,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xecusize) as _) } } #[doc = "LPSPI0 clock selection control."] @@ -302,7 +291,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf4usize) as _) } } #[doc = "LPSPI1 clock selection control."] @@ -316,7 +305,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xfcusize) as _) } } #[doc = "LPUART0 clock selection control."] @@ -330,7 +319,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0104usize) as _) } } #[doc = "LPUART1 clock selection control."] @@ -344,7 +333,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x010cusize) as _) } } #[doc = "LPUART2 clock selection control."] @@ -358,7 +347,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0114usize) as _) } } #[doc = "LPUART3 clock selection control."] @@ -372,7 +361,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x011cusize) as _) } } #[doc = "LPUART4 clock selection control."] @@ -386,7 +375,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0124usize) as _) } } #[doc = "USB0 clock selection control."] @@ -398,9 +387,7 @@ impl Mrcc { } #[doc = "USB0 clock divider control."] #[inline(always)] - pub const fn mrcc_usb0_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_usb0_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x012cusize) as _) } } #[doc = "LPTMR0 clock selection control."] @@ -414,7 +401,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lptmr0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0134usize) as _) } } #[doc = "OSTIMER0 clock selection control."] @@ -428,21 +415,19 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_adc_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0140usize) as _) } } #[doc = "ADCx clock divider control."] #[inline(always)] - pub const fn mrcc_adc_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_adc_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0144usize) as _) } } #[doc = "CMP0_FUNC clock divider control."] #[inline(always)] pub const fn mrcc_cmp0_func_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x014cusize) as _) } } #[doc = "CMP0_RR clock selection control."] @@ -456,14 +441,14 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_cmp0_rr_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0154usize) as _) } } #[doc = "CMP1_FUNC clock divider control."] #[inline(always)] pub const fn mrcc_cmp1_func_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x015cusize) as _) } } #[doc = "CMP1_RR clock selection control."] @@ -477,14 +462,14 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_cmp1_rr_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0164usize) as _) } } #[doc = "CMP2_FUNC clock divider control."] #[inline(always)] pub const fn mrcc_cmp2_func_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x016cusize) as _) } } #[doc = "CMP2_RR clock selection control."] @@ -498,7 +483,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_cmp2_rr_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0174usize) as _) } } #[doc = "DAC0 clock selection control."] @@ -510,9 +495,7 @@ impl Mrcc { } #[doc = "DAC0 clock divider control."] #[inline(always)] - pub const fn mrcc_dac0_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_dac0_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x017cusize) as _) } } #[doc = "FLEXCAN0 clock selection control."] @@ -526,7 +509,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexcan0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0184usize) as _) } } #[doc = "FLEXCAN1 clock selection control."] @@ -540,7 +523,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexcan1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x018cusize) as _) } } #[doc = "LPI2C2 clock selection control."] @@ -554,7 +537,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0194usize) as _) } } #[doc = "LPI2C3 clock selection control."] @@ -568,7 +551,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x019cusize) as _) } } #[doc = "LPUART5 clock selection control."] @@ -582,140 +565,94 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart5_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a4usize) as _) } } #[doc = "DBG_TRACE clock selection control."] #[inline(always)] pub const fn mrcc_dbg_trace_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a8usize) as _) } } #[doc = "DBG_TRACE clock divider control."] #[inline(always)] pub const fn mrcc_dbg_trace_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01acusize) as _) } } #[doc = "CLKOUT clock selection control."] #[inline(always)] pub const fn mrcc_clkout_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b0usize) as _) } } #[doc = "CLKOUT clock divider control."] #[inline(always)] pub const fn mrcc_clkout_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b4usize) as _) } } #[doc = "SYSTICK clock selection control."] #[inline(always)] pub const fn mrcc_systick_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b8usize) as _) } } #[doc = "SYSTICK clock divider control."] #[inline(always)] pub const fn mrcc_systick_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01bcusize) as _) } } } -#[doc = "CMP0_FUNC clock divider control."] +#[doc = "ADCx clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpFuncClkdiv(pub u32); -impl CmpFuncClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct AdcClksel(pub u32); +impl AdcClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> AdcClkselMux { + let val = (self.0 >> 0usize) & 0x07; + AdcClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: AdcClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CmpFuncClkdiv { +impl Default for AdcClksel { #[inline(always)] - fn default() -> CmpFuncClkdiv { - CmpFuncClkdiv(0) + fn default() -> AdcClksel { + AdcClksel(0) } } -impl core::fmt::Debug for CmpFuncClkdiv { +impl core::fmt::Debug for AdcClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpFuncClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("AdcClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpFuncClkdiv { +impl defmt::Format for AdcClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "CmpFuncClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "AdcClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "CMP0_RR clock divider control."] +#[doc = "ADCx clock divider control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpRrClkdiv(pub u32); -impl CmpRrClkdiv { +pub struct Clkdiv(pub u32); +impl Clkdiv { #[doc = "Functional Clock Divider."] #[must_use] #[inline(always)] @@ -765,15 +702,15 @@ impl CmpRrClkdiv { self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); } } -impl Default for CmpRrClkdiv { +impl Default for Clkdiv { #[inline(always)] - fn default() -> CmpRrClkdiv { - CmpRrClkdiv(0) + fn default() -> Clkdiv { + Clkdiv(0) } } -impl core::fmt::Debug for CmpRrClkdiv { +impl core::fmt::Debug for Clkdiv { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpRrClkdiv") + f.debug_struct("Clkdiv") .field("div", &self.div()) .field("reset", &self.reset()) .field("halt", &self.halt()) @@ -782,11 +719,11 @@ impl core::fmt::Debug for CmpRrClkdiv { } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpRrClkdiv { +impl defmt::Format for Clkdiv { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "CmpRrClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", + "Clkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", self.div(), self.reset(), self.halt(), @@ -794,124 +731,78 @@ impl defmt::Format for CmpRrClkdiv { ) } } -#[doc = "CMP0_RR clock selection control."] +#[doc = "CLKOUT clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpRrClksel(pub u32); -impl CmpRrClksel { +pub struct ClkoutClksel(pub u32); +impl ClkoutClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> RrClkselMux { + pub const fn mux(&self) -> ClkoutClkselMux { let val = (self.0 >> 0usize) & 0x07; - RrClkselMux::from_bits(val as u8) + ClkoutClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: RrClkselMux) { + pub const fn set_mux(&mut self, val: ClkoutClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CmpRrClksel { +impl Default for ClkoutClksel { #[inline(always)] - fn default() -> CmpRrClksel { - CmpRrClksel(0) + fn default() -> ClkoutClksel { + ClkoutClksel(0) } } -impl core::fmt::Debug for CmpRrClksel { +impl core::fmt::Debug for ClkoutClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpRrClksel") + f.debug_struct("ClkoutClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpRrClksel { +impl defmt::Format for ClkoutClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "CmpRrClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "ClkoutClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "CTIMER0 clock divider control."] +#[doc = "CMP0_RR clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CtimerClkdiv(pub u32); -impl CtimerClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct CmpRrClksel(pub u32); +impl CmpRrClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> RrClkselMux { + let val = (self.0 >> 0usize) & 0x07; + RrClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: RrClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CtimerClkdiv { +impl Default for CmpRrClksel { #[inline(always)] - fn default() -> CtimerClkdiv { - CtimerClkdiv(0) + fn default() -> CmpRrClksel { + CmpRrClksel(0) } } -impl core::fmt::Debug for CtimerClkdiv { +impl core::fmt::Debug for CmpRrClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CtimerClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("CmpRrClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CtimerClkdiv { +impl defmt::Format for CmpRrClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "CtimerClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "CmpRrClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "CTIMER0 clock selection control."] @@ -951,89 +842,6 @@ impl defmt::Format for CtimerClksel { defmt::write!(f, "CtimerClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "DAC0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DacClkdiv(pub u32); -impl DacClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for DacClkdiv { - #[inline(always)] - fn default() -> DacClkdiv { - DacClkdiv(0) - } -} -impl core::fmt::Debug for DacClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DacClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for DacClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "DacClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} #[doc = "DAC0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1071,1359 +879,122 @@ impl defmt::Format for DacClksel { defmt::write!(f, "DacClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "FLEXCAN0 clock divider control."] +#[doc = "DBG_TRACE clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexcanClkdiv(pub u32); -impl FlexcanClkdiv { - #[doc = "Functional Clock Divider."] +pub struct DbgTraceClksel(pub u32); +impl DbgTraceClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub const fn mux(&self) -> DbgTraceClkselMux { + let val = (self.0 >> 0usize) & 0x03; + DbgTraceClkselMux::from_bits(val as u8) } - #[doc = "Functional Clock Divider."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn set_mux(&mut self, val: DbgTraceClkselMux) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "Reset divider counter."] - #[must_use] +} +impl Default for DbgTraceClksel { #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for FlexcanClkdiv { - #[inline(always)] - fn default() -> FlexcanClkdiv { - FlexcanClkdiv(0) - } -} -impl core::fmt::Debug for FlexcanClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexcanClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexcanClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "FlexcanClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "FLEXCAN0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexcanClksel(pub u32); -impl FlexcanClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FlexcanClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FlexcanClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FlexcanClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for FlexcanClksel { - #[inline(always)] - fn default() -> FlexcanClksel { - FlexcanClksel(0) - } -} -impl core::fmt::Debug for FlexcanClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexcanClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexcanClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexcanClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "FLEXIO0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexioClkdiv(pub u32); -impl FlexioClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for FlexioClkdiv { - #[inline(always)] - fn default() -> FlexioClkdiv { - FlexioClkdiv(0) - } -} -impl core::fmt::Debug for FlexioClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexioClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexioClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "FlexioClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "FLEXIO0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexioClksel(pub u32); -impl FlexioClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FlexioClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FlexioClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FlexioClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for FlexioClksel { - #[inline(always)] - fn default() -> FlexioClksel { - FlexioClksel(0) - } -} -impl core::fmt::Debug for FlexioClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexioClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexioClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexioClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "AHB Clock Control Clear 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbCcClr(pub u32); -impl GlbCcClr { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbCcClr { - #[inline(always)] - fn default() -> GlbCcClr { - GlbCcClr(0) - } -} -impl core::fmt::Debug for GlbCcClr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbCcClr") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbCcClr { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbCcClr {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "AHB Clock Control Set 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbCcSet(pub u32); -impl GlbCcSet { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbCcSet { - #[inline(always)] - fn default() -> GlbCcSet { - GlbCcSet(0) - } -} -impl core::fmt::Debug for GlbCcSet { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbCcSet") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbCcSet { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbCcSet {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "Peripheral Reset Control Clear 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbRstClr(pub u32); -impl GlbRstClr { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbRstClr { - #[inline(always)] - fn default() -> GlbRstClr { - GlbRstClr(0) - } -} -impl core::fmt::Debug for GlbRstClr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbRstClr") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbRstClr { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbRstClr {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "Peripheral Reset Control Set 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbRstSet(pub u32); -impl GlbRstSet { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbRstSet { - #[inline(always)] - fn default() -> GlbRstSet { - GlbRstSet(0) - } -} -impl core::fmt::Debug for GlbRstSet { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbRstSet") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbRstSet { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbRstSet {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "I3C0_FCLK clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I3cFclkClkdiv(pub u32); -impl I3cFclkClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for I3cFclkClkdiv { - #[inline(always)] - fn default() -> I3cFclkClkdiv { - I3cFclkClkdiv(0) - } -} -impl core::fmt::Debug for I3cFclkClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I3cFclkClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for I3cFclkClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "I3cFclkClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "I3C0_FCLK clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I3cFclkClksel(pub u32); -impl I3cFclkClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FclkClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FclkClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FclkClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for I3cFclkClksel { - #[inline(always)] - fn default() -> I3cFclkClksel { - I3cFclkClksel(0) - } -} -impl core::fmt::Debug for I3cFclkClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I3cFclkClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for I3cFclkClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "I3cFclkClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPI2C0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Lpi2cClkdiv(pub u32); -impl Lpi2cClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for Lpi2cClkdiv { - #[inline(always)] - fn default() -> Lpi2cClkdiv { - Lpi2cClkdiv(0) - } -} -impl core::fmt::Debug for Lpi2cClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2cClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Lpi2cClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Lpi2cClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPI2C0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Lpi2cClksel(pub u32); -impl Lpi2cClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> Lpi2cClkselMux { - let val = (self.0 >> 0usize) & 0x07; - Lpi2cClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: Lpi2cClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for Lpi2cClksel { - #[inline(always)] - fn default() -> Lpi2cClksel { - Lpi2cClksel(0) - } -} -impl core::fmt::Debug for Lpi2cClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2cClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Lpi2cClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Lpi2cClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPSPI0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpspiClkdiv(pub u32); -impl LpspiClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LpspiClkdiv { - #[inline(always)] - fn default() -> LpspiClkdiv { - LpspiClkdiv(0) - } -} -impl core::fmt::Debug for LpspiClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpspiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpspiClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LpspiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPSPI0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpspiClksel(pub u32); -impl LpspiClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LpspiClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LpspiClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LpspiClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LpspiClksel { - #[inline(always)] - fn default() -> LpspiClksel { - LpspiClksel(0) - } -} -impl core::fmt::Debug for LpspiClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpspiClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpspiClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LpspiClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPTMR0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LptmrClkdiv(pub u32); -impl LptmrClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LptmrClkdiv { - #[inline(always)] - fn default() -> LptmrClkdiv { - LptmrClkdiv(0) - } -} -impl core::fmt::Debug for LptmrClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LptmrClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LptmrClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LptmrClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPTMR0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LptmrClksel(pub u32); -impl LptmrClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LptmrClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LptmrClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LptmrClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LptmrClksel { - #[inline(always)] - fn default() -> LptmrClksel { - LptmrClksel(0) - } -} -impl core::fmt::Debug for LptmrClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LptmrClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LptmrClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LptmrClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPUART0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpuartClkdiv(pub u32); -impl LpuartClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LpuartClkdiv { - #[inline(always)] - fn default() -> LpuartClkdiv { - LpuartClkdiv(0) - } -} -impl core::fmt::Debug for LpuartClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpuartClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpuartClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LpuartClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPUART0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpuartClksel(pub u32); -impl LpuartClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LpuartClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LpuartClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LpuartClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LpuartClksel { - #[inline(always)] - fn default() -> LpuartClksel { - LpuartClksel(0) - } -} -impl core::fmt::Debug for LpuartClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpuartClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpuartClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LpuartClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "ADCx clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccAdcClkdiv(pub u32); -impl MrccAdcClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for MrccAdcClkdiv { - #[inline(always)] - fn default() -> MrccAdcClkdiv { - MrccAdcClkdiv(0) - } -} -impl core::fmt::Debug for MrccAdcClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccAdcClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccAdcClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccAdcClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "ADCx clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccAdcClksel(pub u32); -impl MrccAdcClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> AdcClkselMux { - let val = (self.0 >> 0usize) & 0x07; - AdcClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: AdcClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for MrccAdcClksel { - #[inline(always)] - fn default() -> MrccAdcClksel { - MrccAdcClksel(0) - } -} -impl core::fmt::Debug for MrccAdcClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccAdcClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccAdcClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccAdcClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "CLKOUT clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccClkoutClkdiv(pub u32); -impl MrccClkoutClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + fn default() -> DbgTraceClksel { + DbgTraceClksel(0) } } -impl Default for MrccClkoutClkdiv { - #[inline(always)] - fn default() -> MrccClkoutClkdiv { - MrccClkoutClkdiv(0) - } -} -impl core::fmt::Debug for MrccClkoutClkdiv { +impl core::fmt::Debug for DbgTraceClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccClkoutClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("DbgTraceClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccClkoutClkdiv { +impl defmt::Format for DbgTraceClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccClkoutClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "DbgTraceClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "CLKOUT clock selection control."] +#[doc = "FLEXCAN0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccClkoutClksel(pub u32); -impl MrccClkoutClksel { +pub struct FlexcanClksel(pub u32); +impl FlexcanClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> ClkoutClkselMux { + pub const fn mux(&self) -> FlexcanClkselMux { let val = (self.0 >> 0usize) & 0x07; - ClkoutClkselMux::from_bits(val as u8) + FlexcanClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: ClkoutClkselMux) { + pub const fn set_mux(&mut self, val: FlexcanClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccClkoutClksel { +impl Default for FlexcanClksel { #[inline(always)] - fn default() -> MrccClkoutClksel { - MrccClkoutClksel(0) + fn default() -> FlexcanClksel { + FlexcanClksel(0) } } -impl core::fmt::Debug for MrccClkoutClksel { +impl core::fmt::Debug for FlexcanClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccClkoutClksel") + f.debug_struct("FlexcanClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccClkoutClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccClkoutClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "DBG_TRACE clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccDbgTraceClkdiv(pub u32); -impl MrccDbgTraceClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for MrccDbgTraceClkdiv { - #[inline(always)] - fn default() -> MrccDbgTraceClkdiv { - MrccDbgTraceClkdiv(0) - } -} -impl core::fmt::Debug for MrccDbgTraceClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccDbgTraceClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccDbgTraceClkdiv { +impl defmt::Format for FlexcanClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccDbgTraceClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "FlexcanClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "DBG_TRACE clock selection control."] +#[doc = "FLEXIO0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccDbgTraceClksel(pub u32); -impl MrccDbgTraceClksel { +pub struct FlexioClksel(pub u32); +impl FlexioClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> DbgTraceClkselMux { - let val = (self.0 >> 0usize) & 0x03; - DbgTraceClkselMux::from_bits(val as u8) + pub const fn mux(&self) -> FlexioClkselMux { + let val = (self.0 >> 0usize) & 0x07; + FlexioClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: DbgTraceClkselMux) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_mux(&mut self, val: FlexioClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccDbgTraceClksel { +impl Default for FlexioClksel { #[inline(always)] - fn default() -> MrccDbgTraceClksel { - MrccDbgTraceClksel(0) + fn default() -> FlexioClksel { + FlexioClksel(0) } } -impl core::fmt::Debug for MrccDbgTraceClksel { +impl core::fmt::Debug for FlexioClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccDbgTraceClksel") + f.debug_struct("FlexioClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccDbgTraceClksel { +impl defmt::Format for FlexioClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccDbgTraceClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "FlexioClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "Control Automatic Clock Gating 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc0(pub u32); -impl MrccGlbAcc0 { +pub struct GlbAcc0(pub u32); +impl GlbAcc0 { #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] @@ -2616,6 +1187,18 @@ impl MrccGlbAcc0 { pub const fn set_erm0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "FMC."] + #[must_use] + #[inline(always)] + pub const fn fmc(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "FMC."] + #[inline(always)] + pub const fn set_fmc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } #[doc = "AOI1."] #[must_use] #[inline(always)] @@ -2797,15 +1380,15 @@ impl MrccGlbAcc0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbAcc0 { +impl Default for GlbAcc0 { #[inline(always)] - fn default() -> MrccGlbAcc0 { - MrccGlbAcc0(0) + fn default() -> GlbAcc0 { + GlbAcc0(0) } } -impl core::fmt::Debug for MrccGlbAcc0 { +impl core::fmt::Debug for GlbAcc0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc0") + f.debug_struct("GlbAcc0") .field("inputmux0", &self.inputmux0()) .field("i3c0", &self.i3c0()) .field("ctimer0", &self.ctimer0()) @@ -2822,6 +1405,7 @@ impl core::fmt::Debug for MrccGlbAcc0 { .field("crc0", &self.crc0()) .field("eim0", &self.eim0()) .field("erm0", &self.erm0()) + .field("fmc", &self.fmc()) .field("aoi1", &self.aoi1()) .field("flexio0", &self.flexio0()) .field("lpi2c0", &self.lpi2c0()) @@ -2841,11 +1425,11 @@ impl core::fmt::Debug for MrccGlbAcc0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc0 { +impl defmt::Format for GlbAcc0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", + "GlbAcc0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, fmc: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", self.inputmux0(), self.i3c0(), self.ctimer0(), @@ -2862,6 +1446,7 @@ impl defmt::Format for MrccGlbAcc0 { self.crc0(), self.eim0(), self.erm0(), + self.fmc(), self.aoi1(), self.flexio0(), self.lpi2c0(), @@ -2883,8 +1468,8 @@ impl defmt::Format for MrccGlbAcc0 { #[doc = "Control Automatic Clock Gating 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc1(pub u32); -impl MrccGlbAcc1 { +pub struct GlbAcc1(pub u32); +impl GlbAcc1 { #[doc = "FLEXPWM1."] #[must_use] #[inline(always)] @@ -3234,15 +1819,15 @@ impl MrccGlbAcc1 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbAcc1 { +impl Default for GlbAcc1 { #[inline(always)] - fn default() -> MrccGlbAcc1 { - MrccGlbAcc1(0) + fn default() -> GlbAcc1 { + GlbAcc1(0) } } -impl core::fmt::Debug for MrccGlbAcc1 { +impl core::fmt::Debug for GlbAcc1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc1") + f.debug_struct("GlbAcc1") .field("flexpwm1", &self.flexpwm1()) .field("ostimer0", &self.ostimer0()) .field("adc0", &self.adc0()) @@ -3276,11 +1861,11 @@ impl core::fmt::Debug for MrccGlbAcc1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc1 { +impl defmt::Format for GlbAcc1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", + "GlbAcc1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", self.flexpwm1(), self.ostimer0(), self.adc0(), @@ -3316,8 +1901,8 @@ impl defmt::Format for MrccGlbAcc1 { #[doc = "Control Automatic Clock Gating 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc2(pub u32); -impl MrccGlbAcc2 { +pub struct GlbAcc2(pub u32); +impl GlbAcc2 { #[doc = "RAMA."] #[must_use] #[inline(always)] @@ -3439,15 +2024,15 @@ impl MrccGlbAcc2 { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } } -impl Default for MrccGlbAcc2 { +impl Default for GlbAcc2 { #[inline(always)] - fn default() -> MrccGlbAcc2 { - MrccGlbAcc2(0) + fn default() -> GlbAcc2 { + GlbAcc2(0) } } -impl core::fmt::Debug for MrccGlbAcc2 { +impl core::fmt::Debug for GlbAcc2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc2") + f.debug_struct("GlbAcc2") .field("rama", &self.rama()) .field("ramb", &self.ramb()) .field("ramc", &self.ramc()) @@ -3462,11 +2047,11 @@ impl core::fmt::Debug for MrccGlbAcc2 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc2 { +impl defmt::Format for GlbAcc2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc2 {{ rama: {=bool:?}, ramb: {=bool:?}, ramc: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?}, romc: {=bool:?} }}", + "GlbAcc2 {{ rama: {=bool:?}, ramb: {=bool:?}, ramc: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?}, romc: {=bool:?} }}", self.rama(), self.ramb(), self.ramc(), @@ -3483,8 +2068,8 @@ impl defmt::Format for MrccGlbAcc2 { #[doc = "AHB Clock Control 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc0(pub u32); -impl MrccGlbCc0 { +pub struct GlbCc0(pub u32); +impl GlbCc0 { #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] @@ -3677,6 +2262,18 @@ impl MrccGlbCc0 { pub const fn set_erm0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } + #[doc = "FMC."] + #[must_use] + #[inline(always)] + pub const fn fmc(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "FMC."] + #[inline(always)] + pub const fn set_fmc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } #[doc = "AOI1."] #[must_use] #[inline(always)] @@ -3858,15 +2455,15 @@ impl MrccGlbCc0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbCc0 { +impl Default for GlbCc0 { #[inline(always)] - fn default() -> MrccGlbCc0 { - MrccGlbCc0(0) + fn default() -> GlbCc0 { + GlbCc0(0) } } -impl core::fmt::Debug for MrccGlbCc0 { +impl core::fmt::Debug for GlbCc0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc0") + f.debug_struct("GlbCc0") .field("inputmux0", &self.inputmux0()) .field("i3c0", &self.i3c0()) .field("ctimer0", &self.ctimer0()) @@ -3883,6 +2480,7 @@ impl core::fmt::Debug for MrccGlbCc0 { .field("crc0", &self.crc0()) .field("eim0", &self.eim0()) .field("erm0", &self.erm0()) + .field("fmc", &self.fmc()) .field("aoi1", &self.aoi1()) .field("flexio0", &self.flexio0()) .field("lpi2c0", &self.lpi2c0()) @@ -3902,11 +2500,11 @@ impl core::fmt::Debug for MrccGlbCc0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc0 { +impl defmt::Format for GlbCc0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", + "GlbCc0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, fmc: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", self.inputmux0(), self.i3c0(), self.ctimer0(), @@ -3923,6 +2521,7 @@ impl defmt::Format for MrccGlbCc0 { self.crc0(), self.eim0(), self.erm0(), + self.fmc(), self.aoi1(), self.flexio0(), self.lpi2c0(), @@ -3944,8 +2543,8 @@ impl defmt::Format for MrccGlbCc0 { #[doc = "AHB Clock Control 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc1(pub u32); -impl MrccGlbCc1 { +pub struct GlbCc1(pub u32); +impl GlbCc1 { #[doc = "FLEXPWM1."] #[must_use] #[inline(always)] @@ -4307,15 +2906,15 @@ impl MrccGlbCc1 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbCc1 { +impl Default for GlbCc1 { #[inline(always)] - fn default() -> MrccGlbCc1 { - MrccGlbCc1(0) + fn default() -> GlbCc1 { + GlbCc1(0) } } -impl core::fmt::Debug for MrccGlbCc1 { +impl core::fmt::Debug for GlbCc1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc1") + f.debug_struct("GlbCc1") .field("flexpwm1", &self.flexpwm1()) .field("ostimer0", &self.ostimer0()) .field("adc0", &self.adc0()) @@ -4350,11 +2949,11 @@ impl core::fmt::Debug for MrccGlbCc1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc1 { +impl defmt::Format for GlbCc1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", + "GlbCc1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", self.flexpwm1(), self.ostimer0(), self.adc0(), @@ -4391,8 +2990,8 @@ impl defmt::Format for MrccGlbCc1 { #[doc = "AHB Clock Control 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc2(pub u32); -impl MrccGlbCc2 { +pub struct GlbCc2(pub u32); +impl GlbCc2 { #[doc = "RAMA."] #[must_use] #[inline(always)] @@ -4496,70 +3095,144 @@ impl MrccGlbCc2 { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "MAU0."] - #[inline(always)] - pub const fn set_mau0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + #[doc = "MAU0."] + #[inline(always)] + pub const fn set_mau0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "ROMC."] + #[must_use] + #[inline(always)] + pub const fn romc(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "ROMC."] + #[inline(always)] + pub const fn set_romc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } +} +impl Default for GlbCc2 { + #[inline(always)] + fn default() -> GlbCc2 { + GlbCc2(0) + } +} +impl core::fmt::Debug for GlbCc2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbCc2") + .field("rama", &self.rama()) + .field("ramb", &self.ramb()) + .field("ramc", &self.ramc()) + .field("gpio0", &self.gpio0()) + .field("gpio1", &self.gpio1()) + .field("gpio2", &self.gpio2()) + .field("gpio3", &self.gpio3()) + .field("gpio4", &self.gpio4()) + .field("mau0", &self.mau0()) + .field("romc", &self.romc()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbCc2 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "GlbCc2 {{ rama: {=bool:?}, ramb: {=bool:?}, ramc: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?}, romc: {=bool:?} }}", + self.rama(), + self.ramb(), + self.ramc(), + self.gpio0(), + self.gpio1(), + self.gpio2(), + self.gpio3(), + self.gpio4(), + self.mau0(), + self.romc() + ) + } +} +#[doc = "AHB Clock Control Clear 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbCcClr(pub u32); +impl GlbCcClr { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for GlbCcClr { + #[inline(always)] + fn default() -> GlbCcClr { + GlbCcClr(0) + } +} +impl core::fmt::Debug for GlbCcClr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbCcClr") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbCcClr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbCcClr {{ data: {=u32:?} }}", self.data()) } - #[doc = "ROMC."] +} +#[doc = "AHB Clock Control Set 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbCcSet(pub u32); +impl GlbCcSet { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] #[must_use] #[inline(always)] - pub const fn romc(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "ROMC."] + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] #[inline(always)] - pub const fn set_romc(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } -impl Default for MrccGlbCc2 { +impl Default for GlbCcSet { #[inline(always)] - fn default() -> MrccGlbCc2 { - MrccGlbCc2(0) + fn default() -> GlbCcSet { + GlbCcSet(0) } } -impl core::fmt::Debug for MrccGlbCc2 { +impl core::fmt::Debug for GlbCcSet { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc2") - .field("rama", &self.rama()) - .field("ramb", &self.ramb()) - .field("ramc", &self.ramc()) - .field("gpio0", &self.gpio0()) - .field("gpio1", &self.gpio1()) - .field("gpio2", &self.gpio2()) - .field("gpio3", &self.gpio3()) - .field("gpio4", &self.gpio4()) - .field("mau0", &self.mau0()) - .field("romc", &self.romc()) + f.debug_struct("GlbCcSet") + .field("data", &self.data()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc2 { +impl defmt::Format for GlbCcSet { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccGlbCc2 {{ rama: {=bool:?}, ramb: {=bool:?}, ramc: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?}, romc: {=bool:?} }}", - self.rama(), - self.ramb(), - self.ramc(), - self.gpio0(), - self.gpio1(), - self.gpio2(), - self.gpio3(), - self.gpio4(), - self.mau0(), - self.romc() - ) + defmt::write!(f, "GlbCcSet {{ data: {=u32:?} }}", self.data()) } } #[doc = "Peripheral Reset Control 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst0(pub u32); -impl MrccGlbRst0 { +pub struct GlbRst0(pub u32); +impl GlbRst0 { #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] @@ -4921,15 +3594,15 @@ impl MrccGlbRst0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbRst0 { +impl Default for GlbRst0 { #[inline(always)] - fn default() -> MrccGlbRst0 { - MrccGlbRst0(0) + fn default() -> GlbRst0 { + GlbRst0(0) } } -impl core::fmt::Debug for MrccGlbRst0 { +impl core::fmt::Debug for GlbRst0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst0") + f.debug_struct("GlbRst0") .field("inputmux0", &self.inputmux0()) .field("i3c0", &self.i3c0()) .field("ctimer0", &self.ctimer0()) @@ -4964,11 +3637,11 @@ impl core::fmt::Debug for MrccGlbRst0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst0 { +impl defmt::Format for GlbRst0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", + "GlbRst0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick0: {=bool:?}, smartdma0: {=bool:?}, dma0: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, aoi1: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, usb0: {=bool:?}, qdc0: {=bool:?}, qdc1: {=bool:?}, flexpwm0: {=bool:?} }}", self.inputmux0(), self.i3c0(), self.ctimer0(), @@ -5005,8 +3678,8 @@ impl defmt::Format for MrccGlbRst0 { #[doc = "Peripheral Reset Control 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst1(pub u32); -impl MrccGlbRst1 { +pub struct GlbRst1(pub u32); +impl GlbRst1 { #[doc = "FLEXPWM1."] #[must_use] #[inline(always)] @@ -5320,15 +3993,15 @@ impl MrccGlbRst1 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbRst1 { +impl Default for GlbRst1 { #[inline(always)] - fn default() -> MrccGlbRst1 { - MrccGlbRst1(0) + fn default() -> GlbRst1 { + GlbRst1(0) } } -impl core::fmt::Debug for MrccGlbRst1 { +impl core::fmt::Debug for GlbRst1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst1") + f.debug_struct("GlbRst1") .field("flexpwm1", &self.flexpwm1()) .field("ostimer0", &self.ostimer0()) .field("adc0", &self.adc0()) @@ -5359,11 +4032,11 @@ impl core::fmt::Debug for MrccGlbRst1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst1 { +impl defmt::Format for GlbRst1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, pkc0: {=bool:?}, trng0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", + "GlbRst1 {{ flexpwm1: {=bool:?}, ostimer0: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp1: {=bool:?}, cmp2: {=bool:?}, dac0: {=bool:?}, opamp0: {=bool:?}, opamp1: {=bool:?}, opamp2: {=bool:?}, opamp3: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, slcd0: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpuart5: {=bool:?}, pkc0: {=bool:?}, trng0: {=bool:?}, adc2: {=bool:?}, adc3: {=bool:?} }}", self.flexpwm1(), self.ostimer0(), self.adc0(), @@ -5396,8 +4069,8 @@ impl defmt::Format for MrccGlbRst1 { #[doc = "Peripheral Reset Control 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst2(pub u32); -impl MrccGlbRst2 { +pub struct GlbRst2(pub u32); +impl GlbRst2 { #[doc = "GPIO0."] #[must_use] #[inline(always)] @@ -5467,161 +4140,300 @@ impl MrccGlbRst2 { } #[doc = "MAU0."] #[inline(always)] - pub const fn set_mau0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + pub const fn set_mau0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } +} +impl Default for GlbRst2 { + #[inline(always)] + fn default() -> GlbRst2 { + GlbRst2(0) + } +} +impl core::fmt::Debug for GlbRst2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbRst2") + .field("gpio0", &self.gpio0()) + .field("gpio1", &self.gpio1()) + .field("gpio2", &self.gpio2()) + .field("gpio3", &self.gpio3()) + .field("gpio4", &self.gpio4()) + .field("mau0", &self.mau0()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbRst2 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "GlbRst2 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?} }}", + self.gpio0(), + self.gpio1(), + self.gpio2(), + self.gpio3(), + self.gpio4(), + self.mau0() + ) + } +} +#[doc = "Peripheral Reset Control Clear 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbRstClr(pub u32); +impl GlbRstClr { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for GlbRstClr { + #[inline(always)] + fn default() -> GlbRstClr { + GlbRstClr(0) + } +} +impl core::fmt::Debug for GlbRstClr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbRstClr") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbRstClr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbRstClr {{ data: {=u32:?} }}", self.data()) + } +} +#[doc = "Peripheral Reset Control Set 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbRstSet(pub u32); +impl GlbRstSet { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for GlbRstSet { + #[inline(always)] + fn default() -> GlbRstSet { + GlbRstSet(0) + } +} +impl core::fmt::Debug for GlbRstSet { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbRstSet") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbRstSet { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbRstSet {{ data: {=u32:?} }}", self.data()) + } +} +#[doc = "I3C0_FCLK clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct I3cFclkClksel(pub u32); +impl I3cFclkClksel { + #[doc = "Functional Clock Mux Select."] + #[must_use] + #[inline(always)] + pub const fn mux(&self) -> FclkClkselMux { + let val = (self.0 >> 0usize) & 0x07; + FclkClkselMux::from_bits(val as u8) + } + #[doc = "Functional Clock Mux Select."] + #[inline(always)] + pub const fn set_mux(&mut self, val: FclkClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } +} +impl Default for I3cFclkClksel { + #[inline(always)] + fn default() -> I3cFclkClksel { + I3cFclkClksel(0) + } +} +impl core::fmt::Debug for I3cFclkClksel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3cFclkClksel") + .field("mux", &self.mux()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for I3cFclkClksel { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "I3cFclkClksel {{ mux: {:?} }}", self.mux()) + } +} +#[doc = "LPI2C0 clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Lpi2cClksel(pub u32); +impl Lpi2cClksel { + #[doc = "Functional Clock Mux Select."] + #[must_use] + #[inline(always)] + pub const fn mux(&self) -> Lpi2cClkselMux { + let val = (self.0 >> 0usize) & 0x07; + Lpi2cClkselMux::from_bits(val as u8) + } + #[doc = "Functional Clock Mux Select."] + #[inline(always)] + pub const fn set_mux(&mut self, val: Lpi2cClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); + } +} +impl Default for Lpi2cClksel { + #[inline(always)] + fn default() -> Lpi2cClksel { + Lpi2cClksel(0) + } +} +impl core::fmt::Debug for Lpi2cClksel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Lpi2cClksel") + .field("mux", &self.mux()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Lpi2cClksel { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Lpi2cClksel {{ mux: {:?} }}", self.mux()) + } +} +#[doc = "LPSPI0 clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct LpspiClksel(pub u32); +impl LpspiClksel { + #[doc = "Functional Clock Mux Select."] + #[must_use] + #[inline(always)] + pub const fn mux(&self) -> LpspiClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LpspiClkselMux::from_bits(val as u8) + } + #[doc = "Functional Clock Mux Select."] + #[inline(always)] + pub const fn set_mux(&mut self, val: LpspiClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccGlbRst2 { +impl Default for LpspiClksel { #[inline(always)] - fn default() -> MrccGlbRst2 { - MrccGlbRst2(0) + fn default() -> LpspiClksel { + LpspiClksel(0) } } -impl core::fmt::Debug for MrccGlbRst2 { +impl core::fmt::Debug for LpspiClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst2") - .field("gpio0", &self.gpio0()) - .field("gpio1", &self.gpio1()) - .field("gpio2", &self.gpio2()) - .field("gpio3", &self.gpio3()) - .field("gpio4", &self.gpio4()) - .field("mau0", &self.mau0()) + f.debug_struct("LpspiClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst2 { +impl defmt::Format for LpspiClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccGlbRst2 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, mau0: {=bool:?} }}", - self.gpio0(), - self.gpio1(), - self.gpio2(), - self.gpio3(), - self.gpio4(), - self.mau0() - ) + defmt::write!(f, "LpspiClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "SYSTICK clock divider control."] +#[doc = "LPTMR0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccSystickClkdiv(pub u32); -impl MrccSystickClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct LptmrClksel(pub u32); +impl LptmrClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> LptmrClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LptmrClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: LptmrClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccSystickClkdiv { +impl Default for LptmrClksel { #[inline(always)] - fn default() -> MrccSystickClkdiv { - MrccSystickClkdiv(0) + fn default() -> LptmrClksel { + LptmrClksel(0) } } -impl core::fmt::Debug for MrccSystickClkdiv { +impl core::fmt::Debug for LptmrClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccSystickClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("LptmrClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccSystickClkdiv { +impl defmt::Format for LptmrClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccSystickClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "LptmrClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "SYSTICK clock selection control."] +#[doc = "LPUART0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccSystickClksel(pub u32); -impl MrccSystickClksel { +pub struct LpuartClksel(pub u32); +impl LpuartClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> SystickClkselMux { - let val = (self.0 >> 0usize) & 0x03; - SystickClkselMux::from_bits(val as u8) + pub const fn mux(&self) -> LpuartClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LpuartClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: SystickClkselMux) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_mux(&mut self, val: LpuartClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccSystickClksel { +impl Default for LpuartClksel { #[inline(always)] - fn default() -> MrccSystickClksel { - MrccSystickClksel(0) + fn default() -> LpuartClksel { + LpuartClksel(0) } } -impl core::fmt::Debug for MrccSystickClksel { +impl core::fmt::Debug for LpuartClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccSystickClksel") + f.debug_struct("LpuartClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccSystickClksel { +impl defmt::Format for LpuartClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccSystickClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "LpuartClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "OSTIMER0 clock selection control."] @@ -5661,87 +4473,41 @@ impl defmt::Format for OstimerClksel { defmt::write!(f, "OstimerClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "USB0 clock divider control."] +#[doc = "SYSTICK clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct UsbClkdiv(pub u32); -impl UsbClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct SystickClksel(pub u32); +impl SystickClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> SystickClkselMux { + let val = (self.0 >> 0usize) & 0x03; + SystickClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: SystickClkselMux) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } } -impl Default for UsbClkdiv { +impl Default for SystickClksel { #[inline(always)] - fn default() -> UsbClkdiv { - UsbClkdiv(0) + fn default() -> SystickClksel { + SystickClksel(0) } } -impl core::fmt::Debug for UsbClkdiv { +impl core::fmt::Debug for SystickClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UsbClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("SystickClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for UsbClkdiv { +impl defmt::Format for SystickClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "UsbClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "SystickClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "USB0 clock selection control."] @@ -5781,105 +4547,22 @@ impl defmt::Format for UsbClksel { defmt::write!(f, "UsbClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "WWDT0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct WwdtClkdiv(pub u32); -impl WwdtClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for WwdtClkdiv { - #[inline(always)] - fn default() -> WwdtClkdiv { - WwdtClkdiv(0) - } -} -impl core::fmt::Debug for WwdtClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WwdtClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for WwdtClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "WwdtClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AdcClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, #[doc = "FRO_HF_GATED."] - CLKROOT_FUNC_1 = 0x01, + ClkrootFunc1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl AdcClkselMux { @@ -5909,9 +4592,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivHalt { #[doc = "Divider clock is running."] - ON = 0x0, + On = 0x0, #[doc = "Divider clock is stopped."] - OFF = 0x01, + Off = 0x01, } impl ClkdivHalt { #[inline(always)] @@ -5940,9 +4623,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivReset { #[doc = "Divider isn't reset."] - ON = 0x0, + On = 0x0, #[doc = "Divider is reset."] - OFF = 0x01, + Off = 0x01, } impl ClkdivReset { #[inline(always)] @@ -5971,9 +4654,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivUnstab { #[doc = "Divider clock is stable."] - ON = 0x0, + On = 0x0, #[doc = "Clock frequency isn't stable."] - OFF = 0x01, + Off = 0x01, } impl ClkdivUnstab { #[inline(always)] @@ -6002,18 +4685,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkoutClkselMux { #[doc = "FRO_12M."] - CLKROOT_12M = 0x0, + Clkroot12m = 0x0, #[doc = "FRO_HF_DIV."] - CLKROOT_FIRC_DIV = 0x01, + ClkrootFircDiv = 0x01, #[doc = "CLK_IN."] - CLKROOT_SOSC = 0x02, + ClkrootSosc = 0x02, #[doc = "CLK_16K."] - CLKROOT_16K = 0x03, + Clkroot16k = 0x03, _RESERVED_4 = 0x04, #[doc = "PLL1_CLK."] - CLKROOT_SPLL = 0x05, + ClkrootSpll = 0x05, #[doc = "SLOW_CLK."] - CLKROOT_SLOW = 0x06, + ClkrootSlow = 0x06, _RESERVED_7 = 0x07, } impl ClkoutClkselMux { @@ -6043,18 +4726,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CtimerClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, #[doc = "FRO_HF_GATED."] - CLKROOT_FUNC_1 = 0x01, + ClkrootFunc1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, #[doc = "CLK_16K."] - CLKROOT_FUNC_4 = 0x04, + ClkrootFunc4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl CtimerClkselMux { @@ -6084,17 +4767,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DacClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl DacClkselMux { @@ -6124,11 +4807,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DbgTraceClkselMux { #[doc = "CPU_CLK."] - CLKROOT_CPU = 0x0, + ClkrootCpu = 0x0, #[doc = "CLK_1M."] - CLKROOT_1M = 0x01, + Clkroot1m = 0x01, #[doc = "CLK_16K."] - CLKROOT_16K = 0x02, + Clkroot16k = 0x02, _RESERVED_3 = 0x03, } impl DbgTraceClkselMux { @@ -6158,17 +4841,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FclkClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl FclkClkselMux { @@ -6199,15 +4882,15 @@ impl From for u8 { pub enum FlexcanClkselMux { _RESERVED_0 = 0x0, #[doc = "FRO_HF_GATED."] - CLKROOT_FIRC_GATED = 0x01, + ClkrootFircGated = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FIRC_DIV = 0x02, + ClkrootFircDiv = 0x02, #[doc = "CLK_IN."] - CLKROOT_SOSC = 0x03, + ClkrootSosc = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - CLKROOT_SPLL = 0x06, + ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } impl FlexcanClkselMux { @@ -6237,17 +4920,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlexioClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, #[doc = "FRO_HF_GATED."] - CLKROOT_FUNC_1 = 0x01, + ClkrootFunc1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl FlexioClkselMux { @@ -6277,17 +4960,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lpi2cClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl Lpi2cClkselMux { @@ -6317,17 +5000,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpspiClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl LpspiClkselMux { @@ -6357,17 +5040,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LptmrClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl LptmrClkselMux { @@ -6397,18 +5080,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpuartClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, #[doc = "CLK_16K."] - CLKROOT_FUNC_4 = 0x04, + ClkrootFunc4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl LpuartClkselMux { @@ -6438,10 +5121,10 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum OstimerClkselMux { #[doc = "CLK_16K."] - CLKROOT_16K = 0x0, + Clkroot16k = 0x0, _RESERVED_1 = 0x01, #[doc = "CLK_1M."] - CLKROOT_1M = 0x02, + Clkroot1m = 0x02, _RESERVED_3 = 0x03, } impl OstimerClkselMux { @@ -6471,17 +5154,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RrClkselMux { #[doc = "FRO_LF_DIV."] - CLKROOT_FUNC_0 = 0x0, + ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - CLKROOT_FUNC_2 = 0x02, + ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - CLKROOT_FUNC_3 = 0x03, + ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - CLKROOT_FUNC_5 = 0x05, + ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - CLKROOT_FUNC_6 = 0x06, + ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl RrClkselMux { @@ -6511,11 +5194,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SystickClkselMux { #[doc = "CPU_CLK."] - CLKROOT_CPU = 0x0, + ClkrootCpu = 0x0, #[doc = "CLK_1M."] - CLKROOT_1M = 0x01, + Clkroot1m = 0x01, #[doc = "CLK_16K."] - CLKROOT_16K = 0x02, + Clkroot16k = 0x02, _RESERVED_3 = 0x03, } impl SystickClkselMux { @@ -6545,11 +5228,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum UsbClkselMux { #[doc = "PLL1_CLK."] - CLKROOT_SPLL = 0x0, + ClkrootSpll = 0x0, #[doc = "CLK_48M."] - SCG_SCG_FIRC_48MHZ_CLK = 0x01, + ScgScgFirc48mhzClk = 0x01, #[doc = "CLK_IN."] - CLKROOT_SOSC = 0x02, + ClkrootSosc = 0x02, _RESERVED_3 = 0x03, } impl UsbClkselMux { diff --git a/nxp-pac/src/meta_peripherals/mcxa/MRCC5xx.rs b/nxp-pac/src/meta_peripherals/mcxa/MRCC5xx.rs index 5d8d6f1..68b9adf 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/MRCC5xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/MRCC5xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "MRCC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mrcc { @@ -19,9 +20,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 0."] #[inline(always)] - pub const fn mrcc_glb_rst0( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0usize) as _) } } #[doc = "Peripheral Reset Control Set 0."] @@ -40,9 +39,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 1."] #[inline(always)] - pub const fn mrcc_glb_rst1( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize) as _) } } #[doc = "Peripheral Reset Control Set 1."] @@ -61,9 +58,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 2."] #[inline(always)] - pub const fn mrcc_glb_rst2( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } } #[doc = "Peripheral Reset Control Set 2."] @@ -82,9 +77,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 3."] #[inline(always)] - pub const fn mrcc_glb_rst3( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst3(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x30usize) as _) } } #[doc = "Peripheral Reset Control Set 3."] @@ -103,9 +96,7 @@ impl Mrcc { } #[doc = "Peripheral Reset Control 4."] #[inline(always)] - pub const fn mrcc_glb_rst4( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_rst4(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize) as _) } } #[doc = "Peripheral Reset Control Set 4."] @@ -124,7 +115,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 0."] #[inline(always)] - pub const fn mrcc_glb_cc0(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x60usize) as _) } } #[doc = "AHB Clock Control Set 0."] @@ -143,7 +134,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 1."] #[inline(always)] - pub const fn mrcc_glb_cc1(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x70usize) as _) } } #[doc = "AHB Clock Control Set 1."] @@ -162,7 +153,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 2."] #[inline(always)] - pub const fn mrcc_glb_cc2(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x80usize) as _) } } #[doc = "AHB Clock Control Set 2."] @@ -181,7 +172,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 3."] #[inline(always)] - pub const fn mrcc_glb_cc3(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc3(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x90usize) as _) } } #[doc = "AHB Clock Control Set 3."] @@ -200,7 +191,7 @@ impl Mrcc { } #[doc = "AHB Clock Control 4."] #[inline(always)] - pub const fn mrcc_glb_cc4(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_cc4(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xa0usize) as _) } } #[doc = "AHB Clock Control Set 4."] @@ -219,62 +210,52 @@ impl Mrcc { } #[doc = "Control Automatic Clock Gating 0."] #[inline(always)] - pub const fn mrcc_glb_acc0( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc0usize) as _) } } #[doc = "Control Automatic Clock Gating 1."] #[inline(always)] - pub const fn mrcc_glb_acc1( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc4usize) as _) } } #[doc = "Control Automatic Clock Gating 2."] #[inline(always)] - pub const fn mrcc_glb_acc2( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xc8usize) as _) } } #[doc = "Control Automatic Clock Gating 3."] #[inline(always)] - pub const fn mrcc_glb_acc3( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc3(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xccusize) as _) } } #[doc = "Control Automatic Clock Gating 4."] #[inline(always)] - pub const fn mrcc_glb_acc4( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_glb_acc4(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd0usize) as _) } } #[doc = "Peripheral Enable Configuration 0. Reset on POR only."] #[inline(always)] - pub const fn mrcc_glb_pr0(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_pr0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xd8usize) as _) } } #[doc = "Peripheral Enable Configuration 1. Reset on POR only."] #[inline(always)] - pub const fn mrcc_glb_pr1(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_pr1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xdcusize) as _) } } #[doc = "Peripheral Enable Configuration 2. Reset on POR only."] #[inline(always)] - pub const fn mrcc_glb_pr2(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_pr2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe0usize) as _) } } #[doc = "Peripheral Enable Configuration 3. Reset on POR only."] #[inline(always)] - pub const fn mrcc_glb_pr3(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_pr3(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe4usize) as _) } } #[doc = "Peripheral Enable Configuration 4. Reset on POR only."] #[inline(always)] - pub const fn mrcc_glb_pr4(self) -> crate::pac::common::Reg { + pub const fn mrcc_glb_pr4(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xe8usize) as _) } } #[doc = "I3C0_FCLK clock selection control."] @@ -288,7 +269,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_i3c0_fclk_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0104usize) as _) } } #[doc = "I3C1_FCLK clock selection control."] @@ -302,7 +283,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_i3c1_fclk_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x010cusize) as _) } } #[doc = "CTIMER0 clock selection control."] @@ -316,7 +297,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0114usize) as _) } } #[doc = "CTIMER1 clock selection control."] @@ -330,7 +311,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x011cusize) as _) } } #[doc = "CTIMER2 clock selection control."] @@ -344,7 +325,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0124usize) as _) } } #[doc = "CTIMER3 clock selection control."] @@ -358,7 +339,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x012cusize) as _) } } #[doc = "CTIMER4 clock selection control."] @@ -372,14 +353,14 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_ctimer4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0134usize) as _) } } #[doc = "WWDT0 clock divider control."] #[inline(always)] pub const fn mrcc_wwdt0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x013cusize) as _) } } #[doc = "WWDT1 clock selection control."] @@ -393,35 +374,33 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_wwdt1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0144usize) as _) } } #[doc = "E1588 clock selection control."] #[inline(always)] pub const fn mrcc_e1588_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0148usize) as _) } } #[doc = "E1588 clock divider control."] #[inline(always)] pub const fn mrcc_e1588_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x014cusize) as _) } } #[doc = "RMII clock selection control."] #[inline(always)] pub const fn mrcc_rmii_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0150usize) as _) } } #[doc = "RMII clock divider control."] #[inline(always)] - pub const fn mrcc_rmii_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_rmii_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0154usize) as _) } } #[doc = "ESPI0 clock selection control."] @@ -435,7 +414,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_espi0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x015cusize) as _) } } #[doc = "FLEXSPI0 clock selection control."] @@ -449,7 +428,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexspi0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0164usize) as _) } } #[doc = "LPSPI2 clock selection control."] @@ -463,7 +442,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x016cusize) as _) } } #[doc = "LPSPI3 clock selection control."] @@ -477,7 +456,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0174usize) as _) } } #[doc = "LPSPI4 clock selection control."] @@ -491,7 +470,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x017cusize) as _) } } #[doc = "LPSPI5 clock selection control."] @@ -505,7 +484,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi5_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0184usize) as _) } } #[doc = "T1S0 clock selection control."] @@ -517,9 +496,7 @@ impl Mrcc { } #[doc = "T1S0 clock divider control."] #[inline(always)] - pub const fn mrcc_t1s0_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_t1s0_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x018cusize) as _) } } #[doc = "USB1 clock selection control."] @@ -540,7 +517,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_usb1_phy_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x019cusize) as _) } } #[doc = "FLEXIO0 clock selection control."] @@ -554,7 +531,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexio0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01a4usize) as _) } } #[doc = "LPI2C0 clock selection control."] @@ -568,7 +545,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01acusize) as _) } } #[doc = "LPI2C1 clock selection control."] @@ -582,7 +559,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01b4usize) as _) } } #[doc = "LPSPI0 clock selection control."] @@ -596,7 +573,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01bcusize) as _) } } #[doc = "LPSPI1 clock selection control."] @@ -610,7 +587,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpspi1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01c4usize) as _) } } #[doc = "I3C2_FCLK clock selection control."] @@ -624,7 +601,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_i3c2_fclk_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01ccusize) as _) } } #[doc = "LPUART0 clock selection control."] @@ -638,7 +615,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01d4usize) as _) } } #[doc = "LPUART1 clock selection control."] @@ -652,7 +629,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01dcusize) as _) } } #[doc = "LPUART2 clock selection control."] @@ -666,7 +643,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01e4usize) as _) } } #[doc = "LPUART3 clock selection control."] @@ -680,7 +657,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01ecusize) as _) } } #[doc = "LPUART4 clock selection control."] @@ -694,7 +671,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01f4usize) as _) } } #[doc = "LPTMR0 clock selection control."] @@ -708,7 +685,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lptmr0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01fcusize) as _) } } #[doc = "OSTIMER0 clock selection control."] @@ -722,21 +699,19 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_adc_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0208usize) as _) } } #[doc = "ADCx clock divider control."] #[inline(always)] - pub const fn mrcc_adc_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_adc_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x020cusize) as _) } } #[doc = "CMP0_FUNC clock divider control."] #[inline(always)] pub const fn mrcc_cmp0_func_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0214usize) as _) } } #[doc = "CMP0_RR clock selection control."] @@ -750,7 +725,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_cmp0_rr_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x021cusize) as _) } } #[doc = "DAC0 clock selection control."] @@ -762,9 +737,7 @@ impl Mrcc { } #[doc = "DAC0 clock divider control."] #[inline(always)] - pub const fn mrcc_dac0_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_dac0_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0224usize) as _) } } #[doc = "DAC1 clock selection control."] @@ -776,9 +749,7 @@ impl Mrcc { } #[doc = "DAC1 clock divider control."] #[inline(always)] - pub const fn mrcc_dac1_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_dac1_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x022cusize) as _) } } #[doc = "TSI0 clock selection control."] @@ -790,9 +761,7 @@ impl Mrcc { } #[doc = "TSI0 clock divider control."] #[inline(always)] - pub const fn mrcc_tsi0_clkdiv( - self, - ) -> crate::pac::common::Reg { + pub const fn mrcc_tsi0_clkdiv(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0234usize) as _) } } #[doc = "FLEXCAN0 clock selection control."] @@ -806,7 +775,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexcan0_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x023cusize) as _) } } #[doc = "FLEXCAN1 clock selection control."] @@ -820,7 +789,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_flexcan1_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0244usize) as _) } } #[doc = "LPI2C2 clock selection control."] @@ -834,7 +803,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c2_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x024cusize) as _) } } #[doc = "LPI2C3 clock selection control."] @@ -848,7 +817,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c3_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0254usize) as _) } } #[doc = "LPI2C4 clock selection control."] @@ -862,7 +831,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpi2c4_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x025cusize) as _) } } #[doc = "LPUART5 clock selection control."] @@ -876,7 +845,7 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_lpuart5_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0264usize) as _) } } #[doc = "I3C3_FCLK clock selection control."] @@ -890,140 +859,94 @@ impl Mrcc { #[inline(always)] pub const fn mrcc_i3c3_fclk_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x026cusize) as _) } } #[doc = "DBG_TRACE clock selection control."] #[inline(always)] pub const fn mrcc_dbg_trace_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0270usize) as _) } } #[doc = "DBG_TRACE clock divider control."] #[inline(always)] pub const fn mrcc_dbg_trace_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0274usize) as _) } } #[doc = "CLKOUT clock selection control."] #[inline(always)] pub const fn mrcc_clkout_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0278usize) as _) } } #[doc = "CLKOUT clock divider control."] #[inline(always)] pub const fn mrcc_clkout_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x027cusize) as _) } } #[doc = "SYSTICK clock selection control."] #[inline(always)] pub const fn mrcc_systick_clksel( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0280usize) as _) } } #[doc = "SYSTICK clock divider control."] #[inline(always)] pub const fn mrcc_systick_clkdiv( self, - ) -> crate::pac::common::Reg { + ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0284usize) as _) } } } -#[doc = "CMP0_FUNC clock divider control."] +#[doc = "ADCx clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpFuncClkdiv(pub u32); -impl CmpFuncClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct AdcClksel(pub u32); +impl AdcClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> AdcClkselMux { + let val = (self.0 >> 0usize) & 0x07; + AdcClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: AdcClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CmpFuncClkdiv { +impl Default for AdcClksel { #[inline(always)] - fn default() -> CmpFuncClkdiv { - CmpFuncClkdiv(0) + fn default() -> AdcClksel { + AdcClksel(0) } } -impl core::fmt::Debug for CmpFuncClkdiv { +impl core::fmt::Debug for AdcClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpFuncClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("AdcClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpFuncClkdiv { +impl defmt::Format for AdcClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "CmpFuncClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "AdcClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "CMP0_RR clock divider control."] +#[doc = "ADCx clock divider control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpRrClkdiv(pub u32); -impl CmpRrClkdiv { +pub struct Clkdiv(pub u32); +impl Clkdiv { #[doc = "Functional Clock Divider."] #[must_use] #[inline(always)] @@ -1073,15 +996,15 @@ impl CmpRrClkdiv { self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); } } -impl Default for CmpRrClkdiv { +impl Default for Clkdiv { #[inline(always)] - fn default() -> CmpRrClkdiv { - CmpRrClkdiv(0) + fn default() -> Clkdiv { + Clkdiv(0) } } -impl core::fmt::Debug for CmpRrClkdiv { +impl core::fmt::Debug for Clkdiv { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpRrClkdiv") + f.debug_struct("Clkdiv") .field("div", &self.div()) .field("reset", &self.reset()) .field("halt", &self.halt()) @@ -1090,11 +1013,11 @@ impl core::fmt::Debug for CmpRrClkdiv { } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpRrClkdiv { +impl defmt::Format for Clkdiv { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "CmpRrClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", + "Clkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", self.div(), self.reset(), self.halt(), @@ -1102,124 +1025,78 @@ impl defmt::Format for CmpRrClkdiv { ) } } -#[doc = "CMP0_RR clock selection control."] +#[doc = "CLKOUT clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CmpRrClksel(pub u32); -impl CmpRrClksel { +pub struct ClkoutClksel(pub u32); +impl ClkoutClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> RrClkselMux { + pub const fn mux(&self) -> ClkoutClkselMux { let val = (self.0 >> 0usize) & 0x07; - RrClkselMux::from_bits(val as u8) + ClkoutClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: RrClkselMux) { + pub const fn set_mux(&mut self, val: ClkoutClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CmpRrClksel { +impl Default for ClkoutClksel { #[inline(always)] - fn default() -> CmpRrClksel { - CmpRrClksel(0) + fn default() -> ClkoutClksel { + ClkoutClksel(0) } } -impl core::fmt::Debug for CmpRrClksel { +impl core::fmt::Debug for ClkoutClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CmpRrClksel") + f.debug_struct("ClkoutClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CmpRrClksel { +impl defmt::Format for ClkoutClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "CmpRrClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "ClkoutClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "CTIMER0 clock divider control."] +#[doc = "CMP0_RR clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct CtimerClkdiv(pub u32); -impl CtimerClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct CmpRrClksel(pub u32); +impl CmpRrClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> RrClkselMux { + let val = (self.0 >> 0usize) & 0x07; + RrClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: RrClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for CtimerClkdiv { +impl Default for CmpRrClksel { #[inline(always)] - fn default() -> CtimerClkdiv { - CtimerClkdiv(0) + fn default() -> CmpRrClksel { + CmpRrClksel(0) } } -impl core::fmt::Debug for CtimerClkdiv { +impl core::fmt::Debug for CmpRrClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CtimerClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("CmpRrClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for CtimerClkdiv { +impl defmt::Format for CmpRrClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "CtimerClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "CmpRrClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "CTIMER0 clock selection control."] @@ -1259,89 +1136,6 @@ impl defmt::Format for CtimerClksel { defmt::write!(f, "CtimerClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "DAC0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct DacClkdiv(pub u32); -impl DacClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for DacClkdiv { - #[inline(always)] - fn default() -> DacClkdiv { - DacClkdiv(0) - } -} -impl core::fmt::Debug for DacClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DacClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for DacClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "DacClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} #[doc = "DAC0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1379,207 +1173,78 @@ impl defmt::Format for DacClksel { defmt::write!(f, "DacClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "E1588 clock divider control."] +#[doc = "DBG_TRACE clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct E158clkdiv(pub u32); -impl E158clkdiv { - #[doc = "Functional Clock Divider."] +pub struct DbgTraceClksel(pub u32); +impl DbgTraceClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub const fn mux(&self) -> DbgTraceClkselMux { + let val = (self.0 >> 0usize) & 0x03; + DbgTraceClkselMux::from_bits(val as u8) } - #[doc = "Functional Clock Divider."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: DbgTraceClkselMux) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } } -impl Default for E158clkdiv { +impl Default for DbgTraceClksel { #[inline(always)] - fn default() -> E158clkdiv { - E158clkdiv(0) + fn default() -> DbgTraceClksel { + DbgTraceClksel(0) } } -impl core::fmt::Debug for E158clkdiv { +impl core::fmt::Debug for DbgTraceClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("E158clkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("DbgTraceClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for E158clkdiv { +impl defmt::Format for DbgTraceClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "E158clkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "DbgTraceClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "E1588 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct E158clksel(pub u32); -impl E158clksel { +pub struct E158Clksel(pub u32); +impl E158Clksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> E158clkselMux { + pub const fn mux(&self) -> E158ClkselMux { let val = (self.0 >> 0usize) & 0x07; - E158clkselMux::from_bits(val as u8) + E158ClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: E158clkselMux) { + pub const fn set_mux(&mut self, val: E158ClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for E158clksel { +impl Default for E158Clksel { #[inline(always)] - fn default() -> E158clksel { - E158clksel(0) + fn default() -> E158Clksel { + E158Clksel(0) } } -impl core::fmt::Debug for E158clksel { +impl core::fmt::Debug for E158Clksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("E158clksel") + f.debug_struct("E158Clksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for E158clksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "E158clksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "ESPI0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct EspiClkdiv(pub u32); -impl EspiClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for EspiClkdiv { - #[inline(always)] - fn default() -> EspiClkdiv { - EspiClkdiv(0) - } -} -impl core::fmt::Debug for EspiClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EspiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for EspiClkdiv { +impl defmt::Format for E158Clksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "EspiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "E158Clksel {{ mux: {:?} }}", self.mux()) } } #[doc = "ESPI0 clock selection control."] @@ -1619,1492 +1284,135 @@ impl defmt::Format for EspiClksel { defmt::write!(f, "EspiClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "FLEXCAN0 clock divider control."] +#[doc = "FLEXCAN0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexcanClkdiv(pub u32); -impl FlexcanClkdiv { - #[doc = "Functional Clock Divider."] +pub struct FlexcanClksel(pub u32); +impl FlexcanClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn mux(&self) -> FlexcanClkselMux { + let val = (self.0 >> 0usize) & 0x07; + FlexcanClkselMux::from_bits(val as u8) } - #[doc = "Reset divider counter."] - #[must_use] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) + pub const fn set_mux(&mut self, val: FlexcanClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } - #[doc = "Reset divider counter."] +} +impl Default for FlexcanClksel { #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + fn default() -> FlexcanClksel { + FlexcanClksel(0) } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) +} +impl core::fmt::Debug for FlexcanClksel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FlexcanClksel") + .field("mux", &self.mux()) + .finish() } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for FlexcanClksel { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "FlexcanClksel {{ mux: {:?} }}", self.mux()) } - #[doc = "Divider status flag."] +} +#[doc = "FLEXIO0 clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct FlexioClksel(pub u32); +impl FlexioClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> FlexioClkselMux { + let val = (self.0 >> 0usize) & 0x07; + FlexioClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: FlexioClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for FlexcanClkdiv { +impl Default for FlexioClksel { #[inline(always)] - fn default() -> FlexcanClkdiv { - FlexcanClkdiv(0) + fn default() -> FlexioClksel { + FlexioClksel(0) } } -impl core::fmt::Debug for FlexcanClkdiv { +impl core::fmt::Debug for FlexioClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexcanClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("FlexioClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for FlexcanClkdiv { +impl defmt::Format for FlexioClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "FlexcanClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "FlexioClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "FLEXCAN0 clock selection control."] +#[doc = "FLEXSPI0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexcanClksel(pub u32); -impl FlexcanClksel { +pub struct FlexspiClksel(pub u32); +impl FlexspiClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> FlexcanClkselMux { + pub const fn mux(&self) -> FlexspiClkselMux { let val = (self.0 >> 0usize) & 0x07; - FlexcanClkselMux::from_bits(val as u8) + FlexspiClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: FlexcanClkselMux) { + pub const fn set_mux(&mut self, val: FlexspiClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for FlexcanClksel { +impl Default for FlexspiClksel { #[inline(always)] - fn default() -> FlexcanClksel { - FlexcanClksel(0) + fn default() -> FlexspiClksel { + FlexspiClksel(0) } } -impl core::fmt::Debug for FlexcanClksel { +impl core::fmt::Debug for FlexspiClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexcanClksel") + f.debug_struct("FlexspiClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for FlexcanClksel { +impl defmt::Format for FlexspiClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexcanClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "FlexspiClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "FLEXIO0 clock divider control."] +#[doc = "Control Automatic Clock Gating 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexioClkdiv(pub u32); -impl FlexioClkdiv { - #[doc = "Functional Clock Divider."] +pub struct GlbAcc0(pub u32); +impl GlbAcc0 { + #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub const fn inputmux0(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Functional Clock Divider."] + #[doc = "INPUTMUX0."] #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn set_inputmux0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for FlexioClkdiv { - #[inline(always)] - fn default() -> FlexioClkdiv { - FlexioClkdiv(0) - } -} -impl core::fmt::Debug for FlexioClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexioClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexioClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "FlexioClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "FLEXIO0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexioClksel(pub u32); -impl FlexioClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FlexioClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FlexioClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FlexioClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for FlexioClksel { - #[inline(always)] - fn default() -> FlexioClksel { - FlexioClksel(0) - } -} -impl core::fmt::Debug for FlexioClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexioClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexioClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexioClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "FLEXSPI0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexspiClkdiv(pub u32); -impl FlexspiClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for FlexspiClkdiv { - #[inline(always)] - fn default() -> FlexspiClkdiv { - FlexspiClkdiv(0) - } -} -impl core::fmt::Debug for FlexspiClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexspiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexspiClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "FlexspiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "FLEXSPI0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct FlexspiClksel(pub u32); -impl FlexspiClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FlexspiClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FlexspiClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FlexspiClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for FlexspiClksel { - #[inline(always)] - fn default() -> FlexspiClksel { - FlexspiClksel(0) - } -} -impl core::fmt::Debug for FlexspiClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("FlexspiClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for FlexspiClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "FlexspiClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "AHB Clock Control Clear 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbCcClr(pub u32); -impl GlbCcClr { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbCcClr { - #[inline(always)] - fn default() -> GlbCcClr { - GlbCcClr(0) - } -} -impl core::fmt::Debug for GlbCcClr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbCcClr") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbCcClr { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbCcClr {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "AHB Clock Control Set 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbCcSet(pub u32); -impl GlbCcSet { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbCcSet { - #[inline(always)] - fn default() -> GlbCcSet { - GlbCcSet(0) - } -} -impl core::fmt::Debug for GlbCcSet { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbCcSet") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbCcSet { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbCcSet {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "Peripheral Reset Control Clear 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbRstClr(pub u32); -impl GlbRstClr { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbRstClr { - #[inline(always)] - fn default() -> GlbRstClr { - GlbRstClr(0) - } -} -impl core::fmt::Debug for GlbRstClr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbRstClr") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbRstClr { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbRstClr {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "Peripheral Reset Control Set 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct GlbRstSet(pub u32); -impl GlbRstSet { - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[must_use] - #[inline(always)] - pub const fn data(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 - } - #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] - #[inline(always)] - pub const fn set_data(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); - } -} -impl Default for GlbRstSet { - #[inline(always)] - fn default() -> GlbRstSet { - GlbRstSet(0) - } -} -impl core::fmt::Debug for GlbRstSet { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GlbRstSet") - .field("data", &self.data()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for GlbRstSet { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "GlbRstSet {{ data: {=u32:?} }}", self.data()) - } -} -#[doc = "I3C0_FCLK clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I3cFclkClkdiv(pub u32); -impl I3cFclkClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for I3cFclkClkdiv { - #[inline(always)] - fn default() -> I3cFclkClkdiv { - I3cFclkClkdiv(0) - } -} -impl core::fmt::Debug for I3cFclkClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I3cFclkClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for I3cFclkClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "I3cFclkClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "I3C0_FCLK clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct I3cFclkClksel(pub u32); -impl I3cFclkClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> FclkClkselMux { - let val = (self.0 >> 0usize) & 0x07; - FclkClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: FclkClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for I3cFclkClksel { - #[inline(always)] - fn default() -> I3cFclkClksel { - I3cFclkClksel(0) - } -} -impl core::fmt::Debug for I3cFclkClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I3cFclkClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for I3cFclkClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "I3cFclkClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPI2C0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Lpi2cClkdiv(pub u32); -impl Lpi2cClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for Lpi2cClkdiv { - #[inline(always)] - fn default() -> Lpi2cClkdiv { - Lpi2cClkdiv(0) - } -} -impl core::fmt::Debug for Lpi2cClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2cClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Lpi2cClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Lpi2cClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPI2C0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Lpi2cClksel(pub u32); -impl Lpi2cClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> Lpi2cClkselMux { - let val = (self.0 >> 0usize) & 0x07; - Lpi2cClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: Lpi2cClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for Lpi2cClksel { - #[inline(always)] - fn default() -> Lpi2cClksel { - Lpi2cClksel(0) - } -} -impl core::fmt::Debug for Lpi2cClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Lpi2cClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Lpi2cClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Lpi2cClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPSPI0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpspiClkdiv(pub u32); -impl LpspiClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LpspiClkdiv { - #[inline(always)] - fn default() -> LpspiClkdiv { - LpspiClkdiv(0) - } -} -impl core::fmt::Debug for LpspiClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpspiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpspiClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LpspiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPSPI0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpspiClksel(pub u32); -impl LpspiClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LpspiClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LpspiClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LpspiClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LpspiClksel { - #[inline(always)] - fn default() -> LpspiClksel { - LpspiClksel(0) - } -} -impl core::fmt::Debug for LpspiClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpspiClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpspiClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LpspiClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPTMR0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LptmrClkdiv(pub u32); -impl LptmrClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LptmrClkdiv { - #[inline(always)] - fn default() -> LptmrClkdiv { - LptmrClkdiv(0) - } -} -impl core::fmt::Debug for LptmrClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LptmrClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LptmrClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LptmrClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPTMR0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LptmrClksel(pub u32); -impl LptmrClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LptmrClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LptmrClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LptmrClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LptmrClksel { - #[inline(always)] - fn default() -> LptmrClksel { - LptmrClksel(0) - } -} -impl core::fmt::Debug for LptmrClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LptmrClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LptmrClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LptmrClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "LPUART0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpuartClkdiv(pub u32); -impl LpuartClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for LpuartClkdiv { - #[inline(always)] - fn default() -> LpuartClkdiv { - LpuartClkdiv(0) - } -} -impl core::fmt::Debug for LpuartClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpuartClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpuartClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "LpuartClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "LPUART0 clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct LpuartClksel(pub u32); -impl LpuartClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> LpuartClkselMux { - let val = (self.0 >> 0usize) & 0x07; - LpuartClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: LpuartClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for LpuartClksel { - #[inline(always)] - fn default() -> LpuartClksel { - LpuartClksel(0) - } -} -impl core::fmt::Debug for LpuartClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("LpuartClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for LpuartClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "LpuartClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "ADCx clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccAdcClkdiv(pub u32); -impl MrccAdcClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for MrccAdcClkdiv { - #[inline(always)] - fn default() -> MrccAdcClkdiv { - MrccAdcClkdiv(0) - } -} -impl core::fmt::Debug for MrccAdcClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccAdcClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccAdcClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccAdcClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "ADCx clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccAdcClksel(pub u32); -impl MrccAdcClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> AdcClkselMux { - let val = (self.0 >> 0usize) & 0x07; - AdcClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: AdcClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for MrccAdcClksel { - #[inline(always)] - fn default() -> MrccAdcClksel { - MrccAdcClksel(0) - } -} -impl core::fmt::Debug for MrccAdcClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccAdcClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccAdcClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccAdcClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "CLKOUT clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccClkoutClkdiv(pub u32); -impl MrccClkoutClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for MrccClkoutClkdiv { - #[inline(always)] - fn default() -> MrccClkoutClkdiv { - MrccClkoutClkdiv(0) - } -} -impl core::fmt::Debug for MrccClkoutClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccClkoutClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccClkoutClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccClkoutClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "CLKOUT clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccClkoutClksel(pub u32); -impl MrccClkoutClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> ClkoutClkselMux { - let val = (self.0 >> 0usize) & 0x07; - ClkoutClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: ClkoutClkselMux) { - self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); - } -} -impl Default for MrccClkoutClksel { - #[inline(always)] - fn default() -> MrccClkoutClksel { - MrccClkoutClksel(0) - } -} -impl core::fmt::Debug for MrccClkoutClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccClkoutClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccClkoutClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccClkoutClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "DBG_TRACE clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccDbgTraceClkdiv(pub u32); -impl MrccDbgTraceClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for MrccDbgTraceClkdiv { - #[inline(always)] - fn default() -> MrccDbgTraceClkdiv { - MrccDbgTraceClkdiv(0) - } -} -impl core::fmt::Debug for MrccDbgTraceClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccDbgTraceClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccDbgTraceClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccDbgTraceClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} -#[doc = "DBG_TRACE clock selection control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccDbgTraceClksel(pub u32); -impl MrccDbgTraceClksel { - #[doc = "Functional Clock Mux Select."] - #[must_use] - #[inline(always)] - pub const fn mux(&self) -> DbgTraceClkselMux { - let val = (self.0 >> 0usize) & 0x03; - DbgTraceClkselMux::from_bits(val as u8) - } - #[doc = "Functional Clock Mux Select."] - #[inline(always)] - pub const fn set_mux(&mut self, val: DbgTraceClkselMux) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); - } -} -impl Default for MrccDbgTraceClksel { - #[inline(always)] - fn default() -> MrccDbgTraceClksel { - MrccDbgTraceClksel(0) - } -} -impl core::fmt::Debug for MrccDbgTraceClksel { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccDbgTraceClksel") - .field("mux", &self.mux()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for MrccDbgTraceClksel { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccDbgTraceClksel {{ mux: {:?} }}", self.mux()) - } -} -#[doc = "Control Automatic Clock Gating 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc0(pub u32); -impl MrccGlbAcc0 { - #[doc = "INPUTMUX0."] - #[must_use] - #[inline(always)] - pub const fn inputmux0(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "INPUTMUX0."] - #[inline(always)] - pub const fn set_inputmux0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "FREQME."] + #[doc = "FREQME."] #[must_use] #[inline(always)] pub const fn freqme(&self) -> bool { @@ -3441,15 +1749,15 @@ impl MrccGlbAcc0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbAcc0 { +impl Default for GlbAcc0 { #[inline(always)] - fn default() -> MrccGlbAcc0 { - MrccGlbAcc0(0) + fn default() -> GlbAcc0 { + GlbAcc0(0) } } -impl core::fmt::Debug for MrccGlbAcc0 { +impl core::fmt::Debug for GlbAcc0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc0") + f.debug_struct("GlbAcc0") .field("inputmux0", &self.inputmux0()) .field("freqme", &self.freqme()) .field("ctimer0", &self.ctimer0()) @@ -3483,11 +1791,11 @@ impl core::fmt::Debug for MrccGlbAcc0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc0 { +impl defmt::Format for GlbAcc0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", + "GlbAcc0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", self.inputmux0(), self.freqme(), self.ctimer0(), @@ -3523,8 +1831,8 @@ impl defmt::Format for MrccGlbAcc0 { #[doc = "Control Automatic Clock Gating 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc1(pub u32); -impl MrccGlbAcc1 { +pub struct GlbAcc1(pub u32); +impl GlbAcc1 { #[doc = "LPSPI0."] #[must_use] #[inline(always)] @@ -3742,15 +2050,15 @@ impl MrccGlbAcc1 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbAcc1 { +impl Default for GlbAcc1 { #[inline(always)] - fn default() -> MrccGlbAcc1 { - MrccGlbAcc1(0) + fn default() -> GlbAcc1 { + GlbAcc1(0) } } -impl core::fmt::Debug for MrccGlbAcc1 { +impl core::fmt::Debug for GlbAcc1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc1") + f.debug_struct("GlbAcc1") .field("lpspi0", &self.lpspi0()) .field("lpspi1", &self.lpspi1()) .field("lpspi2", &self.lpspi2()) @@ -3773,11 +2081,11 @@ impl core::fmt::Debug for MrccGlbAcc1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc1 { +impl defmt::Format for GlbAcc1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", + "GlbAcc1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", self.lpspi0(), self.lpspi1(), self.lpspi2(), @@ -3802,8 +2110,8 @@ impl defmt::Format for MrccGlbAcc1 { #[doc = "Control Automatic Clock Gating 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc2(pub u32); -impl MrccGlbAcc2 { +pub struct GlbAcc2(pub u32); +impl GlbAcc2 { #[doc = "I3C0."] #[must_use] #[inline(always)] @@ -3997,15 +2305,15 @@ impl MrccGlbAcc2 { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } } -impl Default for MrccGlbAcc2 { +impl Default for GlbAcc2 { #[inline(always)] - fn default() -> MrccGlbAcc2 { - MrccGlbAcc2(0) + fn default() -> GlbAcc2 { + GlbAcc2(0) } } -impl core::fmt::Debug for MrccGlbAcc2 { +impl core::fmt::Debug for GlbAcc2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc2") + f.debug_struct("GlbAcc2") .field("i3c0", &self.i3c0()) .field("i3c1", &self.i3c1()) .field("i3c2", &self.i3c2()) @@ -4026,11 +2334,11 @@ impl core::fmt::Debug for MrccGlbAcc2 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc2 { +impl defmt::Format for GlbAcc2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", + "GlbAcc2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", self.i3c0(), self.i3c1(), self.i3c2(), @@ -4053,8 +2361,8 @@ impl defmt::Format for MrccGlbAcc2 { #[doc = "Control Automatic Clock Gating 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc3(pub u32); -impl MrccGlbAcc3 { +pub struct GlbAcc3(pub u32); +impl GlbAcc3 { #[doc = "RAMA."] #[must_use] #[inline(always)] @@ -4164,15 +2472,15 @@ impl MrccGlbAcc3 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbAcc3 { +impl Default for GlbAcc3 { #[inline(always)] - fn default() -> MrccGlbAcc3 { - MrccGlbAcc3(0) + fn default() -> GlbAcc3 { + GlbAcc3(0) } } -impl core::fmt::Debug for MrccGlbAcc3 { +impl core::fmt::Debug for GlbAcc3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc3") + f.debug_struct("GlbAcc3") .field("rama", &self.rama()) .field("ramb", &self.ramb()) .field("gpio0", &self.gpio0()) @@ -4186,11 +2494,11 @@ impl core::fmt::Debug for MrccGlbAcc3 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc3 { +impl defmt::Format for GlbAcc3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc3 {{ rama: {=bool:?}, ramb: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, romc: {=bool:?}, smartdma0: {=bool:?} }}", + "GlbAcc3 {{ rama: {=bool:?}, ramb: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, romc: {=bool:?}, smartdma0: {=bool:?} }}", self.rama(), self.ramb(), self.gpio0(), @@ -4206,8 +2514,8 @@ impl defmt::Format for MrccGlbAcc3 { #[doc = "Control Automatic Clock Gating 4."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbAcc4(pub u32); -impl MrccGlbAcc4 { +pub struct GlbAcc4(pub u32); +impl GlbAcc4 { #[doc = "SECCON."] #[must_use] #[inline(always)] @@ -4305,15 +2613,15 @@ impl MrccGlbAcc4 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbAcc4 { +impl Default for GlbAcc4 { #[inline(always)] - fn default() -> MrccGlbAcc4 { - MrccGlbAcc4(0) + fn default() -> GlbAcc4 { + GlbAcc4(0) } } -impl core::fmt::Debug for MrccGlbAcc4 { +impl core::fmt::Debug for GlbAcc4 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbAcc4") + f.debug_struct("GlbAcc4") .field("seccon", &self.seccon()) .field("glikey0", &self.glikey0()) .field("pkc0", &self.pkc0()) @@ -4326,11 +2634,11 @@ impl core::fmt::Debug for MrccGlbAcc4 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbAcc4 { +impl defmt::Format for GlbAcc4 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbAcc4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, atx0: {=bool:?} }}", + "GlbAcc4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, atx0: {=bool:?} }}", self.seccon(), self.glikey0(), self.pkc0(), @@ -4345,8 +2653,8 @@ impl defmt::Format for MrccGlbAcc4 { #[doc = "AHB Clock Control 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc0(pub u32); -impl MrccGlbCc0 { +pub struct GlbCc0(pub u32); +impl GlbCc0 { #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] @@ -4696,15 +3004,15 @@ impl MrccGlbCc0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbCc0 { +impl Default for GlbCc0 { #[inline(always)] - fn default() -> MrccGlbCc0 { - MrccGlbCc0(0) + fn default() -> GlbCc0 { + GlbCc0(0) } } -impl core::fmt::Debug for MrccGlbCc0 { +impl core::fmt::Debug for GlbCc0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc0") + f.debug_struct("GlbCc0") .field("inputmux0", &self.inputmux0()) .field("freqme", &self.freqme()) .field("ctimer0", &self.ctimer0()) @@ -4738,11 +3046,11 @@ impl core::fmt::Debug for MrccGlbCc0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc0 { +impl defmt::Format for GlbCc0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", + "GlbCc0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", self.inputmux0(), self.freqme(), self.ctimer0(), @@ -4778,8 +3086,8 @@ impl defmt::Format for MrccGlbCc0 { #[doc = "AHB Clock Control 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc1(pub u32); -impl MrccGlbCc1 { +pub struct GlbCc1(pub u32); +impl GlbCc1 { #[doc = "LPSPI0."] #[must_use] #[inline(always)] @@ -5009,15 +3317,15 @@ impl MrccGlbCc1 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbCc1 { +impl Default for GlbCc1 { #[inline(always)] - fn default() -> MrccGlbCc1 { - MrccGlbCc1(0) + fn default() -> GlbCc1 { + GlbCc1(0) } } -impl core::fmt::Debug for MrccGlbCc1 { +impl core::fmt::Debug for GlbCc1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc1") + f.debug_struct("GlbCc1") .field("lpspi0", &self.lpspi0()) .field("lpspi1", &self.lpspi1()) .field("lpspi2", &self.lpspi2()) @@ -5041,11 +3349,11 @@ impl core::fmt::Debug for MrccGlbCc1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc1 { +impl defmt::Format for GlbCc1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, port5: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", + "GlbCc1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, port5: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", self.lpspi0(), self.lpspi1(), self.lpspi2(), @@ -5071,8 +3379,8 @@ impl defmt::Format for MrccGlbCc1 { #[doc = "AHB Clock Control 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc2(pub u32); -impl MrccGlbCc2 { +pub struct GlbCc2(pub u32); +impl GlbCc2 { #[doc = "I3C0."] #[must_use] #[inline(always)] @@ -5266,15 +3574,15 @@ impl MrccGlbCc2 { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } } -impl Default for MrccGlbCc2 { +impl Default for GlbCc2 { #[inline(always)] - fn default() -> MrccGlbCc2 { - MrccGlbCc2(0) + fn default() -> GlbCc2 { + GlbCc2(0) } } -impl core::fmt::Debug for MrccGlbCc2 { +impl core::fmt::Debug for GlbCc2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc2") + f.debug_struct("GlbCc2") .field("i3c0", &self.i3c0()) .field("i3c1", &self.i3c1()) .field("i3c2", &self.i3c2()) @@ -5295,11 +3603,11 @@ impl core::fmt::Debug for MrccGlbCc2 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc2 { +impl defmt::Format for GlbCc2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", + "GlbCc2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", self.i3c0(), self.i3c1(), self.i3c2(), @@ -5322,8 +3630,8 @@ impl defmt::Format for MrccGlbCc2 { #[doc = "AHB Clock Control 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc3(pub u32); -impl MrccGlbCc3 { +pub struct GlbCc3(pub u32); +impl GlbCc3 { #[doc = "RAMA."] #[must_use] #[inline(always)] @@ -5445,15 +3753,15 @@ impl MrccGlbCc3 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbCc3 { +impl Default for GlbCc3 { #[inline(always)] - fn default() -> MrccGlbCc3 { - MrccGlbCc3(0) + fn default() -> GlbCc3 { + GlbCc3(0) } } -impl core::fmt::Debug for MrccGlbCc3 { +impl core::fmt::Debug for GlbCc3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc3") + f.debug_struct("GlbCc3") .field("rama", &self.rama()) .field("ramb", &self.ramb()) .field("gpio0", &self.gpio0()) @@ -5468,11 +3776,11 @@ impl core::fmt::Debug for MrccGlbCc3 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc3 { +impl defmt::Format for GlbCc3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc3 {{ rama: {=bool:?}, ramb: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, gpio5: {=bool:?}, romc: {=bool:?}, smartdma0: {=bool:?} }}", + "GlbCc3 {{ rama: {=bool:?}, ramb: {=bool:?}, gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, gpio5: {=bool:?}, romc: {=bool:?}, smartdma0: {=bool:?} }}", self.rama(), self.ramb(), self.gpio0(), @@ -5489,8 +3797,8 @@ impl defmt::Format for MrccGlbCc3 { #[doc = "AHB Clock Control 4."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbCc4(pub u32); -impl MrccGlbCc4 { +pub struct GlbCc4(pub u32); +impl GlbCc4 { #[doc = "SECCON."] #[must_use] #[inline(always)] @@ -5636,15 +3944,15 @@ impl MrccGlbCc4 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbCc4 { +impl Default for GlbCc4 { #[inline(always)] - fn default() -> MrccGlbCc4 { - MrccGlbCc4(0) + fn default() -> GlbCc4 { + GlbCc4(0) } } -impl core::fmt::Debug for MrccGlbCc4 { +impl core::fmt::Debug for GlbCc4 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbCc4") + f.debug_struct("GlbCc4") .field("seccon", &self.seccon()) .field("glikey0", &self.glikey0()) .field("tdet0", &self.tdet0()) @@ -5661,11 +3969,11 @@ impl core::fmt::Debug for MrccGlbCc4 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbCc4 { +impl defmt::Format for GlbCc4 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbCc4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, itrc0: {=bool:?}, atx0: {=bool:?}, mtr: {=bool:?}, tcu: {=bool:?} }}", + "GlbCc4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, itrc0: {=bool:?}, atx0: {=bool:?}, mtr: {=bool:?}, tcu: {=bool:?} }}", self.seccon(), self.glikey0(), self.tdet0(), @@ -5681,11 +3989,85 @@ impl defmt::Format for MrccGlbCc4 { ) } } +#[doc = "AHB Clock Control Clear 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbCcClr(pub u32); +impl GlbCcClr { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for GlbCcClr { + #[inline(always)] + fn default() -> GlbCcClr { + GlbCcClr(0) + } +} +impl core::fmt::Debug for GlbCcClr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbCcClr") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbCcClr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbCcClr {{ data: {=u32:?} }}", self.data()) + } +} +#[doc = "AHB Clock Control Set 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbCcSet(pub u32); +impl GlbCcSet { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[must_use] + #[inline(always)] + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_CCn."] + #[inline(always)] + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for GlbCcSet { + #[inline(always)] + fn default() -> GlbCcSet { + GlbCcSet(0) + } +} +impl core::fmt::Debug for GlbCcSet { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbCcSet") + .field("data", &self.data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbCcSet { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbCcSet {{ data: {=u32:?} }}", self.data()) + } +} #[doc = "Peripheral Enable Configuration 0. Reset on POR only."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbPr0(pub u32); -impl MrccGlbPr0 { +pub struct GlbPr0(pub u32); +impl GlbPr0 { #[doc = "FREQME."] #[must_use] #[inline(always)] @@ -6023,15 +4405,15 @@ impl MrccGlbPr0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbPr0 { +impl Default for GlbPr0 { #[inline(always)] - fn default() -> MrccGlbPr0 { - MrccGlbPr0(0) + fn default() -> GlbPr0 { + GlbPr0(0) } } -impl core::fmt::Debug for MrccGlbPr0 { +impl core::fmt::Debug for GlbPr0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbPr0") + f.debug_struct("GlbPr0") .field("freqme", &self.freqme()) .field("ctimer0", &self.ctimer0()) .field("ctimer1", &self.ctimer1()) @@ -6064,11 +4446,11 @@ impl core::fmt::Debug for MrccGlbPr0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbPr0 { +impl defmt::Format for GlbPr0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbPr0 {{ freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", + "GlbPr0 {{ freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", self.freqme(), self.ctimer0(), self.ctimer1(), @@ -6103,8 +4485,8 @@ impl defmt::Format for MrccGlbPr0 { #[doc = "Peripheral Enable Configuration 1. Reset on POR only."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbPr1(pub u32); -impl MrccGlbPr1 { +pub struct GlbPr1(pub u32); +impl GlbPr1 { #[doc = "LPSPI0."] #[must_use] #[inline(always)] @@ -6334,15 +4716,15 @@ impl MrccGlbPr1 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbPr1 { +impl Default for GlbPr1 { #[inline(always)] - fn default() -> MrccGlbPr1 { - MrccGlbPr1(0) + fn default() -> GlbPr1 { + GlbPr1(0) } } -impl core::fmt::Debug for MrccGlbPr1 { +impl core::fmt::Debug for GlbPr1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbPr1") + f.debug_struct("GlbPr1") .field("lpspi0", &self.lpspi0()) .field("lpspi1", &self.lpspi1()) .field("lpspi2", &self.lpspi2()) @@ -6366,11 +4748,11 @@ impl core::fmt::Debug for MrccGlbPr1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbPr1 { +impl defmt::Format for GlbPr1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbPr1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, port5: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", + "GlbPr1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, port5: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, cmp0: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?}, tsi0: {=bool:?} }}", self.lpspi0(), self.lpspi1(), self.lpspi2(), @@ -6396,8 +4778,8 @@ impl defmt::Format for MrccGlbPr1 { #[doc = "Peripheral Enable Configuration 2. Reset on POR only."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbPr2(pub u32); -impl MrccGlbPr2 { +pub struct GlbPr2(pub u32); +impl GlbPr2 { #[doc = "I3C0."] #[must_use] #[inline(always)] @@ -6591,15 +4973,15 @@ impl MrccGlbPr2 { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } } -impl Default for MrccGlbPr2 { +impl Default for GlbPr2 { #[inline(always)] - fn default() -> MrccGlbPr2 { - MrccGlbPr2(0) + fn default() -> GlbPr2 { + GlbPr2(0) } } -impl core::fmt::Debug for MrccGlbPr2 { +impl core::fmt::Debug for GlbPr2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbPr2") + f.debug_struct("GlbPr2") .field("i3c0", &self.i3c0()) .field("i3c1", &self.i3c1()) .field("i3c2", &self.i3c2()) @@ -6620,11 +5002,11 @@ impl core::fmt::Debug for MrccGlbPr2 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbPr2 { +impl defmt::Format for GlbPr2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbPr2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", + "GlbPr2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, e1588: {=bool:?}, rmii: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", self.i3c0(), self.i3c1(), self.i3c2(), @@ -6647,8 +5029,8 @@ impl defmt::Format for MrccGlbPr2 { #[doc = "Peripheral Enable Configuration 3. Reset on POR only."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbPr3(pub u32); -impl MrccGlbPr3 { +pub struct GlbPr3(pub u32); +impl GlbPr3 { #[doc = "GPIO0."] #[must_use] #[inline(always)] @@ -6734,15 +5116,15 @@ impl MrccGlbPr3 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbPr3 { +impl Default for GlbPr3 { #[inline(always)] - fn default() -> MrccGlbPr3 { - MrccGlbPr3(0) + fn default() -> GlbPr3 { + GlbPr3(0) } } -impl core::fmt::Debug for MrccGlbPr3 { +impl core::fmt::Debug for GlbPr3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbPr3") + f.debug_struct("GlbPr3") .field("gpio0", &self.gpio0()) .field("gpio1", &self.gpio1()) .field("gpio2", &self.gpio2()) @@ -6754,11 +5136,11 @@ impl core::fmt::Debug for MrccGlbPr3 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbPr3 { +impl defmt::Format for GlbPr3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbPr3 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, gpio5: {=bool:?}, smartdma0: {=bool:?} }}", + "GlbPr3 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, gpio5: {=bool:?}, smartdma0: {=bool:?} }}", self.gpio0(), self.gpio1(), self.gpio2(), @@ -6772,8 +5154,8 @@ impl defmt::Format for MrccGlbPr3 { #[doc = "Peripheral Enable Configuration 4. Reset on POR only."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbPr4(pub u32); -impl MrccGlbPr4 { +pub struct GlbPr4(pub u32); +impl GlbPr4 { #[doc = "SECCON."] #[must_use] #[inline(always)] @@ -6919,15 +5301,15 @@ impl MrccGlbPr4 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbPr4 { +impl Default for GlbPr4 { #[inline(always)] - fn default() -> MrccGlbPr4 { - MrccGlbPr4(0) + fn default() -> GlbPr4 { + GlbPr4(0) } } -impl core::fmt::Debug for MrccGlbPr4 { +impl core::fmt::Debug for GlbPr4 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbPr4") + f.debug_struct("GlbPr4") .field("seccon", &self.seccon()) .field("glikey0", &self.glikey0()) .field("tdet0", &self.tdet0()) @@ -6944,11 +5326,11 @@ impl core::fmt::Debug for MrccGlbPr4 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbPr4 { +impl defmt::Format for GlbPr4 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbPr4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, itrc0: {=bool:?}, atx0: {=bool:?}, mtr: {=bool:?}, tcu: {=bool:?} }}", + "GlbPr4 {{ seccon: {=bool:?}, glikey0: {=bool:?}, tdet0: {=bool:?}, pkc0: {=bool:?}, sgi0: {=bool:?}, trng0: {=bool:?}, udf0: {=bool:?}, dgdet0: {=bool:?}, itrc0: {=bool:?}, atx0: {=bool:?}, mtr: {=bool:?}, tcu: {=bool:?} }}", self.seccon(), self.glikey0(), self.tdet0(), @@ -6967,8 +5349,8 @@ impl defmt::Format for MrccGlbPr4 { #[doc = "Peripheral Reset Control 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst0(pub u32); -impl MrccGlbRst0 { +pub struct GlbRst0(pub u32); +impl GlbRst0 { #[doc = "INPUTMUX0."] #[must_use] #[inline(always)] @@ -7294,15 +5676,15 @@ impl MrccGlbRst0 { self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for MrccGlbRst0 { +impl Default for GlbRst0 { #[inline(always)] - fn default() -> MrccGlbRst0 { - MrccGlbRst0(0) + fn default() -> GlbRst0 { + GlbRst0(0) } } -impl core::fmt::Debug for MrccGlbRst0 { +impl core::fmt::Debug for GlbRst0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst0") + f.debug_struct("GlbRst0") .field("inputmux0", &self.inputmux0()) .field("freqme", &self.freqme()) .field("ctimer0", &self.ctimer0()) @@ -7334,11 +5716,11 @@ impl core::fmt::Debug for MrccGlbRst0 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst0 { +impl defmt::Format for GlbRst0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", + "GlbRst0 {{ inputmux0: {=bool:?}, freqme: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, utick0: {=bool:?}, dma0: {=bool:?}, dma1: {=bool:?}, aoi0: {=bool:?}, crc0: {=bool:?}, eim0: {=bool:?}, erm0: {=bool:?}, flexio0: {=bool:?}, lpi2c0: {=bool:?}, lpi2c1: {=bool:?}, lpi2c2: {=bool:?}, lpi2c3: {=bool:?}, lpi2c4: {=bool:?}, lpuart0: {=bool:?}, lpuart1: {=bool:?}, lpuart2: {=bool:?}, lpuart3: {=bool:?}, lpuart4: {=bool:?}, lpuart5: {=bool:?}, ostimer0: {=bool:?} }}", self.inputmux0(), self.freqme(), self.ctimer0(), @@ -7372,8 +5754,8 @@ impl defmt::Format for MrccGlbRst0 { #[doc = "Peripheral Reset Control 1."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst1(pub u32); -impl MrccGlbRst1 { +pub struct GlbRst1(pub u32); +impl GlbRst1 { #[doc = "LPSPI0."] #[must_use] #[inline(always)] @@ -7567,15 +5949,15 @@ impl MrccGlbRst1 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbRst1 { +impl Default for GlbRst1 { #[inline(always)] - fn default() -> MrccGlbRst1 { - MrccGlbRst1(0) + fn default() -> GlbRst1 { + GlbRst1(0) } } -impl core::fmt::Debug for MrccGlbRst1 { +impl core::fmt::Debug for GlbRst1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst1") + f.debug_struct("GlbRst1") .field("lpspi0", &self.lpspi0()) .field("lpspi1", &self.lpspi1()) .field("lpspi2", &self.lpspi2()) @@ -7596,11 +5978,11 @@ impl core::fmt::Debug for MrccGlbRst1 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst1 { +impl defmt::Format for GlbRst1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?} }}", + "GlbRst1 {{ lpspi0: {=bool:?}, lpspi1: {=bool:?}, lpspi2: {=bool:?}, lpspi3: {=bool:?}, lpspi4: {=bool:?}, lpspi5: {=bool:?}, port0: {=bool:?}, port1: {=bool:?}, port2: {=bool:?}, port3: {=bool:?}, port4: {=bool:?}, adc0: {=bool:?}, adc1: {=bool:?}, dac0: {=bool:?}, dac1: {=bool:?}, vref0: {=bool:?} }}", self.lpspi0(), self.lpspi1(), self.lpspi2(), @@ -7623,8 +6005,8 @@ impl defmt::Format for MrccGlbRst1 { #[doc = "Peripheral Reset Control 2."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst2(pub u32); -impl MrccGlbRst2 { +pub struct GlbRst2(pub u32); +impl GlbRst2 { #[doc = "I3C0."] #[must_use] #[inline(always)] @@ -7794,15 +6176,15 @@ impl MrccGlbRst2 { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } } -impl Default for MrccGlbRst2 { +impl Default for GlbRst2 { #[inline(always)] - fn default() -> MrccGlbRst2 { - MrccGlbRst2(0) + fn default() -> GlbRst2 { + GlbRst2(0) } } -impl core::fmt::Debug for MrccGlbRst2 { +impl core::fmt::Debug for GlbRst2 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst2") + f.debug_struct("GlbRst2") .field("i3c0", &self.i3c0()) .field("i3c1", &self.i3c1()) .field("i3c2", &self.i3c2()) @@ -7821,11 +6203,11 @@ impl core::fmt::Debug for MrccGlbRst2 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst2 { +impl defmt::Format for GlbRst2 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", + "GlbRst2 {{ i3c0: {=bool:?}, i3c1: {=bool:?}, i3c2: {=bool:?}, i3c3: {=bool:?}, flexcan0: {=bool:?}, flexcan1: {=bool:?}, enet0: {=bool:?}, t1s0: {=bool:?}, flexspi0: {=bool:?}, spi0_filter: {=bool:?}, espi0: {=bool:?}, usb1: {=bool:?}, usb1_phy: {=bool:?}, ewm0: {=bool:?} }}", self.i3c0(), self.i3c1(), self.i3c2(), @@ -7846,8 +6228,8 @@ impl defmt::Format for MrccGlbRst2 { #[doc = "Peripheral Reset Control 3."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst3(pub u32); -impl MrccGlbRst3 { +pub struct GlbRst3(pub u32); +impl GlbRst3 { #[doc = "GPIO0."] #[must_use] #[inline(always)] @@ -7921,15 +6303,15 @@ impl MrccGlbRst3 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbRst3 { +impl Default for GlbRst3 { #[inline(always)] - fn default() -> MrccGlbRst3 { - MrccGlbRst3(0) + fn default() -> GlbRst3 { + GlbRst3(0) } } -impl core::fmt::Debug for MrccGlbRst3 { +impl core::fmt::Debug for GlbRst3 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst3") + f.debug_struct("GlbRst3") .field("gpio0", &self.gpio0()) .field("gpio1", &self.gpio1()) .field("gpio2", &self.gpio2()) @@ -7940,11 +6322,11 @@ impl core::fmt::Debug for MrccGlbRst3 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst3 { +impl defmt::Format for GlbRst3 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst3 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, smartdma0: {=bool:?} }}", + "GlbRst3 {{ gpio0: {=bool:?}, gpio1: {=bool:?}, gpio2: {=bool:?}, gpio3: {=bool:?}, gpio4: {=bool:?}, smartdma0: {=bool:?} }}", self.gpio0(), self.gpio1(), self.gpio2(), @@ -7957,8 +6339,8 @@ impl defmt::Format for MrccGlbRst3 { #[doc = "Peripheral Reset Control 4."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccGlbRst4(pub u32); -impl MrccGlbRst4 { +pub struct GlbRst4(pub u32); +impl GlbRst4 { #[doc = "GLIKEY0."] #[must_use] #[inline(always)] @@ -8020,15 +6402,15 @@ impl MrccGlbRst4 { self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); } } -impl Default for MrccGlbRst4 { +impl Default for GlbRst4 { #[inline(always)] - fn default() -> MrccGlbRst4 { - MrccGlbRst4(0) + fn default() -> GlbRst4 { + GlbRst4(0) } } -impl core::fmt::Debug for MrccGlbRst4 { +impl core::fmt::Debug for GlbRst4 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccGlbRst4") + f.debug_struct("GlbRst4") .field("glikey0", &self.glikey0()) .field("pkc0", &self.pkc0()) .field("trng0", &self.trng0()) @@ -8038,11 +6420,11 @@ impl core::fmt::Debug for MrccGlbRst4 { } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccGlbRst4 { +impl defmt::Format for GlbRst4 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "MrccGlbRst4 {{ glikey0: {=bool:?}, pkc0: {=bool:?}, trng0: {=bool:?}, dgdet0: {=bool:?}, atx0: {=bool:?} }}", + "GlbRst4 {{ glikey0: {=bool:?}, pkc0: {=bool:?}, trng0: {=bool:?}, dgdet0: {=bool:?}, atx0: {=bool:?} }}", self.glikey0(), self.pkc0(), self.trng0(), @@ -8051,484 +6433,411 @@ impl defmt::Format for MrccGlbRst4 { ) } } -#[doc = "RMII clock divider control."] +#[doc = "Peripheral Reset Control Clear 0."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccRmiiClkdiv(pub u32); -impl MrccRmiiClkdiv { - #[doc = "Functional Clock Divider."] +pub struct GlbRstClr(pub u32); +impl GlbRstClr { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "Reset divider counter."] - #[must_use] + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } - #[doc = "Reset divider counter."] +} +impl Default for GlbRstClr { #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + fn default() -> GlbRstClr { + GlbRstClr(0) } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) +} +impl core::fmt::Debug for GlbRstClr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GlbRstClr") + .field("data", &self.data()) + .finish() } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for GlbRstClr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "GlbRstClr {{ data: {=u32:?} }}", self.data()) } - #[doc = "Divider status flag."] +} +#[doc = "Peripheral Reset Control Set 0."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct GlbRstSet(pub u32); +impl GlbRstSet { + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn data(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "Divider status flag."] + #[doc = "Data array value, refer to corresponding position in MRCC_GLB_RSTn."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_data(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } -impl Default for MrccRmiiClkdiv { +impl Default for GlbRstSet { #[inline(always)] - fn default() -> MrccRmiiClkdiv { - MrccRmiiClkdiv(0) + fn default() -> GlbRstSet { + GlbRstSet(0) } } -impl core::fmt::Debug for MrccRmiiClkdiv { +impl core::fmt::Debug for GlbRstSet { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccRmiiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("GlbRstSet") + .field("data", &self.data()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccRmiiClkdiv { +impl defmt::Format for GlbRstSet { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccRmiiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "GlbRstSet {{ data: {=u32:?} }}", self.data()) } } -#[doc = "RMII clock selection control."] +#[doc = "I3C0_FCLK clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccRmiiClksel(pub u32); -impl MrccRmiiClksel { +pub struct I3cFclkClksel(pub u32); +impl I3cFclkClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> RmiiClkselMux { + pub const fn mux(&self) -> FclkClkselMux { let val = (self.0 >> 0usize) & 0x07; - RmiiClkselMux::from_bits(val as u8) + FclkClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: RmiiClkselMux) { + pub const fn set_mux(&mut self, val: FclkClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccRmiiClksel { +impl Default for I3cFclkClksel { #[inline(always)] - fn default() -> MrccRmiiClksel { - MrccRmiiClksel(0) + fn default() -> I3cFclkClksel { + I3cFclkClksel(0) } } -impl core::fmt::Debug for MrccRmiiClksel { +impl core::fmt::Debug for I3cFclkClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccRmiiClksel") + f.debug_struct("I3cFclkClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccRmiiClksel { +impl defmt::Format for I3cFclkClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccRmiiClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "I3cFclkClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "SYSTICK clock divider control."] +#[doc = "LPI2C0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccSystickClkdiv(pub u32); -impl MrccSystickClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] +pub struct Lpi2cClksel(pub u32); +impl Lpi2cClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> Lpi2cClkselMux { + let val = (self.0 >> 0usize) & 0x07; + Lpi2cClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: Lpi2cClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccSystickClkdiv { +impl Default for Lpi2cClksel { #[inline(always)] - fn default() -> MrccSystickClkdiv { - MrccSystickClkdiv(0) + fn default() -> Lpi2cClksel { + Lpi2cClksel(0) } } -impl core::fmt::Debug for MrccSystickClkdiv { +impl core::fmt::Debug for Lpi2cClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccSystickClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("Lpi2cClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccSystickClkdiv { +impl defmt::Format for Lpi2cClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "MrccSystickClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "Lpi2cClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "SYSTICK clock selection control."] +#[doc = "LPSPI0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct MrccSystickClksel(pub u32); -impl MrccSystickClksel { +pub struct LpspiClksel(pub u32); +impl LpspiClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> SystickClkselMux { - let val = (self.0 >> 0usize) & 0x03; - SystickClkselMux::from_bits(val as u8) + pub const fn mux(&self) -> LpspiClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LpspiClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: SystickClkselMux) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_mux(&mut self, val: LpspiClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for MrccSystickClksel { +impl Default for LpspiClksel { #[inline(always)] - fn default() -> MrccSystickClksel { - MrccSystickClksel(0) + fn default() -> LpspiClksel { + LpspiClksel(0) } } -impl core::fmt::Debug for MrccSystickClksel { +impl core::fmt::Debug for LpspiClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("MrccSystickClksel") + f.debug_struct("LpspiClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for MrccSystickClksel { +impl defmt::Format for LpspiClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "MrccSystickClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "LpspiClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "OSTIMER0 clock selection control."] +#[doc = "LPTMR0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct OstimerClksel(pub u32); -impl OstimerClksel { +pub struct LptmrClksel(pub u32); +impl LptmrClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> OstimerClkselMux { - let val = (self.0 >> 0usize) & 0x03; - OstimerClkselMux::from_bits(val as u8) + pub const fn mux(&self) -> LptmrClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LptmrClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: OstimerClkselMux) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_mux(&mut self, val: LptmrClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for OstimerClksel { +impl Default for LptmrClksel { #[inline(always)] - fn default() -> OstimerClksel { - OstimerClksel(0) + fn default() -> LptmrClksel { + LptmrClksel(0) } } -impl core::fmt::Debug for OstimerClksel { +impl core::fmt::Debug for LptmrClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("OstimerClksel") + f.debug_struct("LptmrClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for OstimerClksel { +impl defmt::Format for LptmrClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "OstimerClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "LptmrClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "T1S0 clock divider control."] +#[doc = "LPUART0 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct T1sClkdiv(pub u32); -impl T1sClkdiv { - #[doc = "Functional Clock Divider."] +pub struct LpuartClksel(pub u32); +impl LpuartClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn mux(&self) -> LpuartClkselMux { + let val = (self.0 >> 0usize) & 0x07; + LpuartClkselMux::from_bits(val as u8) } - #[doc = "Reset divider counter."] - #[must_use] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) + pub const fn set_mux(&mut self, val: LpuartClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } - #[doc = "Reset divider counter."] +} +impl Default for LpuartClksel { #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + fn default() -> LpuartClksel { + LpuartClksel(0) } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) +} +impl core::fmt::Debug for LpuartClksel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LpuartClksel") + .field("mux", &self.mux()) + .finish() } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for LpuartClksel { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "LpuartClksel {{ mux: {:?} }}", self.mux()) } - #[doc = "Divider status flag."] +} +#[doc = "OSTIMER0 clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct OstimerClksel(pub u32); +impl OstimerClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> OstimerClkselMux { + let val = (self.0 >> 0usize) & 0x03; + OstimerClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: OstimerClkselMux) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } } -impl Default for T1sClkdiv { +impl Default for OstimerClksel { #[inline(always)] - fn default() -> T1sClkdiv { - T1sClkdiv(0) + fn default() -> OstimerClksel { + OstimerClksel(0) } } -impl core::fmt::Debug for T1sClkdiv { +impl core::fmt::Debug for OstimerClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("T1sClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("OstimerClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for T1sClkdiv { +impl defmt::Format for OstimerClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "T1sClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "OstimerClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "T1S0 clock selection control."] +#[doc = "RMII clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct T1sClksel(pub u32); -impl T1sClksel { +pub struct RmiiClksel(pub u32); +impl RmiiClksel { #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn mux(&self) -> T1sClkselMux { + pub const fn mux(&self) -> RmiiClkselMux { let val = (self.0 >> 0usize) & 0x07; - T1sClkselMux::from_bits(val as u8) + RmiiClkselMux::from_bits(val as u8) } #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_mux(&mut self, val: T1sClkselMux) { + pub const fn set_mux(&mut self, val: RmiiClkselMux) { self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for T1sClksel { +impl Default for RmiiClksel { #[inline(always)] - fn default() -> T1sClksel { - T1sClksel(0) + fn default() -> RmiiClksel { + RmiiClksel(0) } } -impl core::fmt::Debug for T1sClksel { +impl core::fmt::Debug for RmiiClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("T1sClksel") + f.debug_struct("RmiiClksel") .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for T1sClksel { +impl defmt::Format for RmiiClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "T1sClksel {{ mux: {:?} }}", self.mux()) + defmt::write!(f, "RmiiClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "TSI0 clock divider control."] +#[doc = "SYSTICK clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct TsiClkdiv(pub u32); -impl TsiClkdiv { - #[doc = "Functional Clock Divider."] +pub struct SystickClksel(pub u32); +impl SystickClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn mux(&self) -> SystickClkselMux { + let val = (self.0 >> 0usize) & 0x03; + SystickClkselMux::from_bits(val as u8) } - #[doc = "Reset divider counter."] - #[must_use] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) + pub const fn set_mux(&mut self, val: SystickClkselMux) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "Reset divider counter."] +} +impl Default for SystickClksel { #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); + fn default() -> SystickClksel { + SystickClksel(0) } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) +} +impl core::fmt::Debug for SystickClksel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SystickClksel") + .field("mux", &self.mux()) + .finish() } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for SystickClksel { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "SystickClksel {{ mux: {:?} }}", self.mux()) } - #[doc = "Divider status flag."] +} +#[doc = "T1S0 clock selection control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct T1sClksel(pub u32); +impl T1sClksel { + #[doc = "Functional Clock Mux Select."] #[must_use] #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) + pub const fn mux(&self) -> T1sClkselMux { + let val = (self.0 >> 0usize) & 0x07; + T1sClkselMux::from_bits(val as u8) } - #[doc = "Divider status flag."] + #[doc = "Functional Clock Mux Select."] #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_mux(&mut self, val: T1sClkselMux) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.to_bits() as u32) & 0x07) << 0usize); } } -impl Default for TsiClkdiv { +impl Default for T1sClksel { #[inline(always)] - fn default() -> TsiClkdiv { - TsiClkdiv(0) + fn default() -> T1sClksel { + T1sClksel(0) } } -impl core::fmt::Debug for TsiClkdiv { +impl core::fmt::Debug for T1sClksel { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TsiClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) + f.debug_struct("T1sClksel") + .field("mux", &self.mux()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for TsiClkdiv { +impl defmt::Format for T1sClksel { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "TsiClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) + defmt::write!(f, "T1sClksel {{ mux: {:?} }}", self.mux()) } } #[doc = "TSI0 clock selection control."] @@ -8605,89 +6914,6 @@ impl defmt::Format for UsbClksel { defmt::write!(f, "UsbClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "USB1_PHY clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct UsbPhyClkdiv(pub u32); -impl UsbPhyClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for UsbPhyClkdiv { - #[inline(always)] - fn default() -> UsbPhyClkdiv { - UsbPhyClkdiv(0) - } -} -impl core::fmt::Debug for UsbPhyClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UsbPhyClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for UsbPhyClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "UsbPhyClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} #[doc = "USB1_PHY clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -8725,89 +6951,6 @@ impl defmt::Format for UsbPhyClksel { defmt::write!(f, "UsbPhyClksel {{ mux: {:?} }}", self.mux()) } } -#[doc = "WWDT0 clock divider control."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct WwdtClkdiv(pub u32); -impl WwdtClkdiv { - #[doc = "Functional Clock Divider."] - #[must_use] - #[inline(always)] - pub const fn div(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 - } - #[doc = "Functional Clock Divider."] - #[inline(always)] - pub const fn set_div(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); - } - #[doc = "Reset divider counter."] - #[must_use] - #[inline(always)] - pub const fn reset(&self) -> ClkdivReset { - let val = (self.0 >> 29usize) & 0x01; - ClkdivReset::from_bits(val as u8) - } - #[doc = "Reset divider counter."] - #[inline(always)] - pub const fn set_reset(&mut self, val: ClkdivReset) { - self.0 = (self.0 & !(0x01 << 29usize)) | (((val.to_bits() as u32) & 0x01) << 29usize); - } - #[doc = "Halt divider counter."] - #[must_use] - #[inline(always)] - pub const fn halt(&self) -> ClkdivHalt { - let val = (self.0 >> 30usize) & 0x01; - ClkdivHalt::from_bits(val as u8) - } - #[doc = "Halt divider counter."] - #[inline(always)] - pub const fn set_halt(&mut self, val: ClkdivHalt) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "Divider status flag."] - #[must_use] - #[inline(always)] - pub const fn unstab(&self) -> ClkdivUnstab { - let val = (self.0 >> 31usize) & 0x01; - ClkdivUnstab::from_bits(val as u8) - } - #[doc = "Divider status flag."] - #[inline(always)] - pub const fn set_unstab(&mut self, val: ClkdivUnstab) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); - } -} -impl Default for WwdtClkdiv { - #[inline(always)] - fn default() -> WwdtClkdiv { - WwdtClkdiv(0) - } -} -impl core::fmt::Debug for WwdtClkdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WwdtClkdiv") - .field("div", &self.div()) - .field("reset", &self.reset()) - .field("halt", &self.halt()) - .field("unstab", &self.unstab()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for WwdtClkdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "WwdtClkdiv {{ div: {=u8:?}, reset: {:?}, halt: {:?}, unstab: {:?} }}", - self.div(), - self.reset(), - self.halt(), - self.unstab() - ) - } -} #[doc = "WWDT1 clock selection control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -8850,18 +6993,18 @@ impl defmt::Format for WwdtClksel { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AdcClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_SIRC_DIV = 0x0, + I0ClkrootSircDiv = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, - #[doc = "USB_PFD_CLK."] - I4_CLKROOT_USBPFD = 0x04, + I3ClkrootSosc = 0x03, + #[doc = "USB_PLL_CLK."] + I4ClkrootUsbpll = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_1M = 0x05, + I5Clkroot1m = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_SPLL_DIV = 0x06, + I6ClkrootSpllDiv = 0x06, _RESERVED_7 = 0x07, } impl AdcClkselMux { @@ -8891,9 +7034,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivHalt { #[doc = "Divider clock is running."] - ON = 0x0, + On = 0x0, #[doc = "Divider clock is stopped."] - OFF = 0x01, + Off = 0x01, } impl ClkdivHalt { #[inline(always)] @@ -8922,9 +7065,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivReset { #[doc = "Divider isn't reset."] - ON = 0x0, + On = 0x0, #[doc = "Divider is reset."] - OFF = 0x01, + Off = 0x01, } impl ClkdivReset { #[inline(always)] @@ -8953,9 +7096,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkdivUnstab { #[doc = "Divider clock is stable."] - ON = 0x0, + On = 0x0, #[doc = "Clock frequency isn't stable."] - OFF = 0x01, + Off = 0x01, } impl ClkdivUnstab { #[inline(always)] @@ -8984,18 +7127,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClkoutClkselMux { #[doc = "FRO_12M."] - I0_CLKROOT_12M = 0x0, + I0Clkroot12m = 0x0, #[doc = "FRO_HF_DIV."] - I1_CLKROOT_FIRC_DIV = 0x01, + I1ClkrootFircDiv = 0x01, #[doc = "CLK_IN."] - I2_CLKROOT_SOSC = 0x02, + I2ClkrootSosc = 0x02, #[doc = "LP_OSC."] - I3_CLKROOT_LPOSC = 0x03, + I3ClkrootLposc = 0x03, _RESERVED_4 = 0x04, #[doc = "PLL1_CLK_DIV."] - I5_CLKROOT_SPLL_DIV = 0x05, + I5ClkrootSpllDiv = 0x05, #[doc = "SLOW_CLK."] - I6_CLKROOT_SLOW = 0x06, + I6ClkrootSlow = 0x06, _RESERVED_7 = 0x07, } impl ClkoutClkselMux { @@ -9025,18 +7168,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CtimerClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_SIRC_DIV = 0x0, + I0ClkrootSircDiv = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, #[doc = "LP_OSC."] - I4_CLKROOT_LPOSC = 0x04, + I4ClkrootLposc = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_1M = 0x05, + I5Clkroot1m = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_SPLL_DIV = 0x06, + I6ClkrootSpllDiv = 0x06, _RESERVED_7 = 0x07, } impl CtimerClkselMux { @@ -9066,17 +7209,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DacClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl DacClkselMux { @@ -9106,11 +7249,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DbgTraceClkselMux { #[doc = "CPU_CLK."] - I0_CLKROOT_CPU_ALIAS = 0x0, + I0ClkrootCpuAlias = 0x0, #[doc = "CLK_1M."] - I1_CLKROOT_1M = 0x01, + I1Clkroot1m = 0x01, #[doc = "CLK_16K."] - I2_CLKROOT_16K = 0x02, + I2Clkroot16k = 0x02, _RESERVED_3 = 0x03, } impl DbgTraceClkselMux { @@ -9138,22 +7281,22 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum E158clkselMux { +pub enum E158ClkselMux { _RESERVED_0 = 0x0, _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, #[doc = "ENET0_TX_CLK."] - I4_IPP__ENET0__CLK_TX_I = 0x04, + I4IppEnet0ClkTxI = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - I6_CLKROOT_SPLL = 0x06, + I6ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } -impl E158clkselMux { +impl E158ClkselMux { #[inline(always)] - pub const fn from_bits(val: u8) -> E158clkselMux { + pub const fn from_bits(val: u8) -> E158ClkselMux { unsafe { core::mem::transmute(val & 0x07) } } #[inline(always)] @@ -9161,16 +7304,16 @@ impl E158clkselMux { unsafe { core::mem::transmute(self) } } } -impl From for E158clkselMux { +impl From for E158ClkselMux { #[inline(always)] - fn from(val: u8) -> E158clkselMux { - E158clkselMux::from_bits(val) + fn from(val: u8) -> E158ClkselMux { + E158ClkselMux::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: E158clkselMux) -> u8 { - E158clkselMux::to_bits(val) + fn from(val: E158ClkselMux) -> u8 { + E158ClkselMux::to_bits(val) } } #[repr(u8)] @@ -9179,15 +7322,15 @@ impl From for u8 { pub enum EspiClkselMux { _RESERVED_0 = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, #[doc = "USB_PLL_CLK."] - I4_CLKROOT_USBPLL = 0x04, + I4ClkrootUsbpll = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_SPLL_DIV = 0x06, + I6ClkrootSpllDiv = 0x06, _RESERVED_7 = 0x07, } impl EspiClkselMux { @@ -9217,17 +7360,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FclkClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl FclkClkselMux { @@ -9258,16 +7401,16 @@ impl From for u8 { pub enum FlexcanClkselMux { _RESERVED_0 = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FIRC_DIV = 0x02, + I2ClkrootFircDiv = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, #[doc = "USB_PLL_CLK."] - I4_CLKROOT_USBPLL = 0x04, + I4ClkrootUsbpll = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - I6_CLKROOT_SPLL = 0x06, + I6ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } impl FlexcanClkselMux { @@ -9297,17 +7440,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlexioClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FUNC_1 = 0x01, + I1ClkrootFunc1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl FlexioClkselMux { @@ -9338,14 +7481,14 @@ impl From for u8 { pub enum FlexspiClkselMux { _RESERVED_0 = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, #[doc = "USB_PFD_CLK."] - I4_CLKROOT_USBPFD = 0x04, + I4ClkrootUsbpfd = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - I6_CLKROOT_SPLL = 0x06, + I6ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } impl FlexspiClkselMux { @@ -9375,17 +7518,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lpi2cClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl Lpi2cClkselMux { @@ -9415,17 +7558,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpspiClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl LpspiClkselMux { @@ -9455,17 +7598,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LptmrClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl LptmrClkselMux { @@ -9495,18 +7638,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpuartClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_SIRC_DIV = 0x0, + I0ClkrootSircDiv = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FIRC_DIV = 0x02, + I2ClkrootFircDiv = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, #[doc = "LP_OSC."] - I4_CLKROOT_LPOSC = 0x04, + I4ClkrootLposc = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_1M = 0x05, + I5Clkroot1m = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_SPLL_DIV = 0x06, + I6ClkrootSpllDiv = 0x06, _RESERVED_7 = 0x07, } impl LpuartClkselMux { @@ -9536,11 +7679,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum OstimerClkselMux { #[doc = "CLK_16K."] - I0_CLKROOT_16K = 0x0, + I0Clkroot16k = 0x0, #[doc = "CLK_32K."] - I1_CLKROOT_32K = 0x01, + I1Clkroot32k = 0x01, #[doc = "CLK_1M."] - I2_CLKROOT_1M = 0x02, + I2Clkroot1m = 0x02, _RESERVED_3 = 0x03, } impl OstimerClkselMux { @@ -9571,9 +7714,9 @@ impl From for u8 { pub enum PhyClkselMux { _RESERVED_0 = 0x0, #[doc = "FRO_HF_GATED."] - I1_CLKROOT_FIRC_GATED = 0x01, + I1ClkrootFircGated = 0x01, #[doc = "CLK_IN."] - I2_CLKROOT_SOSC = 0x02, + I2ClkrootSosc = 0x02, _RESERVED_3 = 0x03, } impl PhyClkselMux { @@ -9606,11 +7749,11 @@ pub enum RmiiClkselMux { _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - I6_CLKROOT_SPLL = 0x06, + I6ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } impl RmiiClkselMux { @@ -9640,17 +7783,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RrClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl RrClkselMux { @@ -9680,11 +7823,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SystickClkselMux { #[doc = "CPU_CLK."] - I0_CLKROOT_CPU = 0x0, + I0ClkrootCpu = 0x0, #[doc = "CLK_1M."] - I1_CLKROOT_1M = 0x01, + I1Clkroot1m = 0x01, #[doc = "CLK_16K."] - I2_CLKROOT_16K = 0x02, + I2Clkroot16k = 0x02, _RESERVED_3 = 0x03, } impl SystickClkselMux { @@ -9717,11 +7860,11 @@ pub enum T1sClkselMux { _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_SOSC = 0x03, + I3ClkrootSosc = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, #[doc = "PLL1_CLK."] - I6_CLKROOT_SPLL = 0x06, + I6ClkrootSpll = 0x06, _RESERVED_7 = 0x07, } impl T1sClkselMux { @@ -9751,17 +7894,17 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TsiClkselMux { #[doc = "FRO_LF_DIV."] - I0_CLKROOT_FUNC_0 = 0x0, + I0ClkrootFunc0 = 0x0, _RESERVED_1 = 0x01, #[doc = "FRO_HF_DIV."] - I2_CLKROOT_FUNC_2 = 0x02, + I2ClkrootFunc2 = 0x02, #[doc = "CLK_IN."] - I3_CLKROOT_FUNC_3 = 0x03, + I3ClkrootFunc3 = 0x03, _RESERVED_4 = 0x04, #[doc = "CLK_1M."] - I5_CLKROOT_FUNC_5 = 0x05, + I5ClkrootFunc5 = 0x05, #[doc = "PLL1_CLK_DIV."] - I6_CLKROOT_FUNC_6 = 0x06, + I6ClkrootFunc6 = 0x06, _RESERVED_7 = 0x07, } impl TsiClkselMux { @@ -9791,11 +7934,11 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum UsbClkselMux { #[doc = "CLK_32K."] - I0_CLKROOT_32K = 0x0, + I0Clkroot32k = 0x0, #[doc = "CLK_1M."] - I1_CLKROOT_1M = 0x01, + I1Clkroot1m = 0x01, #[doc = "CLK__usbhs0_phy__clk_xtal."] - I2_CLK__USBHS0_PHY__CLK_XTAL = 0x02, + I2ClkUsbhs0PhyClkXtal = 0x02, _RESERVED_3 = 0x03, } impl UsbClkselMux { @@ -9825,13 +7968,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum WwdtClkselMux { #[doc = "CLK_16K."] - I0_CLKROOT_16K = 0x0, + I0Clkroot16k = 0x0, #[doc = "FRO_HF_DIV."] - I1_CLKROOT_FIRC_DIV = 0x01, + I1ClkrootFircDiv = 0x01, #[doc = "CLK_1M."] - I2_CLKROOT_1M = 0x02, + I2Clkroot1m = 0x02, #[doc = "CLK_1M."] - I3_CLKROOT_1M = 0x03, + I3Clkroot1m = 0x03, } impl WwdtClkselMux { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/OSTIMER.rs b/nxp-pac/src/meta_peripherals/mcxa/OSTIMER.rs index b577059..7d1d324 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/OSTIMER.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/OSTIMER.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "OS Event Timer."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Ostimer { @@ -334,18 +335,6 @@ impl OseventCtrl { pub const fn set_match_wr_rdy(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Debug Enable."] - #[must_use] - #[inline(always)] - pub const fn debug_en(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 - } - #[doc = "Debug Enable."] - #[inline(always)] - pub const fn set_debug_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); - } } impl Default for OseventCtrl { #[inline(always)] @@ -359,7 +348,6 @@ impl core::fmt::Debug for OseventCtrl { .field("ostimer_intrflag", &self.ostimer_intrflag()) .field("ostimer_intena", &self.ostimer_intena()) .field("match_wr_rdy", &self.match_wr_rdy()) - .field("debug_en", &self.debug_en()) .finish() } } @@ -368,11 +356,10 @@ impl defmt::Format for OseventCtrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "OseventCtrl {{ ostimer_intrflag: {=bool:?}, ostimer_intena: {=bool:?}, match_wr_rdy: {=bool:?}, debug_en: {=bool:?} }}", + "OseventCtrl {{ ostimer_intrflag: {=bool:?}, ostimer_intena: {=bool:?}, match_wr_rdy: {=bool:?} }}", self.ostimer_intrflag(), self.ostimer_intena(), - self.match_wr_rdy(), - self.debug_en() + self.match_wr_rdy() ) } } diff --git a/nxp-pac/src/meta_peripherals/mcxa/PORT.rs b/nxp-pac/src/meta_peripherals/mcxa/PORT.rs index 7c3685f..b18cd41 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/PORT.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/PORT.rs @@ -1,7 +1,8 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] -#[doc = "PORT."] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] +#[doc = "Port Control."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Port { ptr: *mut u8, @@ -37,16 +38,6 @@ impl Port { pub const fn config(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } } - #[doc = "Calibration 0."] - #[inline(always)] - pub const fn calib0(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x60usize) as _) } - } - #[doc = "Calibration 1."] - #[inline(always)] - pub const fn calib1(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x64usize) as _) } - } #[doc = "Pin Control 0."] #[inline(always)] pub const fn pcr(self, n: usize) -> crate::pac::common::Reg { @@ -56,116 +47,6 @@ impl Port { } } } -#[doc = "Calibration 0."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Calib0(pub u32); -impl Calib0 { - #[doc = "Calibration of NMOS Output Driver."] - #[must_use] - #[inline(always)] - pub const fn ncal(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Calibration of NMOS Output Driver."] - #[inline(always)] - pub const fn set_ncal(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "Calibration of PMOS Output Driver."] - #[must_use] - #[inline(always)] - pub const fn pcal(&self) -> u8 { - let val = (self.0 >> 16usize) & 0x3f; - val as u8 - } - #[doc = "Calibration of PMOS Output Driver."] - #[inline(always)] - pub const fn set_pcal(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize); - } -} -impl Default for Calib0 { - #[inline(always)] - fn default() -> Calib0 { - Calib0(0) - } -} -impl core::fmt::Debug for Calib0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Calib0") - .field("ncal", &self.ncal()) - .field("pcal", &self.pcal()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Calib0 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Calib0 {{ ncal: {=u8:?}, pcal: {=u8:?} }}", - self.ncal(), - self.pcal() - ) - } -} -#[doc = "Calibration 1."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Calib1(pub u32); -impl Calib1 { - #[doc = "Calibration of NMOS Output Driver."] - #[must_use] - #[inline(always)] - pub const fn ncal(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 - } - #[doc = "Calibration of NMOS Output Driver."] - #[inline(always)] - pub const fn set_ncal(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); - } - #[doc = "Calibration of PMOS Output Driver."] - #[must_use] - #[inline(always)] - pub const fn pcal(&self) -> u8 { - let val = (self.0 >> 16usize) & 0x3f; - val as u8 - } - #[doc = "Calibration of PMOS Output Driver."] - #[inline(always)] - pub const fn set_pcal(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 16usize)) | (((val as u32) & 0x3f) << 16usize); - } -} -impl Default for Calib1 { - #[inline(always)] - fn default() -> Calib1 { - Calib1(0) - } -} -impl core::fmt::Debug for Calib1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Calib1") - .field("ncal", &self.ncal()) - .field("pcal", &self.pcal()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Calib1 { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Calib1 {{ ncal: {=u8:?}, pcal: {=u8:?} }}", - self.ncal(), - self.pcal() - ) - } -} #[doc = "Configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -608,9 +489,9 @@ impl defmt::Format for Verid { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Dse { #[doc = "Low."] - DSE0 = 0x0, + Dse0 = 0x0, #[doc = "High."] - DSE1 = 0x01, + Dse1 = 0x01, } impl Dse { #[inline(always)] @@ -639,7 +520,7 @@ impl From for u8 { pub struct Feature(u16); impl Feature { #[doc = "Basic implementation."] - pub const FEATURE0: Self = Self(0x0); + pub const Feature0: Self = Self(0x0); } impl Feature { pub const fn from_bits(val: u16) -> Feature { @@ -652,7 +533,7 @@ impl Feature { impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("FEATURE0"), + 0x0 => f.write_str("Feature0"), other => core::write!(f, "0x{:02X}", other), } } @@ -661,7 +542,7 @@ impl core::fmt::Debug for Feature { impl defmt::Format for Feature { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "FEATURE0"), + 0x0 => defmt::write!(f, "Feature0"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -683,9 +564,9 @@ impl From for u16 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Gpwe { #[doc = "Not updated."] - GPWE0 = 0x0, + Gpwe0 = 0x0, #[doc = "Updated."] - GPWE1 = 0x01, + Gpwe1 = 0x01, } impl Gpwe { #[inline(always)] @@ -714,9 +595,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ibe { #[doc = "Disables."] - IBE0 = 0x0, + Ibe0 = 0x0, #[doc = "Enables."] - IBE1 = 0x01, + Ibe1 = 0x01, } impl Ibe { #[inline(always)] @@ -745,9 +626,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Inv { #[doc = "Does not invert."] - INV0 = 0x0, + Inv0 = 0x0, #[doc = "Inverts."] - INV1 = 0x01, + Inv1 = 0x01, } impl Inv { #[inline(always)] @@ -776,9 +657,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lk { #[doc = "Does not lock."] - LK0 = 0x0, + Lk0 = 0x0, #[doc = "Locks."] - LK1 = 0x01, + Lk1 = 0x01, } impl Lk { #[inline(always)] @@ -806,20 +687,20 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Mux { - MUX0 = 0x0, - MUX1 = 0x01, - MUX2 = 0x02, - MUX3 = 0x03, - MUX4 = 0x04, - MUX5 = 0x05, - MUX6 = 0x06, - MUX7 = 0x07, - MUX8 = 0x08, - MUX9 = 0x09, - MUX10 = 0x0a, - MUX11 = 0x0b, - MUX12 = 0x0c, - MUX13 = 0x0d, + Mux0 = 0x0, + Mux1 = 0x01, + Mux2 = 0x02, + Mux3 = 0x03, + Mux4 = 0x04, + Mux5 = 0x05, + Mux6 = 0x06, + Mux7 = 0x07, + Mux8 = 0x08, + Mux9 = 0x09, + Mux10 = 0x0a, + Mux11 = 0x0b, + Mux12 = 0x0c, + Mux13 = 0x0d, _RESERVED_e = 0x0e, _RESERVED_f = 0x0f, } @@ -850,9 +731,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ode { #[doc = "Disables."] - ODE0 = 0x0, + Ode0 = 0x0, #[doc = "Enables."] - ODE1 = 0x01, + Ode1 = 0x01, } impl Ode { #[inline(always)] @@ -881,9 +762,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pe { #[doc = "Disables."] - PE0 = 0x0, + Pe0 = 0x0, #[doc = "Enables."] - PE1 = 0x01, + Pe1 = 0x01, } impl Pe { #[inline(always)] @@ -912,9 +793,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Ps { #[doc = "Enables internal pulldown resistor."] - PS0 = 0x0, + Ps0 = 0x0, #[doc = "Enables internal pullup resistor."] - PS1 = 0x01, + Ps1 = 0x01, } impl Ps { #[inline(always)] @@ -943,9 +824,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Range { #[doc = "1.71 V-3.6 V."] - RANGE0 = 0x0, + Range0 = 0x0, #[doc = "2.70 V-3.6 V."] - RANGE1 = 0x01, + Range1 = 0x01, } impl Range { #[inline(always)] @@ -974,9 +855,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sre { #[doc = "Fast."] - SRE0 = 0x0, + Sre0 = 0x0, #[doc = "Slow."] - SRE1 = 0x01, + Sre1 = 0x01, } impl Sre { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/RTC2xx.rs b/nxp-pac/src/meta_peripherals/mcxa/RTC2xx.rs index f8d210c..3da2bc4 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/RTC2xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/RTC2xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "RTC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rtc { @@ -433,14 +434,14 @@ impl Tcr { #[doc = "Time Compensation Register."] #[must_use] #[inline(always)] - pub const fn tcr(&self) -> TcrVal { + pub const fn tcr(&self) -> u8 { let val = (self.0 >> 0usize) & 0xff; - TcrVal::from_bits(val as u8) + val as u8 } #[doc = "Time Compensation Register."] #[inline(always)] - pub const fn set_tcr(&mut self, val: TcrVal) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + pub const fn set_tcr(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } #[doc = "Compensation Interval Register."] #[must_use] @@ -500,7 +501,7 @@ impl defmt::Format for Tcr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Tcr {{ tcr: {:?}, cir: {=u8:?}, tcv: {=u8:?}, cic: {=u8:?} }}", + "Tcr {{ tcr: {=u8:?}, cir: {=u8:?}, tcv: {=u8:?}, cic: {=u8:?} }}", self.tcr(), self.cir(), self.tcv(), @@ -583,9 +584,9 @@ impl defmt::Format for Tsr { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Crl { #[doc = "Control Register is locked and writes are ignored."] - CRL_0 = 0x0, + Crl0 = 0x0, #[doc = "Control Register is not locked and writes complete as normal."] - CRL_1 = 0x01, + Crl1 = 0x01, } impl Crl { #[inline(always)] @@ -614,9 +615,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lpos { #[doc = "RTC prescaler increments using 32.768 kHz clock."] - LPOS_0 = 0x0, + Lpos0 = 0x0, #[doc = "RTC prescaler increments using 1 kHz LPO, bits \\[4:0\\] of the prescaler are ignored."] - LPOS_1 = 0x01, + Lpos1 = 0x01, } impl Lpos { #[inline(always)] @@ -645,9 +646,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lrl { #[doc = "Lock Register is locked and writes are ignored."] - LRL_0 = 0x0, + Lrl0 = 0x0, #[doc = "Lock Register is not locked and writes complete as normal."] - LRL_1 = 0x01, + Lrl1 = 0x01, } impl Lrl { #[inline(always)] @@ -676,9 +677,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Srl { #[doc = "Status Register is locked and writes are ignored."] - SRL_0 = 0x0, + Srl0 = 0x0, #[doc = "Status Register is not locked and writes complete as normal."] - SRL_1 = 0x01, + Srl1 = 0x01, } impl Srl { #[inline(always)] @@ -707,9 +708,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Swr { #[doc = "No effect."] - SWR_0 = 0x0, + Swr0 = 0x0, #[doc = "Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it."] - SWR_1 = 0x01, + Swr1 = 0x01, } impl Swr { #[inline(always)] @@ -738,9 +739,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tcl { #[doc = "Time Compensation Register is locked and writes are ignored."] - TCL_0 = 0x0, + Tcl0 = 0x0, #[doc = "Time Compensation Register is not locked and writes complete as normal."] - TCL_1 = 0x01, + Tcl1 = 0x01, } impl Tcl { #[inline(always)] @@ -764,94 +765,26 @@ impl From for u8 { Tcl::to_bits(val) } } -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] -pub struct TcrVal(u8); -impl TcrVal { - #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] - pub const TCR_0: Self = Self(0x0); - #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] - pub const TCR_1: Self = Self(0x01); - #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] - pub const TCR_126: Self = Self(0x7e); - #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] - pub const TCR_127: Self = Self(0x7f); - #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] - pub const TCR_128: Self = Self(0x80); - #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] - pub const TCR_129: Self = Self(0x81); - #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] - pub const TCR_255: Self = Self(0xff); -} -impl TcrVal { - pub const fn from_bits(val: u8) -> TcrVal { - Self(val & 0xff) - } - pub const fn to_bits(self) -> u8 { - self.0 - } -} -impl core::fmt::Debug for TcrVal { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - match self.0 { - 0x0 => f.write_str("TCR_0"), - 0x01 => f.write_str("TCR_1"), - 0x7e => f.write_str("TCR_126"), - 0x7f => f.write_str("TCR_127"), - 0x80 => f.write_str("TCR_128"), - 0x81 => f.write_str("TCR_129"), - 0xff => f.write_str("TCR_255"), - other => core::write!(f, "0x{:02X}", other), - } - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for TcrVal { - fn format(&self, f: defmt::Formatter) { - match self.0 { - 0x0 => defmt::write!(f, "TCR_0"), - 0x01 => defmt::write!(f, "TCR_1"), - 0x7e => defmt::write!(f, "TCR_126"), - 0x7f => defmt::write!(f, "TCR_127"), - 0x80 => defmt::write!(f, "TCR_128"), - 0x81 => defmt::write!(f, "TCR_129"), - 0xff => defmt::write!(f, "TCR_255"), - other => defmt::write!(f, "0x{:02X}", other), - } - } -} -impl From for TcrVal { - #[inline(always)] - fn from(val: u8) -> TcrVal { - TcrVal::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: TcrVal) -> u8 { - TcrVal::to_bits(val) - } -} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tsic { #[doc = "1 Hz."] - TSIC_0 = 0x0, + Tsic0 = 0x0, #[doc = "2 Hz."] - TSIC_1 = 0x01, + Tsic1 = 0x01, #[doc = "4 Hz."] - TSIC_2 = 0x02, + Tsic2 = 0x02, #[doc = "8 Hz."] - TSIC_3 = 0x03, + Tsic3 = 0x03, #[doc = "16 Hz."] - TSIC_4 = 0x04, + Tsic4 = 0x04, #[doc = "32 Hz."] - TSIC_5 = 0x05, + Tsic5 = 0x05, #[doc = "64 Hz."] - TSIC_6 = 0x06, + Tsic6 = 0x06, #[doc = "128 Hz."] - TSIC_7 = 0x07, + Tsic7 = 0x07, } impl Tsic { #[inline(always)] @@ -880,9 +813,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Um { #[doc = "Registers cannot be written when locked."] - UM_0 = 0x0, + Um0 = 0x0, #[doc = "Registers can be written when locked under limited conditions."] - UM_1 = 0x01, + Um1 = 0x01, } impl Um { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/RTC5xx.rs b/nxp-pac/src/meta_peripherals/mcxa/RTC5xx.rs index 5c99d85..fb28ac3 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/RTC5xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/RTC5xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Real Time Clock."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Rtc { @@ -82,12 +83,12 @@ impl Rtc { pub const fn ier(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x16usize) as _) } } - #[doc = "Sub Second Alarm."] + #[doc = "Minutes Count Down Timer."] #[inline(always)] - pub const fn alm_subseconds( + pub const fn cntdwn_timer( self, - ) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x1eusize) as _) } + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x18usize) as _) } } #[doc = "Daylight Saving Hour."] #[inline(always)] @@ -109,6 +110,59 @@ impl Rtc { pub const fn compen(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x28usize) as _) } } + #[doc = "Tamper Queue Status and Control."] + #[inline(always)] + pub const fn tamper_qscr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x2eusize) as _) } + } + #[doc = "Tamper Time Stamp Year."] + #[inline(always)] + pub const fn ttsr_year(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x30usize) as _) } + } + #[doc = "Tamper Status and Control."] + #[inline(always)] + pub const fn tamper_scr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x32usize) as _) } + } + #[doc = "Tamper 01 Filter Configuration."] + #[inline(always)] + pub const fn filter01_cfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x34usize) as _) } + } + #[doc = "Tamper 23 Filter Configuration."] + #[inline(always)] + pub const fn filter23_cfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x36usize) as _) } + } + #[doc = "Tamper 05 Filter Configuration."] + #[inline(always)] + pub const fn filter45_cfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x38usize) as _) } + } + #[doc = "Tamper 67 Filter Configuration."] + #[inline(always)] + pub const fn filter67_cfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x3ausize) as _) } + } + #[doc = "Tamper Queue."] + #[inline(always)] + pub const fn tamper_queue(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize) as _) } + } + #[doc = "Control 2."] + #[inline(always)] + pub const fn ctrl2(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x42usize) as _) } + } } #[doc = "Days Alarm."] #[repr(transparent)] @@ -271,47 +325,6 @@ impl defmt::Format for AlmSeconds { ) } } -#[doc = "Sub Second Alarm."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct AlmSubseconds(pub u16); -impl AlmSubseconds { - #[doc = "Alarm Sub Second Counter Value."] - #[must_use] - #[inline(always)] - pub const fn alm_subsecs(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 - } - #[doc = "Alarm Sub Second Counter Value."] - #[inline(always)] - pub const fn set_alm_subsecs(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u16) & 0xffff) << 0usize); - } -} -impl Default for AlmSubseconds { - #[inline(always)] - fn default() -> AlmSubseconds { - AlmSubseconds(0) - } -} -impl core::fmt::Debug for AlmSubseconds { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("AlmSubseconds") - .field("alm_subsecs", &self.alm_subsecs()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for AlmSubseconds { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "AlmSubseconds {{ alm_subsecs: {=u16:?} }}", - self.alm_subsecs() - ) - } -} #[doc = "Year and Months Alarm."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -367,6 +380,47 @@ impl defmt::Format for AlmYearmon { ) } } +#[doc = "Minutes Count Down Timer."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct CntdwnTimer(pub u16); +impl CntdwnTimer { + #[doc = "Count Down Timer Value."] + #[must_use] + #[inline(always)] + pub const fn count_down_timer(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Count Down Timer Value."] + #[inline(always)] + pub const fn set_count_down_timer(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u16) & 0xff) << 0usize); + } +} +impl Default for CntdwnTimer { + #[inline(always)] + fn default() -> CntdwnTimer { + CntdwnTimer(0) + } +} +impl core::fmt::Debug for CntdwnTimer { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CntdwnTimer") + .field("count_down_timer", &self.count_down_timer()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for CntdwnTimer { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "CntdwnTimer {{ count_down_timer: {=u8:?} }}", + self.count_down_timer() + ) + } +} #[doc = "Compensation."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -445,18 +499,6 @@ impl Ctrl { pub const fn set_alm_match(&mut self, val: u8) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u16) & 0x03) << 2usize); } - #[doc = "Alarm Subseconds Match Enable Signal."] - #[must_use] - #[inline(always)] - pub const fn alm_subsecs_match_en(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 - } - #[doc = "Alarm Subseconds Match Enable Signal."] - #[inline(always)] - pub const fn set_alm_subsecs_match_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u16) & 0x01) << 5usize); - } #[doc = "Daylight Saving Enable."] #[must_use] #[inline(always)] @@ -469,6 +511,18 @@ impl Ctrl { pub const fn set_dst_en(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u16) & 0x01) << 6usize); } + #[doc = "BCD Mode Enable."] + #[must_use] + #[inline(always)] + pub const fn bcd_en(&self) -> BcdEn { + let val = (self.0 >> 7usize) & 0x01; + BcdEn::from_bits(val as u8) + } + #[doc = "BCD Mode Enable."] + #[inline(always)] + pub const fn set_bcd_en(&mut self, val: BcdEn) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); + } #[doc = "Software Reset."] #[must_use] #[inline(always)] @@ -530,8 +584,8 @@ impl core::fmt::Debug for Ctrl { .field("fineen", &self.fineen()) .field("comp_en", &self.comp_en()) .field("alm_match", &self.alm_match()) - .field("alm_subsecs_match_en", &self.alm_subsecs_match_en()) .field("dst_en", &self.dst_en()) + .field("bcd_en", &self.bcd_en()) .field("swr", &self.swr()) .field("clk_sel", &self.clk_sel()) .field("clko_dis", &self.clko_dis()) @@ -544,12 +598,12 @@ impl defmt::Format for Ctrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ctrl {{ fineen: {=bool:?}, comp_en: {=bool:?}, alm_match: {=u8:?}, alm_subsecs_match_en: {=bool:?}, dst_en: {=bool:?}, swr: {:?}, clk_sel: {=bool:?}, clko_dis: {=bool:?}, clkout: {=u8:?} }}", + "Ctrl {{ fineen: {=bool:?}, comp_en: {=bool:?}, alm_match: {=u8:?}, dst_en: {=bool:?}, bcd_en: {:?}, swr: {:?}, clk_sel: {=bool:?}, clko_dis: {=bool:?}, clkout: {=u8:?} }}", self.fineen(), self.comp_en(), self.alm_match(), - self.alm_subsecs_match_en(), self.dst_en(), + self.bcd_en(), self.swr(), self.clk_sel(), self.clko_dis(), @@ -557,6 +611,75 @@ impl defmt::Format for Ctrl { ) } } +#[doc = "Control 2."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ctrl2(pub u16); +impl Ctrl2 { + #[doc = "Tamper Configuration Over."] + #[must_use] + #[inline(always)] + pub const fn tamp_cfg_over(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Tamper Configuration Over."] + #[inline(always)] + pub const fn set_tamp_cfg_over(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u16) & 0x01) << 0usize); + } + #[doc = "Wakeup Status."] + #[must_use] + #[inline(always)] + pub const fn wakeup_status(&self) -> WakeupStatus { + let val = (self.0 >> 5usize) & 0x03; + WakeupStatus::from_bits(val as u8) + } + #[doc = "Wakeup Status."] + #[inline(always)] + pub const fn set_wakeup_status(&mut self, val: WakeupStatus) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.to_bits() as u16) & 0x03) << 5usize); + } + #[doc = "Wakeup Mode."] + #[must_use] + #[inline(always)] + pub const fn wakeup_mode(&self) -> WakeupMode { + let val = (self.0 >> 7usize) & 0x01; + WakeupMode::from_bits(val as u8) + } + #[doc = "Wakeup Mode."] + #[inline(always)] + pub const fn set_wakeup_mode(&mut self, val: WakeupMode) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); + } +} +impl Default for Ctrl2 { + #[inline(always)] + fn default() -> Ctrl2 { + Ctrl2(0) + } +} +impl core::fmt::Debug for Ctrl2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ctrl2") + .field("tamp_cfg_over", &self.tamp_cfg_over()) + .field("wakeup_status", &self.wakeup_status()) + .field("wakeup_mode", &self.wakeup_mode()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ctrl2 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Ctrl2 {{ tamp_cfg_over: {=bool:?}, wakeup_status: {:?}, wakeup_mode: {:?} }}", + self.tamp_cfg_over(), + self.wakeup_status(), + self.wakeup_mode() + ) + } +} #[doc = "Days and Day-of-Week Counters."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -777,383 +900,879 @@ impl defmt::Format for DstMonth { ) } } -#[doc = "Hours and Minutes Counters."] +#[doc = "Tamper 01 Filter Configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Hourmin(pub u16); -impl Hourmin { - #[doc = "Minutes Counter Value."] +pub struct Filter01Cfg(pub u16); +impl Filter01Cfg { + #[doc = "Tamper Detect Bit 1 Filter Duration."] #[must_use] #[inline(always)] - pub const fn min_cnt(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 + pub const fn fil_dur1(&self) -> FilDur1 { + let val = (self.0 >> 0usize) & 0x0f; + FilDur1::from_bits(val as u8) } - #[doc = "Minutes Counter Value."] + #[doc = "Tamper Detect Bit 1 Filter Duration."] #[inline(always)] - pub const fn set_min_cnt(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u16) & 0x3f) << 0usize); + pub const fn set_fil_dur1(&mut self, val: FilDur1) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u16) & 0x0f) << 0usize); } - #[doc = "Hours Counter Value."] + #[doc = "Tamper Filter 1 Clock Select."] #[must_use] #[inline(always)] - pub const fn hour_cnt(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x1f; - val as u8 + pub const fn clk_sel1(&self) -> ClkSel1 { + let val = (self.0 >> 4usize) & 0x07; + ClkSel1::from_bits(val as u8) } - #[doc = "Hours Counter Value."] + #[doc = "Tamper Filter 1 Clock Select."] #[inline(always)] - pub const fn set_hour_cnt(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u16) & 0x1f) << 8usize); + pub const fn set_clk_sel1(&mut self, val: ClkSel1) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u16) & 0x07) << 4usize); + } + #[doc = "Tamper Detect Input Bit 1 Polarity Control."] + #[must_use] + #[inline(always)] + pub const fn pol1(&self) -> Pol1 { + let val = (self.0 >> 7usize) & 0x01; + Pol1::from_bits(val as u8) + } + #[doc = "Tamper Detect Input Bit 1 Polarity Control."] + #[inline(always)] + pub const fn set_pol1(&mut self, val: Pol1) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); + } + #[doc = "Tamper Detect Bit 0 Filter Duration."] + #[must_use] + #[inline(always)] + pub const fn fil_dur0(&self) -> FilDur0 { + let val = (self.0 >> 8usize) & 0x0f; + FilDur0::from_bits(val as u8) + } + #[doc = "Tamper Detect Bit 0 Filter Duration."] + #[inline(always)] + pub const fn set_fil_dur0(&mut self, val: FilDur0) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u16) & 0x0f) << 8usize); + } + #[doc = "Tamper Filter 0 Clock Select."] + #[must_use] + #[inline(always)] + pub const fn clk_sel0(&self) -> ClkSel0 { + let val = (self.0 >> 12usize) & 0x07; + ClkSel0::from_bits(val as u8) + } + #[doc = "Tamper Filter 0 Clock Select."] + #[inline(always)] + pub const fn set_clk_sel0(&mut self, val: ClkSel0) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u16) & 0x07) << 12usize); + } + #[doc = "Tamper Detect Input Bit 0 Polarity Control."] + #[must_use] + #[inline(always)] + pub const fn pol0(&self) -> Pol0 { + let val = (self.0 >> 15usize) & 0x01; + Pol0::from_bits(val as u8) + } + #[doc = "Tamper Detect Input Bit 0 Polarity Control."] + #[inline(always)] + pub const fn set_pol0(&mut self, val: Pol0) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u16) & 0x01) << 15usize); } } -impl Default for Hourmin { +impl Default for Filter01Cfg { #[inline(always)] - fn default() -> Hourmin { - Hourmin(0) + fn default() -> Filter01Cfg { + Filter01Cfg(0) } } -impl core::fmt::Debug for Hourmin { +impl core::fmt::Debug for Filter01Cfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Hourmin") - .field("min_cnt", &self.min_cnt()) - .field("hour_cnt", &self.hour_cnt()) + f.debug_struct("Filter01Cfg") + .field("fil_dur1", &self.fil_dur1()) + .field("clk_sel1", &self.clk_sel1()) + .field("pol1", &self.pol1()) + .field("fil_dur0", &self.fil_dur0()) + .field("clk_sel0", &self.clk_sel0()) + .field("pol0", &self.pol0()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Hourmin { +impl defmt::Format for Filter01Cfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Hourmin {{ min_cnt: {=u8:?}, hour_cnt: {=u8:?} }}", - self.min_cnt(), - self.hour_cnt() + "Filter01Cfg {{ fil_dur1: {:?}, clk_sel1: {:?}, pol1: {:?}, fil_dur0: {:?}, clk_sel0: {:?}, pol0: {:?} }}", + self.fil_dur1(), + self.clk_sel1(), + self.pol1(), + self.fil_dur0(), + self.clk_sel0(), + self.pol0() ) } } -#[doc = "Interrupt Enable."] +#[doc = "Tamper 23 Filter Configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ier(pub u16); -impl Ier { - #[doc = "Alarm Interrupt Enable."] +pub struct Filter23Cfg(pub u16); +impl Filter23Cfg { + #[doc = "Tamper Detect Bit 3 Filter Duration."] #[must_use] #[inline(always)] - pub const fn alm_ie(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub const fn fil_dur3(&self) -> FilDur3 { + let val = (self.0 >> 0usize) & 0x0f; + FilDur3::from_bits(val as u8) } - #[doc = "Alarm Interrupt Enable."] + #[doc = "Tamper Detect Bit 3 Filter Duration."] #[inline(always)] - pub const fn set_alm_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u16) & 0x01) << 2usize); + pub const fn set_fil_dur3(&mut self, val: FilDur3) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u16) & 0x0f) << 0usize); } - #[doc = "Days Interrupt Enable."] + #[doc = "Tamper Filter 3 Clock Select."] #[must_use] #[inline(always)] - pub const fn day_ie(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 + pub const fn clk_sel3(&self) -> ClkSel3 { + let val = (self.0 >> 4usize) & 0x07; + ClkSel3::from_bits(val as u8) } - #[doc = "Days Interrupt Enable."] + #[doc = "Tamper Filter 3 Clock Select."] #[inline(always)] - pub const fn set_day_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u16) & 0x01) << 3usize); + pub const fn set_clk_sel3(&mut self, val: ClkSel3) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u16) & 0x07) << 4usize); } - #[doc = "Hours Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 3 Polarity Control."] #[must_use] #[inline(always)] - pub const fn hour_ie(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 + pub const fn pol3(&self) -> Pol3 { + let val = (self.0 >> 7usize) & 0x01; + Pol3::from_bits(val as u8) } - #[doc = "Hours Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 3 Polarity Control."] #[inline(always)] - pub const fn set_hour_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u16) & 0x01) << 4usize); + pub const fn set_pol3(&mut self, val: Pol3) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); } - #[doc = "Minutes Interrupt Enable."] + #[doc = "Tamper Detect Bit 2 Filter Duration."] #[must_use] #[inline(always)] - pub const fn min_ie(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn fil_dur2(&self) -> FilDur2 { + let val = (self.0 >> 8usize) & 0x0f; + FilDur2::from_bits(val as u8) } - #[doc = "Minutes Interrupt Enable."] + #[doc = "Tamper Detect Bit 2 Filter Duration."] #[inline(always)] - pub const fn set_min_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u16) & 0x01) << 5usize); + pub const fn set_fil_dur2(&mut self, val: FilDur2) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u16) & 0x0f) << 8usize); } - #[doc = "1 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 2 Clock Select."] #[must_use] #[inline(always)] - pub const fn ie_1hz(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; - val != 0 + pub const fn clk_sel2(&self) -> ClkSel2 { + let val = (self.0 >> 12usize) & 0x07; + ClkSel2::from_bits(val as u8) } - #[doc = "1 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 2 Clock Select."] #[inline(always)] - pub const fn set_ie_1hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u16) & 0x01) << 6usize); + pub const fn set_clk_sel2(&mut self, val: ClkSel2) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u16) & 0x07) << 12usize); } - #[doc = "2 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 2 Polarity Control."] #[must_use] #[inline(always)] - pub const fn ie_2hz(&self) -> bool { - let val = (self.0 >> 7usize) & 0x01; - val != 0 + pub const fn pol2(&self) -> Pol2 { + let val = (self.0 >> 15usize) & 0x01; + Pol2::from_bits(val as u8) } - #[doc = "2 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 2 Polarity Control."] #[inline(always)] - pub const fn set_ie_2hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u16) & 0x01) << 7usize); + pub const fn set_pol2(&mut self, val: Pol2) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u16) & 0x01) << 15usize); } - #[doc = "4 Hz Interval Interrupt Enable."] +} +impl Default for Filter23Cfg { + #[inline(always)] + fn default() -> Filter23Cfg { + Filter23Cfg(0) + } +} +impl core::fmt::Debug for Filter23Cfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Filter23Cfg") + .field("fil_dur3", &self.fil_dur3()) + .field("clk_sel3", &self.clk_sel3()) + .field("pol3", &self.pol3()) + .field("fil_dur2", &self.fil_dur2()) + .field("clk_sel2", &self.clk_sel2()) + .field("pol2", &self.pol2()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Filter23Cfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Filter23Cfg {{ fil_dur3: {:?}, clk_sel3: {:?}, pol3: {:?}, fil_dur2: {:?}, clk_sel2: {:?}, pol2: {:?} }}", + self.fil_dur3(), + self.clk_sel3(), + self.pol3(), + self.fil_dur2(), + self.clk_sel2(), + self.pol2() + ) + } +} +#[doc = "Tamper 05 Filter Configuration."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Filter45Cfg(pub u16); +impl Filter45Cfg { + #[doc = "Tamper Detect Bit 5 Filter Duration."] #[must_use] #[inline(always)] - pub const fn ie_4hz(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 + pub const fn fil_dur5(&self) -> FilDur5 { + let val = (self.0 >> 0usize) & 0x0f; + FilDur5::from_bits(val as u8) } - #[doc = "4 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Bit 5 Filter Duration."] #[inline(always)] - pub const fn set_ie_4hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u16) & 0x01) << 8usize); + pub const fn set_fil_dur5(&mut self, val: FilDur5) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u16) & 0x0f) << 0usize); } - #[doc = "8 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 5 Clock Select."] #[must_use] #[inline(always)] - pub const fn ie_8hz(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 + pub const fn clk_sel5(&self) -> ClkSel5 { + let val = (self.0 >> 4usize) & 0x07; + ClkSel5::from_bits(val as u8) } - #[doc = "8 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 5 Clock Select."] #[inline(always)] - pub const fn set_ie_8hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u16) & 0x01) << 9usize); + pub const fn set_clk_sel5(&mut self, val: ClkSel5) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u16) & 0x07) << 4usize); } - #[doc = "16 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 5 Polarity Control."] #[must_use] #[inline(always)] - pub const fn ie_16hz(&self) -> bool { - let val = (self.0 >> 10usize) & 0x01; - val != 0 + pub const fn pol5(&self) -> Pol5 { + let val = (self.0 >> 7usize) & 0x01; + Pol5::from_bits(val as u8) } - #[doc = "16 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 5 Polarity Control."] #[inline(always)] - pub const fn set_ie_16hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u16) & 0x01) << 10usize); + pub const fn set_pol5(&mut self, val: Pol5) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); } - #[doc = "32 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Bit 4 Filter Duration."] #[must_use] #[inline(always)] - pub const fn ie_32hz(&self) -> bool { - let val = (self.0 >> 11usize) & 0x01; - val != 0 + pub const fn fil_dur4(&self) -> FilDur4 { + let val = (self.0 >> 8usize) & 0x0f; + FilDur4::from_bits(val as u8) } - #[doc = "32 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Bit 4 Filter Duration."] #[inline(always)] - pub const fn set_ie_32hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u16) & 0x01) << 11usize); + pub const fn set_fil_dur4(&mut self, val: FilDur4) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u16) & 0x0f) << 8usize); } - #[doc = "64 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 4 Clock Select."] #[must_use] #[inline(always)] - pub const fn ie_64hz(&self) -> bool { - let val = (self.0 >> 12usize) & 0x01; - val != 0 + pub const fn clk_sel4(&self) -> ClkSel4 { + let val = (self.0 >> 12usize) & 0x07; + ClkSel4::from_bits(val as u8) } - #[doc = "64 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 4 Clock Select."] #[inline(always)] - pub const fn set_ie_64hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u16) & 0x01) << 12usize); + pub const fn set_clk_sel4(&mut self, val: ClkSel4) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u16) & 0x07) << 12usize); } - #[doc = "128 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 4 Polarity Control."] #[must_use] #[inline(always)] - pub const fn ie_128hz(&self) -> bool { - let val = (self.0 >> 13usize) & 0x01; - val != 0 + pub const fn pol4(&self) -> Pol4 { + let val = (self.0 >> 15usize) & 0x01; + Pol4::from_bits(val as u8) } - #[doc = "128 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 4 Polarity Control."] #[inline(always)] - pub const fn set_ie_128hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u16) & 0x01) << 13usize); + pub const fn set_pol4(&mut self, val: Pol4) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u16) & 0x01) << 15usize); } - #[doc = "256 Hz Interval Interrupt Enable."] +} +impl Default for Filter45Cfg { + #[inline(always)] + fn default() -> Filter45Cfg { + Filter45Cfg(0) + } +} +impl core::fmt::Debug for Filter45Cfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Filter45Cfg") + .field("fil_dur5", &self.fil_dur5()) + .field("clk_sel5", &self.clk_sel5()) + .field("pol5", &self.pol5()) + .field("fil_dur4", &self.fil_dur4()) + .field("clk_sel4", &self.clk_sel4()) + .field("pol4", &self.pol4()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Filter45Cfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Filter45Cfg {{ fil_dur5: {:?}, clk_sel5: {:?}, pol5: {:?}, fil_dur4: {:?}, clk_sel4: {:?}, pol4: {:?} }}", + self.fil_dur5(), + self.clk_sel5(), + self.pol5(), + self.fil_dur4(), + self.clk_sel4(), + self.pol4() + ) + } +} +#[doc = "Tamper 67 Filter Configuration."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Filter67Cfg(pub u16); +impl Filter67Cfg { + #[doc = "Tamper Detect Bit 7 Filter Duration."] #[must_use] #[inline(always)] - pub const fn ie_256hz(&self) -> bool { - let val = (self.0 >> 14usize) & 0x01; - val != 0 + pub const fn fil_dur7(&self) -> FilDur7 { + let val = (self.0 >> 0usize) & 0x0f; + FilDur7::from_bits(val as u8) } - #[doc = "256 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Bit 7 Filter Duration."] #[inline(always)] - pub const fn set_ie_256hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u16) & 0x01) << 14usize); + pub const fn set_fil_dur7(&mut self, val: FilDur7) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u16) & 0x0f) << 0usize); } - #[doc = "512 Hz Interval Interrupt Enable."] + #[doc = "Tamper Filter 7 Clock Select."] #[must_use] #[inline(always)] - pub const fn ie_512hz(&self) -> bool { + pub const fn clk_sel7(&self) -> ClkSel7 { + let val = (self.0 >> 4usize) & 0x07; + ClkSel7::from_bits(val as u8) + } + #[doc = "Tamper Filter 7 Clock Select."] + #[inline(always)] + pub const fn set_clk_sel7(&mut self, val: ClkSel7) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.to_bits() as u16) & 0x07) << 4usize); + } + #[doc = "Tamper Detect Input Bit 7 Polarity Control."] + #[must_use] + #[inline(always)] + pub const fn pol7(&self) -> Pol7 { + let val = (self.0 >> 7usize) & 0x01; + Pol7::from_bits(val as u8) + } + #[doc = "Tamper Detect Input Bit 7 Polarity Control."] + #[inline(always)] + pub const fn set_pol7(&mut self, val: Pol7) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u16) & 0x01) << 7usize); + } + #[doc = "Tamper Detect Bit 6 Filter Duration."] + #[must_use] + #[inline(always)] + pub const fn fil_dur6(&self) -> FilDur6 { + let val = (self.0 >> 8usize) & 0x0f; + FilDur6::from_bits(val as u8) + } + #[doc = "Tamper Detect Bit 6 Filter Duration."] + #[inline(always)] + pub const fn set_fil_dur6(&mut self, val: FilDur6) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u16) & 0x0f) << 8usize); + } + #[doc = "Tamper Filter 6 Clock Select."] + #[must_use] + #[inline(always)] + pub const fn clk_sel6(&self) -> ClkSel6 { + let val = (self.0 >> 12usize) & 0x07; + ClkSel6::from_bits(val as u8) + } + #[doc = "Tamper Filter 6 Clock Select."] + #[inline(always)] + pub const fn set_clk_sel6(&mut self, val: ClkSel6) { + self.0 = (self.0 & !(0x07 << 12usize)) | (((val.to_bits() as u16) & 0x07) << 12usize); + } + #[doc = "Tamper Detect Input Bit 6 Polarity Control."] + #[must_use] + #[inline(always)] + pub const fn pol6(&self) -> Pol6 { let val = (self.0 >> 15usize) & 0x01; - val != 0 + Pol6::from_bits(val as u8) } - #[doc = "512 Hz Interval Interrupt Enable."] + #[doc = "Tamper Detect Input Bit 6 Polarity Control."] #[inline(always)] - pub const fn set_ie_512hz(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u16) & 0x01) << 15usize); + pub const fn set_pol6(&mut self, val: Pol6) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.to_bits() as u16) & 0x01) << 15usize); } } -impl Default for Ier { +impl Default for Filter67Cfg { #[inline(always)] - fn default() -> Ier { - Ier(0) + fn default() -> Filter67Cfg { + Filter67Cfg(0) } } -impl core::fmt::Debug for Ier { +impl core::fmt::Debug for Filter67Cfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ier") - .field("alm_ie", &self.alm_ie()) - .field("day_ie", &self.day_ie()) - .field("hour_ie", &self.hour_ie()) - .field("min_ie", &self.min_ie()) - .field("ie_1hz", &self.ie_1hz()) - .field("ie_2hz", &self.ie_2hz()) - .field("ie_4hz", &self.ie_4hz()) - .field("ie_8hz", &self.ie_8hz()) - .field("ie_16hz", &self.ie_16hz()) - .field("ie_32hz", &self.ie_32hz()) - .field("ie_64hz", &self.ie_64hz()) - .field("ie_128hz", &self.ie_128hz()) - .field("ie_256hz", &self.ie_256hz()) - .field("ie_512hz", &self.ie_512hz()) + f.debug_struct("Filter67Cfg") + .field("fil_dur7", &self.fil_dur7()) + .field("clk_sel7", &self.clk_sel7()) + .field("pol7", &self.pol7()) + .field("fil_dur6", &self.fil_dur6()) + .field("clk_sel6", &self.clk_sel6()) + .field("pol6", &self.pol6()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Ier { +impl defmt::Format for Filter67Cfg { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ier {{ alm_ie: {=bool:?}, day_ie: {=bool:?}, hour_ie: {=bool:?}, min_ie: {=bool:?}, ie_1hz: {=bool:?}, ie_2hz: {=bool:?}, ie_4hz: {=bool:?}, ie_8hz: {=bool:?}, ie_16hz: {=bool:?}, ie_32hz: {=bool:?}, ie_64hz: {=bool:?}, ie_128hz: {=bool:?}, ie_256hz: {=bool:?}, ie_512hz: {=bool:?} }}", - self.alm_ie(), - self.day_ie(), - self.hour_ie(), - self.min_ie(), - self.ie_1hz(), - self.ie_2hz(), - self.ie_4hz(), - self.ie_8hz(), - self.ie_16hz(), - self.ie_32hz(), - self.ie_64hz(), - self.ie_128hz(), - self.ie_256hz(), - self.ie_512hz() + "Filter67Cfg {{ fil_dur7: {:?}, clk_sel7: {:?}, pol7: {:?}, fil_dur6: {:?}, clk_sel6: {:?}, pol6: {:?} }}", + self.fil_dur7(), + self.clk_sel7(), + self.pol7(), + self.fil_dur6(), + self.clk_sel6(), + self.pol6() ) } } -#[doc = "Interrupt Status."] +#[doc = "Hours and Minutes Counters."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Isr(pub u16); -impl Isr { - #[doc = "Alarm Interrupt Status."] +pub struct Hourmin(pub u16); +impl Hourmin { + #[doc = "Minutes Counter Value."] #[must_use] #[inline(always)] - pub const fn alm_is(&self) -> bool { + pub const fn min_cnt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Minutes Counter Value."] + #[inline(always)] + pub const fn set_min_cnt(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u16) & 0x3f) << 0usize); + } + #[doc = "Hours Counter Value."] + #[must_use] + #[inline(always)] + pub const fn hour_cnt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "Hours Counter Value."] + #[inline(always)] + pub const fn set_hour_cnt(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u16) & 0x1f) << 8usize); + } +} +impl Default for Hourmin { + #[inline(always)] + fn default() -> Hourmin { + Hourmin(0) + } +} +impl core::fmt::Debug for Hourmin { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Hourmin") + .field("min_cnt", &self.min_cnt()) + .field("hour_cnt", &self.hour_cnt()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Hourmin { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Hourmin {{ min_cnt: {=u8:?}, hour_cnt: {=u8:?} }}", + self.min_cnt(), + self.hour_cnt() + ) + } +} +#[doc = "Interrupt Enable."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ier(pub u16); +impl Ier { + #[doc = "Tamper Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn tamper_ie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Tamper Interrupt Enable."] + #[inline(always)] + pub const fn set_tamper_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u16) & 0x01) << 0usize); + } + #[doc = "Count Down Timer Timeout Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn cnt_dn_timeout_ie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Count Down Timer Timeout Interrupt Enable."] + #[inline(always)] + pub const fn set_cnt_dn_timeout_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u16) & 0x01) << 1usize); + } + #[doc = "Alarm Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn alm_ie(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Alarm Interrupt Status."] + #[doc = "Alarm Interrupt Enable."] #[inline(always)] - pub const fn set_alm_is(&mut self, val: bool) { + pub const fn set_alm_ie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u16) & 0x01) << 2usize); } - #[doc = "Days Interrupt Status."] + #[doc = "Days Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn day_is(&self) -> bool { + pub const fn day_ie(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Days Interrupt Status."] + #[doc = "Days Interrupt Enable."] #[inline(always)] - pub const fn set_day_is(&mut self, val: bool) { + pub const fn set_day_ie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u16) & 0x01) << 3usize); } - #[doc = "Hours Interrupt Status."] + #[doc = "Hours Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn hour_is(&self) -> bool { + pub const fn hour_ie(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Hours Interrupt Status."] + #[doc = "Hours Interrupt Enable."] #[inline(always)] - pub const fn set_hour_is(&mut self, val: bool) { + pub const fn set_hour_ie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u16) & 0x01) << 4usize); } - #[doc = "Minutes Interrupt Status."] + #[doc = "Minutes Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn min_is(&self) -> bool { + pub const fn min_ie(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "Minutes Interrupt Status."] + #[doc = "Minutes Interrupt Enable."] #[inline(always)] - pub const fn set_min_is(&mut self, val: bool) { + pub const fn set_min_ie(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u16) & 0x01) << 5usize); } - #[doc = "1 Hz Interval Interrupt Status."] + #[doc = "1 Hz Interval Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn is_1hz(&self) -> bool { + pub const fn ie_1hz(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "1 Hz Interval Interrupt Status."] + #[doc = "1 Hz Interval Interrupt Enable."] #[inline(always)] - pub const fn set_is_1hz(&mut self, val: bool) { + pub const fn set_ie_1hz(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u16) & 0x01) << 6usize); } - #[doc = "2 Hz Interval Interrupt Status."] + #[doc = "2 Hz Interval Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn is_2hz(&self) -> bool { + pub const fn ie_2hz(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "2 Hz Interval Interrupt Status."] + #[doc = "2 Hz Interval Interrupt Enable."] #[inline(always)] - pub const fn set_is_2hz(&mut self, val: bool) { + pub const fn set_ie_2hz(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u16) & 0x01) << 7usize); } - #[doc = "4 Hz Interval Interrupt Status."] + #[doc = "4 Hz Interval Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn is_4hz(&self) -> bool { + pub const fn ie_4hz(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "4 Hz Interval Interrupt Status."] + #[doc = "4 Hz Interval Interrupt Enable."] #[inline(always)] - pub const fn set_is_4hz(&mut self, val: bool) { + pub const fn set_ie_4hz(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u16) & 0x01) << 8usize); } - #[doc = "8 Hz Interval Interrupt Status."] + #[doc = "8 Hz Interval Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn is_8hz(&self) -> bool { + pub const fn ie_8hz(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "8 Hz Interval Interrupt Status."] + #[doc = "8 Hz Interval Interrupt Enable."] #[inline(always)] - pub const fn set_is_8hz(&mut self, val: bool) { + pub const fn set_ie_8hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u16) & 0x01) << 9usize); + } + #[doc = "16 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_16hz(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "16 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_16hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u16) & 0x01) << 10usize); + } + #[doc = "32 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_32hz(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "32 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_32hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u16) & 0x01) << 11usize); + } + #[doc = "64 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_64hz(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "64 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_64hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u16) & 0x01) << 12usize); + } + #[doc = "128 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_128hz(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "128 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_128hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u16) & 0x01) << 13usize); + } + #[doc = "256 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_256hz(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "256 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_256hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u16) & 0x01) << 14usize); + } + #[doc = "512 Hz Interval Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn ie_512hz(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "512 Hz Interval Interrupt Enable."] + #[inline(always)] + pub const fn set_ie_512hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u16) & 0x01) << 15usize); + } +} +impl Default for Ier { + #[inline(always)] + fn default() -> Ier { + Ier(0) + } +} +impl core::fmt::Debug for Ier { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ier") + .field("tamper_ie", &self.tamper_ie()) + .field("cnt_dn_timeout_ie", &self.cnt_dn_timeout_ie()) + .field("alm_ie", &self.alm_ie()) + .field("day_ie", &self.day_ie()) + .field("hour_ie", &self.hour_ie()) + .field("min_ie", &self.min_ie()) + .field("ie_1hz", &self.ie_1hz()) + .field("ie_2hz", &self.ie_2hz()) + .field("ie_4hz", &self.ie_4hz()) + .field("ie_8hz", &self.ie_8hz()) + .field("ie_16hz", &self.ie_16hz()) + .field("ie_32hz", &self.ie_32hz()) + .field("ie_64hz", &self.ie_64hz()) + .field("ie_128hz", &self.ie_128hz()) + .field("ie_256hz", &self.ie_256hz()) + .field("ie_512hz", &self.ie_512hz()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Ier { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Ier {{ tamper_ie: {=bool:?}, cnt_dn_timeout_ie: {=bool:?}, alm_ie: {=bool:?}, day_ie: {=bool:?}, hour_ie: {=bool:?}, min_ie: {=bool:?}, ie_1hz: {=bool:?}, ie_2hz: {=bool:?}, ie_4hz: {=bool:?}, ie_8hz: {=bool:?}, ie_16hz: {=bool:?}, ie_32hz: {=bool:?}, ie_64hz: {=bool:?}, ie_128hz: {=bool:?}, ie_256hz: {=bool:?}, ie_512hz: {=bool:?} }}", + self.tamper_ie(), + self.cnt_dn_timeout_ie(), + self.alm_ie(), + self.day_ie(), + self.hour_ie(), + self.min_ie(), + self.ie_1hz(), + self.ie_2hz(), + self.ie_4hz(), + self.ie_8hz(), + self.ie_16hz(), + self.ie_32hz(), + self.ie_64hz(), + self.ie_128hz(), + self.ie_256hz(), + self.ie_512hz() + ) + } +} +#[doc = "Interrupt Status."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Isr(pub u16); +impl Isr { + #[doc = "Tamper Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn tamper_is(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Tamper Interrupt Status."] + #[inline(always)] + pub const fn set_tamper_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u16) & 0x01) << 0usize); + } + #[doc = "Count Down Timer Timeout Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn cnt_dn_timeout_is(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Count Down Timer Timeout Interrupt Status."] + #[inline(always)] + pub const fn set_cnt_dn_timeout_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u16) & 0x01) << 1usize); + } + #[doc = "Alarm Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn alm_is(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Alarm Interrupt Status."] + #[inline(always)] + pub const fn set_alm_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u16) & 0x01) << 2usize); + } + #[doc = "Days Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn day_is(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Days Interrupt Status."] + #[inline(always)] + pub const fn set_day_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u16) & 0x01) << 3usize); + } + #[doc = "Hours Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn hour_is(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Hours Interrupt Status."] + #[inline(always)] + pub const fn set_hour_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u16) & 0x01) << 4usize); + } + #[doc = "Minutes Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn min_is(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Minutes Interrupt Status."] + #[inline(always)] + pub const fn set_min_is(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u16) & 0x01) << 5usize); + } + #[doc = "1 Hz Interval Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn is_1hz(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "1 Hz Interval Interrupt Status."] + #[inline(always)] + pub const fn set_is_1hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u16) & 0x01) << 6usize); + } + #[doc = "2 Hz Interval Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn is_2hz(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "2 Hz Interval Interrupt Status."] + #[inline(always)] + pub const fn set_is_2hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u16) & 0x01) << 7usize); + } + #[doc = "4 Hz Interval Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn is_4hz(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "4 Hz Interval Interrupt Status."] + #[inline(always)] + pub const fn set_is_4hz(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u16) & 0x01) << 8usize); + } + #[doc = "8 Hz Interval Interrupt Status."] + #[must_use] + #[inline(always)] + pub const fn is_8hz(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "8 Hz Interval Interrupt Status."] + #[inline(always)] + pub const fn set_is_8hz(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u16) & 0x01) << 9usize); } #[doc = "16 Hz Interval Interrupt Status."] @@ -1238,6 +1857,8 @@ impl Default for Isr { impl core::fmt::Debug for Isr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Isr") + .field("tamper_is", &self.tamper_is()) + .field("cnt_dn_timeout_is", &self.cnt_dn_timeout_is()) .field("alm_is", &self.alm_is()) .field("day_is", &self.day_is()) .field("hour_is", &self.hour_is()) @@ -1260,7 +1881,9 @@ impl defmt::Format for Isr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Isr {{ alm_is: {=bool:?}, day_is: {=bool:?}, hour_is: {=bool:?}, min_is: {=bool:?}, is_1hz: {=bool:?}, is_2hz: {=bool:?}, is_4hz: {=bool:?}, is_8hz: {=bool:?}, is_16hz: {=bool:?}, is_32hz: {=bool:?}, is_64hz: {=bool:?}, is_128hz: {=bool:?}, is_256hz: {=bool:?}, is_512hz: {=bool:?} }}", + "Isr {{ tamper_is: {=bool:?}, cnt_dn_timeout_is: {=bool:?}, alm_is: {=bool:?}, day_is: {=bool:?}, hour_is: {=bool:?}, min_is: {=bool:?}, is_1hz: {=bool:?}, is_2hz: {=bool:?}, is_4hz: {=bool:?}, is_8hz: {=bool:?}, is_16hz: {=bool:?}, is_32hz: {=bool:?}, is_64hz: {=bool:?}, is_128hz: {=bool:?}, is_256hz: {=bool:?}, is_512hz: {=bool:?} }}", + self.tamper_is(), + self.cnt_dn_timeout_is(), self.alm_is(), self.day_is(), self.hour_is(), @@ -1344,6 +1967,18 @@ impl Status { pub const fn set_write_prot_en(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u16) & 0x01) << 1usize); } + #[doc = "Down Counter Invalidate Read/Write Access."] + #[must_use] + #[inline(always)] + pub const fn dwn_cntr_inval_bit(&self) -> DwnCntrInvalBit { + let val = (self.0 >> 4usize) & 0x01; + DwnCntrInvalBit::from_bits(val as u8) + } + #[doc = "Down Counter Invalidate Read/Write Access."] + #[inline(always)] + pub const fn set_dwn_cntr_inval_bit(&mut self, val: DwnCntrInvalBit) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u16) & 0x01) << 4usize); + } #[doc = "Compensation Interval."] #[must_use] #[inline(always)] @@ -1404,6 +2039,7 @@ impl core::fmt::Debug for Status { f.debug_struct("Status") .field("inval_bit", &self.inval_bit()) .field("write_prot_en", &self.write_prot_en()) + .field("dwn_cntr_inval_bit", &self.dwn_cntr_inval_bit()) .field("cmp_int", &self.cmp_int()) .field("we", &self.we()) .field("bus_err", &self.bus_err()) @@ -1416,9 +2052,10 @@ impl defmt::Format for Status { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Status {{ inval_bit: {=bool:?}, write_prot_en: {=bool:?}, cmp_int: {=bool:?}, we: {=u8:?}, bus_err: {:?}, cmp_done: {=bool:?} }}", + "Status {{ inval_bit: {=bool:?}, write_prot_en: {=bool:?}, dwn_cntr_inval_bit: {:?}, cmp_int: {=bool:?}, we: {=u8:?}, bus_err: {:?}, cmp_done: {=bool:?} }}", self.inval_bit(), self.write_prot_en(), + self.dwn_cntr_inval_bit(), self.cmp_int(), self.we(), self.bus_err(), @@ -1426,22 +2063,252 @@ impl defmt::Format for Status { ) } } -#[doc = "Year and Month Counters."] +#[doc = "Tamper Queue Status and Control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Yearmon(pub u16); -impl Yearmon { - #[doc = "Month Counter."] +pub struct TamperQscr(pub u16); +impl TamperQscr { + #[doc = "Q_FULL."] #[must_use] #[inline(always)] - pub const fn mon_cnt(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; - val as u8 + pub const fn q_full(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Month Counter."] + #[doc = "Q_FULL."] #[inline(always)] - pub const fn set_mon_cnt(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u16) & 0x0f) << 0usize); + pub const fn set_q_full(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u16) & 0x01) << 0usize); + } + #[doc = "Q_FULL_INT_EN."] + #[must_use] + #[inline(always)] + pub const fn q_full_int_en(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Q_FULL_INT_EN."] + #[inline(always)] + pub const fn set_q_full_int_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u16) & 0x01) << 1usize); + } + #[doc = "Q_CLEAR."] + #[must_use] + #[inline(always)] + pub const fn q_clear(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Q_CLEAR."] + #[inline(always)] + pub const fn set_q_clear(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u16) & 0x01) << 2usize); + } + #[doc = "LFSR_CLK_SEL."] + #[must_use] + #[inline(always)] + pub const fn lfsr_clk_sel(&self) -> LfsrClkSel { + let val = (self.0 >> 8usize) & 0x07; + LfsrClkSel::from_bits(val as u8) + } + #[doc = "LFSR_CLK_SEL."] + #[inline(always)] + pub const fn set_lfsr_clk_sel(&mut self, val: LfsrClkSel) { + self.0 = (self.0 & !(0x07 << 8usize)) | (((val.to_bits() as u16) & 0x07) << 8usize); + } + #[doc = "LFSR_DURATION."] + #[must_use] + #[inline(always)] + pub const fn lfsr_duration(&self) -> u8 { + let val = (self.0 >> 12usize) & 0x0f; + val as u8 + } + #[doc = "LFSR_DURATION."] + #[inline(always)] + pub const fn set_lfsr_duration(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 12usize)) | (((val as u16) & 0x0f) << 12usize); + } +} +impl Default for TamperQscr { + #[inline(always)] + fn default() -> TamperQscr { + TamperQscr(0) + } +} +impl core::fmt::Debug for TamperQscr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TamperQscr") + .field("q_full", &self.q_full()) + .field("q_full_int_en", &self.q_full_int_en()) + .field("q_clear", &self.q_clear()) + .field("lfsr_clk_sel", &self.lfsr_clk_sel()) + .field("lfsr_duration", &self.lfsr_duration()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for TamperQscr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "TamperQscr {{ q_full: {=bool:?}, q_full_int_en: {=bool:?}, q_clear: {=bool:?}, lfsr_clk_sel: {:?}, lfsr_duration: {=u8:?} }}", + self.q_full(), + self.q_full_int_en(), + self.q_clear(), + self.lfsr_clk_sel(), + self.lfsr_duration() + ) + } +} +#[doc = "Tamper Queue."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct TamperQueue(pub u16); +impl TamperQueue { + #[doc = "Tamper type stamp and pin number information register."] + #[must_use] + #[inline(always)] + pub const fn tamper_data(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tamper type stamp and pin number information register."] + #[inline(always)] + pub const fn set_tamper_data(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u16) & 0xffff) << 0usize); + } +} +impl Default for TamperQueue { + #[inline(always)] + fn default() -> TamperQueue { + TamperQueue(0) + } +} +impl core::fmt::Debug for TamperQueue { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TamperQueue") + .field("tamper_data", &self.tamper_data()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for TamperQueue { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "TamperQueue {{ tamper_data: {=u16:?} }}", + self.tamper_data() + ) + } +} +#[doc = "Tamper Status and Control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct TamperScr(pub u16); +impl TamperScr { + #[doc = "Tamper Control."] + #[must_use] + #[inline(always)] + pub const fn tmpr_en(&self) -> TmprEn { + let val = (self.0 >> 0usize) & 0x0f; + TmprEn::from_bits(val as u8) + } + #[doc = "Tamper Control."] + #[inline(always)] + pub const fn set_tmpr_en(&mut self, val: TmprEn) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u16) & 0x0f) << 0usize); + } + #[doc = "Tamper Status."] + #[must_use] + #[inline(always)] + pub const fn tmpr_sts(&self) -> TmprSts { + let val = (self.0 >> 8usize) & 0x0f; + TmprSts::from_bits(val as u8) + } + #[doc = "Tamper Status."] + #[inline(always)] + pub const fn set_tmpr_sts(&mut self, val: TmprSts) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.to_bits() as u16) & 0x0f) << 8usize); + } +} +impl Default for TamperScr { + #[inline(always)] + fn default() -> TamperScr { + TamperScr(0) + } +} +impl core::fmt::Debug for TamperScr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TamperScr") + .field("tmpr_en", &self.tmpr_en()) + .field("tmpr_sts", &self.tmpr_sts()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for TamperScr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "TamperScr {{ tmpr_en: {:?}, tmpr_sts: {:?} }}", + self.tmpr_en(), + self.tmpr_sts() + ) + } +} +#[doc = "Tamper Time Stamp Year."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct TtsrYear(pub u16); +impl TtsrYear { + #[doc = "Year Value for Tamper Time Stamp."] + #[must_use] + #[inline(always)] + pub const fn ts_yrofst(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Year Value for Tamper Time Stamp."] + #[inline(always)] + pub const fn set_ts_yrofst(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u16) & 0xff) << 8usize); + } +} +impl Default for TtsrYear { + #[inline(always)] + fn default() -> TtsrYear { + TtsrYear(0) + } +} +impl core::fmt::Debug for TtsrYear { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TtsrYear") + .field("ts_yrofst", &self.ts_yrofst()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for TtsrYear { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "TtsrYear {{ ts_yrofst: {=u8:?} }}", self.ts_yrofst()) + } +} +#[doc = "Year and Month Counters."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Yearmon(pub u16); +impl Yearmon { + #[doc = "Month Counter."] + #[must_use] + #[inline(always)] + pub const fn mon_cnt(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Month Counter."] + #[inline(always)] + pub const fn set_mon_cnt(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u16) & 0x0f) << 0usize); } #[doc = "Year Offset Count Value."] #[must_use] @@ -1484,11 +2351,42 @@ impl defmt::Format for Yearmon { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum BcdEn { + #[doc = "Binary mode."] + BinaryMode = 0x0, + #[doc = "BCD mode."] + BcdMode = 0x01, +} +impl BcdEn { + #[inline(always)] + pub const fn from_bits(val: u8) -> BcdEn { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for BcdEn { + #[inline(always)] + fn from(val: u8) -> BcdEn { + BcdEn::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: BcdEn) -> u8 { + BcdEn::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusErr { #[doc = "Read and write accesses are normal."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "Read or write accesses occurred when STATUS\\[INVAL_BIT\\] was asserted."] - ASSERTED = 0x01, + Asserted = 0x01, } impl BusErr { #[inline(always)] @@ -1515,31 +2413,1252 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Swr { - #[doc = "Software Reset cleared."] - CLEARED = 0x0, - #[doc = "Software Reset asserted."] - ASSERTED = 0x01, +pub enum ClkSel0 { + #[doc = "32/16 kHz clock."] + Clk32khz = 0x0, + #[doc = "512 Hz clock."] + Clk512hz = 0x01, + #[doc = "128 Hz clock."] + Clk128hz = 0x02, + #[doc = "64 Hz clock."] + Clk64hz = 0x03, + #[doc = "16 Hz clock."] + Clk16hz = 0x04, + #[doc = "8 Hz clock."] + Clk8hz = 0x05, + #[doc = "4 Hz clock."] + Clk4hz = 0x06, + #[doc = "2 Hz clock."] + Clk2hz = 0x07, +} +impl ClkSel0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel0 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } } -impl Swr { +impl From for ClkSel0 { #[inline(always)] - pub const fn from_bits(val: u8) -> Swr { - unsafe { core::mem::transmute(val & 0x01) } + fn from(val: u8) -> ClkSel0 { + ClkSel0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel0) -> u8 { + ClkSel0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel1 { + #[doc = "32/16 kHz clock."] + Clk32khz = 0x0, + #[doc = "512 Hz clock."] + Clk512hz = 0x01, + #[doc = "128 Hz clock."] + Clk128hz = 0x02, + #[doc = "64 Hz clock."] + Clk64hz = 0x03, + #[doc = "16 Hz clock."] + Clk16hz = 0x04, + #[doc = "8 Hz clock."] + Clk8hz = 0x05, + #[doc = "4 Hz clock."] + Clk4hz = 0x06, + #[doc = "2 Hz clock."] + Clk2hz = 0x07, +} +impl ClkSel1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel1 { + unsafe { core::mem::transmute(val & 0x07) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for Swr { +impl From for ClkSel1 { #[inline(always)] - fn from(val: u8) -> Swr { - Swr::from_bits(val) + fn from(val: u8) -> ClkSel1 { + ClkSel1::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Swr) -> u8 { - Swr::to_bits(val) + fn from(val: ClkSel1) -> u8 { + ClkSel1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel2 { + #[doc = "32/16 kHz clock."] + Clk32khz = 0x0, + #[doc = "512 Hz clock."] + Clk512hz = 0x01, + #[doc = "128 Hz clock."] + Clk128hz = 0x02, + #[doc = "64 Hz clock."] + Clk64hz = 0x03, + #[doc = "16 Hz clock."] + Clk16hz = 0x04, + #[doc = "8 Hz clock."] + Clk8hz = 0x05, + #[doc = "4 Hz clock."] + Clk4hz = 0x06, + #[doc = "2 Hz clock."] + Clk2hz = 0x07, +} +impl ClkSel2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel2 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel2 { + #[inline(always)] + fn from(val: u8) -> ClkSel2 { + ClkSel2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel2) -> u8 { + ClkSel2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel3 { + #[doc = "32/16 kHz clock."] + Clk32khz = 0x0, + #[doc = "512 Hz clock."] + Clk512hz = 0x01, + #[doc = "128 Hz clock."] + Clk128hz = 0x02, + #[doc = "64 Hz clock."] + Clk64hz = 0x03, + #[doc = "16 Hz clock."] + Clk16hz = 0x04, + #[doc = "8 Hz clock."] + Clk8hz = 0x05, + #[doc = "4 Hz clock."] + Clk4hz = 0x06, + #[doc = "2 Hz clock."] + Clk2hz = 0x07, +} +impl ClkSel3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel3 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel3 { + #[inline(always)] + fn from(val: u8) -> ClkSel3 { + ClkSel3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel3) -> u8 { + ClkSel3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel4 { + #[doc = "Clock to tamper filter 4 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us."] + Clk32768khz = 0x0, + #[doc = "Clock to tamper filter 4 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms."] + Clk512hz = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl ClkSel4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel4 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel4 { + #[inline(always)] + fn from(val: u8) -> ClkSel4 { + ClkSel4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel4) -> u8 { + ClkSel4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel5 { + #[doc = "Clock to tamper filter 5 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us."] + Clk32768khz = 0x0, + #[doc = "Clock to tamper filter 5 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms."] + Clk512hz = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl ClkSel5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel5 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel5 { + #[inline(always)] + fn from(val: u8) -> ClkSel5 { + ClkSel5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel5) -> u8 { + ClkSel5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel6 { + #[doc = "Clock to tamper filter 6 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us."] + Clk32768khz = 0x0, + #[doc = "Clock to tamper filter 6 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms."] + Clk512hz = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl ClkSel6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel6 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel6 { + #[inline(always)] + fn from(val: u8) -> ClkSel6 { + ClkSel6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel6) -> u8 { + ClkSel6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkSel7 { + #[doc = "Clock to tamper filter 7 is 32.768/16.384 kHz (Oscillator clock) Tamper filter duration is 45.5us (i.e. 1.5 clock) to 1.95ms (64 clocks) in increments of 30.5us."] + Clk32768khz = 0x0, + #[doc = "Clock to tamper filter 7 is 512 Hz Tamper filter duration is 2.85ms (i.e. 1.5 clock) to 125ms (64 clocks) in increments of 1.95ms."] + Clk512hz = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl ClkSel7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkSel7 { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ClkSel7 { + #[inline(always)] + fn from(val: u8) -> ClkSel7 { + ClkSel7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ClkSel7) -> u8 { + ClkSel7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DwnCntrInvalBit { + #[doc = "Count down timer can be changed or read."] + Valid = 0x0, + #[doc = "Count down timer (if running) is changing value and cannot be read or written."] + Invalid = 0x01, +} +impl DwnCntrInvalBit { + #[inline(always)] + pub const fn from_bits(val: u8) -> DwnCntrInvalBit { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for DwnCntrInvalBit { + #[inline(always)] + fn from(val: u8) -> DwnCntrInvalBit { + DwnCntrInvalBit::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: DwnCntrInvalBit) -> u8 { + DwnCntrInvalBit::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur0 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur0 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur0 { + #[inline(always)] + fn from(val: u8) -> FilDur0 { + FilDur0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur0) -> u8 { + FilDur0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur1 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + Enabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur1 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur1 { + #[inline(always)] + fn from(val: u8) -> FilDur1 { + FilDur1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur1) -> u8 { + FilDur1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur2 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur2 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur2 { + #[inline(always)] + fn from(val: u8) -> FilDur2 { + FilDur2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur2) -> u8 { + FilDur2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur3 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur3 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur3 { + #[inline(always)] + fn from(val: u8) -> FilDur3 { + FilDur3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur3) -> u8 { + FilDur3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur4 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur4 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur4 { + #[inline(always)] + fn from(val: u8) -> FilDur4 { + FilDur4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur4) -> u8 { + FilDur4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur5 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur5 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur5 { + #[inline(always)] + fn from(val: u8) -> FilDur5 { + FilDur5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur5) -> u8 { + FilDur5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur6 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur6 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur6 { + #[inline(always)] + fn from(val: u8) -> FilDur6 { + FilDur6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur6) -> u8 { + FilDur6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilDur7 { + #[doc = "Filtering operation disabled."] + Disabled = 0x0, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled1 = 0x01, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled2 = 0x02, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled3 = 0x03, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled4 = 0x04, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled5 = 0x05, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled6 = 0x06, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled7 = 0x07, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled8 = 0x08, + #[doc = "Number of tamper filter clock cycles to be counted when tamper is asserted."] + NumberOfClkCyclesEnabled9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl FilDur7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> FilDur7 { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FilDur7 { + #[inline(always)] + fn from(val: u8) -> FilDur7 { + FilDur7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FilDur7) -> u8 { + FilDur7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum LfsrClkSel { + #[doc = "32/16 KHz."] + Clk3216khz = 0x0, + #[doc = "512 Hz."] + Clk512hz = 0x01, + #[doc = "128 Hz."] + Clk128hz = 0x02, + #[doc = "64 Hz."] + Clk64hz = 0x03, + #[doc = "16 Hz."] + Clk16hz = 0x04, + #[doc = "8 Hz."] + Clk8hz = 0x05, + #[doc = "4 Hz."] + Clk4hz = 0x06, + #[doc = "2 Hz."] + Clk2hz = 0x07, +} +impl LfsrClkSel { + #[inline(always)] + pub const fn from_bits(val: u8) -> LfsrClkSel { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for LfsrClkSel { + #[inline(always)] + fn from(val: u8) -> LfsrClkSel { + LfsrClkSel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: LfsrClkSel) -> u8 { + LfsrClkSel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol0 { + #[doc = "Tamper detect input bit 0 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 0 is active low."] + ActiveLow = 0x01, +} +impl Pol0 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol0 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol0 { + #[inline(always)] + fn from(val: u8) -> Pol0 { + Pol0::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol0) -> u8 { + Pol0::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol1 { + #[doc = "Tamper detect input bit 1 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 1 is active low."] + ActiveLow = 0x01, +} +impl Pol1 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol1 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol1 { + #[inline(always)] + fn from(val: u8) -> Pol1 { + Pol1::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol1) -> u8 { + Pol1::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol2 { + #[doc = "Tamper detect input bit 2 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 2 is active low."] + ActiveLow = 0x01, +} +impl Pol2 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol2 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol2 { + #[inline(always)] + fn from(val: u8) -> Pol2 { + Pol2::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol2) -> u8 { + Pol2::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol3 { + #[doc = "Tamper detect input bit 3 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 3 is active low."] + ActiveLow = 0x01, +} +impl Pol3 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol3 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol3 { + #[inline(always)] + fn from(val: u8) -> Pol3 { + Pol3::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol3) -> u8 { + Pol3::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol4 { + #[doc = "Tamper detect input bit 4is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 4 is active low."] + ActiveLow = 0x01, +} +impl Pol4 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol4 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol4 { + #[inline(always)] + fn from(val: u8) -> Pol4 { + Pol4::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol4) -> u8 { + Pol4::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol5 { + #[doc = "Tamper detect input bit 5 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 5 is active low."] + ActiveLow = 0x01, +} +impl Pol5 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol5 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol5 { + #[inline(always)] + fn from(val: u8) -> Pol5 { + Pol5::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol5) -> u8 { + Pol5::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol6 { + #[doc = "Tamper detect input bit 6 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 6 is active low."] + ActiveLow = 0x01, +} +impl Pol6 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol6 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol6 { + #[inline(always)] + fn from(val: u8) -> Pol6 { + Pol6::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol6) -> u8 { + Pol6::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pol7 { + #[doc = "Tamper detect input bit 7 is active high."] + ActiveHigh = 0x0, + #[doc = "Tamper detect input bit 7 is active low."] + ActiveLow = 0x01, +} +impl Pol7 { + #[inline(always)] + pub const fn from_bits(val: u8) -> Pol7 { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Pol7 { + #[inline(always)] + fn from(val: u8) -> Pol7 { + Pol7::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Pol7) -> u8 { + Pol7::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Swr { + #[doc = "Software Reset cleared."] + Cleared = 0x0, + #[doc = "Software Reset asserted."] + Asserted = 0x01, +} +impl Swr { + #[inline(always)] + pub const fn from_bits(val: u8) -> Swr { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Swr { + #[inline(always)] + fn from(val: u8) -> Swr { + Swr::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Swr) -> u8 { + Swr::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TmprEn { + #[doc = "Tamper Status reporting disabled."] + Disabled = 0x0, + #[doc = "Tamper Status reporting enabled."] + Enabled = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl TmprEn { + #[inline(always)] + pub const fn from_bits(val: u8) -> TmprEn { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TmprEn { + #[inline(always)] + fn from(val: u8) -> TmprEn { + TmprEn::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TmprEn) -> u8 { + TmprEn::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TmprSts { + #[doc = "No Tamper Detected."] + NoTamper = 0x0, + #[doc = "Tamper Event Detected."] + TamperDetected = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl TmprSts { + #[inline(always)] + pub const fn from_bits(val: u8) -> TmprSts { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TmprSts { + #[inline(always)] + fn from(val: u8) -> TmprSts { + TmprSts::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TmprSts) -> u8 { + TmprSts::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WakeupMode { + #[doc = "Tamper pin 0 is used as the tamper pin."] + TamperPin = 0x0, + #[doc = "Tamper pin 0 is used as a wakeup and hibernation pin."] + WakeupPin = 0x01, +} +impl WakeupMode { + #[inline(always)] + pub const fn from_bits(val: u8) -> WakeupMode { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for WakeupMode { + #[inline(always)] + fn from(val: u8) -> WakeupMode { + WakeupMode::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: WakeupMode) -> u8 { + WakeupMode::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WakeupStatus { + #[doc = "The wakeup and hibernation pin is in HiZ mode."] + HiZMode = 0x0, + #[doc = "The wakeup and hibernation pin is at logic 0. MCU is in sleep mode."] + Logic0 = 0x01, + #[doc = "The wakeup and hibernation pin is at logic 1. MCU is in sleep mode."] + Logic1 = 0x02, + _RESERVED_3 = 0x03, +} +impl WakeupStatus { + #[inline(always)] + pub const fn from_bits(val: u8) -> WakeupStatus { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for WakeupStatus { + #[inline(always)] + fn from(val: u8) -> WakeupStatus { + WakeupStatus::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: WakeupStatus) -> u8 { + WakeupStatus::to_bits(val) } } diff --git a/nxp-pac/src/meta_peripherals/mcxa/SCG.rs b/nxp-pac/src/meta_peripherals/mcxa/SCG.rs index 295f841..28bfcb8 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/SCG.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/SCG.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "System Clock Generator."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Scg { @@ -52,6 +53,11 @@ impl Scg { pub const fn sosccfg(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0108usize) as _) } } + #[doc = "SOSC Test Register."] + #[inline(always)] + pub const fn sosctest(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x01fcusize) as _) } + } #[doc = "SIRC Control Status Register."] #[inline(always)] pub const fn sirccsr(self) -> crate::pac::common::Reg { @@ -72,6 +78,11 @@ impl Scg { pub const fn sircstat(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0218usize) as _) } } + #[doc = "SIRC Test Register."] + #[inline(always)] + pub const fn sirctest(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x02fcusize) as _) } + } #[doc = "FIRC Control Status Register."] #[inline(always)] pub const fn firccsr(self) -> crate::pac::common::Reg { @@ -82,16 +93,99 @@ impl Scg { pub const fn firccfg(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0308usize) as _) } } + #[doc = "FIRC Trim Configuration Register."] + #[inline(always)] + pub const fn firctcfg(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x030cusize) as _) } + } #[doc = "FIRC Trim Register."] #[inline(always)] pub const fn firctrim(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0310usize) as _) } } + #[doc = "FIRC Auto-trimming Status Register."] + #[inline(always)] + pub const fn fircstat(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0318usize) as _) } + } + #[doc = "FIRC Test Register."] + #[inline(always)] + pub const fn firctest(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x03fcusize) as _) } + } #[doc = "ROSC Control Status Register."] #[inline(always)] pub const fn rosccsr(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0400usize) as _) } } + #[doc = "APLL Control Status Register."] + #[inline(always)] + pub const fn apllcsr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0500usize) as _) } + } + #[doc = "APLL Control Register."] + #[inline(always)] + pub const fn apllctrl(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0504usize) as _) } + } + #[doc = "APLL Status Register."] + #[inline(always)] + pub const fn apllstat(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0508usize) as _) } + } + #[doc = "APLL N Divider Register."] + #[inline(always)] + pub const fn apllndiv(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x050cusize) as _) } + } + #[doc = "APLL M Divider Register."] + #[inline(always)] + pub const fn apllmdiv(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0510usize) as _) } + } + #[doc = "APLL P Divider Register."] + #[inline(always)] + pub const fn apllpdiv(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0514usize) as _) } + } + #[doc = "APLL LOCK Configuration Register."] + #[inline(always)] + pub const fn aplllock_cnfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0518usize) as _) } + } + #[doc = "APLL SSCG Status Register."] + #[inline(always)] + pub const fn apllsscgstat( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0520usize) as _) } + } + #[doc = "APLL Spread Spectrum Control 0 Register."] + #[inline(always)] + pub const fn apllsscg0(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0524usize) as _) } + } + #[doc = "APLL Spread Spectrum Control 1 Register."] + #[inline(always)] + pub const fn apllsscg1(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0528usize) as _) } + } + #[doc = "APLL Test Status Register."] + #[inline(always)] + pub const fn apllteststat( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x05f8usize) as _) } + } + #[doc = "APLL Test Control Register."] + #[inline(always)] + pub const fn aplltestctrl( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x05fcusize) as _) } + } #[doc = "SPLL Control Status Register."] #[inline(always)] pub const fn spllcsr(self) -> crate::pac::common::Reg { @@ -146,2214 +240,4565 @@ impl Scg { pub const fn spllsscg1(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0628usize) as _) } } - #[doc = "LDO Control and Status Register."] + #[doc = "SPLL Test Status Register."] #[inline(always)] - pub const fn ldocsr(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0800usize) as _) } + pub const fn spllteststat( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x06f8usize) as _) } } -} -#[doc = "Clock Status Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Csr(pub u32); -impl Csr { - #[doc = "System Clock Source."] - #[must_use] + #[doc = "SPLL Test Control Register."] #[inline(always)] - pub const fn scs(&self) -> Scs { - let val = (self.0 >> 24usize) & 0x07; - Scs::from_bits(val as u8) + pub const fn splltestctrl( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x06fcusize) as _) } } - #[doc = "System Clock Source."] + #[doc = "UPLL Control Status Register."] #[inline(always)] - pub const fn set_scs(&mut self, val: Scs) { - self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + pub const fn upllcsr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0700usize) as _) } } -} -impl Default for Csr { + #[doc = "LDO Control and Status Register."] #[inline(always)] - fn default() -> Csr { - Csr(0) - } -} -impl core::fmt::Debug for Csr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Csr").field("scs", &self.scs()).finish() + pub const fn ldocsr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0800usize) as _) } } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Csr { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Csr {{ scs: {:?} }}", self.scs()) + #[doc = "LDO Test Register."] + #[inline(always)] + pub const fn ldotest(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x08fcusize) as _) } } } -#[doc = "FIRC Configuration Register."] +#[doc = "APLL Control Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Firccfg(pub u32); -impl Firccfg { - #[doc = "Frequency select."] +pub struct Apllcsr(pub u32); +impl Apllcsr { + #[doc = "APLL Power Enable."] #[must_use] #[inline(always)] - pub const fn freq_sel(&self) -> FreqSel { - let val = (self.0 >> 1usize) & 0x07; - FreqSel::from_bits(val as u8) + pub const fn apllpwren(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "Frequency select."] + #[doc = "APLL Power Enable."] #[inline(always)] - pub const fn set_freq_sel(&mut self, val: FreqSel) { - self.0 = (self.0 & !(0x07 << 1usize)) | (((val.to_bits() as u32) & 0x07) << 1usize); + pub const fn set_apllpwren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } -} -impl Default for Firccfg { + #[doc = "APLL Clock Enable."] + #[must_use] #[inline(always)] - fn default() -> Firccfg { - Firccfg(0) - } -} -impl core::fmt::Debug for Firccfg { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Firccfg") - .field("freq_sel", &self.freq_sel()) - .finish() + pub const fn apllclken(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Firccfg { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Firccfg {{ freq_sel: {:?} }}", self.freq_sel()) + #[doc = "APLL Clock Enable."] + #[inline(always)] + pub const fn set_apllclken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } -} -#[doc = "FIRC Control Status Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Firccsr(pub u32); -impl Firccsr { - #[doc = "FIRC Enable."] + #[doc = "APLL Stop Enable."] #[must_use] #[inline(always)] - pub const fn fircen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub const fn apllsten(&self) -> Apllsten { + let val = (self.0 >> 2usize) & 0x01; + Apllsten::from_bits(val as u8) } - #[doc = "FIRC Enable."] + #[doc = "APLL Stop Enable."] #[inline(always)] - pub const fn set_fircen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub const fn set_apllsten(&mut self, val: Apllsten) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); } - #[doc = "FIRC Stop Enable."] + #[doc = "Free running mode clock stable."] #[must_use] #[inline(always)] - pub const fn fircsten(&self) -> Fircsten { - let val = (self.0 >> 1usize) & 0x01; - Fircsten::from_bits(val as u8) + pub const fn frm_clockstable(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 } - #[doc = "FIRC Stop Enable."] + #[doc = "Free running mode clock stable."] #[inline(always)] - pub const fn set_fircsten(&mut self, val: Fircsten) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_frm_clockstable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "FIRC 45 MHz Clock to peripherals Enable."] + #[doc = "APLL Clock Monitor."] #[must_use] #[inline(always)] - pub const fn firc_sclk_periph_en(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn apllcm(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "FIRC 45 MHz Clock to peripherals Enable."] + #[doc = "APLL Clock Monitor."] #[inline(always)] - pub const fn set_firc_sclk_periph_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub const fn set_apllcm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "FRO_HF Clock to peripherals Enable."] + #[doc = "APLL Clock Monitor Reset Enable."] #[must_use] #[inline(always)] - pub const fn firc_fclk_periph_en(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn apllcmre(&self) -> Apllcmre { + let val = (self.0 >> 17usize) & 0x01; + Apllcmre::from_bits(val as u8) } - #[doc = "FRO_HF Clock to peripherals Enable."] + #[doc = "APLL Clock Monitor Reset Enable."] #[inline(always)] - pub const fn set_firc_fclk_periph_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + pub const fn set_apllcmre(&mut self, val: Apllcmre) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); } #[doc = "Lock Register."] #[must_use] #[inline(always)] - pub const fn lk(&self) -> FirccsrLk { + pub const fn lk(&self) -> ApllcsrLk { let val = (self.0 >> 23usize) & 0x01; - FirccsrLk::from_bits(val as u8) + ApllcsrLk::from_bits(val as u8) } #[doc = "Lock Register."] #[inline(always)] - pub const fn set_lk(&mut self, val: FirccsrLk) { + pub const fn set_lk(&mut self, val: ApllcsrLk) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); } - #[doc = "FIRC Valid status."] + #[doc = "APLL LOCK."] #[must_use] #[inline(always)] - pub const fn fircvld(&self) -> Fircvld { + pub const fn apll_lock(&self) -> ApllLock { let val = (self.0 >> 24usize) & 0x01; - Fircvld::from_bits(val as u8) + ApllLock::from_bits(val as u8) } - #[doc = "FIRC Valid status."] + #[doc = "APLL LOCK."] #[inline(always)] - pub const fn set_fircvld(&mut self, val: Fircvld) { + pub const fn set_apll_lock(&mut self, val: ApllLock) { self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); } - #[doc = "FIRC Selected."] + #[doc = "APLL Selected."] #[must_use] #[inline(always)] - pub const fn fircsel(&self) -> bool { + pub const fn apllsel(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "FIRC Selected."] + #[doc = "APLL Selected."] #[inline(always)] - pub const fn set_fircsel(&mut self, val: bool) { + pub const fn set_apllsel(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "FIRC Clock Error."] + #[doc = "APLL Clock Error."] #[must_use] #[inline(always)] - pub const fn fircerr(&self) -> Fircerr { + pub const fn apllerr(&self) -> Apllerr { let val = (self.0 >> 26usize) & 0x01; - Fircerr::from_bits(val as u8) + Apllerr::from_bits(val as u8) } - #[doc = "FIRC Clock Error."] + #[doc = "APLL Clock Error."] #[inline(always)] - pub const fn set_fircerr(&mut self, val: Fircerr) { + pub const fn set_apllerr(&mut self, val: Apllerr) { self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); } - #[doc = "FIRC Clock Error Interrupt Enable."] - #[must_use] - #[inline(always)] - pub const fn fircerr_ie(&self) -> FircerrIe { - let val = (self.0 >> 27usize) & 0x01; - FircerrIe::from_bits(val as u8) - } - #[doc = "FIRC Clock Error Interrupt Enable."] - #[inline(always)] - pub const fn set_fircerr_ie(&mut self, val: FircerrIe) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); - } - #[doc = "FIRC Accurate Interrupt Enable."] + #[doc = "APLL LOCK Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn fircacc_ie(&self) -> FircaccIe { + pub const fn apll_lock_ie(&self) -> bool { let val = (self.0 >> 30usize) & 0x01; - FircaccIe::from_bits(val as u8) - } - #[doc = "FIRC Accurate Interrupt Enable."] - #[inline(always)] - pub const fn set_fircacc_ie(&mut self, val: FircaccIe) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); - } - #[doc = "FIRC Frequency Accurate."] - #[must_use] - #[inline(always)] - pub const fn fircacc(&self) -> Fircacc { - let val = (self.0 >> 31usize) & 0x01; - Fircacc::from_bits(val as u8) + val != 0 } - #[doc = "FIRC Frequency Accurate."] + #[doc = "APLL LOCK Interrupt Enable."] #[inline(always)] - pub const fn set_fircacc(&mut self, val: Fircacc) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_apll_lock_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); } } -impl Default for Firccsr { +impl Default for Apllcsr { #[inline(always)] - fn default() -> Firccsr { - Firccsr(0) + fn default() -> Apllcsr { + Apllcsr(0) } } -impl core::fmt::Debug for Firccsr { +impl core::fmt::Debug for Apllcsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Firccsr") - .field("fircen", &self.fircen()) - .field("fircsten", &self.fircsten()) - .field("firc_sclk_periph_en", &self.firc_sclk_periph_en()) - .field("firc_fclk_periph_en", &self.firc_fclk_periph_en()) + f.debug_struct("Apllcsr") + .field("apllpwren", &self.apllpwren()) + .field("apllclken", &self.apllclken()) + .field("apllsten", &self.apllsten()) + .field("frm_clockstable", &self.frm_clockstable()) + .field("apllcm", &self.apllcm()) + .field("apllcmre", &self.apllcmre()) .field("lk", &self.lk()) - .field("fircvld", &self.fircvld()) - .field("fircsel", &self.fircsel()) - .field("fircerr", &self.fircerr()) - .field("fircerr_ie", &self.fircerr_ie()) - .field("fircacc_ie", &self.fircacc_ie()) - .field("fircacc", &self.fircacc()) + .field("apll_lock", &self.apll_lock()) + .field("apllsel", &self.apllsel()) + .field("apllerr", &self.apllerr()) + .field("apll_lock_ie", &self.apll_lock_ie()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Firccsr { +impl defmt::Format for Apllcsr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Firccsr {{ fircen: {=bool:?}, fircsten: {:?}, firc_sclk_periph_en: {=bool:?}, firc_fclk_periph_en: {=bool:?}, lk: {:?}, fircvld: {:?}, fircsel: {=bool:?}, fircerr: {:?}, fircerr_ie: {:?}, fircacc_ie: {:?}, fircacc: {:?} }}", - self.fircen(), - self.fircsten(), - self.firc_sclk_periph_en(), - self.firc_fclk_periph_en(), + "Apllcsr {{ apllpwren: {=bool:?}, apllclken: {=bool:?}, apllsten: {:?}, frm_clockstable: {=bool:?}, apllcm: {=bool:?}, apllcmre: {:?}, lk: {:?}, apll_lock: {:?}, apllsel: {=bool:?}, apllerr: {:?}, apll_lock_ie: {=bool:?} }}", + self.apllpwren(), + self.apllclken(), + self.apllsten(), + self.frm_clockstable(), + self.apllcm(), + self.apllcmre(), self.lk(), - self.fircvld(), - self.fircsel(), - self.fircerr(), - self.fircerr_ie(), - self.fircacc_ie(), - self.fircacc() + self.apll_lock(), + self.apllsel(), + self.apllerr(), + self.apll_lock_ie() ) } } -#[doc = "FIRC Trim Register."] +#[doc = "APLL Control Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Firctrim(pub u32); -impl Firctrim { - #[doc = "Trim Fine."] +pub struct Apllctrl(pub u32); +impl Apllctrl { + #[doc = "Bandwidth select R (resistor) value."] #[must_use] #[inline(always)] - pub const fn trimfine(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; + pub const fn selr(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; val as u8 } - #[doc = "Trim Fine."] + #[doc = "Bandwidth select R (resistor) value."] #[inline(always)] - pub const fn set_trimfine(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub const fn set_selr(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); } - #[doc = "Trim Coarse."] + #[doc = "Bandwidth select I (integration) value."] #[must_use] #[inline(always)] - pub const fn trimcoar(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x3f; + pub const fn seli(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x3f; val as u8 } - #[doc = "Trim Coarse."] + #[doc = "Bandwidth select I (integration) value."] #[inline(always)] - pub const fn set_trimcoar(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + pub const fn set_seli(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 4usize)) | (((val as u32) & 0x3f) << 4usize); } - #[doc = "Trim Temperature."] + #[doc = "Bandwidth select P (proportional) value."] #[must_use] #[inline(always)] - pub const fn trimtemp(&self) -> u8 { - let val = (self.0 >> 16usize) & 0x0f; + pub const fn selp(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x1f; val as u8 } - #[doc = "Trim Temperature."] + #[doc = "Bandwidth select P (proportional) value."] #[inline(always)] - pub const fn set_trimtemp(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 16usize)) | (((val as u32) & 0x0f) << 16usize); + pub const fn set_selp(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize); } - #[doc = "Trim Start."] + #[doc = "Bypass of Divide-by-2 Divider."] #[must_use] #[inline(always)] - pub const fn trimstart(&self) -> u8 { - let val = (self.0 >> 24usize) & 0x3f; - val as u8 + pub const fn bypasspostdiv2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 } - #[doc = "Trim Start."] + #[doc = "Bypass of Divide-by-2 Divider."] #[inline(always)] - pub const fn set_trimstart(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 24usize)) | (((val as u32) & 0x3f) << 24usize); + pub const fn set_bypasspostdiv2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } -} -impl Default for Firctrim { + #[doc = "Up Limiter."] + #[must_use] #[inline(always)] - fn default() -> Firctrim { - Firctrim(0) + pub const fn limupoff(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 } -} -impl core::fmt::Debug for Firctrim { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Firctrim") - .field("trimfine", &self.trimfine()) - .field("trimcoar", &self.trimcoar()) - .field("trimtemp", &self.trimtemp()) - .field("trimstart", &self.trimstart()) - .finish() + #[doc = "Up Limiter."] + #[inline(always)] + pub const fn set_limupoff(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Firctrim { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Firctrim {{ trimfine: {=u8:?}, trimcoar: {=u8:?}, trimtemp: {=u8:?}, trimstart: {=u8:?} }}", - self.trimfine(), - self.trimcoar(), - self.trimtemp(), - self.trimstart() - ) + #[doc = "Control of the bandwidth of the PLL."] + #[must_use] + #[inline(always)] + pub const fn banddirect(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 } -} -#[doc = "LDO Control and Status Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Ldocsr(pub u32); -impl Ldocsr { - #[doc = "LDO Enable."] + #[doc = "Control of the bandwidth of the PLL."] + #[inline(always)] + pub const fn set_banddirect(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bypass of the predivider."] #[must_use] #[inline(always)] - pub const fn ldoen(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; + pub const fn bypassprediv(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "LDO Enable."] + #[doc = "Bypass of the predivider."] #[inline(always)] - pub const fn set_ldoen(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub const fn set_bypassprediv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "LDO output voltage select."] + #[doc = "Bypass of the postdivider."] #[must_use] #[inline(always)] - pub const fn vout_sel(&self) -> VoutSel { - let val = (self.0 >> 1usize) & 0x07; - VoutSel::from_bits(val as u8) + pub const fn bypasspostdiv(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 } - #[doc = "LDO output voltage select."] + #[doc = "Bypass of the postdivider."] #[inline(always)] - pub const fn set_vout_sel(&mut self, val: VoutSel) { - self.0 = (self.0 & !(0x07 << 1usize)) | (((val.to_bits() as u32) & 0x07) << 1usize); + pub const fn set_bypasspostdiv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "LDO Bypass."] + #[doc = "Free Running Mode Enable."] #[must_use] #[inline(always)] - pub const fn ldobypass(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; + pub const fn frm(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; val != 0 } - #[doc = "LDO Bypass."] + #[doc = "Free Running Mode Enable."] #[inline(always)] - pub const fn set_ldobypass(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub const fn set_frm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); } - #[doc = "LDO VOUT OK Inform."] + #[doc = "Skew mode."] #[must_use] #[inline(always)] - pub const fn vout_ok(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; + pub const fn skew_en(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; val != 0 } - #[doc = "LDO VOUT OK Inform."] + #[doc = "Skew mode."] #[inline(always)] - pub const fn set_vout_ok(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_skew_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Clock Source."] + #[must_use] + #[inline(always)] + pub const fn source(&self) -> ApllctrlSource { + let val = (self.0 >> 25usize) & 0x03; + ApllctrlSource::from_bits(val as u8) + } + #[doc = "Clock Source."] + #[inline(always)] + pub const fn set_source(&mut self, val: ApllctrlSource) { + self.0 = (self.0 & !(0x03 << 25usize)) | (((val.to_bits() as u32) & 0x03) << 25usize); } } -impl Default for Ldocsr { +impl Default for Apllctrl { #[inline(always)] - fn default() -> Ldocsr { - Ldocsr(0) + fn default() -> Apllctrl { + Apllctrl(0) } } -impl core::fmt::Debug for Ldocsr { +impl core::fmt::Debug for Apllctrl { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Ldocsr") - .field("ldoen", &self.ldoen()) - .field("vout_sel", &self.vout_sel()) - .field("ldobypass", &self.ldobypass()) - .field("vout_ok", &self.vout_ok()) + f.debug_struct("Apllctrl") + .field("selr", &self.selr()) + .field("seli", &self.seli()) + .field("selp", &self.selp()) + .field("bypasspostdiv2", &self.bypasspostdiv2()) + .field("limupoff", &self.limupoff()) + .field("banddirect", &self.banddirect()) + .field("bypassprediv", &self.bypassprediv()) + .field("bypasspostdiv", &self.bypasspostdiv()) + .field("frm", &self.frm()) + .field("skew_en", &self.skew_en()) + .field("source", &self.source()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Ldocsr { +impl defmt::Format for Apllctrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ldocsr {{ ldoen: {=bool:?}, vout_sel: {:?}, ldobypass: {=bool:?}, vout_ok: {=bool:?} }}", - self.ldoen(), - self.vout_sel(), - self.ldobypass(), - self.vout_ok() + "Apllctrl {{ selr: {=u8:?}, seli: {=u8:?}, selp: {=u8:?}, bypasspostdiv2: {=bool:?}, limupoff: {=bool:?}, banddirect: {=bool:?}, bypassprediv: {=bool:?}, bypasspostdiv: {=bool:?}, frm: {=bool:?}, skew_en: {=bool:?}, source: {:?} }}", + self.selr(), + self.seli(), + self.selp(), + self.bypasspostdiv2(), + self.limupoff(), + self.banddirect(), + self.bypassprediv(), + self.bypasspostdiv(), + self.frm(), + self.skew_en(), + self.source() ) } } -#[doc = "Parameter Register."] +#[doc = "APLL LOCK Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Param(pub u32); -impl Param { - #[doc = "SOSC Clock Present."] +pub struct AplllockCnfg(pub u32); +impl AplllockCnfg { + #[doc = "Configures the number of reference clocks to count before APLL is considered locked."] #[must_use] #[inline(always)] - pub const fn soscclkpres(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 - } - #[doc = "SOSC Clock Present."] - #[inline(always)] - pub const fn set_soscclkpres(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub const fn lock_time(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x0001_ffff; + val as u32 } - #[doc = "SIRC Clock Present."] - #[must_use] + #[doc = "Configures the number of reference clocks to count before APLL is considered locked."] #[inline(always)] - pub const fn sircclkpres(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub const fn set_lock_time(&mut self, val: u32) { + self.0 = (self.0 & !(0x0001_ffff << 0usize)) | (((val as u32) & 0x0001_ffff) << 0usize); } - #[doc = "SIRC Clock Present."] +} +impl Default for AplllockCnfg { #[inline(always)] - pub const fn set_sircclkpres(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + fn default() -> AplllockCnfg { + AplllockCnfg(0) } - #[doc = "FIRC Clock Present."] - #[must_use] - #[inline(always)] - pub const fn fircclkpres(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 +} +impl core::fmt::Debug for AplllockCnfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AplllockCnfg") + .field("lock_time", &self.lock_time()) + .finish() } - #[doc = "FIRC Clock Present."] - #[inline(always)] - pub const fn set_fircclkpres(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for AplllockCnfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "AplllockCnfg {{ lock_time: {=u32:?} }}", + self.lock_time() + ) } - #[doc = "ROSC Clock Present."] +} +#[doc = "APLL M Divider Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Apllmdiv(pub u32); +impl Apllmdiv { + #[doc = "Feedback divider divider ratio (M-divider)."] #[must_use] #[inline(always)] - pub const fn roscclkpres(&self) -> bool { - let val = (self.0 >> 4usize) & 0x01; - val != 0 + pub const fn mdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 } - #[doc = "ROSC Clock Present."] + #[doc = "Feedback divider divider ratio (M-divider)."] #[inline(always)] - pub const fn set_roscclkpres(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub const fn set_mdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); } - #[doc = "SPLL Clock Present."] + #[doc = "Feedback ratio change request."] #[must_use] #[inline(always)] - pub const fn spllclkpres(&self) -> bool { - let val = (self.0 >> 6usize) & 0x01; + pub const fn mreq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; val != 0 } - #[doc = "SPLL Clock Present."] + #[doc = "Feedback ratio change request."] #[inline(always)] - pub const fn set_spllclkpres(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + pub const fn set_mreq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for Param { +impl Default for Apllmdiv { #[inline(always)] - fn default() -> Param { - Param(0) + fn default() -> Apllmdiv { + Apllmdiv(0) } } -impl core::fmt::Debug for Param { +impl core::fmt::Debug for Apllmdiv { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Param") - .field("soscclkpres", &self.soscclkpres()) - .field("sircclkpres", &self.sircclkpres()) - .field("fircclkpres", &self.fircclkpres()) - .field("roscclkpres", &self.roscclkpres()) - .field("spllclkpres", &self.spllclkpres()) + f.debug_struct("Apllmdiv") + .field("mdiv", &self.mdiv()) + .field("mreq", &self.mreq()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Param { +impl defmt::Format for Apllmdiv { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Param {{ soscclkpres: {=bool:?}, sircclkpres: {=bool:?}, fircclkpres: {=bool:?}, roscclkpres: {=bool:?}, spllclkpres: {=bool:?} }}", - self.soscclkpres(), - self.sircclkpres(), - self.fircclkpres(), - self.roscclkpres(), - self.spllclkpres() + "Apllmdiv {{ mdiv: {=u16:?}, mreq: {=bool:?} }}", + self.mdiv(), + self.mreq() ) } } -#[doc = "Run Clock Control Register."] +#[doc = "APLL N Divider Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Rccr(pub u32); -impl Rccr { - #[doc = "System Clock Source."] +pub struct Apllndiv(pub u32); +impl Apllndiv { + #[doc = "Predivider divider ratio (N-divider)."] #[must_use] #[inline(always)] - pub const fn scs(&self) -> Scs { - let val = (self.0 >> 24usize) & 0x07; - Scs::from_bits(val as u8) + pub const fn ndiv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } - #[doc = "System Clock Source."] + #[doc = "Predivider divider ratio (N-divider)."] #[inline(always)] - pub const fn set_scs(&mut self, val: Scs) { - self.0 = (self.0 & !(0x07 << 24usize)) | (((val.to_bits() as u32) & 0x07) << 24usize); + pub const fn set_ndiv(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Predivider ratio change request."] + #[must_use] + #[inline(always)] + pub const fn nreq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Predivider ratio change request."] + #[inline(always)] + pub const fn set_nreq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for Rccr { +impl Default for Apllndiv { #[inline(always)] - fn default() -> Rccr { - Rccr(0) + fn default() -> Apllndiv { + Apllndiv(0) } } -impl core::fmt::Debug for Rccr { +impl core::fmt::Debug for Apllndiv { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Rccr").field("scs", &self.scs()).finish() + f.debug_struct("Apllndiv") + .field("ndiv", &self.ndiv()) + .field("nreq", &self.nreq()) + .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Rccr { +impl defmt::Format for Apllndiv { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Rccr {{ scs: {:?} }}", self.scs()) + defmt::write!( + f, + "Apllndiv {{ ndiv: {=u8:?}, nreq: {=bool:?} }}", + self.ndiv(), + self.nreq() + ) } } -#[doc = "ROSC Control Status Register."] +#[doc = "APLL P Divider Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Rosccsr(pub u32); -impl Rosccsr { - #[doc = "Lock Register."] +pub struct Apllpdiv(pub u32); +impl Apllpdiv { + #[doc = "Postdivider divider ratio (P-divider)."] #[must_use] #[inline(always)] - pub const fn lk(&self) -> RosccsrLk { - let val = (self.0 >> 23usize) & 0x01; - RosccsrLk::from_bits(val as u8) + pub const fn pdiv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 } - #[doc = "Lock Register."] + #[doc = "Postdivider divider ratio (P-divider)."] #[inline(always)] - pub const fn set_lk(&mut self, val: RosccsrLk) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + pub const fn set_pdiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); } - #[doc = "ROSC Valid."] + #[doc = "Postdivider ratio change request."] #[must_use] #[inline(always)] - pub const fn roscvld(&self) -> Roscvld { - let val = (self.0 >> 24usize) & 0x01; - Roscvld::from_bits(val as u8) + pub const fn preq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 } - #[doc = "ROSC Valid."] + #[doc = "Postdivider ratio change request."] #[inline(always)] - pub const fn set_roscvld(&mut self, val: Roscvld) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + pub const fn set_preq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } - #[doc = "ROSC Selected."] - #[must_use] +} +impl Default for Apllpdiv { #[inline(always)] - pub const fn roscsel(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 + fn default() -> Apllpdiv { + Apllpdiv(0) } - #[doc = "ROSC Selected."] - #[inline(always)] - pub const fn set_roscsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); +} +impl core::fmt::Debug for Apllpdiv { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Apllpdiv") + .field("pdiv", &self.pdiv()) + .field("preq", &self.preq()) + .finish() } - #[doc = "ROSC Clock Error."] +} +#[cfg(feature = "defmt")] +impl defmt::Format for Apllpdiv { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Apllpdiv {{ pdiv: {=u8:?}, preq: {=bool:?} }}", + self.pdiv(), + self.preq() + ) + } +} +#[doc = "APLL Spread Spectrum Control 0 Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Apllsscg0(pub u32); +impl Apllsscg0 { + #[doc = "SS_MDIV."] #[must_use] #[inline(always)] - pub const fn roscerr(&self) -> Roscerr { - let val = (self.0 >> 26usize) & 0x01; - Roscerr::from_bits(val as u8) + pub const fn ss_mdiv_lsb(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 } - #[doc = "ROSC Clock Error."] + #[doc = "SS_MDIV."] #[inline(always)] - pub const fn set_roscerr(&mut self, val: Roscerr) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + pub const fn set_ss_mdiv_lsb(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); } } -impl Default for Rosccsr { +impl Default for Apllsscg0 { #[inline(always)] - fn default() -> Rosccsr { - Rosccsr(0) + fn default() -> Apllsscg0 { + Apllsscg0(0) } } -impl core::fmt::Debug for Rosccsr { +impl core::fmt::Debug for Apllsscg0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Rosccsr") - .field("lk", &self.lk()) - .field("roscvld", &self.roscvld()) - .field("roscsel", &self.roscsel()) - .field("roscerr", &self.roscerr()) + f.debug_struct("Apllsscg0") + .field("ss_mdiv_lsb", &self.ss_mdiv_lsb()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Rosccsr { +impl defmt::Format for Apllsscg0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Rosccsr {{ lk: {:?}, roscvld: {:?}, roscsel: {=bool:?}, roscerr: {:?} }}", - self.lk(), - self.roscvld(), - self.roscsel(), - self.roscerr() + "Apllsscg0 {{ ss_mdiv_lsb: {=u32:?} }}", + self.ss_mdiv_lsb() ) } } -#[doc = "SIRC Control Status Register."] +#[doc = "APLL Spread Spectrum Control 1 Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sirccsr(pub u32); -impl Sirccsr { - #[doc = "SIRC Stop Enable."] +pub struct Apllsscg1(pub u32); +impl Apllsscg1 { + #[doc = "SS_MDIV\\[32\\]."] #[must_use] #[inline(always)] - pub const fn sircsten(&self) -> bool { + pub const fn ss_mdiv_msb(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SS_MDIV\\[32\\]."] + #[inline(always)] + pub const fn set_ss_mdiv_msb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SS_MDIV\\[32:0\\] change request."] + #[must_use] + #[inline(always)] + pub const fn ss_mdiv_req(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "SIRC Stop Enable."] + #[doc = "SS_MDIV\\[32:0\\] change request."] #[inline(always)] - pub const fn set_sircsten(&mut self, val: bool) { + pub const fn set_ss_mdiv_req(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "SIRC Clock to Peripherals Enable."] + #[doc = "Modulation Frequency Control."] #[must_use] #[inline(always)] - pub const fn sirc_clk_periph_en(&self) -> bool { - let val = (self.0 >> 5usize) & 0x01; - val != 0 + pub const fn mf(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x07; + val as u8 } - #[doc = "SIRC Clock to Peripherals Enable."] + #[doc = "Modulation Frequency Control."] #[inline(always)] - pub const fn set_sirc_clk_periph_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + pub const fn set_mf(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u32) & 0x07) << 2usize); } - #[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)."] + #[doc = "Modulation Depth Control."] #[must_use] #[inline(always)] - pub const fn sirctren(&self) -> bool { - let val = (self.0 >> 8usize) & 0x01; - val != 0 + pub const fn mr(&self) -> u8 { + let val = (self.0 >> 5usize) & 0x07; + val as u8 } - #[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)."] + #[doc = "Modulation Depth Control."] #[inline(always)] - pub const fn set_sirctren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + pub const fn set_mr(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u32) & 0x07) << 5usize); } - #[doc = "SIRC Trim Update."] + #[doc = "Modulation Waveform Control."] #[must_use] #[inline(always)] - pub const fn sirctrup(&self) -> bool { - let val = (self.0 >> 9usize) & 0x01; - val != 0 + pub const fn mc(&self) -> Apllsscg1Mc { + let val = (self.0 >> 8usize) & 0x03; + Apllsscg1Mc::from_bits(val as u8) } - #[doc = "SIRC Trim Update."] + #[doc = "Modulation Waveform Control."] #[inline(always)] - pub const fn set_sirctrup(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + pub const fn set_mc(&mut self, val: Apllsscg1Mc) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } - #[doc = "SIRC TRIM LOCK."] + #[doc = "Dither Enable."] #[must_use] #[inline(always)] - pub const fn trim_lock(&self) -> TrimLockVal { + pub const fn dither(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; - TrimLockVal::from_bits(val as u8) + val != 0 } - #[doc = "SIRC TRIM LOCK."] + #[doc = "Dither Enable."] #[inline(always)] - pub const fn set_trim_lock(&mut self, val: TrimLockVal) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_dither(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "Coarse Auto Trim Bypass."] + #[doc = "SS_MDIV select."] #[must_use] #[inline(always)] - pub const fn coarse_trim_bypass(&self) -> bool { + pub const fn sel_ss_mdiv(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "Coarse Auto Trim Bypass."] + #[doc = "SS_MDIV select."] #[inline(always)] - pub const fn set_coarse_trim_bypass(&mut self, val: bool) { + pub const fn set_sel_ss_mdiv(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "Lock Register."] + #[doc = "SSCG Power Down."] #[must_use] #[inline(always)] - pub const fn lk(&self) -> SirccsrLk { - let val = (self.0 >> 23usize) & 0x01; - SirccsrLk::from_bits(val as u8) + pub const fn ss_pd(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 } - #[doc = "Lock Register."] + #[doc = "SSCG Power Down."] #[inline(always)] - pub const fn set_lk(&mut self, val: SirccsrLk) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + pub const fn set_ss_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } - #[doc = "SIRC Valid."] - #[must_use] +} +impl Default for Apllsscg1 { #[inline(always)] - pub const fn sircvld(&self) -> Sircvld { - let val = (self.0 >> 24usize) & 0x01; - Sircvld::from_bits(val as u8) + fn default() -> Apllsscg1 { + Apllsscg1(0) } - #[doc = "SIRC Valid."] - #[inline(always)] - pub const fn set_sircvld(&mut self, val: Sircvld) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); +} +impl core::fmt::Debug for Apllsscg1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Apllsscg1") + .field("ss_mdiv_msb", &self.ss_mdiv_msb()) + .field("ss_mdiv_req", &self.ss_mdiv_req()) + .field("mf", &self.mf()) + .field("mr", &self.mr()) + .field("mc", &self.mc()) + .field("dither", &self.dither()) + .field("sel_ss_mdiv", &self.sel_ss_mdiv()) + .field("ss_pd", &self.ss_pd()) + .finish() } - #[doc = "SIRC Selected."] +} +#[cfg(feature = "defmt")] +impl defmt::Format for Apllsscg1 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Apllsscg1 {{ ss_mdiv_msb: {=bool:?}, ss_mdiv_req: {=bool:?}, mf: {=u8:?}, mr: {=u8:?}, mc: {:?}, dither: {=bool:?}, sel_ss_mdiv: {=bool:?}, ss_pd: {=bool:?} }}", + self.ss_mdiv_msb(), + self.ss_mdiv_req(), + self.mf(), + self.mr(), + self.mc(), + self.dither(), + self.sel_ss_mdiv(), + self.ss_pd() + ) + } +} +#[doc = "APLL SSCG Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Apllsscgstat(pub u32); +impl Apllsscgstat { + #[doc = "SS_MDIV change acknowledge."] #[must_use] #[inline(always)] - pub const fn sircsel(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; + pub const fn ss_mdiv_ack(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "SIRC Selected."] + #[doc = "SS_MDIV change acknowledge."] #[inline(always)] - pub const fn set_sircsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + pub const fn set_ss_mdiv_ack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "SIRC Clock Error."] - #[must_use] +} +impl Default for Apllsscgstat { #[inline(always)] - pub const fn sircerr(&self) -> Sircerr { - let val = (self.0 >> 26usize) & 0x01; - Sircerr::from_bits(val as u8) - } - #[doc = "SIRC Clock Error."] - #[inline(always)] - pub const fn set_sircerr(&mut self, val: Sircerr) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); - } - #[doc = "SIRC Clock Error Interrupt Enable."] - #[must_use] - #[inline(always)] - pub const fn sircerr_ie(&self) -> SircerrIe { - let val = (self.0 >> 27usize) & 0x01; - SircerrIe::from_bits(val as u8) - } - #[doc = "SIRC Clock Error Interrupt Enable."] - #[inline(always)] - pub const fn set_sircerr_ie(&mut self, val: SircerrIe) { - self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); - } -} -impl Default for Sirccsr { - #[inline(always)] - fn default() -> Sirccsr { - Sirccsr(0) + fn default() -> Apllsscgstat { + Apllsscgstat(0) } } -impl core::fmt::Debug for Sirccsr { +impl core::fmt::Debug for Apllsscgstat { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sirccsr") - .field("sircsten", &self.sircsten()) - .field("sirc_clk_periph_en", &self.sirc_clk_periph_en()) - .field("sirctren", &self.sirctren()) - .field("sirctrup", &self.sirctrup()) - .field("trim_lock", &self.trim_lock()) - .field("coarse_trim_bypass", &self.coarse_trim_bypass()) - .field("lk", &self.lk()) - .field("sircvld", &self.sircvld()) - .field("sircsel", &self.sircsel()) - .field("sircerr", &self.sircerr()) - .field("sircerr_ie", &self.sircerr_ie()) + f.debug_struct("Apllsscgstat") + .field("ss_mdiv_ack", &self.ss_mdiv_ack()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sirccsr { +impl defmt::Format for Apllsscgstat { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sirccsr {{ sircsten: {=bool:?}, sirc_clk_periph_en: {=bool:?}, sirctren: {=bool:?}, sirctrup: {=bool:?}, trim_lock: {:?}, coarse_trim_bypass: {=bool:?}, lk: {:?}, sircvld: {:?}, sircsel: {=bool:?}, sircerr: {:?}, sircerr_ie: {:?} }}", - self.sircsten(), - self.sirc_clk_periph_en(), - self.sirctren(), - self.sirctrup(), - self.trim_lock(), - self.coarse_trim_bypass(), - self.lk(), - self.sircvld(), - self.sircsel(), - self.sircerr(), - self.sircerr_ie() + "Apllsscgstat {{ ss_mdiv_ack: {=bool:?} }}", + self.ss_mdiv_ack() ) } } -#[doc = "SIRC Auto-trimming Status Register."] +#[doc = "APLL Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sircstat(pub u32); -impl Sircstat { - #[doc = "CCO Trim."] +pub struct Apllstat(pub u32); +impl Apllstat { + #[doc = "Lock detector output (active high)."] #[must_use] #[inline(always)] - pub const fn ccotrim(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; - val as u8 + pub const fn lock(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 } - #[doc = "CCO Trim."] + #[doc = "Lock detector output (active high)."] #[inline(always)] - pub const fn set_ccotrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + pub const fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "CL Trim."] + #[doc = "Predivider(N) ratio change acknowledge."] #[must_use] #[inline(always)] - pub const fn cltrim(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x3f; - val as u8 + pub const fn ndivack(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 } - #[doc = "CL Trim."] + #[doc = "Predivider(N) ratio change acknowledge."] #[inline(always)] - pub const fn set_cltrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + pub const fn set_ndivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Feedback(M) divider ratio change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn mdivack(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Feedback(M) divider ratio change acknowledge."] + #[inline(always)] + pub const fn set_mdivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Postdivider(P) ratio change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn pdivack(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Postdivider(P) ratio change acknowledge."] + #[inline(always)] + pub const fn set_pdivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Free running detector (active high)."] + #[must_use] + #[inline(always)] + pub const fn frmdet(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Free running detector (active high)."] + #[inline(always)] + pub const fn set_frmdet(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } } -impl Default for Sircstat { +impl Default for Apllstat { #[inline(always)] - fn default() -> Sircstat { - Sircstat(0) + fn default() -> Apllstat { + Apllstat(0) } } -impl core::fmt::Debug for Sircstat { +impl core::fmt::Debug for Apllstat { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sircstat") - .field("ccotrim", &self.ccotrim()) - .field("cltrim", &self.cltrim()) + f.debug_struct("Apllstat") + .field("lock", &self.lock()) + .field("ndivack", &self.ndivack()) + .field("mdivack", &self.mdivack()) + .field("pdivack", &self.pdivack()) + .field("frmdet", &self.frmdet()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sircstat { +impl defmt::Format for Apllstat { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sircstat {{ ccotrim: {=u8:?}, cltrim: {=u8:?} }}", - self.ccotrim(), - self.cltrim() + "Apllstat {{ lock: {=bool:?}, ndivack: {=bool:?}, mdivack: {=bool:?}, pdivack: {=bool:?}, frmdet: {=bool:?} }}", + self.lock(), + self.ndivack(), + self.mdivack(), + self.pdivack(), + self.frmdet() ) } } -#[doc = "SIRC Trim Configuration Register."] +#[doc = "APLL Test Control Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sirctcfg(pub u32); -impl Sirctcfg { - #[doc = "Trim Source."] +pub struct Aplltestctrl(pub u32); +impl Aplltestctrl { + #[doc = "Input to functional test the predivider (N-divider)."] #[must_use] #[inline(always)] - pub const fn trimsrc(&self) -> Trimsrc { - let val = (self.0 >> 0usize) & 0x03; - Trimsrc::from_bits(val as u8) + pub const fn nfunctest(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 } - #[doc = "Trim Source."] + #[doc = "Input to functional test the predivider (N-divider)."] #[inline(always)] - pub const fn set_trimsrc(&mut self, val: Trimsrc) { - self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + pub const fn set_nfunctest(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); } - #[doc = "SIRC Trim Pre-divider."] + #[doc = "Input to functional test the feedback-divider (M-divider)."] #[must_use] #[inline(always)] - pub const fn trimdiv(&self) -> u8 { - let val = (self.0 >> 16usize) & 0x7f; + pub const fn mfunctest(&self) -> u16 { + let val = (self.0 >> 7usize) & 0x7fff; + val as u16 + } + #[doc = "Input to functional test the feedback-divider (M-divider)."] + #[inline(always)] + pub const fn set_mfunctest(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 7usize)) | (((val as u32) & 0x7fff) << 7usize); + } + #[doc = "Input to functional test the postdivider (P-divider)."] + #[must_use] + #[inline(always)] + pub const fn pfunctest(&self) -> u8 { + let val = (self.0 >> 22usize) & 0x0f; val as u8 } - #[doc = "SIRC Trim Pre-divider."] + #[doc = "Input to functional test the postdivider (P-divider)."] #[inline(always)] - pub const fn set_trimdiv(&mut self, val: u8) { - self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + pub const fn set_pfunctest(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 22usize)) | (((val as u32) & 0x0f) << 22usize); + } + #[doc = "Enable test mux."] + #[must_use] + #[inline(always)] + pub const fn testv_en(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Enable test mux."] + #[inline(always)] + pub const fn set_testv_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Select analog signal channel that need to be test."] + #[must_use] + #[inline(always)] + pub const fn testv_sel(&self) -> AplltestctrlTestvSel { + let val = (self.0 >> 27usize) & 0x07; + AplltestctrlTestvSel::from_bits(val as u8) + } + #[doc = "Select analog signal channel that need to be test."] + #[inline(always)] + pub const fn set_testv_sel(&mut self, val: AplltestctrlTestvSel) { + self.0 = (self.0 & !(0x07 << 27usize)) | (((val.to_bits() as u32) & 0x07) << 27usize); + } + #[doc = "Bypass PLL."] + #[must_use] + #[inline(always)] + pub const fn bypasspll(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Bypass PLL."] + #[inline(always)] + pub const fn set_bypasspll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for Sirctcfg { +impl Default for Aplltestctrl { #[inline(always)] - fn default() -> Sirctcfg { - Sirctcfg(0) + fn default() -> Aplltestctrl { + Aplltestctrl(0) } } -impl core::fmt::Debug for Sirctcfg { +impl core::fmt::Debug for Aplltestctrl { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sirctcfg") - .field("trimsrc", &self.trimsrc()) - .field("trimdiv", &self.trimdiv()) + f.debug_struct("Aplltestctrl") + .field("nfunctest", &self.nfunctest()) + .field("mfunctest", &self.mfunctest()) + .field("pfunctest", &self.pfunctest()) + .field("testv_en", &self.testv_en()) + .field("testv_sel", &self.testv_sel()) + .field("bypasspll", &self.bypasspll()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sirctcfg { +impl defmt::Format for Aplltestctrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sirctcfg {{ trimsrc: {:?}, trimdiv: {=u8:?} }}", - self.trimsrc(), - self.trimdiv() + "Aplltestctrl {{ nfunctest: {=u8:?}, mfunctest: {=u16:?}, pfunctest: {=u8:?}, testv_en: {=bool:?}, testv_sel: {:?}, bypasspll: {=bool:?} }}", + self.nfunctest(), + self.mfunctest(), + self.pfunctest(), + self.testv_en(), + self.testv_sel(), + self.bypasspll() ) } } -#[doc = "SIRC Trim Register."] +#[doc = "APLL Test Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sirctrim(pub u32); -impl Sirctrim { - #[doc = "CCO Trim."] +pub struct Apllteststat(pub u32); +impl Apllteststat { + #[doc = "Output to observe the functional predivider test."] #[must_use] #[inline(always)] - pub const fn ccotrim(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x3f; + pub const fn nmotest(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; val as u8 } - #[doc = "CCO Trim."] + #[doc = "Output to observe the functional predivider test."] #[inline(always)] - pub const fn set_ccotrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + pub const fn set_nmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); } - #[doc = "CL Trim."] + #[doc = "Output to observe the functional feedback-divider test."] #[must_use] #[inline(always)] - pub const fn cltrim(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x3f; + pub const fn mmotest(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; val as u8 } - #[doc = "CL Trim."] + #[doc = "Output to observe the functional feedback-divider test."] #[inline(always)] - pub const fn set_cltrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + pub const fn set_mmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); } - #[doc = "Trim Temp."] + #[doc = "Output to observe the functional postdivider test."] #[must_use] #[inline(always)] - pub const fn tctrim(&self) -> u8 { - let val = (self.0 >> 16usize) & 0x1f; + pub const fn pmotest(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x03; val as u8 } - #[doc = "Trim Temp."] + #[doc = "Output to observe the functional postdivider test."] #[inline(always)] - pub const fn set_tctrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + pub const fn set_pmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize); } - #[doc = "Calibrates the replica voltage in FSU for CCO to get well frequency at initial period."] + #[doc = "PLL functional divider test clock pulse."] #[must_use] #[inline(always)] - pub const fn fvchtrim(&self) -> u8 { - let val = (self.0 >> 24usize) & 0x1f; - val as u8 + pub const fn pll_xfunc_test_pulse(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 } - #[doc = "Calibrates the replica voltage in FSU for CCO to get well frequency at initial period."] + #[doc = "PLL functional divider test clock pulse."] #[inline(always)] - pub const fn set_fvchtrim(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + pub const fn set_pll_xfunc_test_pulse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "Enable PLL functional divider test clock pulse."] + #[must_use] + #[inline(always)] + pub const fn pll_xfunc_test_en(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Enable PLL functional divider test clock pulse."] + #[inline(always)] + pub const fn set_pll_xfunc_test_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "Enable to observe the xMOTEST flags."] + #[must_use] + #[inline(always)] + pub const fn pll_xmo_test_en(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Enable to observe the xMOTEST flags."] + #[inline(always)] + pub const fn set_pll_xmo_test_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for Sirctrim { +impl Default for Apllteststat { #[inline(always)] - fn default() -> Sirctrim { - Sirctrim(0) + fn default() -> Apllteststat { + Apllteststat(0) } } -impl core::fmt::Debug for Sirctrim { +impl core::fmt::Debug for Apllteststat { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sirctrim") - .field("ccotrim", &self.ccotrim()) - .field("cltrim", &self.cltrim()) - .field("tctrim", &self.tctrim()) - .field("fvchtrim", &self.fvchtrim()) + f.debug_struct("Apllteststat") + .field("nmotest", &self.nmotest()) + .field("mmotest", &self.mmotest()) + .field("pmotest", &self.pmotest()) + .field("pll_xfunc_test_pulse", &self.pll_xfunc_test_pulse()) + .field("pll_xfunc_test_en", &self.pll_xfunc_test_en()) + .field("pll_xmo_test_en", &self.pll_xmo_test_en()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sirctrim { +impl defmt::Format for Apllteststat { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sirctrim {{ ccotrim: {=u8:?}, cltrim: {=u8:?}, tctrim: {=u8:?}, fvchtrim: {=u8:?} }}", - self.ccotrim(), - self.cltrim(), - self.tctrim(), - self.fvchtrim() + "Apllteststat {{ nmotest: {=u8:?}, mmotest: {=u8:?}, pmotest: {=u8:?}, pll_xfunc_test_pulse: {=bool:?}, pll_xfunc_test_en: {=bool:?}, pll_xmo_test_en: {=bool:?} }}", + self.nmotest(), + self.mmotest(), + self.pmotest(), + self.pll_xfunc_test_pulse(), + self.pll_xfunc_test_en(), + self.pll_xmo_test_en() ) } } -#[doc = "SOSC Configuration Register."] +#[doc = "Clock Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sosccfg(pub u32); -impl Sosccfg { - #[doc = "External Reference Select."] +pub struct Csr(pub u32); +impl Csr { + #[doc = "System Clock Source."] #[must_use] #[inline(always)] - pub const fn erefs(&self) -> Erefs { - let val = (self.0 >> 2usize) & 0x01; - Erefs::from_bits(val as u8) + pub const fn scs(&self) -> Scs { + let val = (self.0 >> 24usize) & 0x0f; + Scs::from_bits(val as u8) } - #[doc = "External Reference Select."] + #[doc = "System Clock Source."] #[inline(always)] - pub const fn set_erefs(&mut self, val: Erefs) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_scs(&mut self, val: Scs) { + self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize); } - #[doc = "SOSC Range Select."] +} +impl Default for Csr { + #[inline(always)] + fn default() -> Csr { + Csr(0) + } +} +impl core::fmt::Debug for Csr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Csr").field("scs", &self.scs()).finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Csr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Csr {{ scs: {:?} }}", self.scs()) + } +} +#[doc = "FIRC Configuration Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Firccfg(pub u32); +impl Firccfg { + #[doc = "Frequency Range."] #[must_use] #[inline(always)] - pub const fn range(&self) -> Range { - let val = (self.0 >> 4usize) & 0x03; - Range::from_bits(val as u8) + pub const fn freq_sel(&self) -> FreqSel { + let val = (self.0 >> 0usize) & 0x0f; + FreqSel::from_bits(val as u8) } - #[doc = "SOSC Range Select."] + #[doc = "Frequency Range."] #[inline(always)] - pub const fn set_range(&mut self, val: Range) { - self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + pub const fn set_freq_sel(&mut self, val: FreqSel) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); } } -impl Default for Sosccfg { +impl Default for Firccfg { #[inline(always)] - fn default() -> Sosccfg { - Sosccfg(0) + fn default() -> Firccfg { + Firccfg(0) } } -impl core::fmt::Debug for Sosccfg { +impl core::fmt::Debug for Firccfg { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sosccfg") - .field("erefs", &self.erefs()) - .field("range", &self.range()) + f.debug_struct("Firccfg") + .field("freq_sel", &self.freq_sel()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sosccfg { +impl defmt::Format for Firccfg { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Sosccfg {{ erefs: {:?}, range: {:?} }}", - self.erefs(), - self.range() - ) + defmt::write!(f, "Firccfg {{ freq_sel: {:?} }}", self.freq_sel()) } } -#[doc = "SOSC Control Status Register."] +#[doc = "FIRC Control Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Sosccsr(pub u32); -impl Sosccsr { - #[doc = "SOSC Enable."] +pub struct Firccsr(pub u32); +impl Firccsr { + #[doc = "FIRC Enable."] #[must_use] #[inline(always)] - pub const fn soscen(&self) -> bool { + pub const fn fircen(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "SOSC Enable."] + #[doc = "FIRC Enable."] #[inline(always)] - pub const fn set_soscen(&mut self, val: bool) { + pub const fn set_fircen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "SOSC Stop Enable."] + #[doc = "FIRC Stop Enable."] #[must_use] #[inline(always)] - pub const fn soscsten(&self) -> bool { + pub const fn fircsten(&self) -> Fircsten { let val = (self.0 >> 1usize) & 0x01; + Fircsten::from_bits(val as u8) + } + #[doc = "FIRC Stop Enable."] + #[inline(always)] + pub const fn set_fircsten(&mut self, val: Fircsten) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + #[doc = "FIRC 48 MHz Clock to peripherals Enable."] + #[must_use] + #[inline(always)] + pub const fn firc_sclk_periph_en(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "SOSC Stop Enable."] + #[doc = "FIRC 48 MHz Clock to peripherals Enable."] #[inline(always)] - pub const fn set_soscsten(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub const fn set_firc_sclk_periph_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "SOSC Clock Monitor Enable."] + #[doc = "FIRC 144 MHz Clock to peripherals Enable."] #[must_use] #[inline(always)] - pub const fn sosccm(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; + pub const fn firc_fclk_periph_en(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "SOSC Clock Monitor Enable."] + #[doc = "FIRC 144 MHz Clock to peripherals Enable."] #[inline(always)] - pub const fn set_sosccm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + pub const fn set_firc_fclk_periph_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "SOSC Clock Monitor Reset Enable."] + #[doc = "FIRC 144 MHz Trim Enable (FIRCCFG\\[RANGE\\]=1)."] #[must_use] #[inline(always)] - pub const fn sosccmre(&self) -> Sosccmre { - let val = (self.0 >> 17usize) & 0x01; - Sosccmre::from_bits(val as u8) + pub const fn firctren(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 } - #[doc = "SOSC Clock Monitor Reset Enable."] + #[doc = "FIRC 144 MHz Trim Enable (FIRCCFG\\[RANGE\\]=1)."] #[inline(always)] - pub const fn set_sosccmre(&mut self, val: Sosccmre) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + pub const fn set_firctren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIRC Trim Update."] + #[must_use] + #[inline(always)] + pub const fn firctrup(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "FIRC Trim Update."] + #[inline(always)] + pub const fn set_firctrup(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "FIRC TRIM LOCK."] + #[must_use] + #[inline(always)] + pub const fn trim_lock(&self) -> FirccsrTrimLock { + let val = (self.0 >> 10usize) & 0x01; + FirccsrTrimLock::from_bits(val as u8) + } + #[doc = "FIRC TRIM LOCK."] + #[inline(always)] + pub const fn set_trim_lock(&mut self, val: FirccsrTrimLock) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + } + #[doc = "Coarse Auto Trim Bypass."] + #[must_use] + #[inline(always)] + pub const fn coarse_trim_bypass(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Coarse Auto Trim Bypass."] + #[inline(always)] + pub const fn set_coarse_trim_bypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } #[doc = "Lock Register."] #[must_use] #[inline(always)] - pub const fn lk(&self) -> SosccsrLk { + pub const fn lk(&self) -> FirccsrLk { let val = (self.0 >> 23usize) & 0x01; - SosccsrLk::from_bits(val as u8) + FirccsrLk::from_bits(val as u8) } #[doc = "Lock Register."] #[inline(always)] - pub const fn set_lk(&mut self, val: SosccsrLk) { + pub const fn set_lk(&mut self, val: FirccsrLk) { self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); } - #[doc = "SOSC Valid."] + #[doc = "FIRC Valid status."] #[must_use] #[inline(always)] - pub const fn soscvld(&self) -> bool { + pub const fn fircvld(&self) -> Fircvld { let val = (self.0 >> 24usize) & 0x01; - val != 0 + Fircvld::from_bits(val as u8) } - #[doc = "SOSC Valid."] + #[doc = "FIRC Valid status."] #[inline(always)] - pub const fn set_soscvld(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + pub const fn set_fircvld(&mut self, val: Fircvld) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); } - #[doc = "SOSC Selected."] + #[doc = "FIRC Selected."] #[must_use] #[inline(always)] - pub const fn soscsel(&self) -> bool { + pub const fn fircsel(&self) -> bool { let val = (self.0 >> 25usize) & 0x01; val != 0 } - #[doc = "SOSC Selected."] + #[doc = "FIRC Selected."] #[inline(always)] - pub const fn set_soscsel(&mut self, val: bool) { + pub const fn set_fircsel(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); } - #[doc = "SOSC Clock Error."] + #[doc = "FIRC Clock Error."] #[must_use] #[inline(always)] - pub const fn soscerr(&self) -> Soscerr { + pub const fn fircerr(&self) -> Fircerr { let val = (self.0 >> 26usize) & 0x01; - Soscerr::from_bits(val as u8) + Fircerr::from_bits(val as u8) } - #[doc = "SOSC Clock Error."] + #[doc = "FIRC Clock Error."] #[inline(always)] - pub const fn set_soscerr(&mut self, val: Soscerr) { + pub const fn set_fircerr(&mut self, val: Fircerr) { self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); } - #[doc = "SOSC Valid Interrupt Enable."] + #[doc = "FIRC Clock Error Interrupt Enable."] #[must_use] #[inline(always)] - pub const fn soscvld_ie(&self) -> bool { + pub const fn fircerr_ie(&self) -> FircerrIe { + let val = (self.0 >> 27usize) & 0x01; + FircerrIe::from_bits(val as u8) + } + #[doc = "FIRC Clock Error Interrupt Enable."] + #[inline(always)] + pub const fn set_fircerr_ie(&mut self, val: FircerrIe) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); + } + #[doc = "FIRC Accurate Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn fircacc_ie(&self) -> FircaccIe { let val = (self.0 >> 30usize) & 0x01; - val != 0 + FircaccIe::from_bits(val as u8) } - #[doc = "SOSC Valid Interrupt Enable."] + #[doc = "FIRC Accurate Interrupt Enable."] #[inline(always)] - pub const fn set_soscvld_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + pub const fn set_fircacc_ie(&mut self, val: FircaccIe) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val.to_bits() as u32) & 0x01) << 30usize); } - #[doc = "SOSC clock safety enable."] + #[doc = "FIRC Frequency Accurate."] #[must_use] #[inline(always)] - pub const fn sosc_safe_en(&self) -> bool { + pub const fn fircacc(&self) -> Fircacc { let val = (self.0 >> 31usize) & 0x01; - val != 0 + Fircacc::from_bits(val as u8) } - #[doc = "SOSC clock safety enable."] + #[doc = "FIRC Frequency Accurate."] #[inline(always)] - pub const fn set_sosc_safe_en(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_fircacc(&mut self, val: Fircacc) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); } } -impl Default for Sosccsr { +impl Default for Firccsr { #[inline(always)] - fn default() -> Sosccsr { - Sosccsr(0) + fn default() -> Firccsr { + Firccsr(0) } } -impl core::fmt::Debug for Sosccsr { +impl core::fmt::Debug for Firccsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Sosccsr") - .field("soscen", &self.soscen()) - .field("soscsten", &self.soscsten()) - .field("sosccm", &self.sosccm()) - .field("sosccmre", &self.sosccmre()) + f.debug_struct("Firccsr") + .field("fircen", &self.fircen()) + .field("fircsten", &self.fircsten()) + .field("firc_sclk_periph_en", &self.firc_sclk_periph_en()) + .field("firc_fclk_periph_en", &self.firc_fclk_periph_en()) + .field("firctren", &self.firctren()) + .field("firctrup", &self.firctrup()) + .field("trim_lock", &self.trim_lock()) + .field("coarse_trim_bypass", &self.coarse_trim_bypass()) .field("lk", &self.lk()) - .field("soscvld", &self.soscvld()) - .field("soscsel", &self.soscsel()) - .field("soscerr", &self.soscerr()) - .field("soscvld_ie", &self.soscvld_ie()) - .field("sosc_safe_en", &self.sosc_safe_en()) + .field("fircvld", &self.fircvld()) + .field("fircsel", &self.fircsel()) + .field("fircerr", &self.fircerr()) + .field("fircerr_ie", &self.fircerr_ie()) + .field("fircacc_ie", &self.fircacc_ie()) + .field("fircacc", &self.fircacc()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Sosccsr { +impl defmt::Format for Firccsr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Sosccsr {{ soscen: {=bool:?}, soscsten: {=bool:?}, sosccm: {=bool:?}, sosccmre: {:?}, lk: {:?}, soscvld: {=bool:?}, soscsel: {=bool:?}, soscerr: {:?}, soscvld_ie: {=bool:?}, sosc_safe_en: {=bool:?} }}", - self.soscen(), - self.soscsten(), - self.sosccm(), - self.sosccmre(), + "Firccsr {{ fircen: {=bool:?}, fircsten: {:?}, firc_sclk_periph_en: {=bool:?}, firc_fclk_periph_en: {=bool:?}, firctren: {=bool:?}, firctrup: {=bool:?}, trim_lock: {:?}, coarse_trim_bypass: {=bool:?}, lk: {:?}, fircvld: {:?}, fircsel: {=bool:?}, fircerr: {:?}, fircerr_ie: {:?}, fircacc_ie: {:?}, fircacc: {:?} }}", + self.fircen(), + self.fircsten(), + self.firc_sclk_periph_en(), + self.firc_fclk_periph_en(), + self.firctren(), + self.firctrup(), + self.trim_lock(), + self.coarse_trim_bypass(), self.lk(), - self.soscvld(), - self.soscsel(), - self.soscerr(), - self.soscvld_ie(), - self.sosc_safe_en() + self.fircvld(), + self.fircsel(), + self.fircerr(), + self.fircerr_ie(), + self.fircacc_ie(), + self.fircacc() ) } } -#[doc = "SPLL Control Status Register."] +#[doc = "FIRC Auto-trimming Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllcsr(pub u32); -impl Spllcsr { - #[doc = "SPLL Power Enable."] +pub struct Fircstat(pub u32); +impl Fircstat { + #[doc = "Trim Fine."] #[must_use] #[inline(always)] - pub const fn spllpwren(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub const fn trimfine(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 } - #[doc = "SPLL Power Enable."] + #[doc = "Trim Fine."] #[inline(always)] - pub const fn set_spllpwren(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub const fn set_trimfine(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } - #[doc = "SPLL Clock Enable."] + #[doc = "Trim Coarse."] #[must_use] #[inline(always)] - pub const fn spllclken(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + pub const fn trimcoar(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 } - #[doc = "SPLL Clock Enable."] + #[doc = "Trim Coarse."] #[inline(always)] - pub const fn set_spllclken(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub const fn set_trimcoar(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); } - #[doc = "SPLL Stop Enable."] +} +impl Default for Fircstat { + #[inline(always)] + fn default() -> Fircstat { + Fircstat(0) + } +} +impl core::fmt::Debug for Fircstat { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Fircstat") + .field("trimfine", &self.trimfine()) + .field("trimcoar", &self.trimcoar()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Fircstat { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Fircstat {{ trimfine: {=u8:?}, trimcoar: {=u8:?} }}", + self.trimfine(), + self.trimcoar() + ) + } +} +#[doc = "FIRC Trim Configuration Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Firctcfg(pub u32); +impl Firctcfg { + #[doc = "Trim Source."] #[must_use] #[inline(always)] - pub const fn spllsten(&self) -> Spllsten { - let val = (self.0 >> 2usize) & 0x01; - Spllsten::from_bits(val as u8) + pub const fn trimsrc(&self) -> FirctcfgTrimsrc { + let val = (self.0 >> 0usize) & 0x03; + FirctcfgTrimsrc::from_bits(val as u8) } - #[doc = "SPLL Stop Enable."] + #[doc = "Trim Source."] #[inline(always)] - pub const fn set_spllsten(&mut self, val: Spllsten) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_trimsrc(&mut self, val: FirctcfgTrimsrc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "Free running mode clock stable."] + #[doc = "FIRC Trim Predivider."] #[must_use] #[inline(always)] - pub const fn frm_clockstable(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; - val != 0 + pub const fn trimdiv(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 } - #[doc = "Free running mode clock stable."] + #[doc = "FIRC Trim Predivider."] #[inline(always)] - pub const fn set_frm_clockstable(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub const fn set_trimdiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); } - #[doc = "SPLL Clock Monitor."] +} +impl Default for Firctcfg { + #[inline(always)] + fn default() -> Firctcfg { + Firctcfg(0) + } +} +impl core::fmt::Debug for Firctcfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Firctcfg") + .field("trimsrc", &self.trimsrc()) + .field("trimdiv", &self.trimdiv()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Firctcfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Firctcfg {{ trimsrc: {:?}, trimdiv: {=u8:?} }}", + self.trimsrc(), + self.trimdiv() + ) + } +} +#[doc = "FIRC Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Firctest(pub u32); +impl Firctest { + #[doc = "Test Enable."] #[must_use] #[inline(always)] - pub const fn spllcm(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 + pub const fn testen(&self) -> Testen { + let val = (self.0 >> 0usize) & 0x01; + Testen::from_bits(val as u8) } - #[doc = "SPLL Clock Monitor."] + #[doc = "Test Enable."] #[inline(always)] - pub const fn set_spllcm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + pub const fn set_testen(&mut self, val: Testen) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); } - #[doc = "SPLL Clock Monitor Reset Enable."] + #[doc = "Test Select."] #[must_use] #[inline(always)] - pub const fn spllcmre(&self) -> Spllcmre { - let val = (self.0 >> 17usize) & 0x01; - Spllcmre::from_bits(val as u8) + pub const fn testsel(&self) -> Testsel { + let val = (self.0 >> 3usize) & 0x03; + Testsel::from_bits(val as u8) } - #[doc = "SPLL Clock Monitor Reset Enable."] + #[doc = "Test Select."] #[inline(always)] - pub const fn set_spllcmre(&mut self, val: Spllcmre) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + pub const fn set_testsel(&mut self, val: Testsel) { + self.0 = (self.0 & !(0x03 << 3usize)) | (((val.to_bits() as u32) & 0x03) << 3usize); } - #[doc = "Lock Register."] + #[doc = "Over Stress Test."] #[must_use] #[inline(always)] - pub const fn lk(&self) -> SpllcsrLk { - let val = (self.0 >> 23usize) & 0x01; - SpllcsrLk::from_bits(val as u8) + pub const fn overstress(&self) -> Overstress { + let val = (self.0 >> 5usize) & 0x01; + Overstress::from_bits(val as u8) } - #[doc = "Lock Register."] + #[doc = "Over Stress Test."] #[inline(always)] - pub const fn set_lk(&mut self, val: SpllcsrLk) { - self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + pub const fn set_overstress(&mut self, val: Overstress) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); } - #[doc = "SPLL LOCK."] + #[doc = "Test Buffer Enable."] #[must_use] #[inline(always)] - pub const fn spll_lock(&self) -> SpllLock { - let val = (self.0 >> 24usize) & 0x01; - SpllLock::from_bits(val as u8) + pub const fn test_buf_en(&self) -> TestBufEn { + let val = (self.0 >> 6usize) & 0x01; + TestBufEn::from_bits(val as u8) } - #[doc = "SPLL LOCK."] + #[doc = "Test Buffer Enable."] #[inline(always)] - pub const fn set_spll_lock(&mut self, val: SpllLock) { - self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + pub const fn set_test_buf_en(&mut self, val: TestBufEn) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); } - #[doc = "SPLL Selected."] + #[doc = "Test Buffer Flip."] #[must_use] #[inline(always)] - pub const fn spllsel(&self) -> bool { - let val = (self.0 >> 25usize) & 0x01; - val != 0 + pub const fn test_buf_flip(&self) -> TestBufFlip { + let val = (self.0 >> 7usize) & 0x01; + TestBufFlip::from_bits(val as u8) } - #[doc = "SPLL Selected."] + #[doc = "Test Buffer Flip."] #[inline(always)] - pub const fn set_spllsel(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + pub const fn set_test_buf_flip(&mut self, val: TestBufFlip) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.to_bits() as u32) & 0x01) << 7usize); } - #[doc = "SPLL Clock Error."] + #[doc = "Analog output clk_valid_lv."] #[must_use] #[inline(always)] - pub const fn spllerr(&self) -> Spllerr { - let val = (self.0 >> 26usize) & 0x01; - Spllerr::from_bits(val as u8) + pub const fn clk_valid(&self) -> ClkValid { + let val = (self.0 >> 16usize) & 0x01; + ClkValid::from_bits(val as u8) } - #[doc = "SPLL Clock Error."] + #[doc = "Analog output clk_valid_lv."] #[inline(always)] - pub const fn set_spllerr(&mut self, val: Spllerr) { - self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + pub const fn set_clk_valid(&mut self, val: ClkValid) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize); } - #[doc = "SPLL LOCK Interrupt Enable."] + #[doc = "Analog output start_valid_lv."] #[must_use] #[inline(always)] - pub const fn spll_lock_ie(&self) -> bool { - let val = (self.0 >> 30usize) & 0x01; - val != 0 + pub const fn start_valid(&self) -> StartValid { + let val = (self.0 >> 17usize) & 0x01; + StartValid::from_bits(val as u8) } - #[doc = "SPLL LOCK Interrupt Enable."] + #[doc = "Analog output start_valid_lv."] #[inline(always)] - pub const fn set_spll_lock_ie(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + pub const fn set_start_valid(&mut self, val: StartValid) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); } } -impl Default for Spllcsr { +impl Default for Firctest { #[inline(always)] - fn default() -> Spllcsr { - Spllcsr(0) + fn default() -> Firctest { + Firctest(0) } } -impl core::fmt::Debug for Spllcsr { +impl core::fmt::Debug for Firctest { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllcsr") - .field("spllpwren", &self.spllpwren()) - .field("spllclken", &self.spllclken()) - .field("spllsten", &self.spllsten()) - .field("frm_clockstable", &self.frm_clockstable()) - .field("spllcm", &self.spllcm()) - .field("spllcmre", &self.spllcmre()) - .field("lk", &self.lk()) - .field("spll_lock", &self.spll_lock()) - .field("spllsel", &self.spllsel()) - .field("spllerr", &self.spllerr()) - .field("spll_lock_ie", &self.spll_lock_ie()) + f.debug_struct("Firctest") + .field("testen", &self.testen()) + .field("testsel", &self.testsel()) + .field("overstress", &self.overstress()) + .field("test_buf_en", &self.test_buf_en()) + .field("test_buf_flip", &self.test_buf_flip()) + .field("clk_valid", &self.clk_valid()) + .field("start_valid", &self.start_valid()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllcsr { +impl defmt::Format for Firctest { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllcsr {{ spllpwren: {=bool:?}, spllclken: {=bool:?}, spllsten: {:?}, frm_clockstable: {=bool:?}, spllcm: {=bool:?}, spllcmre: {:?}, lk: {:?}, spll_lock: {:?}, spllsel: {=bool:?}, spllerr: {:?}, spll_lock_ie: {=bool:?} }}", - self.spllpwren(), - self.spllclken(), - self.spllsten(), - self.frm_clockstable(), - self.spllcm(), - self.spllcmre(), - self.lk(), - self.spll_lock(), - self.spllsel(), - self.spllerr(), - self.spll_lock_ie() + "Firctest {{ testen: {:?}, testsel: {:?}, overstress: {:?}, test_buf_en: {:?}, test_buf_flip: {:?}, clk_valid: {:?}, start_valid: {:?} }}", + self.testen(), + self.testsel(), + self.overstress(), + self.test_buf_en(), + self.test_buf_flip(), + self.clk_valid(), + self.start_valid() ) } } -#[doc = "SPLL Control Register."] +#[doc = "FIRC Trim Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllctrl(pub u32); -impl Spllctrl { - #[doc = "Bandwidth select R (resistor) value."] +pub struct Firctrim(pub u32); +impl Firctrim { + #[doc = "Trim Fine."] #[must_use] #[inline(always)] - pub const fn selr(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x0f; + pub const fn trimfine(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; val as u8 } - #[doc = "Bandwidth select R (resistor) value."] + #[doc = "Trim Fine."] #[inline(always)] - pub const fn set_selr(&mut self, val: u8) { - self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + pub const fn set_trimfine(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); } - #[doc = "Bandwidth select I (interation) value."] + #[doc = "Trim Coarse."] #[must_use] #[inline(always)] - pub const fn seli(&self) -> u8 { - let val = (self.0 >> 4usize) & 0x3f; + pub const fn trimcoar(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; val as u8 } - #[doc = "Bandwidth select I (interation) value."] + #[doc = "Trim Coarse."] #[inline(always)] - pub const fn set_seli(&mut self, val: u8) { - self.0 = (self.0 & !(0x3f << 4usize)) | (((val as u32) & 0x3f) << 4usize); + pub const fn set_trimcoar(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); } - #[doc = "Bandwidth select P (proportional) value."] + #[doc = "Trim Temperature."] #[must_use] #[inline(always)] - pub const fn selp(&self) -> u8 { - let val = (self.0 >> 10usize) & 0x1f; + pub const fn trimtemp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x03; val as u8 } - #[doc = "Bandwidth select P (proportional) value."] + #[doc = "Trim Temperature."] #[inline(always)] - pub const fn set_selp(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize); + pub const fn set_trimtemp(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize); } - #[doc = "Bypass of the divide-by-2 divider."] + #[doc = "Trim Start."] #[must_use] #[inline(always)] - pub const fn bypasspostdiv2(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 + pub const fn trimstart(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x3f; + val as u8 } - #[doc = "Bypass of the divide-by-2 divider."] + #[doc = "Trim Start."] #[inline(always)] - pub const fn set_bypasspostdiv2(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + pub const fn set_trimstart(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 24usize)) | (((val as u32) & 0x3f) << 24usize); } - #[doc = "Up Limiter."] - #[must_use] +} +impl Default for Firctrim { #[inline(always)] - pub const fn limupoff(&self) -> bool { - let val = (self.0 >> 17usize) & 0x01; - val != 0 + fn default() -> Firctrim { + Firctrim(0) } - #[doc = "Up Limiter."] - #[inline(always)] - pub const fn set_limupoff(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); +} +impl core::fmt::Debug for Firctrim { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Firctrim") + .field("trimfine", &self.trimfine()) + .field("trimcoar", &self.trimcoar()) + .field("trimtemp", &self.trimtemp()) + .field("trimstart", &self.trimstart()) + .finish() } - #[doc = "Control of the bandwidth of the PLL."] - #[must_use] - #[inline(always)] - pub const fn banddirect(&self) -> bool { - let val = (self.0 >> 18usize) & 0x01; - val != 0 - } - #[doc = "Control of the bandwidth of the PLL."] - #[inline(always)] - pub const fn set_banddirect(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); +} +#[cfg(feature = "defmt")] +impl defmt::Format for Firctrim { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Firctrim {{ trimfine: {=u8:?}, trimcoar: {=u8:?}, trimtemp: {=u8:?}, trimstart: {=u8:?} }}", + self.trimfine(), + self.trimcoar(), + self.trimtemp(), + self.trimstart() + ) } - #[doc = "Bypass of the pre-divider."] +} +#[doc = "LDO Control and Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Ldocsr(pub u32); +impl Ldocsr { + #[doc = "LDO Enable."] #[must_use] #[inline(always)] - pub const fn bypassprediv(&self) -> bool { - let val = (self.0 >> 19usize) & 0x01; + pub const fn ldoen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Bypass of the pre-divider."] + #[doc = "LDO Enable."] #[inline(always)] - pub const fn set_bypassprediv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + pub const fn set_ldoen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Bypass of the post-divider."] + #[doc = "LDO output voltage select."] #[must_use] #[inline(always)] - pub const fn bypasspostdiv(&self) -> bool { - let val = (self.0 >> 20usize) & 0x01; - val != 0 + pub const fn vout_sel(&self) -> VoutSel { + let val = (self.0 >> 1usize) & 0x07; + VoutSel::from_bits(val as u8) } - #[doc = "Bypass of the post-divider."] + #[doc = "LDO output voltage select."] #[inline(always)] - pub const fn set_bypasspostdiv(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + pub const fn set_vout_sel(&mut self, val: VoutSel) { + self.0 = (self.0 & !(0x07 << 1usize)) | (((val.to_bits() as u32) & 0x07) << 1usize); } - #[doc = "Free Running Mode Enable."] + #[doc = "LDO Bypass."] #[must_use] #[inline(always)] - pub const fn frm(&self) -> bool { - let val = (self.0 >> 22usize) & 0x01; + pub const fn ldobypass(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "Free Running Mode Enable."] + #[doc = "LDO Bypass."] #[inline(always)] - pub const fn set_frm(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + pub const fn set_ldobypass(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "Clock Source."] + #[doc = "LDO VOUT OK Inform."] #[must_use] #[inline(always)] - pub const fn source(&self) -> Source { - let val = (self.0 >> 25usize) & 0x03; - Source::from_bits(val as u8) + pub const fn vout_ok(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 } - #[doc = "Clock Source."] + #[doc = "LDO VOUT OK Inform."] #[inline(always)] - pub const fn set_source(&mut self, val: Source) { - self.0 = (self.0 & !(0x03 << 25usize)) | (((val.to_bits() as u32) & 0x03) << 25usize); + pub const fn set_vout_ok(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } -impl Default for Spllctrl { +impl Default for Ldocsr { #[inline(always)] - fn default() -> Spllctrl { - Spllctrl(0) + fn default() -> Ldocsr { + Ldocsr(0) } } -impl core::fmt::Debug for Spllctrl { +impl core::fmt::Debug for Ldocsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllctrl") - .field("selr", &self.selr()) - .field("seli", &self.seli()) - .field("selp", &self.selp()) - .field("bypasspostdiv2", &self.bypasspostdiv2()) - .field("limupoff", &self.limupoff()) - .field("banddirect", &self.banddirect()) - .field("bypassprediv", &self.bypassprediv()) - .field("bypasspostdiv", &self.bypasspostdiv()) - .field("frm", &self.frm()) - .field("source", &self.source()) + f.debug_struct("Ldocsr") + .field("ldoen", &self.ldoen()) + .field("vout_sel", &self.vout_sel()) + .field("ldobypass", &self.ldobypass()) + .field("vout_ok", &self.vout_ok()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllctrl { +impl defmt::Format for Ldocsr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllctrl {{ selr: {=u8:?}, seli: {=u8:?}, selp: {=u8:?}, bypasspostdiv2: {=bool:?}, limupoff: {=bool:?}, banddirect: {=bool:?}, bypassprediv: {=bool:?}, bypasspostdiv: {=bool:?}, frm: {=bool:?}, source: {:?} }}", - self.selr(), - self.seli(), - self.selp(), - self.bypasspostdiv2(), - self.limupoff(), - self.banddirect(), - self.bypassprediv(), - self.bypasspostdiv(), - self.frm(), - self.source() + "Ldocsr {{ ldoen: {=bool:?}, vout_sel: {:?}, ldobypass: {=bool:?}, vout_ok: {=bool:?} }}", + self.ldoen(), + self.vout_sel(), + self.ldobypass(), + self.vout_ok() ) } } -#[doc = "SPLL LOCK Configuration Register."] +#[doc = "LDO Test Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct SplllockCnfg(pub u32); -impl SplllockCnfg { - #[doc = "Configures the number of reference clocks to count before SPLL is considered locked."] +pub struct Ldotest(pub u32); +impl Ldotest { + #[doc = "Select analog test bus."] #[must_use] #[inline(always)] - pub const fn lock_time(&self) -> u32 { - let val = (self.0 >> 0usize) & 0x0001_ffff; - val as u32 + pub const fn sel_atx(&self) -> SelAtx { + let val = (self.0 >> 0usize) & 0x03; + SelAtx::from_bits(val as u8) } - #[doc = "Configures the number of reference clocks to count before SPLL is considered locked."] + #[doc = "Select analog test bus."] #[inline(always)] - pub const fn set_lock_time(&mut self, val: u32) { - self.0 = (self.0 & !(0x0001_ffff << 0usize)) | (((val as u32) & 0x0001_ffff) << 0usize); + pub const fn set_sel_atx(&mut self, val: SelAtx) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } } -impl Default for SplllockCnfg { +impl Default for Ldotest { #[inline(always)] - fn default() -> SplllockCnfg { - SplllockCnfg(0) + fn default() -> Ldotest { + Ldotest(0) } } -impl core::fmt::Debug for SplllockCnfg { +impl core::fmt::Debug for Ldotest { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SplllockCnfg") - .field("lock_time", &self.lock_time()) + f.debug_struct("Ldotest") + .field("sel_atx", &self.sel_atx()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for SplllockCnfg { +impl defmt::Format for Ldotest { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "SplllockCnfg {{ lock_time: {=u32:?} }}", - self.lock_time() - ) + defmt::write!(f, "Ldotest {{ sel_atx: {:?} }}", self.sel_atx()) } } -#[doc = "SPLL M Divider Register."] +#[doc = "Parameter Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllmdiv(pub u32); -impl Spllmdiv { - #[doc = "Feedback divider ratio (M-divider)."] +pub struct Param(pub u32); +impl Param { + #[doc = "SOSC Clock Present."] #[must_use] #[inline(always)] - pub const fn mdiv(&self) -> u16 { - let val = (self.0 >> 0usize) & 0xffff; - val as u16 + pub const fn soscclkpres(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 } - #[doc = "Feedback divider ratio (M-divider)."] + #[doc = "SOSC Clock Present."] #[inline(always)] - pub const fn set_mdiv(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + pub const fn set_soscclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Feedback ratio change request."] + #[doc = "SIRC Clock Present."] #[must_use] #[inline(always)] - pub const fn mreq(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; + pub const fn sircclkpres(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "Feedback ratio change request."] + #[doc = "SIRC Clock Present."] #[inline(always)] - pub const fn set_mreq(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_sircclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } -} -impl Default for Spllmdiv { + #[doc = "FIRC Clock Present."] + #[must_use] #[inline(always)] - fn default() -> Spllmdiv { - Spllmdiv(0) + pub const fn fircclkpres(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 } -} -impl core::fmt::Debug for Spllmdiv { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllmdiv") - .field("mdiv", &self.mdiv()) - .field("mreq", &self.mreq()) - .finish() + #[doc = "FIRC Clock Present."] + #[inline(always)] + pub const fn set_fircclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Spllmdiv { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Spllmdiv {{ mdiv: {=u16:?}, mreq: {=bool:?} }}", - self.mdiv(), - self.mreq() - ) + #[doc = "ROSC Clock Present."] + #[must_use] + #[inline(always)] + pub const fn roscclkpres(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 } -} -#[doc = "SPLL N Divider Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllndiv(pub u32); -impl Spllndiv { - #[doc = "Pre-divider divider ratio (N-divider)."] + #[doc = "ROSC Clock Present."] + #[inline(always)] + pub const fn set_roscclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "APLL Clock Present."] #[must_use] #[inline(always)] - pub const fn ndiv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 + pub const fn apllclkpres(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 } - #[doc = "Pre-divider divider ratio (N-divider)."] + #[doc = "APLL Clock Present."] #[inline(always)] - pub const fn set_ndiv(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub const fn set_apllclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Pre-divider ratio change request."] + #[doc = "SPLL Clock Present."] #[must_use] #[inline(always)] - pub const fn nreq(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; + pub const fn spllclkpres(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "Pre-divider ratio change request."] + #[doc = "SPLL Clock Present."] #[inline(always)] - pub const fn set_nreq(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_spllclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "UPLL Clock Present."] + #[must_use] + #[inline(always)] + pub const fn upllclkpres(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "UPLL Clock Present."] + #[inline(always)] + pub const fn set_upllclkpres(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } } -impl Default for Spllndiv { +impl Default for Param { #[inline(always)] - fn default() -> Spllndiv { - Spllndiv(0) + fn default() -> Param { + Param(0) } } -impl core::fmt::Debug for Spllndiv { +impl core::fmt::Debug for Param { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllndiv") - .field("ndiv", &self.ndiv()) - .field("nreq", &self.nreq()) + f.debug_struct("Param") + .field("soscclkpres", &self.soscclkpres()) + .field("sircclkpres", &self.sircclkpres()) + .field("fircclkpres", &self.fircclkpres()) + .field("roscclkpres", &self.roscclkpres()) + .field("apllclkpres", &self.apllclkpres()) + .field("spllclkpres", &self.spllclkpres()) + .field("upllclkpres", &self.upllclkpres()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllndiv { +impl defmt::Format for Param { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllndiv {{ ndiv: {=u8:?}, nreq: {=bool:?} }}", - self.ndiv(), - self.nreq() + "Param {{ soscclkpres: {=bool:?}, sircclkpres: {=bool:?}, fircclkpres: {=bool:?}, roscclkpres: {=bool:?}, apllclkpres: {=bool:?}, spllclkpres: {=bool:?}, upllclkpres: {=bool:?} }}", + self.soscclkpres(), + self.sircclkpres(), + self.fircclkpres(), + self.roscclkpres(), + self.apllclkpres(), + self.spllclkpres(), + self.upllclkpres() ) } } -#[doc = "SPLL P Divider Register."] +#[doc = "Run Clock Control Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllpdiv(pub u32); -impl Spllpdiv { - #[doc = "Post-divider divider ratio (P-divider)."] - #[must_use] - #[inline(always)] - pub const fn pdiv(&self) -> u8 { - let val = (self.0 >> 0usize) & 0x1f; - val as u8 - } - #[doc = "Post-divider divider ratio (P-divider)."] - #[inline(always)] - pub const fn set_pdiv(&mut self, val: u8) { - self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); - } - #[doc = "Post-divider ratio change request."] +pub struct Rccr(pub u32); +impl Rccr { + #[doc = "System Clock Source."] #[must_use] #[inline(always)] - pub const fn preq(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 + pub const fn scs(&self) -> Scs { + let val = (self.0 >> 24usize) & 0x0f; + Scs::from_bits(val as u8) } - #[doc = "Post-divider ratio change request."] + #[doc = "System Clock Source."] #[inline(always)] - pub const fn set_preq(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_scs(&mut self, val: Scs) { + self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize); } } -impl Default for Spllpdiv { +impl Default for Rccr { #[inline(always)] - fn default() -> Spllpdiv { - Spllpdiv(0) + fn default() -> Rccr { + Rccr(0) } } -impl core::fmt::Debug for Spllpdiv { +impl core::fmt::Debug for Rccr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllpdiv") - .field("pdiv", &self.pdiv()) - .field("preq", &self.preq()) - .finish() + f.debug_struct("Rccr").field("scs", &self.scs()).finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllpdiv { +impl defmt::Format for Rccr { fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Spllpdiv {{ pdiv: {=u8:?}, preq: {=bool:?} }}", - self.pdiv(), - self.preq() - ) + defmt::write!(f, "Rccr {{ scs: {:?} }}", self.scs()) } } -#[doc = "SPLL Spread Spectrum Control 0 Register."] +#[doc = "ROSC Control Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllsscg0(pub u32); -impl Spllsscg0 { - #[doc = "SS_MDIV\\[31:0\\]."] +pub struct Rosccsr(pub u32); +impl Rosccsr { + #[doc = "ROSC Clock Monitor."] #[must_use] #[inline(always)] - pub const fn ss_mdiv_lsb(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 + pub const fn rosccm(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 } - #[doc = "SS_MDIV\\[31:0\\]."] + #[doc = "ROSC Clock Monitor."] #[inline(always)] - pub const fn set_ss_mdiv_lsb(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + pub const fn set_rosccm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ROSC Clock Monitor Reset Enable."] + #[must_use] + #[inline(always)] + pub const fn rosccmre(&self) -> Rosccmre { + let val = (self.0 >> 17usize) & 0x01; + Rosccmre::from_bits(val as u8) + } + #[doc = "ROSC Clock Monitor Reset Enable."] + #[inline(always)] + pub const fn set_rosccmre(&mut self, val: Rosccmre) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + } + #[doc = "Lock Register."] + #[must_use] + #[inline(always)] + pub const fn lk(&self) -> RosccsrLk { + let val = (self.0 >> 23usize) & 0x01; + RosccsrLk::from_bits(val as u8) + } + #[doc = "Lock Register."] + #[inline(always)] + pub const fn set_lk(&mut self, val: RosccsrLk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + } + #[doc = "ROSC Valid."] + #[must_use] + #[inline(always)] + pub const fn roscvld(&self) -> Roscvld { + let val = (self.0 >> 24usize) & 0x01; + Roscvld::from_bits(val as u8) + } + #[doc = "ROSC Valid."] + #[inline(always)] + pub const fn set_roscvld(&mut self, val: Roscvld) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + } + #[doc = "ROSC Selected."] + #[must_use] + #[inline(always)] + pub const fn roscsel(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "ROSC Selected."] + #[inline(always)] + pub const fn set_roscsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "ROSC Clock Error."] + #[must_use] + #[inline(always)] + pub const fn roscerr(&self) -> Roscerr { + let val = (self.0 >> 26usize) & 0x01; + Roscerr::from_bits(val as u8) + } + #[doc = "ROSC Clock Error."] + #[inline(always)] + pub const fn set_roscerr(&mut self, val: Roscerr) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); } } -impl Default for Spllsscg0 { +impl Default for Rosccsr { #[inline(always)] - fn default() -> Spllsscg0 { - Spllsscg0(0) + fn default() -> Rosccsr { + Rosccsr(0) } } -impl core::fmt::Debug for Spllsscg0 { +impl core::fmt::Debug for Rosccsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllsscg0") - .field("ss_mdiv_lsb", &self.ss_mdiv_lsb()) + f.debug_struct("Rosccsr") + .field("rosccm", &self.rosccm()) + .field("rosccmre", &self.rosccmre()) + .field("lk", &self.lk()) + .field("roscvld", &self.roscvld()) + .field("roscsel", &self.roscsel()) + .field("roscerr", &self.roscerr()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllsscg0 { +impl defmt::Format for Rosccsr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllsscg0 {{ ss_mdiv_lsb: {=u32:?} }}", - self.ss_mdiv_lsb() + "Rosccsr {{ rosccm: {=bool:?}, rosccmre: {:?}, lk: {:?}, roscvld: {:?}, roscsel: {=bool:?}, roscerr: {:?} }}", + self.rosccm(), + self.rosccmre(), + self.lk(), + self.roscvld(), + self.roscsel(), + self.roscerr() ) } } -#[doc = "SPLL Spread Spectrum Control 1 Register."] +#[doc = "SIRC Control Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllsscg1(pub u32); -impl Spllsscg1 { - #[doc = "SS_MDIV\\[32\\]."] - #[must_use] - #[inline(always)] - pub const fn ss_mdiv_msb(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 - } - #[doc = "SS_MDIV\\[32\\]."] - #[inline(always)] - pub const fn set_ss_mdiv_msb(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); - } - #[doc = "SS_MDIV\\[32:0\\] change request."] +pub struct Sirccsr(pub u32); +impl Sirccsr { + #[doc = "SIRC Stop Enable."] #[must_use] #[inline(always)] - pub const fn ss_mdiv_req(&self) -> bool { + pub const fn sircsten(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "SS_MDIV\\[32:0\\] change request."] + #[doc = "SIRC Stop Enable."] #[inline(always)] - pub const fn set_ss_mdiv_req(&mut self, val: bool) { + pub const fn set_sircsten(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "Modulation Frequency Control."] + #[doc = "SIRC Clock to Peripherals Enable."] #[must_use] #[inline(always)] - pub const fn mf(&self) -> u8 { - let val = (self.0 >> 2usize) & 0x07; - val as u8 + pub const fn sirc_clk_periph_en(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 } - #[doc = "Modulation Frequency Control."] + #[doc = "SIRC Clock to Peripherals Enable."] #[inline(always)] - pub const fn set_mf(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u32) & 0x07) << 2usize); + pub const fn set_sirc_clk_periph_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "Modulation Depth Control."] + #[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)."] #[must_use] #[inline(always)] - pub const fn mr(&self) -> u8 { - let val = (self.0 >> 5usize) & 0x07; - val as u8 + pub const fn sirctren(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 } - #[doc = "Modulation Depth Control."] + #[doc = "SIRC 12 MHz Trim Enable (SIRCCFG\\[RANGE\\]=1)."] #[inline(always)] - pub const fn set_mr(&mut self, val: u8) { - self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u32) & 0x07) << 5usize); + pub const fn set_sirctren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "Modulation Waveform Control."] + #[doc = "SIRC Trim Update."] #[must_use] #[inline(always)] - pub const fn mc(&self) -> u8 { - let val = (self.0 >> 8usize) & 0x03; - val as u8 + pub const fn sirctrup(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 } - #[doc = "Modulation Waveform Control."] + #[doc = "SIRC Trim Update."] #[inline(always)] - pub const fn set_mc(&mut self, val: u8) { - self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + pub const fn set_sirctrup(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } - #[doc = "Dither Enable."] + #[doc = "SIRC TRIM LOCK."] #[must_use] #[inline(always)] - pub const fn dither(&self) -> bool { + pub const fn trim_lock(&self) -> SirccsrTrimLock { let val = (self.0 >> 10usize) & 0x01; - val != 0 + SirccsrTrimLock::from_bits(val as u8) } - #[doc = "Dither Enable."] + #[doc = "SIRC TRIM LOCK."] #[inline(always)] - pub const fn set_dither(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + pub const fn set_trim_lock(&mut self, val: SirccsrTrimLock) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); } - #[doc = "SS_MDIV select."] + #[doc = "Coarse Auto Trim Bypass."] #[must_use] #[inline(always)] - pub const fn sel_ss_mdiv(&self) -> bool { + pub const fn coarse_trim_bypass(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "SS_MDIV select."] + #[doc = "Coarse Auto Trim Bypass."] #[inline(always)] - pub const fn set_sel_ss_mdiv(&mut self, val: bool) { + pub const fn set_coarse_trim_bypass(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "SSCG Power Down."] + #[doc = "Lock Register."] #[must_use] #[inline(always)] - pub const fn ss_pd(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 + pub const fn lk(&self) -> SirccsrLk { + let val = (self.0 >> 23usize) & 0x01; + SirccsrLk::from_bits(val as u8) } - #[doc = "SSCG Power Down."] + #[doc = "Lock Register."] #[inline(always)] - pub const fn set_ss_pd(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_lk(&mut self, val: SirccsrLk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); } -} -impl Default for Spllsscg1 { + #[doc = "SIRC Valid."] + #[must_use] #[inline(always)] - fn default() -> Spllsscg1 { - Spllsscg1(0) + pub const fn sircvld(&self) -> Sircvld { + let val = (self.0 >> 24usize) & 0x01; + Sircvld::from_bits(val as u8) } -} -impl core::fmt::Debug for Spllsscg1 { + #[doc = "SIRC Valid."] + #[inline(always)] + pub const fn set_sircvld(&mut self, val: Sircvld) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + } + #[doc = "SIRC Selected."] + #[must_use] + #[inline(always)] + pub const fn sircsel(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "SIRC Selected."] + #[inline(always)] + pub const fn set_sircsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "SIRC Clock Error."] + #[must_use] + #[inline(always)] + pub const fn sircerr(&self) -> Sircerr { + let val = (self.0 >> 26usize) & 0x01; + Sircerr::from_bits(val as u8) + } + #[doc = "SIRC Clock Error."] + #[inline(always)] + pub const fn set_sircerr(&mut self, val: Sircerr) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + } + #[doc = "SIRC Clock Error Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn sircerr_ie(&self) -> SircerrIe { + let val = (self.0 >> 27usize) & 0x01; + SircerrIe::from_bits(val as u8) + } + #[doc = "SIRC Clock Error Interrupt Enable."] + #[inline(always)] + pub const fn set_sircerr_ie(&mut self, val: SircerrIe) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val.to_bits() as u32) & 0x01) << 27usize); + } +} +impl Default for Sirccsr { + #[inline(always)] + fn default() -> Sirccsr { + Sirccsr(0) + } +} +impl core::fmt::Debug for Sirccsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllsscg1") - .field("ss_mdiv_msb", &self.ss_mdiv_msb()) - .field("ss_mdiv_req", &self.ss_mdiv_req()) - .field("mf", &self.mf()) - .field("mr", &self.mr()) - .field("mc", &self.mc()) - .field("dither", &self.dither()) - .field("sel_ss_mdiv", &self.sel_ss_mdiv()) - .field("ss_pd", &self.ss_pd()) + f.debug_struct("Sirccsr") + .field("sircsten", &self.sircsten()) + .field("sirc_clk_periph_en", &self.sirc_clk_periph_en()) + .field("sirctren", &self.sirctren()) + .field("sirctrup", &self.sirctrup()) + .field("trim_lock", &self.trim_lock()) + .field("coarse_trim_bypass", &self.coarse_trim_bypass()) + .field("lk", &self.lk()) + .field("sircvld", &self.sircvld()) + .field("sircsel", &self.sircsel()) + .field("sircerr", &self.sircerr()) + .field("sircerr_ie", &self.sircerr_ie()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllsscg1 { +impl defmt::Format for Sirccsr { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllsscg1 {{ ss_mdiv_msb: {=bool:?}, ss_mdiv_req: {=bool:?}, mf: {=u8:?}, mr: {=u8:?}, mc: {=u8:?}, dither: {=bool:?}, sel_ss_mdiv: {=bool:?}, ss_pd: {=bool:?} }}", - self.ss_mdiv_msb(), - self.ss_mdiv_req(), - self.mf(), - self.mr(), - self.mc(), - self.dither(), - self.sel_ss_mdiv(), - self.ss_pd() + "Sirccsr {{ sircsten: {=bool:?}, sirc_clk_periph_en: {=bool:?}, sirctren: {=bool:?}, sirctrup: {=bool:?}, trim_lock: {:?}, coarse_trim_bypass: {=bool:?}, lk: {:?}, sircvld: {:?}, sircsel: {=bool:?}, sircerr: {:?}, sircerr_ie: {:?} }}", + self.sircsten(), + self.sirc_clk_periph_en(), + self.sirctren(), + self.sirctrup(), + self.trim_lock(), + self.coarse_trim_bypass(), + self.lk(), + self.sircvld(), + self.sircsel(), + self.sircerr(), + self.sircerr_ie() ) } } -#[doc = "SPLL SSCG Status Register."] +#[doc = "SIRC Auto-trimming Status Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllsscgstat(pub u32); -impl Spllsscgstat { - #[doc = "SS_MDIV change acknowledge."] +pub struct Sircstat(pub u32); +impl Sircstat { + #[doc = "CCO Trim."] #[must_use] #[inline(always)] - pub const fn ss_mdiv_ack(&self) -> bool { - let val = (self.0 >> 0usize) & 0x01; - val != 0 + pub const fn ccotrim(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 } - #[doc = "SS_MDIV change acknowledge."] + #[doc = "CCO Trim."] #[inline(always)] - pub const fn set_ss_mdiv_ack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + pub const fn set_ccotrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "CL Trim."] + #[must_use] + #[inline(always)] + pub const fn cltrim(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "CL Trim."] + #[inline(always)] + pub const fn set_cltrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); } } -impl Default for Spllsscgstat { +impl Default for Sircstat { #[inline(always)] - fn default() -> Spllsscgstat { - Spllsscgstat(0) + fn default() -> Sircstat { + Sircstat(0) } } -impl core::fmt::Debug for Spllsscgstat { +impl core::fmt::Debug for Sircstat { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllsscgstat") - .field("ss_mdiv_ack", &self.ss_mdiv_ack()) + f.debug_struct("Sircstat") + .field("ccotrim", &self.ccotrim()) + .field("cltrim", &self.cltrim()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllsscgstat { +impl defmt::Format for Sircstat { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllsscgstat {{ ss_mdiv_ack: {=bool:?} }}", - self.ss_mdiv_ack() + "Sircstat {{ ccotrim: {=u8:?}, cltrim: {=u8:?} }}", + self.ccotrim(), + self.cltrim() ) } } -#[doc = "SPLL Status Register."] +#[doc = "SIRC Trim Configuration Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Spllstat(pub u32); -impl Spllstat { - #[doc = "Pre-divider (N) ratio change acknowledge."] +pub struct Sirctcfg(pub u32); +impl Sirctcfg { + #[doc = "Trim Source."] #[must_use] #[inline(always)] - pub const fn ndivack(&self) -> bool { - let val = (self.0 >> 1usize) & 0x01; - val != 0 + pub const fn trimsrc(&self) -> SirctcfgTrimsrc { + let val = (self.0 >> 0usize) & 0x03; + SirctcfgTrimsrc::from_bits(val as u8) } - #[doc = "Pre-divider (N) ratio change acknowledge."] + #[doc = "Trim Source."] #[inline(always)] - pub const fn set_ndivack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + pub const fn set_trimsrc(&mut self, val: SirctcfgTrimsrc) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "Feedback (M) divider ratio change acknowledge."] + #[doc = "SIRC Trim Predivider."] #[must_use] #[inline(always)] - pub const fn mdivack(&self) -> bool { - let val = (self.0 >> 2usize) & 0x01; - val != 0 + pub const fn trimdiv(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x7f; + val as u8 } - #[doc = "Feedback (M) divider ratio change acknowledge."] + #[doc = "SIRC Trim Predivider."] #[inline(always)] - pub const fn set_mdivack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + pub const fn set_trimdiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize); + } +} +impl Default for Sirctcfg { + #[inline(always)] + fn default() -> Sirctcfg { + Sirctcfg(0) + } +} +impl core::fmt::Debug for Sirctcfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sirctcfg") + .field("trimsrc", &self.trimsrc()) + .field("trimdiv", &self.trimdiv()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sirctcfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sirctcfg {{ trimsrc: {:?}, trimdiv: {=u8:?} }}", + self.trimsrc(), + self.trimdiv() + ) } - #[doc = "Post-divider (P) ratio change acknowledge."] +} +#[doc = "SIRC Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sirctest(pub u32); +impl Sirctest { + #[doc = "SIRC ATX Test Enable."] #[must_use] #[inline(always)] - pub const fn pdivack(&self) -> bool { - let val = (self.0 >> 3usize) & 0x01; + pub const fn test(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Post-divider (P) ratio change acknowledge."] + #[doc = "SIRC ATX Test Enable."] #[inline(always)] - pub const fn set_pdivack(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + pub const fn set_test(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "Free running detector (active high)."] + #[doc = "SIRC Div-by-16 Output Enable."] #[must_use] #[inline(always)] - pub const fn frmdet(&self) -> bool { + pub const fn div16en(&self) -> Div16en { let val = (self.0 >> 4usize) & 0x01; - val != 0 + Div16en::from_bits(val as u8) } - #[doc = "Free running detector (active high)."] + #[doc = "SIRC Div-by-16 Output Enable."] #[inline(always)] - pub const fn set_frmdet(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + pub const fn set_div16en(&mut self, val: Div16en) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } + #[doc = "SIRC Flip Buffer Inputs Enable."] + #[must_use] + #[inline(always)] + pub const fn flip_buf_in(&self) -> FlipBufIn { + let val = (self.0 >> 5usize) & 0x01; + FlipBufIn::from_bits(val as u8) + } + #[doc = "SIRC Flip Buffer Inputs Enable."] + #[inline(always)] + pub const fn set_flip_buf_in(&mut self, val: FlipBufIn) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + } + #[doc = "SIRC Buffer Bypass."] + #[must_use] + #[inline(always)] + pub const fn test_buf_bypass(&self) -> TestBufBypass { + let val = (self.0 >> 6usize) & 0x01; + TestBufBypass::from_bits(val as u8) + } + #[doc = "SIRC Buffer Bypass."] + #[inline(always)] + pub const fn set_test_buf_bypass(&mut self, val: TestBufBypass) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + } + #[doc = "SIRC Test Select."] + #[must_use] + #[inline(always)] + pub const fn test_sel(&self) -> TestSel { + let val = (self.0 >> 8usize) & 0x03; + TestSel::from_bits(val as u8) + } + #[doc = "SIRC Test Select."] + #[inline(always)] + pub const fn set_test_sel(&mut self, val: TestSel) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); } } -impl Default for Spllstat { +impl Default for Sirctest { #[inline(always)] - fn default() -> Spllstat { - Spllstat(0) + fn default() -> Sirctest { + Sirctest(0) } } -impl core::fmt::Debug for Spllstat { +impl core::fmt::Debug for Sirctest { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Spllstat") - .field("ndivack", &self.ndivack()) - .field("mdivack", &self.mdivack()) - .field("pdivack", &self.pdivack()) - .field("frmdet", &self.frmdet()) + f.debug_struct("Sirctest") + .field("test", &self.test()) + .field("div16en", &self.div16en()) + .field("flip_buf_in", &self.flip_buf_in()) + .field("test_buf_bypass", &self.test_buf_bypass()) + .field("test_sel", &self.test_sel()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Spllstat { +impl defmt::Format for Sirctest { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Spllstat {{ ndivack: {=bool:?}, mdivack: {=bool:?}, pdivack: {=bool:?}, frmdet: {=bool:?} }}", - self.ndivack(), - self.mdivack(), - self.pdivack(), - self.frmdet() + "Sirctest {{ test: {=bool:?}, div16en: {:?}, flip_buf_in: {:?}, test_buf_bypass: {:?}, test_sel: {:?} }}", + self.test(), + self.div16en(), + self.flip_buf_in(), + self.test_buf_bypass(), + self.test_sel() ) } } -#[doc = "Trim Lock register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct TrimLock(pub u32); -impl TrimLock { - #[doc = "TRIM_UNLOCK."] - #[must_use] +#[doc = "SIRC Trim Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sirctrim(pub u32); +impl Sirctrim { + #[doc = "CCO Trim."] + #[must_use] + #[inline(always)] + pub const fn ccotrim(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "CCO Trim."] + #[inline(always)] + pub const fn set_ccotrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "CL Trim."] + #[must_use] + #[inline(always)] + pub const fn cltrim(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x3f; + val as u8 + } + #[doc = "CL Trim."] + #[inline(always)] + pub const fn set_cltrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 8usize)) | (((val as u32) & 0x3f) << 8usize); + } + #[doc = "Trim Temp."] + #[must_use] + #[inline(always)] + pub const fn tctrim(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "Trim Temp."] + #[inline(always)] + pub const fn set_tctrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "Calibrates the replica voltage in FSU for CCO to get well frequency at initial period."] + #[must_use] + #[inline(always)] + pub const fn fvchtrim(&self) -> u8 { + let val = (self.0 >> 24usize) & 0x1f; + val as u8 + } + #[doc = "Calibrates the replica voltage in FSU for CCO to get well frequency at initial period."] + #[inline(always)] + pub const fn set_fvchtrim(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 24usize)) | (((val as u32) & 0x1f) << 24usize); + } +} +impl Default for Sirctrim { + #[inline(always)] + fn default() -> Sirctrim { + Sirctrim(0) + } +} +impl core::fmt::Debug for Sirctrim { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sirctrim") + .field("ccotrim", &self.ccotrim()) + .field("cltrim", &self.cltrim()) + .field("tctrim", &self.tctrim()) + .field("fvchtrim", &self.fvchtrim()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sirctrim { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sirctrim {{ ccotrim: {=u8:?}, cltrim: {=u8:?}, tctrim: {=u8:?}, fvchtrim: {=u8:?} }}", + self.ccotrim(), + self.cltrim(), + self.tctrim(), + self.fvchtrim() + ) + } +} +#[doc = "SOSC Configuration Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sosccfg(pub u32); +impl Sosccfg { + #[doc = "External Reference Select(connect to analog pin ~en_byp_lv)."] + #[must_use] + #[inline(always)] + pub const fn erefs(&self) -> Erefs { + let val = (self.0 >> 2usize) & 0x01; + Erefs::from_bits(val as u8) + } + #[doc = "External Reference Select(connect to analog pin ~en_byp_lv)."] + #[inline(always)] + pub const fn set_erefs(&mut self, val: Erefs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "SOSC Range Select(connect to analog pin gm_lv\\[1:0\\])."] + #[must_use] + #[inline(always)] + pub const fn range(&self) -> Range { + let val = (self.0 >> 4usize) & 0x03; + Range::from_bits(val as u8) + } + #[doc = "SOSC Range Select(connect to analog pin gm_lv\\[1:0\\])."] + #[inline(always)] + pub const fn set_range(&mut self, val: Range) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); + } +} +impl Default for Sosccfg { + #[inline(always)] + fn default() -> Sosccfg { + Sosccfg(0) + } +} +impl core::fmt::Debug for Sosccfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sosccfg") + .field("erefs", &self.erefs()) + .field("range", &self.range()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sosccfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sosccfg {{ erefs: {:?}, range: {:?} }}", + self.erefs(), + self.range() + ) + } +} +#[doc = "SOSC Control Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sosccsr(pub u32); +impl Sosccsr { + #[doc = "SOSC Enable."] + #[must_use] + #[inline(always)] + pub const fn soscen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SOSC Enable."] + #[inline(always)] + pub const fn set_soscen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SOSC Stop Enable."] + #[must_use] + #[inline(always)] + pub const fn soscsten(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SOSC Stop Enable."] + #[inline(always)] + pub const fn set_soscsten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SOSC Clock Monitor Enable."] + #[must_use] + #[inline(always)] + pub const fn sosccm(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SOSC Clock Monitor Enable."] + #[inline(always)] + pub const fn set_sosccm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "SOSC Clock Monitor Reset Enable."] + #[must_use] + #[inline(always)] + pub const fn sosccmre(&self) -> Sosccmre { + let val = (self.0 >> 17usize) & 0x01; + Sosccmre::from_bits(val as u8) + } + #[doc = "SOSC Clock Monitor Reset Enable."] + #[inline(always)] + pub const fn set_sosccmre(&mut self, val: Sosccmre) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + } + #[doc = "Lock Register."] + #[must_use] + #[inline(always)] + pub const fn lk(&self) -> SosccsrLk { + let val = (self.0 >> 23usize) & 0x01; + SosccsrLk::from_bits(val as u8) + } + #[doc = "Lock Register."] + #[inline(always)] + pub const fn set_lk(&mut self, val: SosccsrLk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + } + #[doc = "SOSC Valid."] + #[must_use] + #[inline(always)] + pub const fn soscvld(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "SOSC Valid."] + #[inline(always)] + pub const fn set_soscvld(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "SOSC Selected."] + #[must_use] + #[inline(always)] + pub const fn soscsel(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "SOSC Selected."] + #[inline(always)] + pub const fn set_soscsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "SOSC Clock Error."] + #[must_use] + #[inline(always)] + pub const fn soscerr(&self) -> Soscerr { + let val = (self.0 >> 26usize) & 0x01; + Soscerr::from_bits(val as u8) + } + #[doc = "SOSC Clock Error."] + #[inline(always)] + pub const fn set_soscerr(&mut self, val: Soscerr) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + } + #[doc = "SOSC Valid Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn soscvld_ie(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "SOSC Valid Interrupt Enable."] + #[inline(always)] + pub const fn set_soscvld_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } +} +impl Default for Sosccsr { + #[inline(always)] + fn default() -> Sosccsr { + Sosccsr(0) + } +} +impl core::fmt::Debug for Sosccsr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sosccsr") + .field("soscen", &self.soscen()) + .field("soscsten", &self.soscsten()) + .field("sosccm", &self.sosccm()) + .field("sosccmre", &self.sosccmre()) + .field("lk", &self.lk()) + .field("soscvld", &self.soscvld()) + .field("soscsel", &self.soscsel()) + .field("soscerr", &self.soscerr()) + .field("soscvld_ie", &self.soscvld_ie()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sosccsr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sosccsr {{ soscen: {=bool:?}, soscsten: {=bool:?}, sosccm: {=bool:?}, sosccmre: {:?}, lk: {:?}, soscvld: {=bool:?}, soscsel: {=bool:?}, soscerr: {:?}, soscvld_ie: {=bool:?} }}", + self.soscen(), + self.soscsten(), + self.sosccm(), + self.sosccmre(), + self.lk(), + self.soscvld(), + self.soscsel(), + self.soscerr(), + self.soscvld_ie() + ) + } +} +#[doc = "SOSC Test Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Sosctest(pub u32); +impl Sosctest { + #[doc = "SOSC XTM Test Mode Enable (connect to analog pin xtm_lv)."] + #[must_use] + #[inline(always)] + pub const fn sosc_xtm_test_mode_en(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "SOSC XTM Test Mode Enable (connect to analog pin xtm_lv)."] + #[inline(always)] + pub const fn set_sosc_xtm_test_mode_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "OSC Test Select (connect to analog pin tst_md_lv\\[1:0\\])."] + #[must_use] + #[inline(always)] + pub const fn tstmd(&self) -> Tstmd { + let val = (self.0 >> 8usize) & 0x03; + Tstmd::from_bits(val as u8) + } + #[doc = "OSC Test Select (connect to analog pin tst_md_lv\\[1:0\\])."] + #[inline(always)] + pub const fn set_tstmd(&mut self, val: Tstmd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } + #[doc = "The analog output xo_ok_lv."] + #[must_use] + #[inline(always)] + pub const fn xo_ok_lv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "The analog output xo_ok_lv."] + #[inline(always)] + pub const fn set_xo_ok_lv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } +} +impl Default for Sosctest { + #[inline(always)] + fn default() -> Sosctest { + Sosctest(0) + } +} +impl core::fmt::Debug for Sosctest { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sosctest") + .field("sosc_xtm_test_mode_en", &self.sosc_xtm_test_mode_en()) + .field("tstmd", &self.tstmd()) + .field("xo_ok_lv", &self.xo_ok_lv()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Sosctest { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Sosctest {{ sosc_xtm_test_mode_en: {=bool:?}, tstmd: {:?}, xo_ok_lv: {=bool:?} }}", + self.sosc_xtm_test_mode_en(), + self.tstmd(), + self.xo_ok_lv() + ) + } +} +#[doc = "SPLL Control Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllcsr(pub u32); +impl Spllcsr { + #[doc = "SPLL Power Enable."] + #[must_use] + #[inline(always)] + pub const fn spllpwren(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SPLL Power Enable."] + #[inline(always)] + pub const fn set_spllpwren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SPLL Clock Enable."] + #[must_use] + #[inline(always)] + pub const fn spllclken(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SPLL Clock Enable."] + #[inline(always)] + pub const fn set_spllclken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SPLL Stop Enable."] + #[must_use] + #[inline(always)] + pub const fn spllsten(&self) -> Spllsten { + let val = (self.0 >> 2usize) & 0x01; + Spllsten::from_bits(val as u8) + } + #[doc = "SPLL Stop Enable."] + #[inline(always)] + pub const fn set_spllsten(&mut self, val: Spllsten) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "Free running mode clock stable."] + #[must_use] + #[inline(always)] + pub const fn frm_clockstable(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Free running mode clock stable."] + #[inline(always)] + pub const fn set_frm_clockstable(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SPLL Clock Monitor."] + #[must_use] + #[inline(always)] + pub const fn spllcm(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SPLL Clock Monitor."] + #[inline(always)] + pub const fn set_spllcm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "SPLL Clock Monitor Reset Enable."] + #[must_use] + #[inline(always)] + pub const fn spllcmre(&self) -> Spllcmre { + let val = (self.0 >> 17usize) & 0x01; + Spllcmre::from_bits(val as u8) + } + #[doc = "SPLL Clock Monitor Reset Enable."] + #[inline(always)] + pub const fn set_spllcmre(&mut self, val: Spllcmre) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + } + #[doc = "Lock Register."] + #[must_use] + #[inline(always)] + pub const fn lk(&self) -> SpllcsrLk { + let val = (self.0 >> 23usize) & 0x01; + SpllcsrLk::from_bits(val as u8) + } + #[doc = "Lock Register."] + #[inline(always)] + pub const fn set_lk(&mut self, val: SpllcsrLk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + } + #[doc = "SPLL LOCK."] + #[must_use] + #[inline(always)] + pub const fn spll_lock(&self) -> SpllLock { + let val = (self.0 >> 24usize) & 0x01; + SpllLock::from_bits(val as u8) + } + #[doc = "SPLL LOCK."] + #[inline(always)] + pub const fn set_spll_lock(&mut self, val: SpllLock) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + } + #[doc = "SPLL Selected."] + #[must_use] + #[inline(always)] + pub const fn spllsel(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "SPLL Selected."] + #[inline(always)] + pub const fn set_spllsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "SPLL Clock Error."] + #[must_use] + #[inline(always)] + pub const fn spllerr(&self) -> Spllerr { + let val = (self.0 >> 26usize) & 0x01; + Spllerr::from_bits(val as u8) + } + #[doc = "SPLL Clock Error."] + #[inline(always)] + pub const fn set_spllerr(&mut self, val: Spllerr) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + } + #[doc = "SPLL LOCK Interrupt Enable."] + #[must_use] + #[inline(always)] + pub const fn spll_lock_ie(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "SPLL LOCK Interrupt Enable."] + #[inline(always)] + pub const fn set_spll_lock_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } +} +impl Default for Spllcsr { + #[inline(always)] + fn default() -> Spllcsr { + Spllcsr(0) + } +} +impl core::fmt::Debug for Spllcsr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllcsr") + .field("spllpwren", &self.spllpwren()) + .field("spllclken", &self.spllclken()) + .field("spllsten", &self.spllsten()) + .field("frm_clockstable", &self.frm_clockstable()) + .field("spllcm", &self.spllcm()) + .field("spllcmre", &self.spllcmre()) + .field("lk", &self.lk()) + .field("spll_lock", &self.spll_lock()) + .field("spllsel", &self.spllsel()) + .field("spllerr", &self.spllerr()) + .field("spll_lock_ie", &self.spll_lock_ie()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllcsr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllcsr {{ spllpwren: {=bool:?}, spllclken: {=bool:?}, spllsten: {:?}, frm_clockstable: {=bool:?}, spllcm: {=bool:?}, spllcmre: {:?}, lk: {:?}, spll_lock: {:?}, spllsel: {=bool:?}, spllerr: {:?}, spll_lock_ie: {=bool:?} }}", + self.spllpwren(), + self.spllclken(), + self.spllsten(), + self.frm_clockstable(), + self.spllcm(), + self.spllcmre(), + self.lk(), + self.spll_lock(), + self.spllsel(), + self.spllerr(), + self.spll_lock_ie() + ) + } +} +#[doc = "SPLL Control Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllctrl(pub u32); +impl Spllctrl { + #[doc = "Bandwidth select R (resistor) value."] + #[must_use] + #[inline(always)] + pub const fn selr(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Bandwidth select R (resistor) value."] + #[inline(always)] + pub const fn set_selr(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "Bandwidth select I (integration) value."] + #[must_use] + #[inline(always)] + pub const fn seli(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x3f; + val as u8 + } + #[doc = "Bandwidth select I (integration) value."] + #[inline(always)] + pub const fn set_seli(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 4usize)) | (((val as u32) & 0x3f) << 4usize); + } + #[doc = "Bandwidth select P (proportional) value."] + #[must_use] + #[inline(always)] + pub const fn selp(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x1f; + val as u8 + } + #[doc = "Bandwidth select P (proportional) value."] + #[inline(always)] + pub const fn set_selp(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 10usize)) | (((val as u32) & 0x1f) << 10usize); + } + #[doc = "Bypass of Divide-by-2 Divider."] + #[must_use] + #[inline(always)] + pub const fn bypasspostdiv2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Bypass of Divide-by-2 Divider."] + #[inline(always)] + pub const fn set_bypasspostdiv2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Up Limiter."] + #[must_use] + #[inline(always)] + pub const fn limupoff(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Up Limiter."] + #[inline(always)] + pub const fn set_limupoff(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Control of the bandwidth of the PLL."] + #[must_use] + #[inline(always)] + pub const fn banddirect(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Control of the bandwidth of the PLL."] + #[inline(always)] + pub const fn set_banddirect(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bypass of the predivider."] + #[must_use] + #[inline(always)] + pub const fn bypassprediv(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bypass of the predivider."] + #[inline(always)] + pub const fn set_bypassprediv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Bypass of the postdivider."] + #[must_use] + #[inline(always)] + pub const fn bypasspostdiv(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Bypass of the postdivider."] + #[inline(always)] + pub const fn set_bypasspostdiv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "Free Running Mode Enable."] + #[must_use] + #[inline(always)] + pub const fn frm(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Free Running Mode Enable."] + #[inline(always)] + pub const fn set_frm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Skew mode."] + #[must_use] + #[inline(always)] + pub const fn skew_en(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Skew mode."] + #[inline(always)] + pub const fn set_skew_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Clock Source."] + #[must_use] + #[inline(always)] + pub const fn source(&self) -> Source { + let val = (self.0 >> 25usize) & 0x03; + Source::from_bits(val as u8) + } + #[doc = "Clock Source."] + #[inline(always)] + pub const fn set_source(&mut self, val: Source) { + self.0 = (self.0 & !(0x03 << 25usize)) | (((val.to_bits() as u32) & 0x03) << 25usize); + } +} +impl Default for Spllctrl { + #[inline(always)] + fn default() -> Spllctrl { + Spllctrl(0) + } +} +impl core::fmt::Debug for Spllctrl { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllctrl") + .field("selr", &self.selr()) + .field("seli", &self.seli()) + .field("selp", &self.selp()) + .field("bypasspostdiv2", &self.bypasspostdiv2()) + .field("limupoff", &self.limupoff()) + .field("banddirect", &self.banddirect()) + .field("bypassprediv", &self.bypassprediv()) + .field("bypasspostdiv", &self.bypasspostdiv()) + .field("frm", &self.frm()) + .field("skew_en", &self.skew_en()) + .field("source", &self.source()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllctrl { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllctrl {{ selr: {=u8:?}, seli: {=u8:?}, selp: {=u8:?}, bypasspostdiv2: {=bool:?}, limupoff: {=bool:?}, banddirect: {=bool:?}, bypassprediv: {=bool:?}, bypasspostdiv: {=bool:?}, frm: {=bool:?}, skew_en: {=bool:?}, source: {:?} }}", + self.selr(), + self.seli(), + self.selp(), + self.bypasspostdiv2(), + self.limupoff(), + self.banddirect(), + self.bypassprediv(), + self.bypasspostdiv(), + self.frm(), + self.skew_en(), + self.source() + ) + } +} +#[doc = "SPLL LOCK Configuration Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct SplllockCnfg(pub u32); +impl SplllockCnfg { + #[doc = "Configures the number of reference clocks to count before SPLL is considered locked."] + #[must_use] + #[inline(always)] + pub const fn lock_time(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x0001_ffff; + val as u32 + } + #[doc = "Configures the number of reference clocks to count before SPLL is considered locked."] + #[inline(always)] + pub const fn set_lock_time(&mut self, val: u32) { + self.0 = (self.0 & !(0x0001_ffff << 0usize)) | (((val as u32) & 0x0001_ffff) << 0usize); + } +} +impl Default for SplllockCnfg { + #[inline(always)] + fn default() -> SplllockCnfg { + SplllockCnfg(0) + } +} +impl core::fmt::Debug for SplllockCnfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SplllockCnfg") + .field("lock_time", &self.lock_time()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for SplllockCnfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "SplllockCnfg {{ lock_time: {=u32:?} }}", + self.lock_time() + ) + } +} +#[doc = "SPLL M Divider Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllmdiv(pub u32); +impl Spllmdiv { + #[doc = "Feedback divider divider ratio (M-divider)."] + #[must_use] + #[inline(always)] + pub const fn mdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Feedback divider divider ratio (M-divider)."] + #[inline(always)] + pub const fn set_mdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + #[doc = "Feedback ratio change request."] + #[must_use] + #[inline(always)] + pub const fn mreq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Feedback ratio change request."] + #[inline(always)] + pub const fn set_mreq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Spllmdiv { + #[inline(always)] + fn default() -> Spllmdiv { + Spllmdiv(0) + } +} +impl core::fmt::Debug for Spllmdiv { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllmdiv") + .field("mdiv", &self.mdiv()) + .field("mreq", &self.mreq()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllmdiv { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllmdiv {{ mdiv: {=u16:?}, mreq: {=bool:?} }}", + self.mdiv(), + self.mreq() + ) + } +} +#[doc = "SPLL N Divider Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllndiv(pub u32); +impl Spllndiv { + #[doc = "Predivider divider ratio (N-divider)."] + #[must_use] + #[inline(always)] + pub const fn ndiv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Predivider divider ratio (N-divider)."] + #[inline(always)] + pub const fn set_ndiv(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Predivider ratio change request."] + #[must_use] + #[inline(always)] + pub const fn nreq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Predivider ratio change request."] + #[inline(always)] + pub const fn set_nreq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Spllndiv { + #[inline(always)] + fn default() -> Spllndiv { + Spllndiv(0) + } +} +impl core::fmt::Debug for Spllndiv { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllndiv") + .field("ndiv", &self.ndiv()) + .field("nreq", &self.nreq()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllndiv { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllndiv {{ ndiv: {=u8:?}, nreq: {=bool:?} }}", + self.ndiv(), + self.nreq() + ) + } +} +#[doc = "SPLL P Divider Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllpdiv(pub u32); +impl Spllpdiv { + #[doc = "Postdivider divider ratio (P-divider)."] + #[must_use] + #[inline(always)] + pub const fn pdiv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "Postdivider divider ratio (P-divider)."] + #[inline(always)] + pub const fn set_pdiv(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "Postdivider ratio change request."] + #[must_use] + #[inline(always)] + pub const fn preq(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Postdivider ratio change request."] + #[inline(always)] + pub const fn set_preq(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Spllpdiv { + #[inline(always)] + fn default() -> Spllpdiv { + Spllpdiv(0) + } +} +impl core::fmt::Debug for Spllpdiv { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllpdiv") + .field("pdiv", &self.pdiv()) + .field("preq", &self.preq()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllpdiv { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllpdiv {{ pdiv: {=u8:?}, preq: {=bool:?} }}", + self.pdiv(), + self.preq() + ) + } +} +#[doc = "SPLL Spread Spectrum Control 0 Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllsscg0(pub u32); +impl Spllsscg0 { + #[doc = "SS_MDIV\\[31:0\\]."] + #[must_use] + #[inline(always)] + pub const fn ss_mdiv_lsb(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "SS_MDIV\\[31:0\\]."] + #[inline(always)] + pub const fn set_ss_mdiv_lsb(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Spllsscg0 { + #[inline(always)] + fn default() -> Spllsscg0 { + Spllsscg0(0) + } +} +impl core::fmt::Debug for Spllsscg0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllsscg0") + .field("ss_mdiv_lsb", &self.ss_mdiv_lsb()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllsscg0 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllsscg0 {{ ss_mdiv_lsb: {=u32:?} }}", + self.ss_mdiv_lsb() + ) + } +} +#[doc = "SPLL Spread Spectrum Control 1 Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllsscg1(pub u32); +impl Spllsscg1 { + #[doc = "SS_MDIV\\[32\\]."] + #[must_use] + #[inline(always)] + pub const fn ss_mdiv_msb(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SS_MDIV\\[32\\]."] + #[inline(always)] + pub const fn set_ss_mdiv_msb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SS_MDIV\\[32:0\\] change request."] + #[must_use] + #[inline(always)] + pub const fn ss_mdiv_req(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SS_MDIV\\[32:0\\] change request."] + #[inline(always)] + pub const fn set_ss_mdiv_req(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Modulation Frequency Control."] + #[must_use] + #[inline(always)] + pub const fn mf(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x07; + val as u8 + } + #[doc = "Modulation Frequency Control."] + #[inline(always)] + pub const fn set_mf(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 2usize)) | (((val as u32) & 0x07) << 2usize); + } + #[doc = "Modulation Depth Control."] + #[must_use] + #[inline(always)] + pub const fn mr(&self) -> u8 { + let val = (self.0 >> 5usize) & 0x07; + val as u8 + } + #[doc = "Modulation Depth Control."] + #[inline(always)] + pub const fn set_mr(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 5usize)) | (((val as u32) & 0x07) << 5usize); + } + #[doc = "Modulation Waveform Control."] + #[must_use] + #[inline(always)] + pub const fn mc(&self) -> Spllsscg1Mc { + let val = (self.0 >> 8usize) & 0x03; + Spllsscg1Mc::from_bits(val as u8) + } + #[doc = "Modulation Waveform Control."] + #[inline(always)] + pub const fn set_mc(&mut self, val: Spllsscg1Mc) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize); + } + #[doc = "Dither Enable."] + #[must_use] + #[inline(always)] + pub const fn dither(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Dither Enable."] + #[inline(always)] + pub const fn set_dither(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "SS_MDIV select."] + #[must_use] + #[inline(always)] + pub const fn sel_ss_mdiv(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SS_MDIV select."] + #[inline(always)] + pub const fn set_sel_ss_mdiv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "SSCG Power Down."] + #[must_use] + #[inline(always)] + pub const fn ss_pd(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "SSCG Power Down."] + #[inline(always)] + pub const fn set_ss_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Spllsscg1 { + #[inline(always)] + fn default() -> Spllsscg1 { + Spllsscg1(0) + } +} +impl core::fmt::Debug for Spllsscg1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllsscg1") + .field("ss_mdiv_msb", &self.ss_mdiv_msb()) + .field("ss_mdiv_req", &self.ss_mdiv_req()) + .field("mf", &self.mf()) + .field("mr", &self.mr()) + .field("mc", &self.mc()) + .field("dither", &self.dither()) + .field("sel_ss_mdiv", &self.sel_ss_mdiv()) + .field("ss_pd", &self.ss_pd()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllsscg1 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllsscg1 {{ ss_mdiv_msb: {=bool:?}, ss_mdiv_req: {=bool:?}, mf: {=u8:?}, mr: {=u8:?}, mc: {:?}, dither: {=bool:?}, sel_ss_mdiv: {=bool:?}, ss_pd: {=bool:?} }}", + self.ss_mdiv_msb(), + self.ss_mdiv_req(), + self.mf(), + self.mr(), + self.mc(), + self.dither(), + self.sel_ss_mdiv(), + self.ss_pd() + ) + } +} +#[doc = "SPLL SSCG Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllsscgstat(pub u32); +impl Spllsscgstat { + #[doc = "SS_MDIV change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn ss_mdiv_ack(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SS_MDIV change acknowledge."] + #[inline(always)] + pub const fn set_ss_mdiv_ack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } +} +impl Default for Spllsscgstat { + #[inline(always)] + fn default() -> Spllsscgstat { + Spllsscgstat(0) + } +} +impl core::fmt::Debug for Spllsscgstat { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllsscgstat") + .field("ss_mdiv_ack", &self.ss_mdiv_ack()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllsscgstat { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllsscgstat {{ ss_mdiv_ack: {=bool:?} }}", + self.ss_mdiv_ack() + ) + } +} +#[doc = "SPLL Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllstat(pub u32); +impl Spllstat { + #[doc = "Lock detector output (active high)."] + #[must_use] + #[inline(always)] + pub const fn lock(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Lock detector output (active high)."] + #[inline(always)] + pub const fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Predivider (N) ratio change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn ndivack(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Predivider (N) ratio change acknowledge."] + #[inline(always)] + pub const fn set_ndivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Feedback (M) divider ratio change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn mdivack(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Feedback (M) divider ratio change acknowledge."] + #[inline(always)] + pub const fn set_mdivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Postdivider (P) ratio change acknowledge."] + #[must_use] + #[inline(always)] + pub const fn pdivack(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Postdivider (P) ratio change acknowledge."] + #[inline(always)] + pub const fn set_pdivack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Free running detector (active high)."] + #[must_use] + #[inline(always)] + pub const fn frmdet(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Free running detector (active high)."] + #[inline(always)] + pub const fn set_frmdet(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } +} +impl Default for Spllstat { + #[inline(always)] + fn default() -> Spllstat { + Spllstat(0) + } +} +impl core::fmt::Debug for Spllstat { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllstat") + .field("lock", &self.lock()) + .field("ndivack", &self.ndivack()) + .field("mdivack", &self.mdivack()) + .field("pdivack", &self.pdivack()) + .field("frmdet", &self.frmdet()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllstat { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllstat {{ lock: {=bool:?}, ndivack: {=bool:?}, mdivack: {=bool:?}, pdivack: {=bool:?}, frmdet: {=bool:?} }}", + self.lock(), + self.ndivack(), + self.mdivack(), + self.pdivack(), + self.frmdet() + ) + } +} +#[doc = "SPLL Test Control Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Splltestctrl(pub u32); +impl Splltestctrl { + #[doc = "Input to functional test the predivider (N-divider)."] + #[must_use] + #[inline(always)] + pub const fn nfunctest(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x7f; + val as u8 + } + #[doc = "Input to functional test the predivider (N-divider)."] + #[inline(always)] + pub const fn set_nfunctest(&mut self, val: u8) { + self.0 = (self.0 & !(0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize); + } + #[doc = "Input to functional test the feedback divider (M-divider)."] + #[must_use] + #[inline(always)] + pub const fn mfunctest(&self) -> u16 { + let val = (self.0 >> 7usize) & 0x7fff; + val as u16 + } + #[doc = "Input to functional test the feedback divider (M-divider)."] + #[inline(always)] + pub const fn set_mfunctest(&mut self, val: u16) { + self.0 = (self.0 & !(0x7fff << 7usize)) | (((val as u32) & 0x7fff) << 7usize); + } + #[doc = "Input to functional test the postdivider (P-divider)."] + #[must_use] + #[inline(always)] + pub const fn pfunctest(&self) -> u8 { + let val = (self.0 >> 22usize) & 0x0f; + val as u8 + } + #[doc = "Input to functional test the postdivider (P-divider)."] + #[inline(always)] + pub const fn set_pfunctest(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 22usize)) | (((val as u32) & 0x0f) << 22usize); + } + #[doc = "Enable test mux."] + #[must_use] + #[inline(always)] + pub const fn testv_en(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Enable test mux."] + #[inline(always)] + pub const fn set_testv_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "Select analog signal channel that need to be test."] + #[must_use] + #[inline(always)] + pub const fn testv_sel(&self) -> SplltestctrlTestvSel { + let val = (self.0 >> 27usize) & 0x07; + SplltestctrlTestvSel::from_bits(val as u8) + } + #[doc = "Select analog signal channel that need to be test."] + #[inline(always)] + pub const fn set_testv_sel(&mut self, val: SplltestctrlTestvSel) { + self.0 = (self.0 & !(0x07 << 27usize)) | (((val.to_bits() as u32) & 0x07) << 27usize); + } + #[doc = "Bypass PLL."] + #[must_use] + #[inline(always)] + pub const fn bypasspll(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Bypass PLL."] + #[inline(always)] + pub const fn set_bypasspll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Splltestctrl { + #[inline(always)] + fn default() -> Splltestctrl { + Splltestctrl(0) + } +} +impl core::fmt::Debug for Splltestctrl { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Splltestctrl") + .field("nfunctest", &self.nfunctest()) + .field("mfunctest", &self.mfunctest()) + .field("pfunctest", &self.pfunctest()) + .field("testv_en", &self.testv_en()) + .field("testv_sel", &self.testv_sel()) + .field("bypasspll", &self.bypasspll()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Splltestctrl { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Splltestctrl {{ nfunctest: {=u8:?}, mfunctest: {=u16:?}, pfunctest: {=u8:?}, testv_en: {=bool:?}, testv_sel: {:?}, bypasspll: {=bool:?} }}", + self.nfunctest(), + self.mfunctest(), + self.pfunctest(), + self.testv_en(), + self.testv_sel(), + self.bypasspll() + ) + } +} +#[doc = "SPLL Test Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Spllteststat(pub u32); +impl Spllteststat { + #[doc = "Output to observe the functional predivider test."] + #[must_use] + #[inline(always)] + pub const fn nmotest(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "Output to observe the functional predivider test."] + #[inline(always)] + pub const fn set_nmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Output to observe the functional feedback divider test."] + #[must_use] + #[inline(always)] + pub const fn mmotest(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; + val as u8 + } + #[doc = "Output to observe the functional feedback divider test."] + #[inline(always)] + pub const fn set_mmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + } + #[doc = "Output to observe the functional postdivider test."] + #[must_use] + #[inline(always)] + pub const fn pmotest(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x03; + val as u8 + } + #[doc = "Output to observe the functional postdivider test."] + #[inline(always)] + pub const fn set_pmotest(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize); + } + #[doc = "PLL functional divider test clock pulse."] + #[must_use] + #[inline(always)] + pub const fn pll_xfunc_test_pulse(&self) -> bool { + let val = (self.0 >> 29usize) & 0x01; + val != 0 + } + #[doc = "PLL functional divider test clock pulse."] + #[inline(always)] + pub const fn set_pll_xfunc_test_pulse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize); + } + #[doc = "Enable PLL functional divider test clock pulse."] + #[must_use] + #[inline(always)] + pub const fn pll_xfunc_test_en(&self) -> bool { + let val = (self.0 >> 30usize) & 0x01; + val != 0 + } + #[doc = "Enable PLL functional divider test clock pulse."] + #[inline(always)] + pub const fn set_pll_xfunc_test_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize); + } + #[doc = "Enable to observe the xMOTEST flags."] + #[must_use] + #[inline(always)] + pub const fn pll_xmo_test_en(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Enable to observe the xMOTEST flags."] + #[inline(always)] + pub const fn set_pll_xmo_test_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Spllteststat { + #[inline(always)] + fn default() -> Spllteststat { + Spllteststat(0) + } +} +impl core::fmt::Debug for Spllteststat { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spllteststat") + .field("nmotest", &self.nmotest()) + .field("mmotest", &self.mmotest()) + .field("pmotest", &self.pmotest()) + .field("pll_xfunc_test_pulse", &self.pll_xfunc_test_pulse()) + .field("pll_xfunc_test_en", &self.pll_xfunc_test_en()) + .field("pll_xmo_test_en", &self.pll_xmo_test_en()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Spllteststat { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Spllteststat {{ nmotest: {=u8:?}, mmotest: {=u8:?}, pmotest: {=u8:?}, pll_xfunc_test_pulse: {=bool:?}, pll_xfunc_test_en: {=bool:?}, pll_xmo_test_en: {=bool:?} }}", + self.nmotest(), + self.mmotest(), + self.pmotest(), + self.pll_xfunc_test_pulse(), + self.pll_xfunc_test_en(), + self.pll_xmo_test_en() + ) + } +} +#[doc = "Trim Lock register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct TrimLock(pub u32); +impl TrimLock { + #[doc = "TRIM_UNLOCK."] + #[must_use] + #[inline(always)] + pub const fn trim_unlock(&self) -> TrimUnlock { + let val = (self.0 >> 0usize) & 0x01; + TrimUnlock::from_bits(val as u8) + } + #[doc = "TRIM_UNLOCK."] + #[inline(always)] + pub const fn set_trim_unlock(&mut self, val: TrimUnlock) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "IFR_DISABLE."] + #[must_use] + #[inline(always)] + pub const fn ifr_disable(&self) -> IfrDisable { + let val = (self.0 >> 1usize) & 0x01; + IfrDisable::from_bits(val as u8) + } + #[doc = "IFR_DISABLE."] + #[inline(always)] + pub const fn set_ifr_disable(&mut self, val: IfrDisable) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + #[doc = "TRIM_LOCK_KEY."] + #[must_use] + #[inline(always)] + pub const fn trim_lock_key(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "TRIM_LOCK_KEY."] + #[inline(always)] + pub const fn set_trim_lock_key(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } +} +impl Default for TrimLock { + #[inline(always)] + fn default() -> TrimLock { + TrimLock(0) + } +} +impl core::fmt::Debug for TrimLock { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TrimLock") + .field("trim_unlock", &self.trim_unlock()) + .field("ifr_disable", &self.ifr_disable()) + .field("trim_lock_key", &self.trim_lock_key()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for TrimLock { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "TrimLock {{ trim_unlock: {:?}, ifr_disable: {:?}, trim_lock_key: {=u16:?} }}", + self.trim_unlock(), + self.ifr_disable(), + self.trim_lock_key() + ) + } +} +#[doc = "UPLL Control Status Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Upllcsr(pub u32); +impl Upllcsr { + #[doc = "UPLL Clock Monitor."] + #[must_use] + #[inline(always)] + pub const fn upllcm(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "UPLL Clock Monitor."] + #[inline(always)] + pub const fn set_upllcm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "UPLL Clock Monitor Reset Enable."] + #[must_use] + #[inline(always)] + pub const fn upllcmre(&self) -> Upllcmre { + let val = (self.0 >> 17usize) & 0x01; + Upllcmre::from_bits(val as u8) + } + #[doc = "UPLL Clock Monitor Reset Enable."] + #[inline(always)] + pub const fn set_upllcmre(&mut self, val: Upllcmre) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.to_bits() as u32) & 0x01) << 17usize); + } + #[doc = "Lock Register."] + #[must_use] + #[inline(always)] + pub const fn lk(&self) -> UpllcsrLk { + let val = (self.0 >> 23usize) & 0x01; + UpllcsrLk::from_bits(val as u8) + } + #[doc = "Lock Register."] + #[inline(always)] + pub const fn set_lk(&mut self, val: UpllcsrLk) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val.to_bits() as u32) & 0x01) << 23usize); + } + #[doc = "UPLL Valid."] + #[must_use] + #[inline(always)] + pub const fn upllvld(&self) -> Upllvld { + let val = (self.0 >> 24usize) & 0x01; + Upllvld::from_bits(val as u8) + } + #[doc = "UPLL Valid."] + #[inline(always)] + pub const fn set_upllvld(&mut self, val: Upllvld) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val.to_bits() as u32) & 0x01) << 24usize); + } + #[doc = "UPLL Selected."] + #[must_use] + #[inline(always)] + pub const fn upllsel(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "UPLL Selected."] + #[inline(always)] + pub const fn set_upllsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "UPLL Clock Error."] + #[must_use] + #[inline(always)] + pub const fn upllerr(&self) -> Upllerr { + let val = (self.0 >> 26usize) & 0x01; + Upllerr::from_bits(val as u8) + } + #[doc = "UPLL Clock Error."] + #[inline(always)] + pub const fn set_upllerr(&mut self, val: Upllerr) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val.to_bits() as u32) & 0x01) << 26usize); + } +} +impl Default for Upllcsr { + #[inline(always)] + fn default() -> Upllcsr { + Upllcsr(0) + } +} +impl core::fmt::Debug for Upllcsr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Upllcsr") + .field("upllcm", &self.upllcm()) + .field("upllcmre", &self.upllcmre()) + .field("lk", &self.lk()) + .field("upllvld", &self.upllvld()) + .field("upllsel", &self.upllsel()) + .field("upllerr", &self.upllerr()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Upllcsr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Upllcsr {{ upllcm: {=bool:?}, upllcmre: {:?}, lk: {:?}, upllvld: {:?}, upllsel: {=bool:?}, upllerr: {:?} }}", + self.upllcm(), + self.upllcmre(), + self.lk(), + self.upllvld(), + self.upllsel(), + self.upllerr() + ) + } +} +#[doc = "Version ID Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Verid(pub u32); +impl Verid { + #[doc = "SCG Version Number."] + #[must_use] + #[inline(always)] + pub const fn version(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "SCG Version Number."] + #[inline(always)] + pub const fn set_version(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for Verid { + #[inline(always)] + fn default() -> Verid { + Verid(0) + } +} +impl core::fmt::Debug for Verid { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Verid") + .field("version", &self.version()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Verid { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Verid {{ version: {=u32:?} }}", self.version()) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ApllLock { + #[doc = "APLL is not powered on or not locked."] + DisabledOrNotValid = 0x0, + #[doc = "APLL is locked."] + EnabledAndValid = 0x01, +} +impl ApllLock { + #[inline(always)] + pub const fn from_bits(val: u8) -> ApllLock { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ApllLock { + #[inline(always)] + fn from(val: u8) -> ApllLock { + ApllLock::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ApllLock) -> u8 { + ApllLock::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Apllcmre { + #[doc = "Clock monitor generates an interrupt when an error is detected."] + GenerateInterrupt = 0x0, + #[doc = "Clock monitor generates a reset when an error is detected."] + GenerateReset = 0x01, +} +impl Apllcmre { + #[inline(always)] + pub const fn from_bits(val: u8) -> Apllcmre { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Apllcmre { + #[inline(always)] + fn from(val: u8) -> Apllcmre { + Apllcmre::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Apllcmre) -> u8 { + Apllcmre::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ApllcsrLk { + #[doc = "Control Status Register can be written."] + WriteEnabled = 0x0, + #[doc = "Control Status Register cannot be written."] + WriteDisabled = 0x01, +} +impl ApllcsrLk { + #[inline(always)] + pub const fn from_bits(val: u8) -> ApllcsrLk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ApllcsrLk { + #[inline(always)] + fn from(val: u8) -> ApllcsrLk { + ApllcsrLk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ApllcsrLk) -> u8 { + ApllcsrLk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ApllctrlSource { + #[doc = "SOSC."] + Sosc = 0x0, + #[doc = "FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock."] + Firc = 0x01, + _RESERVED_2 = 0x02, + #[doc = "No clock."] + Rsvd = 0x03, +} +impl ApllctrlSource { + #[inline(always)] + pub const fn from_bits(val: u8) -> ApllctrlSource { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for ApllctrlSource { + #[inline(always)] + fn from(val: u8) -> ApllctrlSource { + ApllctrlSource::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: ApllctrlSource) -> u8 { + ApllctrlSource::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Apllerr { + #[doc = "APLL Clock Monitor is disabled or has not detected an error."] + DisabledOrNoError = 0x0, + #[doc = "APLL Clock Monitor is enabled and detected an error."] + EnabledAndError = 0x01, +} +impl Apllerr { + #[inline(always)] + pub const fn from_bits(val: u8) -> Apllerr { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Apllerr { + #[inline(always)] + fn from(val: u8) -> Apllerr { + Apllerr::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Apllerr) -> u8 { + Apllerr::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Apllsscg1Mc { + #[doc = "MC\\[1:0\\] no compensation."] + NoComp = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + #[doc = "MC\\[1:0\\] maximum compensation."] + MaxComp = 0x03, +} +impl Apllsscg1Mc { + #[inline(always)] + pub const fn from_bits(val: u8) -> Apllsscg1Mc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Apllsscg1Mc { + #[inline(always)] + fn from(val: u8) -> Apllsscg1Mc { + Apllsscg1Mc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Apllsscg1Mc) -> u8 { + Apllsscg1Mc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Apllsten { + #[doc = "APLL is disabled in Deep Sleep mode."] + DisabledInStop = 0x0, + #[doc = "APLL is enabled in Deep Sleep mode."] + EnabledInStop = 0x01, +} +impl Apllsten { #[inline(always)] - pub const fn trim_unlock(&self) -> TrimUnlock { - let val = (self.0 >> 0usize) & 0x01; - TrimUnlock::from_bits(val as u8) + pub const fn from_bits(val: u8) -> Apllsten { + unsafe { core::mem::transmute(val & 0x01) } } - #[doc = "TRIM_UNLOCK."] #[inline(always)] - pub const fn set_trim_unlock(&mut self, val: TrimUnlock) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } - #[doc = "IFR_DISABLE."] - #[must_use] +} +impl From for Apllsten { #[inline(always)] - pub const fn ifr_disable(&self) -> IfrDisable { - let val = (self.0 >> 1usize) & 0x01; - IfrDisable::from_bits(val as u8) + fn from(val: u8) -> Apllsten { + Apllsten::from_bits(val) } - #[doc = "IFR_DISABLE."] +} +impl From for u8 { #[inline(always)] - pub const fn set_ifr_disable(&mut self, val: IfrDisable) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + fn from(val: Apllsten) -> u8 { + Apllsten::to_bits(val) } - #[doc = "TRIM_LOCK_KEY."] - #[must_use] +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AplltestctrlTestvSel { + #[doc = "pll_bias_source."] + PllBias = 0x0, + #[doc = "pll_cco_current."] + PllCco = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "ldo_ldo1p1."] + Ldo = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl AplltestctrlTestvSel { #[inline(always)] - pub const fn trim_lock_key(&self) -> u16 { - let val = (self.0 >> 16usize) & 0xffff; - val as u16 + pub const fn from_bits(val: u8) -> AplltestctrlTestvSel { + unsafe { core::mem::transmute(val & 0x07) } } - #[doc = "TRIM_LOCK_KEY."] #[inline(always)] - pub const fn set_trim_lock_key(&mut self, val: u16) { - self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } -impl Default for TrimLock { +impl From for AplltestctrlTestvSel { #[inline(always)] - fn default() -> TrimLock { - TrimLock(0) + fn from(val: u8) -> AplltestctrlTestvSel { + AplltestctrlTestvSel::from_bits(val) } } -impl core::fmt::Debug for TrimLock { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TrimLock") - .field("trim_unlock", &self.trim_unlock()) - .field("ifr_disable", &self.ifr_disable()) - .field("trim_lock_key", &self.trim_lock_key()) - .finish() +impl From for u8 { + #[inline(always)] + fn from(val: AplltestctrlTestvSel) -> u8 { + AplltestctrlTestvSel::to_bits(val) } } -#[cfg(feature = "defmt")] -impl defmt::Format for TrimLock { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "TrimLock {{ trim_unlock: {:?}, ifr_disable: {:?}, trim_lock_key: {=u16:?} }}", - self.trim_unlock(), - self.ifr_disable(), - self.trim_lock_key() - ) +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkValid { + #[doc = "clk_valid_lv is not set."] + ClkValid0 = 0x0, + #[doc = "clk_valid_lv is set."] + ClkValid1 = 0x01, +} +impl ClkValid { + #[inline(always)] + pub const fn from_bits(val: u8) -> ClkValid { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } -#[doc = "Version ID Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Verid(pub u32); -impl Verid { - #[doc = "SCG Version Number."] - #[must_use] +impl From for ClkValid { #[inline(always)] - pub const fn version(&self) -> u32 { - let val = (self.0 >> 0usize) & 0xffff_ffff; - val as u32 + fn from(val: u8) -> ClkValid { + ClkValid::from_bits(val) } - #[doc = "SCG Version Number."] +} +impl From for u8 { #[inline(always)] - pub const fn set_version(&mut self, val: u32) { - self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + fn from(val: ClkValid) -> u8 { + ClkValid::to_bits(val) } } -impl Default for Verid { +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Div16en { + #[doc = "Divide-by-16 disabled, 12 MHz clock output."] + Div16Disabled = 0x0, + #[doc = "Divide-by-16 enabled, 750 kHz clock output."] + Div16Enabled = 0x01, +} +impl Div16en { #[inline(always)] - fn default() -> Verid { - Verid(0) + pub const fn from_bits(val: u8) -> Div16en { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } } } -impl core::fmt::Debug for Verid { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Verid") - .field("version", &self.version()) - .finish() +impl From for Div16en { + #[inline(always)] + fn from(val: u8) -> Div16en { + Div16en::from_bits(val) } } -#[cfg(feature = "defmt")] -impl defmt::Format for Verid { - fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Verid {{ version: {=u32:?} }}", self.version()) +impl From for u8 { + #[inline(always)] + fn from(val: Div16en) -> u8 { + Div16en::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Erefs { - #[doc = "External reference clock selected."] - EXTERNAL = 0x0, + #[doc = "External reference clock from PAD pin selected. LDO can be disabled in this case."] + External = 0x0, #[doc = "Internal crystal oscillator of OSC selected."] - INTERNAL = 0x01, + Internal = 0x01, } impl Erefs { #[inline(always)] @@ -2382,9 +4827,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fircacc { #[doc = "FIRC is not enabled or clock is not accurate."] - NOT_ENABLED_OR_NOT_VALID = 0x0, - #[doc = "FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock."] - ENABLED_AND_VALID = 0x01, + NotEnabledOrNotValid = 0x0, + #[doc = "FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog."] + EnabledAndValid = 0x01, } impl Fircacc { #[inline(always)] @@ -2413,9 +4858,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FircaccIe { #[doc = "FIRCACC interrupt is not enabled."] - FIRCACCNOT = 0x0, + Fircaccnot = 0x0, #[doc = "FIRCACC interrupt is enabled."] - FIRCACCYES = 0x01, + Fircaccyes = 0x01, } impl FircaccIe { #[inline(always)] @@ -2444,9 +4889,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FirccsrLk { #[doc = "Control Status Register can be written."] - WRITE_ENABLED = 0x0, + WriteEnabled = 0x0, #[doc = "Control Status Register cannot be written."] - WRITE_DISABLED = 0x01, + WriteDisabled = 0x01, } impl FirccsrLk { #[inline(always)] @@ -2473,11 +4918,42 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FirccsrTrimLock { + #[doc = "FIRC auto trim not locked to target frequency range."] + FircNotLocked = 0x0, + #[doc = "FIRC auto trim locked to target frequency range."] + FircLocked = 0x01, +} +impl FirccsrTrimLock { + #[inline(always)] + pub const fn from_bits(val: u8) -> FirccsrTrimLock { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FirccsrTrimLock { + #[inline(always)] + fn from(val: u8) -> FirccsrTrimLock { + FirccsrTrimLock::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FirccsrTrimLock) -> u8 { + FirccsrTrimLock::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fircerr { #[doc = "Error not detected with the FIRC trimming."] - ERROR_NOT_DETECTED = 0x0, + ErrorNotDetected = 0x0, #[doc = "Error detected with the FIRC trimming."] - ERROR_DETECTED = 0x01, + ErrorDetected = 0x01, } impl Fircerr { #[inline(always)] @@ -2506,9 +4982,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FircerrIe { #[doc = "FIRCERR interrupt is not enabled."] - ERROR_NOT_DETECTED = 0x0, + ErrorNotDetected = 0x0, #[doc = "FIRCERR interrupt is enabled."] - ERROR_DETECTED = 0x01, + ErrorDetected = 0x01, } impl FircerrIe { #[inline(always)] @@ -2537,9 +5013,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fircsten { #[doc = "FIRC is disabled in Deep Sleep mode."] - DISABLED_IN_STOP_MODES = 0x0, + DisabledInStopModes = 0x0, #[doc = "FIRC is enabled in Deep Sleep mode."] - ENABLED_IN_STOP_MODES = 0x01, + EnabledInStopModes = 0x01, } impl Fircsten { #[inline(always)] @@ -2566,11 +5042,45 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FirctcfgTrimsrc { + #[doc = "USB0 Start of Frame (1 kHz). This option does not use TRIMDIV because the clock came externally from USB."] + Usb0 = 0x0, + _RESERVED_1 = 0x01, + #[doc = "SOSC."] + Sosc = 0x02, + #[doc = "ROSC."] + Rosc = 0x03, +} +impl FirctcfgTrimsrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> FirctcfgTrimsrc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FirctcfgTrimsrc { + #[inline(always)] + fn from(val: u8) -> FirctcfgTrimsrc { + FirctcfgTrimsrc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FirctcfgTrimsrc) -> u8 { + FirctcfgTrimsrc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Fircvld { #[doc = "FIRC is not enabled or clock is not valid."] - NOT_ENABLED_OR_NOT_VALID = 0x0, + NotEnabledOrNotValid = 0x0, #[doc = "FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog."] - ENABLED_AND_VALID = 0x01, + EnabledAndValid = 0x01, } impl Fircvld { #[inline(always)] @@ -2597,24 +5107,59 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FlipBufIn { + #[doc = "Flip Buffer Inputs disabled."] + FlipBufInDisabled = 0x0, + #[doc = "Flip Buffer Inputs enabled."] + FlipBufInEnabled = 0x01, +} +impl FlipBufIn { + #[inline(always)] + pub const fn from_bits(val: u8) -> FlipBufIn { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for FlipBufIn { + #[inline(always)] + fn from(val: u8) -> FlipBufIn { + FlipBufIn::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: FlipBufIn) -> u8 { + FlipBufIn::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FreqSel { _RESERVED_0 = 0x0, - #[doc = "45 MHz FIRC clock selected, divided from 180 MHz."] - FIRC_48MHZ_192S = 0x01, + Firc45_48mhz = 0x01, _RESERVED_2 = 0x02, - #[doc = "60 MHz FIRC clock selected."] - FIRC_64MHZ = 0x03, + Firc60_64mhz = 0x03, _RESERVED_4 = 0x04, - #[doc = "90 MHz FIRC clock selected."] - FIRC_96MHZ = 0x05, + Firc90_96mhz = 0x05, _RESERVED_6 = 0x06, - #[doc = "180 MHz FIRC clock selected."] - FIRC_192MHZ = 0x07, + Firc180_192mhz = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, } impl FreqSel { #[inline(always)] pub const fn from_bits(val: u8) -> FreqSel { - unsafe { core::mem::transmute(val & 0x07) } + unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { @@ -2638,9 +5183,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IfrDisable { #[doc = "IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset."] - ENABLED = 0x0, + Enabled = 0x0, #[doc = "IFR write access to SCG trim registers during system reset is blocked."] - DISABLED = 0x01, + Disabled = 0x01, } impl IfrDisable { #[inline(always)] @@ -2667,15 +5212,46 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Overstress { + #[doc = "Over stress test is disabled."] + OverstressDis = 0x0, + #[doc = "Over stress test is enabled."] + OverstressEn = 0x01, +} +impl Overstress { + #[inline(always)] + pub const fn from_bits(val: u8) -> Overstress { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Overstress { + #[inline(always)] + fn from(val: u8) -> Overstress { + Overstress::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Overstress) -> u8 { + Overstress::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Range { - #[doc = "Frequency range select of 8-16 MHz."] - FREQ_16TO20MHZ = 0x0, - #[doc = "Frequency range select of 16-25 MHz."] - LOW_FREQ = 0x01, - #[doc = "Frequency range select of 25-40 MHz."] - MEDIUM_FREQ = 0x02, - #[doc = "Frequency range select of 40-50 MHz."] - HIGH_FREQ = 0x03, + #[doc = "Frequency range select of 16-20 MHz."] + Freq16to20mhz = 0x0, + #[doc = "Frequency range select of 20-30 MHz."] + LowFreq = 0x01, + #[doc = "Frequency range select of 30-50 MHz."] + MediumFreq = 0x02, + #[doc = "Frequency range select of 50-66 MHz."] + HighFreq = 0x03, } impl Range { #[inline(always)] @@ -2702,11 +5278,42 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Rosccmre { + #[doc = "Clock monitor generates an interrupt when an error is detected."] + GenerateInterrupt = 0x0, + #[doc = "Clock monitor generates a reset when an error is detected."] + GenerateReset = 0x01, +} +impl Rosccmre { + #[inline(always)] + pub const fn from_bits(val: u8) -> Rosccmre { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Rosccmre { + #[inline(always)] + fn from(val: u8) -> Rosccmre { + Rosccmre::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Rosccmre) -> u8 { + Rosccmre::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RosccsrLk { #[doc = "Control Status Register can be written."] - WRITE_ENABLED = 0x0, + WriteEnabled = 0x0, #[doc = "Control Status Register cannot be written."] - WRITE_DISABLED = 0x01, + WriteDisabled = 0x01, } impl RosccsrLk { #[inline(always)] @@ -2734,10 +5341,10 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Roscerr { - #[doc = "ROSC Clock has not detected an error."] - DISABLED_OR_NO_ERROR = 0x0, - #[doc = "ROSC Clock has detected an error."] - ENABLED_AND_ERROR = 0x01, + #[doc = "ROSC Clock Monitor is disabled or has not detected an error."] + DisabledOrNoError = 0x0, + #[doc = "ROSC Clock Monitor is enabled and detected an RTC loss of clock error."] + EnabledAndError = 0x01, } impl Roscerr { #[inline(always)] @@ -2766,9 +5373,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Roscvld { #[doc = "ROSC is not enabled or clock is not valid."] - DISABLED_OR_NOT_VALID = 0x0, + DisabledOrNotValid = 0x0, #[doc = "ROSC is enabled and output clock is valid."] - ENABLED_AND_VALID = 0x01, + EnabledAndValid = 0x01, } impl Roscvld { #[inline(always)] @@ -2798,22 +5405,32 @@ impl From for u8 { pub enum Scs { _RESERVED_0 = 0x0, #[doc = "SOSC."] - SOSC = 0x01, + Sosc = 0x01, #[doc = "SIRC."] - SIRC = 0x02, + Sirc = 0x02, #[doc = "FIRC."] - FIRC = 0x03, + Firc = 0x03, #[doc = "ROSC."] - ROSC = 0x04, - _RESERVED_5 = 0x05, + Rosc = 0x04, + #[doc = "APLL."] + Apll = 0x05, #[doc = "SPLL."] - SPLL = 0x06, - _RESERVED_7 = 0x07, + Spll = 0x06, + #[doc = "UPLL."] + Upll = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + _RESERVED_a = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, } impl Scs { #[inline(always)] pub const fn from_bits(val: u8) -> Scs { - unsafe { core::mem::transmute(val & 0x07) } + unsafe { core::mem::transmute(val & 0x0f) } } #[inline(always)] pub const fn to_bits(self) -> u8 { @@ -2835,11 +5452,46 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum SelAtx { + #[doc = "ldo1p1v_atxout_ana_atx3v_a: floating; ldo1p1v_atxout_ana_atx3v_b: floating."] + Floating = 0x0, + #[doc = "ldo1p1v_atxout_ana_atx3v_a: ref_1v; ldo1p1v_atxout_ana_atx3v_b: vbiasn."] + Vbiasn = 0x01, + #[doc = "ldo1p1v_atxout_ana_atx3v_a: vea; ldo1p1v_atxout_ana_atx3v_b: vgate."] + Vgate = 0x02, + #[doc = "ldo1p1v_atxout_ana_atx3v_a: ldo1p1v_vout_ok_lv; ldo1p1v_atxout_ana_atx3v_b: ldo1p1v_vout_1p1v_ana_1p8v."] + LdoP8v = 0x03, +} +impl SelAtx { + #[inline(always)] + pub const fn from_bits(val: u8) -> SelAtx { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for SelAtx { + #[inline(always)] + fn from(val: u8) -> SelAtx { + SelAtx::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: SelAtx) -> u8 { + SelAtx::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SirccsrLk { #[doc = "Control Status Register can be written."] - WRITE_ENABLED = 0x0, + WriteEnabled = 0x0, #[doc = "Control Status Register cannot be written."] - WRITE_DISABLED = 0x01, + WriteDisabled = 0x01, } impl SirccsrLk { #[inline(always)] @@ -2859,8 +5511,39 @@ impl From for SirccsrLk { } impl From for u8 { #[inline(always)] - fn from(val: SirccsrLk) -> u8 { - SirccsrLk::to_bits(val) + fn from(val: SirccsrLk) -> u8 { + SirccsrLk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum SirccsrTrimLock { + #[doc = "SIRC auto trim not locked to target frequency range."] + SircNotLocked = 0x0, + #[doc = "SIRC auto trim locked to target frequency range."] + SircLocked = 0x01, +} +impl SirccsrTrimLock { + #[inline(always)] + pub const fn from_bits(val: u8) -> SirccsrTrimLock { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for SirccsrTrimLock { + #[inline(always)] + fn from(val: u8) -> SirccsrTrimLock { + SirccsrTrimLock::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: SirccsrTrimLock) -> u8 { + SirccsrTrimLock::to_bits(val) } } #[repr(u8)] @@ -2868,9 +5551,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sircerr { #[doc = "Error not detected with the SIRC trimming."] - ERROR_NOT_DETECTED = 0x0, + ErrorNotDetected = 0x0, #[doc = "Error detected with the SIRC trimming."] - ERROR_DETECTED = 0x01, + ErrorDetected = 0x01, } impl Sircerr { #[inline(always)] @@ -2899,9 +5582,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SircerrIe { #[doc = "SIRCERR interrupt is not enabled."] - ERROR_NOT_DETECTED = 0x0, + ErrorNotDetected = 0x0, #[doc = "SIRCERR interrupt is enabled."] - ERROR_DETECTED = 0x01, + ErrorDetected = 0x01, } impl SircerrIe { #[inline(always)] @@ -2928,11 +5611,44 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum SirctcfgTrimsrc { + _RESERVED_0 = 0x0, + _RESERVED_1 = 0x01, + #[doc = "SOSC."] + Sosc = 0x02, + #[doc = "ROSC (32.768 kHz)."] + Rosc = 0x03, +} +impl SirctcfgTrimsrc { + #[inline(always)] + pub const fn from_bits(val: u8) -> SirctcfgTrimsrc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for SirctcfgTrimsrc { + #[inline(always)] + fn from(val: u8) -> SirctcfgTrimsrc { + SirctcfgTrimsrc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: SirctcfgTrimsrc) -> u8 { + SirctcfgTrimsrc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sircvld { #[doc = "SIRC is not enabled or clock is not valid."] - DISABLED_OR_NOT_VALID = 0x0, + DisabledOrNotValid = 0x0, #[doc = "SIRC is enabled and output clock is valid."] - ENABLED_AND_VALID = 0x01, + EnabledAndValid = 0x01, } impl Sircvld { #[inline(always)] @@ -2961,9 +5677,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sosccmre { #[doc = "Clock monitor generates an interrupt when an error is detected."] - GENERATE_INTERRUPT = 0x0, + GenerateInterrupt = 0x0, #[doc = "Clock monitor generates a reset when an error is detected."] - GENERATE_RESET = 0x01, + GenerateReset = 0x01, } impl Sosccmre { #[inline(always)] @@ -2992,9 +5708,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SosccsrLk { #[doc = "This Control Status Register can be written."] - WRITE_ENABLED = 0x0, + WriteEnabled = 0x0, #[doc = "This Control Status Register cannot be written."] - WRITE_DISABLED = 0x01, + WriteDisabled = 0x01, } impl SosccsrLk { #[inline(always)] @@ -3023,9 +5739,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Soscerr { #[doc = "SOSC Clock Monitor is disabled or has not detected an error."] - DISABLED_OR_NO_ERROR = 0x0, + DisabledOrNoError = 0x0, #[doc = "SOSC Clock Monitor is enabled and detected an error."] - ENABLED_AND_ERROR = 0x01, + EnabledAndError = 0x01, } impl Soscerr { #[inline(always)] @@ -3053,14 +5769,14 @@ impl From for u8 { #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Source { - #[doc = "SOSC."] - SOSC = 0x0, + #[doc = "SOSC"] + Sosc = 0x0, #[doc = "FIRC 45 MHz clock. FIRC_SCLK_PERIPH_EN needs to be set to use FIRC 45 MHz clock."] - FIRC = 0x01, - #[doc = "ROSC."] - ROSC = 0x02, - #[doc = "SIRC 12 MHz clock."] - SIRC = 0x03, + Firc = 0x01, + #[doc = "ROSC"] + Rosc = 0x02, + #[doc = "SIRC 12 MHz clock"] + Sirc = 0x03, } impl Source { #[inline(always)] @@ -3089,9 +5805,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SpllLock { #[doc = "SPLL is not powered on or not locked."] - DISABLED_OR_NOT_VALID = 0x0, + DisabledOrNotValid = 0x0, #[doc = "SPLL is locked."] - ENABLED_AND_VALID = 0x01, + EnabledAndValid = 0x01, } impl SpllLock { #[inline(always)] @@ -3120,9 +5836,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Spllcmre { #[doc = "Clock monitor generates an interrupt when an error is detected."] - GENERATE_INTERRUPT = 0x0, + GenerateInterrupt = 0x0, #[doc = "Clock monitor generates a reset when an error is detected."] - GENERATE_RESET = 0x01, + GenerateReset = 0x01, } impl Spllcmre { #[inline(always)] @@ -3151,9 +5867,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SpllcsrLk { #[doc = "Control Status Register can be written."] - WRITE_ENABLED = 0x0, + WriteEnabled = 0x0, #[doc = "Control Status Register cannot be written."] - WRITE_DISABLED = 0x01, + WriteDisabled = 0x01, } impl SpllcsrLk { #[inline(always)] @@ -3182,9 +5898,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Spllerr { #[doc = "SPLL Clock Monitor is disabled or has not detected an error."] - DISABLED_OR_NO_ERROR = 0x0, + DisabledOrNoError = 0x0, #[doc = "SPLL Clock Monitor is enabled and detected an error."] - ENABLED_AND_ERROR = 0x01, + EnabledAndError = 0x01, } impl Spllerr { #[inline(always)] @@ -3211,11 +5927,44 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Spllsscg1Mc { + #[doc = "MC\\[1:0\\] no compensation."] + NoComp = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + #[doc = "MC\\[1:0\\] maximum compensation."] + MaxComp = 0x03, +} +impl Spllsscg1Mc { + #[inline(always)] + pub const fn from_bits(val: u8) -> Spllsscg1Mc { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Spllsscg1Mc { + #[inline(always)] + fn from(val: u8) -> Spllsscg1Mc { + Spllsscg1Mc::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Spllsscg1Mc) -> u8 { + Spllsscg1Mc::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Spllsten { #[doc = "SPLL is disabled in Deep Sleep mode."] - DISABLED_IN_STOP = 0x0, + DisabledInStop = 0x0, #[doc = "SPLL is enabled in Deep Sleep mode."] - ENABLED_IN_STOP = 0x01, + EnabledInStop = 0x01, } impl Spllsten { #[inline(always)] @@ -3242,15 +5991,212 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum TrimLockVal { - #[doc = "SIRC auto trim not locked to target frequency range."] - SIRC_NOT_LOCKED = 0x0, - #[doc = "SIRC auto trim locked to target frequency range."] - SIRC_LOCKED = 0x01, +pub enum SplltestctrlTestvSel { + #[doc = "pll_bias_source."] + PllBias = 0x0, + #[doc = "pll_cco_current."] + PllCco = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + #[doc = "ldo_ldo1p1."] + Ldo = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, +} +impl SplltestctrlTestvSel { + #[inline(always)] + pub const fn from_bits(val: u8) -> SplltestctrlTestvSel { + unsafe { core::mem::transmute(val & 0x07) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for SplltestctrlTestvSel { + #[inline(always)] + fn from(val: u8) -> SplltestctrlTestvSel { + SplltestctrlTestvSel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: SplltestctrlTestvSel) -> u8 { + SplltestctrlTestvSel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum StartValid { + #[doc = "start_valid_lv is not set."] + StartValid0 = 0x0, + #[doc = "start_valid_lv is set."] + StartValid1 = 0x01, +} +impl StartValid { + #[inline(always)] + pub const fn from_bits(val: u8) -> StartValid { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for StartValid { + #[inline(always)] + fn from(val: u8) -> StartValid { + StartValid::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: StartValid) -> u8 { + StartValid::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TestBufBypass { + #[doc = "Not bypass buffer."] + TestBufBypassDisabled = 0x0, + #[doc = "Bypass buffer."] + TestBufBypassEnabled = 0x01, +} +impl TestBufBypass { + #[inline(always)] + pub const fn from_bits(val: u8) -> TestBufBypass { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TestBufBypass { + #[inline(always)] + fn from(val: u8) -> TestBufBypass { + TestBufBypass::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TestBufBypass) -> u8 { + TestBufBypass::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TestBufEn { + #[doc = "Test buffer is disabled."] + TestBufEnDis = 0x0, + #[doc = "Test buffer is enabled."] + TestBufEnEn = 0x01, +} +impl TestBufEn { + #[inline(always)] + pub const fn from_bits(val: u8) -> TestBufEn { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TestBufEn { + #[inline(always)] + fn from(val: u8) -> TestBufEn { + TestBufEn::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TestBufEn) -> u8 { + TestBufEn::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TestBufFlip { + #[doc = "Input of the buffer is not flipped."] + TestBufFlipDis = 0x0, + #[doc = "Input of the buffer is flipped."] + TestBufFlipEn = 0x01, +} +impl TestBufFlip { + #[inline(always)] + pub const fn from_bits(val: u8) -> TestBufFlip { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TestBufFlip { + #[inline(always)] + fn from(val: u8) -> TestBufFlip { + TestBufFlip::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TestBufFlip) -> u8 { + TestBufFlip::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TestSel { + #[doc = "VREF."] + TestSel00 = 0x0, + #[doc = "VFB."] + TestSel01 = 0x01, + #[doc = "BP."] + TestSel10 = 0x02, + #[doc = "VCCO."] + TestSel11 = 0x03, +} +impl TestSel { + #[inline(always)] + pub const fn from_bits(val: u8) -> TestSel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for TestSel { + #[inline(always)] + fn from(val: u8) -> TestSel { + TestSel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: TestSel) -> u8 { + TestSel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Testen { + #[doc = "FIRC test is disabled."] + FircTestDis = 0x0, + #[doc = "FIRC test is enabled."] + FircTestEn = 0x01, } -impl TrimLockVal { +impl Testen { #[inline(always)] - pub const fn from_bits(val: u8) -> TrimLockVal { + pub const fn from_bits(val: u8) -> Testen { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -3258,26 +6204,60 @@ impl TrimLockVal { unsafe { core::mem::transmute(self) } } } -impl From for TrimLockVal { +impl From for Testen { + #[inline(always)] + fn from(val: u8) -> Testen { + Testen::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Testen) -> u8 { + Testen::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Testsel { + _RESERVED_0 = 0x0, + #[doc = "VREGOUT test."] + Regout = 0x01, + #[doc = "VSW test."] + Vsw = 0x02, + #[doc = "VREF test."] + Vref = 0x03, +} +impl Testsel { + #[inline(always)] + pub const fn from_bits(val: u8) -> Testsel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Testsel { #[inline(always)] - fn from(val: u8) -> TrimLockVal { - TrimLockVal::from_bits(val) + fn from(val: u8) -> Testsel { + Testsel::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: TrimLockVal) -> u8 { - TrimLockVal::to_bits(val) + fn from(val: Testsel) -> u8 { + Testsel::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TrimUnlock { - #[doc = "SCG Trim Registers locked and not writable."] - LOCKED = 0x0, - #[doc = "SCG Trim registers unlocked and writable."] - NOT_LOCKED = 0x01, + #[doc = "SCG Trim /Test registers are locked and not writable."] + Locked = 0x0, + #[doc = "SCG Trim /Test registers are unlocked and writable."] + NotLocked = 0x01, } impl TrimUnlock { #[inline(always)] @@ -3304,33 +6284,160 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Trimsrc { - _RESERVED_0 = 0x0, - _RESERVED_1 = 0x01, - #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."] - SOSC = 0x02, - _RESERVED_3 = 0x03, +pub enum Tstmd { + #[doc = "ipt_test_ana_atx3v_a=High-Z; ipt_test_ana_atx3v_b=High-Z."] + Tstmd00 = 0x0, + #[doc = "ipt_test_ana_atx3v_a=osc_in(EXTAL); ipt_test_ana_atx3v_b=High-Z."] + Tstmd01 = 0x01, + #[doc = "ipt_test_ana_atx3v_a=High-Z; ipt_test_ana_atx3v_b=osc_out(XTAL)."] + Tstmd10 = 0x02, + #[doc = "ipt_test_ana_atx3v_a=osc_in(EXTAL); ipt_test_ana_atx3v_b=osc_out(XTAL)."] + Tstmd11 = 0x03, +} +impl Tstmd { + #[inline(always)] + pub const fn from_bits(val: u8) -> Tstmd { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } } -impl Trimsrc { +impl From for Tstmd { #[inline(always)] - pub const fn from_bits(val: u8) -> Trimsrc { - unsafe { core::mem::transmute(val & 0x03) } + fn from(val: u8) -> Tstmd { + Tstmd::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Tstmd) -> u8 { + Tstmd::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Upllcmre { + #[doc = "Clock monitor generates an interrupt when an error is detected."] + GenerateInterrupt = 0x0, + #[doc = "Clock monitor generates a reset when an error is detected."] + GenerateReset = 0x01, +} +impl Upllcmre { + #[inline(always)] + pub const fn from_bits(val: u8) -> Upllcmre { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Upllcmre { + #[inline(always)] + fn from(val: u8) -> Upllcmre { + Upllcmre::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Upllcmre) -> u8 { + Upllcmre::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum UpllcsrLk { + #[doc = "Control Status Register can be written."] + WriteEnabled = 0x0, + #[doc = "Control Status Register cannot be written."] + WriteDisabled = 0x01, +} +impl UpllcsrLk { + #[inline(always)] + pub const fn from_bits(val: u8) -> UpllcsrLk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for UpllcsrLk { + #[inline(always)] + fn from(val: u8) -> UpllcsrLk { + UpllcsrLk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: UpllcsrLk) -> u8 { + UpllcsrLk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Upllerr { + #[doc = "UPLL Clock Monitor is disabled or has not detected an error."] + DisabledOrNoError = 0x0, + #[doc = "UPLL Clock Monitor is enabled and detected an error."] + EnabledAndError = 0x01, +} +impl Upllerr { + #[inline(always)] + pub const fn from_bits(val: u8) -> Upllerr { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for Upllerr { + #[inline(always)] + fn from(val: u8) -> Upllerr { + Upllerr::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Upllerr) -> u8 { + Upllerr::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Upllvld { + #[doc = "UPLL is not enabled or clock is not valid."] + DisabledOrNotValid = 0x0, + #[doc = "UPLL is enabled and output clock is valid."] + EnabledAndValid = 0x01, +} +impl Upllvld { + #[inline(always)] + pub const fn from_bits(val: u8) -> Upllvld { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for Trimsrc { +impl From for Upllvld { #[inline(always)] - fn from(val: u8) -> Trimsrc { - Trimsrc::from_bits(val) + fn from(val: u8) -> Upllvld { + Upllvld::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Trimsrc) -> u8 { - Trimsrc::to_bits(val) + fn from(val: Upllvld) -> u8 { + Upllvld::to_bits(val) } } #[repr(u8)] @@ -3338,21 +6445,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum VoutSel { #[doc = "VOUT = 1V."] - VOUT_1V_1 = 0x0, + Vout1v1 = 0x0, #[doc = "VOUT = 1V."] - VOUT_1V_2 = 0x01, + Vout1v2 = 0x01, #[doc = "VOUT = 1V."] - VOUT_1V_3 = 0x02, + Vout1v3 = 0x02, #[doc = "VOUT = 1.05V."] - VOUT_105V = 0x03, + Vout105v = 0x03, #[doc = "VOUT = 1.1V."] - VOUT_11V = 0x04, + Vout11v = 0x04, #[doc = "VOUT = 1.15V."] - VOUT_115V = 0x05, + Vout115v = 0x05, #[doc = "VOUT = 1.2V."] - VOUT_12V = 0x06, + Vout12v = 0x06, #[doc = "VOUT = 1.25V."] - VOUT_125V = 0x07, + Vout125v = 0x07, } impl VoutSel { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/SGI.rs b/nxp-pac/src/meta_peripherals/mcxa/SGI.rs index fa076db..cc54e17 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/SGI.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/SGI.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "no description available."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Sgi { @@ -4437,13 +4438,13 @@ impl defmt::Format for SgiVersion { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AesKeysize { #[doc = "128 0nly."] - AES_128_ONLY = 0x0, + Aes128Only = 0x0, #[doc = "192 only."] - AES_192_ONLY = 0x01, + Aes192Only = 0x01, #[doc = "256 only."] - AES_256_ONLY = 0x02, + Aes256Only = 0x02, #[doc = "All key sizes."] - ALL_KEYSIZE = 0x03, + AllKeysize = 0x03, } impl AesKeysize { #[inline(always)] @@ -4472,9 +4473,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AesNoKl { #[doc = "new AES key will be loaded."] - NEW = 0x0, + New = 0x0, #[doc = "No AES key will be loaded, and previously loaded key will be used."] - NO = 0x01, + No = 0x01, } impl AesNoKl { #[inline(always)] @@ -4503,9 +4504,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AesSel { #[doc = "First AES selected."] - FIRST_AES = 0x0, + FirstAes = 0x0, #[doc = "Second AES selected (when enabled)."] - SECOND_AES = 0x01, + SecondAes = 0x01, } impl AesSel { #[inline(always)] @@ -4534,37 +4535,37 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AesUsed { #[doc = "Apollo."] - APOLLO = 0x0, + Apollo = 0x0, #[doc = "Aegis."] - AEGIS = 0x01, + Aegis = 0x01, #[doc = "Ayna."] - AYNA = 0x02, + Ayna = 0x02, #[doc = "Athenium."] - ATHENIUM = 0x03, + Athenium = 0x03, #[doc = "Ajax."] - AJAX = 0x04, + Ajax = 0x04, #[doc = "Aegis_hs."] - AEGIS_HS = 0x05, + AegisHs = 0x05, #[doc = "Athenium_hs."] - ATHENIUM_HS = 0x06, + AtheniumHs = 0x06, #[doc = "ATE."] - ATE = 0x07, + Ate = 0x07, #[doc = "ATOM."] - ATOM = 0x08, + Atom = 0x08, #[doc = "Asterix."] - ASTERIX = 0x09, + Asterix = 0x09, #[doc = "RFU."] - RFU_10 = 0x0a, + Rfu10 = 0x0a, #[doc = "RFU."] - RFU_11 = 0x0b, + Rfu11 = 0x0b, #[doc = "RFU."] - RFU_12 = 0x0c, + Rfu12 = 0x0c, #[doc = "RFU."] - RFU_13 = 0x0d, + Rfu13 = 0x0d, #[doc = "RFU."] - RFU_14 = 0x0e, + Rfu14 = 0x0e, #[doc = "RFU."] - RFU_15 = 0x0f, + Rfu15 = 0x0f, } impl AesUsed { #[inline(always)] @@ -4593,13 +4594,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Aeskeysz { #[doc = "AES-128."] - AES_128 = 0x0, + Aes128 = 0x0, #[doc = "AES-192."] - AES_192 = 0x01, + Aes192 = 0x01, #[doc = "AES-256."] - AES_256 = 0x02, + Aes256 = 0x02, #[doc = "RFU (defaults to AES-128)."] - RFU = 0x03, + Rfu = 0x03, } impl Aeskeysz { #[inline(always)] @@ -4628,9 +4629,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BytesOrder { #[doc = "Normal."] - NORMAL_ORDER = 0x0, + NormalOrder = 0x0, #[doc = "Swapped."] - SWAPPED_ORDER = 0x01, + SwappedOrder = 0x01, } impl BytesOrder { #[inline(always)] @@ -4659,17 +4660,17 @@ impl From for u8 { pub struct Cmd(u8); impl Cmd { #[doc = "ECB mode."] - pub const ECB: Self = Self(0x0); + pub const Ecb: Self = Self(0x0); #[doc = "CTR mode."] - pub const CTR: Self = Self(0x01); + pub const Ctr: Self = Self(0x01); #[doc = "CBC mode."] - pub const CBC: Self = Self(0x02); + pub const Cbc: Self = Self(0x02); #[doc = "CBCMAC mode."] - pub const CBCMAC: Self = Self(0x03); + pub const Cbcmac: Self = Self(0x03); #[doc = "Key Wrap/Unwrap (128 bit key data)."] - pub const WRAP_128_BIT: Self = Self(0x10); + pub const Wrap128Bit: Self = Self(0x10); #[doc = "Key Wrap/Unwrap (256 bit key data)."] - pub const WRAP_256_BIT: Self = Self(0x11); + pub const Wrap256Bit: Self = Self(0x11); } impl Cmd { pub const fn from_bits(val: u8) -> Cmd { @@ -4682,12 +4683,12 @@ impl Cmd { impl core::fmt::Debug for Cmd { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("ECB"), - 0x01 => f.write_str("CTR"), - 0x02 => f.write_str("CBC"), - 0x03 => f.write_str("CBCMAC"), - 0x10 => f.write_str("WRAP_128_BIT"), - 0x11 => f.write_str("WRAP_256_BIT"), + 0x0 => f.write_str("Ecb"), + 0x01 => f.write_str("Ctr"), + 0x02 => f.write_str("Cbc"), + 0x03 => f.write_str("Cbcmac"), + 0x10 => f.write_str("Wrap128Bit"), + 0x11 => f.write_str("Wrap256Bit"), other => core::write!(f, "0x{:02X}", other), } } @@ -4696,12 +4697,12 @@ impl core::fmt::Debug for Cmd { impl defmt::Format for Cmd { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "ECB"), - 0x01 => defmt::write!(f, "CTR"), - 0x02 => defmt::write!(f, "CBC"), - 0x03 => defmt::write!(f, "CBCMAC"), - 0x10 => defmt::write!(f, "WRAP_128_BIT"), - 0x11 => defmt::write!(f, "WRAP_256_BIT"), + 0x0 => defmt::write!(f, "Ecb"), + 0x01 => defmt::write!(f, "Ctr"), + 0x02 => defmt::write!(f, "Cbc"), + 0x03 => defmt::write!(f, "Cbcmac"), + 0x10 => defmt::write!(f, "Wrap128Bit"), + 0x11 => defmt::write!(f, "Wrap256Bit"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -4723,21 +4724,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CryptoOp { #[doc = "AES."] - AES = 0x0, + Aes = 0x0, #[doc = "DES (If Included)."] - DES = 0x01, + Des = 0x01, #[doc = "TDES (If Included)."] - TDES = 0x02, + Tdes = 0x02, #[doc = "GFMUL(If Included)."] - GFMUL = 0x03, + Gfmul = 0x03, #[doc = "SHA2 (If Included)."] - SHA = 0x04, + Sha = 0x04, #[doc = "CMAC (If Included)."] - CMAC = 0x05, + Cmac = 0x05, #[doc = "others - RFU (Defaults to 1st available OP)."] - OTHERS_6 = 0x06, + Others6 = 0x06, #[doc = "others - RFU (Defaults to 1st available OP)."] - OTHERS_7 = 0x07, + Others7 = 0x07, } impl CryptoOp { #[inline(always)] @@ -4766,9 +4767,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DatinFlush { #[doc = "Clr has no effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Set to start flush."] - FLUSH = 0x01, + Flush = 0x01, } impl DatinFlush { #[inline(always)] @@ -4797,13 +4798,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DatoutRes { #[doc = "END_UP."] - END_UP = 0x0, + EndUp = 0x0, #[doc = "START_UP."] - START_UP = 0x01, + StartUp = 0x01, #[doc = "TRIGGER_UP."] - TRIGGER_UP = 0x02, + TriggerUp = 0x02, #[doc = "NO_UP."] - NO_UP = 0x03, + NoUp = 0x03, } impl DatoutRes { #[inline(always)] @@ -4832,9 +4833,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Decrypt { #[doc = "Encryption."] - ENC = 0x0, + Enc = 0x0, #[doc = "Decryption."] - DEC = 0x01, + Dec = 0x01, } impl Decrypt { #[inline(always)] @@ -4863,25 +4864,25 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DesUsed { #[doc = "Dakar."] - DAKAR = 0x0, + Dakar = 0x0, #[doc = "Danube."] - DANUBE = 0x01, + Danube = 0x01, #[doc = "Depicta."] - DEPICTA = 0x02, + Depicta = 0x02, #[doc = "Digi."] - DIGI = 0x03, + Digi = 0x03, #[doc = "Date."] - DATE = 0x04, + Date = 0x04, #[doc = "Desert."] - DESERT = 0x05, + Desert = 0x05, #[doc = "RFU."] - RFU_6 = 0x06, + Rfu6 = 0x06, #[doc = "RFU."] - RFU_7 = 0x07, + Rfu7 = 0x07, #[doc = "RFU."] - RFU_8 = 0x08, + Rfu8 = 0x08, #[doc = "RFU."] - RFU_9 = 0x09, + Rfu9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, @@ -4916,13 +4917,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Error { #[doc = "ERROR (all values other than 0x05 indicate ERROR)."] - ERROR = 0x0, + Error = 0x0, _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, #[doc = "NO_ERROR."] - NO_ERROR = 0x05, + NoError = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, } @@ -4953,9 +4954,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Flush { #[doc = "Clr has no effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Set to start flush."] - FLUSH = 0x01, + Flush = 0x01, } impl Flush { #[inline(always)] @@ -4984,9 +4985,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IncrCin { #[doc = "Carry-In for INCR is 1."] - INCR_ONE = 0x0, + IncrOne = 0x0, #[doc = "Carry-In for INCR is overflow from previous INCR operation."] - INCR_PREVIOUS = 0x01, + IncrPrevious = 0x01, } impl IncrCin { #[inline(always)] @@ -5015,13 +5016,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IncrMode { #[doc = "2**32 increment mode."] - INCR_MODE_32 = 0x0, + IncrMode32 = 0x0, #[doc = "2**64 increment mode."] - INCR_MODE_64 = 0x01, + IncrMode64 = 0x01, #[doc = "2**96 increment mode."] - INCR_MODE_96 = 0x02, + IncrMode96 = 0x02, #[doc = "2**128 increment mode."] - INCR_MODE_128 = 0x03, + IncrMode128 = 0x03, } impl IncrMode { #[inline(always)] @@ -5050,25 +5051,25 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Insel { #[doc = "DATIN\\[0\\]."] - DATIN0 = 0x0, + Datin0 = 0x0, #[doc = "DATIN\\[1\\]*."] - DATIN1 = 0x01, + Datin1 = 0x01, #[doc = "DATIN\\[2\\]*."] - DATIN2 = 0x02, + Datin2 = 0x02, #[doc = "DATIN\\[3\\]*."] - DATIN3 = 0x03, + Datin3 = 0x03, #[doc = "DATIN\\[0\\] ^ DATOUT."] - DATIN0_DATOUT = 0x04, + Datin0Datout = 0x04, #[doc = "DATIN\\[1\\] ^ DATOUT*."] - DATIN1_DATOUT = 0x05, + Datin1Datout = 0x05, #[doc = "DATIN\\[2\\] ^ DATOUT*."] - DATIN2_DATOUT = 0x06, + Datin2Datout = 0x06, #[doc = "DATIN\\[3\\] ^ DATOUT*."] - DATIN3_DATOUT = 0x07, + Datin3Datout = 0x07, #[doc = "DATOUT."] - DATOUT = 0x08, + Datout = 0x08, #[doc = "others - DATIN\\[0\\] * - only if DATIN\\[num\\] exists, else \\[0\\]."] - OTHERS_9 = 0x09, + Others9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, @@ -5103,9 +5104,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum KeyFlush { #[doc = "Clr has no effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Set to start flush."] - FLUSH = 0x01, + Flush = 0x01, } impl KeyFlush { #[inline(always)] @@ -5134,13 +5135,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Milestone { #[doc = "PREL."] - PREL = 0x0, + Prel = 0x0, #[doc = "BR."] - BR = 0x01, + Br = 0x01, #[doc = "SI."] - SI = 0x02, + Si = 0x02, #[doc = "GO."] - GO = 0x03, + Go = 0x03, } impl Milestone { #[inline(always)] @@ -5169,9 +5170,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum NoAutoInit { #[doc = "SHA automatic HASH initialisation."] - SHA_INIT = 0x0, + ShaInit = 0x0, #[doc = "No SHA automatic HASH initialisation."] - NO_SHA_INIT = 0x01, + NoShaInit = 0x01, } impl NoAutoInit { #[inline(always)] @@ -5200,21 +5201,21 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Outsel { #[doc = "DATOUT = 'Kernel Res'."] - DATOUT_KER_RES = 0x0, + DatoutKerRes = 0x0, #[doc = "DATOUT = 'Kernel Res' ^ DATIN\\[0\\]."] - DATOUT_DATIN0 = 0x01, + DatoutDatin0 = 0x01, #[doc = "DATOUT = 'Kernel Res' ^ DATIN\\[1\\]*."] - DATOUT_DATIN1 = 0x02, + DatoutDatin1 = 0x02, #[doc = "DATOUT = 'Kernel Res' ^ DATIN\\[2\\]*."] - DATOUT_DATIN2 = 0x03, + DatoutDatin2 = 0x03, #[doc = "DATOUT = 'Kernel Res' ^DATIN\\[3\\]*."] - DATOUT_DATIN3 = 0x04, + DatoutDatin3 = 0x04, #[doc = "others - DATOUT = 'Kernel Res' * - only if DATIN\\[num\\] exists, else \\[0\\]."] - OTHERS_5 = 0x05, + Others5 = 0x05, #[doc = "others - DATOUT = 'Kernel Res' * - only if DATIN\\[num\\] exists, else \\[0\\]."] - OTHERS_6 = 0x06, + Others6 = 0x06, #[doc = "others - DATOUT = 'Kernel Res' * - only if DATIN\\[num\\] exists, else \\[0\\]."] - OTHERS_7 = 0x07, + Others7 = 0x07, } impl Outsel { #[inline(always)] @@ -5243,9 +5244,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Rkey { #[doc = "DATOUT register bank."] - DATOUT = 0x0, + Datout = 0x0, #[doc = "KEY register bank."] - KEY = 0x01, + Key = 0x01, } impl Rkey { #[inline(always)] @@ -5274,9 +5275,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sha2CountEn { #[doc = "SHA operation DOES NOT increment COUNT."] - COUNT = 0x0, + Count = 0x0, #[doc = "SHA operation DOES increment count."] - NO_COUNT = 0x01, + NoCount = 0x01, } impl Sha2CountEn { #[inline(always)] @@ -5305,9 +5306,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sha2Mode { #[doc = "SHA NORM Mode."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "SHA AUTO Mode."] - AUTO = 0x01, + Auto = 0x01, } impl Sha2Mode { #[inline(always)] @@ -5336,13 +5337,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sha2Size { #[doc = "SHA-224."] - SHA_224 = 0x0, + Sha224 = 0x0, #[doc = "SHA-256."] - SHA_256 = 0x01, + Sha256 = 0x01, #[doc = "SHA-384(or SHA-224 if SHA-256 only)."] - SHA_384 = 0x02, + Sha384 = 0x02, #[doc = "SHA-512 (or SHA-256 if SHA-256 only)."] - SHA_512 = 0x03, + Sha512 = 0x03, } impl Sha2Size { #[inline(always)] @@ -5371,9 +5372,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Sha2Stop { #[doc = "Keep running."] - RUNNING = 0x0, + Running = 0x0, #[doc = "Stop auto mode."] - STOP = 0x01, + Stop = 0x01, } impl Sha2Stop { #[inline(always)] @@ -5402,9 +5403,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Smaskstep { #[doc = "SFRSEED increments every regbank access."] - REGBANK = 0x0, + Regbank = 0x0, #[doc = "SFRSEED increments every regbank access PLUS when SFRSEED in read."] - REGBANK_AND_PLUS = 0x01, + RegbankAndPlus = 0x01, } impl Smaskstep { #[inline(always)] @@ -5433,9 +5434,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Smasksw { #[doc = "SFR MASK output directly controlled by HW mask generator."] - HW = 0x0, + Hw = 0x0, #[doc = "SFR MASK output directly controlled by SW."] - SW = 0x01, + Sw = 0x01, } impl Smasksw { #[inline(always)] @@ -5464,9 +5465,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Start { #[doc = "Clr has no effect."] - NO_EFFECT = 0x0, + NoEffect = 0x0, #[doc = "Set to start operation."] - START_OP = 0x01, + StartOp = 0x01, } impl Start { #[inline(always)] @@ -5495,9 +5496,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Tdeskey { #[doc = "2-key TDES."] - TWO_KEY = 0x0, + TwoKey = 0x0, #[doc = "3-key TDES."] - THREE_KEY = 0x01, + ThreeKey = 0x01, } impl Tdeskey { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/SPC.rs b/nxp-pac/src/meta_peripherals/mcxa/SPC.rs index 7dd2586..014f21e 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/SPC.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/SPC.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "SPC."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Spc { @@ -112,7 +113,7 @@ impl Spc { } #[doc = "LDO_CORE Configuration."] #[inline(always)] - pub const fn coreldo_cfg(self) -> crate::pac::common::Reg { + pub const fn coreldo_cfg(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0300usize) as _) } } } @@ -319,47 +320,6 @@ impl defmt::Format for ActiveVdelay { ) } } -#[doc = "LDO_CORE Configuration."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct CoreldoCfg(pub u32); -impl CoreldoCfg { - #[doc = "CORELDO SPARE0."] - #[must_use] - #[inline(always)] - pub const fn coreldo_spare0(&self) -> bool { - let val = (self.0 >> 16usize) & 0x01; - val != 0 - } - #[doc = "CORELDO SPARE0."] - #[inline(always)] - pub const fn set_coreldo_spare0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); - } -} -impl Default for CoreldoCfg { - #[inline(always)] - fn default() -> CoreldoCfg { - CoreldoCfg(0) - } -} -impl core::fmt::Debug for CoreldoCfg { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CoreldoCfg") - .field("coreldo_spare0", &self.coreldo_spare0()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for CoreldoCfg { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "CoreldoCfg {{ coreldo_spare0: {=bool:?} }}", - self.coreldo_spare0() - ) - } -} #[doc = "External Voltage Domain Configuration."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1341,11 +1301,11 @@ impl defmt::Format for Verid { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ActiveCfgBgmode { #[doc = "Bandgap disabled."] - BGMODE0 = 0x0, + Bgmode0 = 0x0, #[doc = "Bandgap enabled, buffer disabled."] - BGMODE01 = 0x01, + Bgmode01 = 0x01, #[doc = "Bandgap enabled, buffer enabled."] - BGMODE10 = 0x02, + Bgmode10 = 0x02, _RESERVED_3 = 0x03, } impl ActiveCfgBgmode { @@ -1375,9 +1335,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ActiveCfgCoreldoVddDs { #[doc = "Low."] - LOW = 0x0, + Low = 0x0, #[doc = "Normal."] - NORMAL = 0x01, + Normal = 0x01, } impl ActiveCfgCoreldoVddDs { #[inline(always)] @@ -1407,11 +1367,11 @@ impl From for u8 { pub enum ActiveCfgCoreldoVddLvl { _RESERVED_0 = 0x0, #[doc = "Regulate to mid voltage (1.0 V)."] - MID = 0x01, + Mid = 0x01, #[doc = "Regulate to normal voltage (1.1 V)."] - NORMAL = 0x02, + Normal = 0x02, #[doc = "Regulate to overdrive voltage (1.15 V)."] - OVER = 0x03, + Over = 0x03, } impl ActiveCfgCoreldoVddLvl { #[inline(always)] @@ -1440,9 +1400,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CorevddLvdf { #[doc = "Event not detected."] - EVENT_NO = 0x0, + EventNo = 0x0, #[doc = "Event detected."] - EVENT_YES = 0x01, + EventYes = 0x01, } impl CorevddLvdf { #[inline(always)] @@ -1471,7 +1431,7 @@ impl From for u8 { pub struct Feature(u16); impl Feature { #[doc = "Standard features."] - pub const STANDARD: Self = Self(0x0); + pub const Standard: Self = Self(0x0); } impl Feature { pub const fn from_bits(val: u16) -> Feature { @@ -1484,7 +1444,7 @@ impl Feature { impl core::fmt::Debug for Feature { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("STANDARD"), + 0x0 => f.write_str("Standard"), other => core::write!(f, "0x{:02X}", other), } } @@ -1493,7 +1453,7 @@ impl core::fmt::Debug for Feature { impl defmt::Format for Feature { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "STANDARD"), + 0x0 => defmt::write!(f, "Standard"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -1515,11 +1475,11 @@ impl From for u16 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpCfgBgmode { #[doc = "Bandgap disabled."] - BGMODE0 = 0x0, + Bgmode0 = 0x0, #[doc = "Bandgap enabled, buffer disabled."] - BGMODE01 = 0x01, + Bgmode01 = 0x01, #[doc = "Bandgap enabled, buffer enabled."] - BGMODE10 = 0x02, + Bgmode10 = 0x02, _RESERVED_3 = 0x03, } impl LpCfgBgmode { @@ -1549,9 +1509,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpCfgCoreldoVddDs { #[doc = "Low."] - LOW = 0x0, + Low = 0x0, #[doc = "Normal."] - NORMAL = 0x01, + Normal = 0x01, } impl LpCfgCoreldoVddDs { #[inline(always)] @@ -1581,11 +1541,11 @@ impl From for u8 { pub enum LpCfgCoreldoVddLvl { _RESERVED_0 = 0x0, #[doc = "Mid voltage (1.0 V)."] - MID = 0x01, + Mid = 0x01, #[doc = "Normal voltage (1.1 V)."] - NORMAL = 0x02, + Normal = 0x02, #[doc = "Overdrive voltage (1.15 V)."] - OVER = 0x03, + Over = 0x03, } impl LpCfgCoreldoVddLvl { #[inline(always)] @@ -1614,18 +1574,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LpMode { #[doc = "SLEEP with system clock running."] - MODE0 = 0x0, + Mode0 = 0x0, #[doc = "DSLEEP with system clock off."] - MODE1 = 0x01, + Mode1 = 0x01, #[doc = "PDOWN with system clock off."] - MODE2 = 0x02, + Mode2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, #[doc = "DPDOWN with system clock off."] - MODE8 = 0x08, + Mode8 = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, @@ -1661,12 +1621,12 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lpreqov { #[doc = "Not forced."] - FORCE_NO = 0x0, + ForceNo = 0x0, _RESERVED_1 = 0x01, #[doc = "Forced low (ignore LPREQPOL settings)."] - FORCE_LOW = 0x02, + ForceLow = 0x02, #[doc = "Forced high (ignore LPREQPOL settings)."] - FORCE_HIGH = 0x03, + ForceHigh = 0x03, } impl Lpreqov { #[inline(always)] @@ -1695,9 +1655,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Lpreqpol { #[doc = "High."] - HIGH = 0x0, + High = 0x0, #[doc = "Low."] - LOW = 0x01, + Low = 0x01, } impl Lpreqpol { #[inline(always)] @@ -1726,9 +1686,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PdLpReq { #[doc = "Did not request."] - REQ_NO = 0x0, + ReqNo = 0x0, #[doc = "Requested."] - REQ_YES = 0x01, + ReqYes = 0x01, } impl PdLpReq { #[inline(always)] @@ -1757,9 +1717,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PwrReqStatus { #[doc = "Did not request."] - REQ_NO = 0x0, + ReqNo = 0x0, #[doc = "Requested."] - REQ_YES = 0x01, + ReqYes = 0x01, } impl PwrReqStatus { #[inline(always)] @@ -1788,18 +1748,18 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SpcLpMode { #[doc = "Sleep mode with system clock running."] - MODE0 = 0x0, + Mode0 = 0x0, #[doc = "DSLEEP with system clock off."] - MODE1 = 0x01, + Mode1 = 0x01, #[doc = "PDOWN with system clock off."] - MODE2 = 0x02, + Mode2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, _RESERVED_5 = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, #[doc = "DPDOWN with system clock off."] - MODE8 = 0x08, + Mode8 = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, @@ -1835,9 +1795,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SpcLpReq { #[doc = "SPC is in Active mode; the ACTIVE_CFG register has control."] - ACTIVE = 0x0, + Active = 0x0, #[doc = "All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register."] - LOW_POWER = 0x01, + LowPower = 0x01, } impl SpcLpReq { #[inline(always)] @@ -1866,9 +1826,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SysvddHvdf { #[doc = "Event not detected."] - EVENT_NO = 0x0, + EventNo = 0x0, #[doc = "Event detected."] - EVENT_YES = 0x01, + EventYes = 0x01, } impl SysvddHvdf { #[inline(always)] @@ -1897,9 +1857,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SysvddLvdf { #[doc = "Event not detected."] - EVENT_NO = 0x0, + EventNo = 0x0, #[doc = "Event detected."] - EVENT_YES = 0x01, + EventYes = 0x01, } impl SysvddLvdf { #[inline(always)] @@ -1928,9 +1888,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum VdCoreCfgLock { #[doc = "Allow."] - ALLOW = 0x0, + Allow = 0x0, #[doc = "Deny."] - DENY = 0x01, + Deny = 0x01, } impl VdCoreCfgLock { #[inline(always)] @@ -1959,9 +1919,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum VdSysCfgLock { #[doc = "Allow."] - ALLOW = 0x0, + Allow = 0x0, #[doc = "Deny."] - DENY = 0x01, + Deny = 0x01, } impl VdSysCfgLock { #[inline(always)] @@ -1990,9 +1950,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum VddVdDisable { #[doc = "Enable."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable."] - DISABLE = 0x01, + Disable = 0x01, } impl VddVdDisable { #[inline(always)] @@ -2022,10 +1982,11 @@ impl From for u8 { pub enum Vsm { _RESERVED_0 = 0x0, #[doc = "SRAM configured for 1.0V"] - SRAM1V0 = 0x01, - _RESERVED_2 = 0x02, + Sram1v0 = 0x01, + #[doc = "SRAM configured for 1.1V"] + Sram1v1 = 0x02, #[doc = "SRAM configured for 1.2V"] - SRAM1V2 = 0x03, + Sram1v2 = 0x03, } impl Vsm { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/SYSCON2xx.rs b/nxp-pac/src/meta_peripherals/mcxa/SYSCON2xx.rs index 0cdd38e..08d4c7a 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/SYSCON2xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/SYSCON2xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "SYSCON."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Syscon { @@ -158,11 +159,27 @@ impl Syscon { ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0b6cusize) as _) } } + #[doc = "UDF Control."] + #[inline(always)] + pub const fn els_udf(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0e10usize) as _) } + } #[doc = "MSF Configuration."] #[inline(always)] pub const fn msfcfg(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0e1cusize) as _) } } + #[doc = "Device UID n."] + #[inline(always)] + pub const fn els_uid( + self, + n: usize, + ) -> crate::pac::common::Reg { + assert!(n < 4usize); + unsafe { + crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0e20usize + n * 4usize) as _) + } + } #[doc = "ROP State Register."] #[inline(always)] pub const fn rop_state(self) -> crate::pac::common::Reg { @@ -1352,6 +1369,112 @@ impl defmt::Format for ElsOtpLcStateDp { ) } } +#[doc = "UDF Control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct ElsUdf(pub u32); +impl ElsUdf { + #[doc = "UDF KEY Select."] + #[must_use] + #[inline(always)] + pub const fn key_sel(&self) -> KeySel { + let val = (self.0 >> 0usize) & 0x03; + KeySel::from_bits(val as u8) + } + #[doc = "UDF KEY Select."] + #[inline(always)] + pub const fn set_key_sel(&mut self, val: KeySel) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } + #[doc = "UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] + #[must_use] + #[inline(always)] + pub const fn uid_hidden(&self) -> UidHidden { + let val = (self.0 >> 24usize) & 0x0f; + UidHidden::from_bits(val as u8) + } + #[doc = "UID register hidden control. Write values other than 1010b, locked the write of UID_HIDDEN until a system reset."] + #[inline(always)] + pub const fn set_uid_hidden(&mut self, val: UidHidden) { + self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize); + } + #[doc = "UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] + #[must_use] + #[inline(always)] + pub const fn udf_hidden(&self) -> UdfHidden { + let val = (self.0 >> 28usize) & 0x0f; + UdfHidden::from_bits(val as u8) + } + #[doc = "UDF register hidden control. Write values other than 1010b, locked the write of UDF_HIDDEN until a system reset."] + #[inline(always)] + pub const fn set_udf_hidden(&mut self, val: UdfHidden) { + self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); + } +} +impl Default for ElsUdf { + #[inline(always)] + fn default() -> ElsUdf { + ElsUdf(0) + } +} +impl core::fmt::Debug for ElsUdf { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ElsUdf") + .field("key_sel", &self.key_sel()) + .field("uid_hidden", &self.uid_hidden()) + .field("udf_hidden", &self.udf_hidden()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for ElsUdf { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "ElsUdf {{ key_sel: {:?}, uid_hidden: {:?}, udf_hidden: {:?} }}", + self.key_sel(), + self.uid_hidden(), + self.udf_hidden() + ) + } +} +#[doc = "Device UID n."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct ElsUid(pub u32); +impl ElsUid { + #[doc = "UID."] + #[must_use] + #[inline(always)] + pub const fn uid0(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "UID."] + #[inline(always)] + pub const fn set_uid0(&mut self, val: u32) { + self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } +} +impl Default for ElsUid { + #[inline(always)] + fn default() -> ElsUid { + ElsUid(0) + } +} +impl core::fmt::Debug for ElsUid { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ElsUid") + .field("uid0", &self.uid0()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for ElsUid { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "ElsUid {{ uid0: {=u32:?} }}", self.uid0()) + } +} #[doc = "FRO_HF_DIV Clock Divider."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2123,14 +2246,14 @@ impl Protlvl { pub const fn set_locknsmpu(&mut self, val: Locknsmpu) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val.to_bits() as u32) & 0x01) << 16usize); } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] #[must_use] #[inline(always)] pub const fn lock(&self) -> ProtlvlLock { let val = (self.0 >> 31usize) & 0x01; ProtlvlLock::from_bits(val as u8) } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] #[inline(always)] pub const fn set_lock(&mut self, val: ProtlvlLock) { self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); @@ -2480,28 +2603,28 @@ impl Remap { pub const fn set_cpu0_sbus(&mut self, val: RemapCpu0Sbus) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } - #[doc = "RAMX0 address remap for SmartDMA I-BUS."] + #[doc = "RAMX0 address remap for SmartDMA D-BUS."] #[must_use] #[inline(always)] - pub const fn smart_dma_i(&self) -> SmartDmaI { + pub const fn smart_dma_d(&self) -> SmartDmaD { let val = (self.0 >> 4usize) & 0x03; - SmartDmaI::from_bits(val as u8) + SmartDmaD::from_bits(val as u8) } - #[doc = "RAMX0 address remap for SmartDMA I-BUS."] + #[doc = "RAMX0 address remap for SmartDMA D-BUS."] #[inline(always)] - pub const fn set_smart_dma_i(&mut self, val: SmartDmaI) { + pub const fn set_smart_dma_d(&mut self, val: SmartDmaD) { self.0 = (self.0 & !(0x03 << 4usize)) | (((val.to_bits() as u32) & 0x03) << 4usize); } - #[doc = "RAMX0 address remap for SmartDMA D-BUS."] + #[doc = "RAMX0 address remap for SmartDMA I-BUS."] #[must_use] #[inline(always)] - pub const fn smart_dma_d(&self) -> SmartDmaD { + pub const fn smart_dma_i(&self) -> SmartDmaI { let val = (self.0 >> 6usize) & 0x03; - SmartDmaD::from_bits(val as u8) + SmartDmaI::from_bits(val as u8) } - #[doc = "RAMX0 address remap for SmartDMA D-BUS."] + #[doc = "RAMX0 address remap for SmartDMA I-BUS."] #[inline(always)] - pub const fn set_smart_dma_d(&mut self, val: SmartDmaD) { + pub const fn set_smart_dma_i(&mut self, val: SmartDmaI) { self.0 = (self.0 & !(0x03 << 6usize)) | (((val.to_bits() as u32) & 0x03) << 6usize); } #[doc = "RAMX0 address remap for DMA0."] @@ -2540,14 +2663,14 @@ impl Remap { pub const fn set_usb0(&mut self, val: Usb0) { self.0 = (self.0 & !(0x03 << 24usize)) | (((val.to_bits() as u32) & 0x03) << 24usize); } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] #[must_use] #[inline(always)] pub const fn lock(&self) -> RemapLock { let val = (self.0 >> 31usize) & 0x01; RemapLock::from_bits(val as u8) } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."] #[inline(always)] pub const fn set_lock(&mut self, val: RemapLock) { self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); @@ -2563,8 +2686,8 @@ impl core::fmt::Debug for Remap { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Remap") .field("cpu0_sbus", &self.cpu0_sbus()) - .field("smart_dma_i", &self.smart_dma_i()) .field("smart_dma_d", &self.smart_dma_d()) + .field("smart_dma_i", &self.smart_dma_i()) .field("dma0", &self.dma0()) .field("pkc", &self.pkc()) .field("usb0", &self.usb0()) @@ -2577,10 +2700,10 @@ impl defmt::Format for Remap { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Remap {{ cpu0_sbus: {:?}, smart_dma_i: {:?}, smart_dma_d: {:?}, dma0: {:?}, pkc: {:?}, usb0: {:?}, lock: {:?} }}", + "Remap {{ cpu0_sbus: {:?}, smart_dma_d: {:?}, smart_dma_i: {:?}, dma0: {:?}, pkc: {:?}, usb0: {:?}, lock: {:?} }}", self.cpu0_sbus(), - self.smart_dma_i(), self.smart_dma_d(), + self.smart_dma_i(), self.dma0(), self.pkc(), self.usb0(), @@ -2713,122 +2836,122 @@ impl defmt::Format for Slowclkdiv { #[derive(Copy, Clone, Eq, PartialEq)] pub struct SmartDmaint(pub u32); impl SmartDmaint { - #[doc = "SmartDMA hijack NVIC IRQ2."] + #[doc = "SmartDMA hijack NVIC IRQ1."] #[must_use] #[inline(always)] pub const fn int0(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ2."] + #[doc = "SmartDMA hijack NVIC IRQ1."] #[inline(always)] pub const fn set_int0(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } - #[doc = "SmartDMA hijack NVIC IRQ23."] + #[doc = "SmartDMA hijack NVIC IRQ17."] #[must_use] #[inline(always)] pub const fn int1(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ23."] + #[doc = "SmartDMA hijack NVIC IRQ17."] #[inline(always)] pub const fn set_int1(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } - #[doc = "SmartDMA hijack NVIC IRQ26."] + #[doc = "SmartDMA hijack NVIC IRQ18."] #[must_use] #[inline(always)] pub const fn int2(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ26."] + #[doc = "SmartDMA hijack NVIC IRQ18."] #[inline(always)] pub const fn set_int2(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "SmartDMA hijack NVIC IRQ27."] + #[doc = "SmartDMA hijack NVIC IRQ29."] #[must_use] #[inline(always)] pub const fn int3(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ27."] + #[doc = "SmartDMA hijack NVIC IRQ29."] #[inline(always)] pub const fn set_int3(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } - #[doc = "SmartDMA hijack NVIC IRQ28."] + #[doc = "SmartDMA hijack NVIC IRQ30."] #[must_use] #[inline(always)] pub const fn int4(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ28."] + #[doc = "SmartDMA hijack NVIC IRQ30."] #[inline(always)] pub const fn set_int4(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } - #[doc = "SmartDMA hijack NVIC IRQ29."] + #[doc = "SmartDMA hijack NVIC IRQ31."] #[must_use] #[inline(always)] pub const fn int5(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ29."] + #[doc = "SmartDMA hijack NVIC IRQ31."] #[inline(always)] pub const fn set_int5(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "SmartDMA hijack NVIC IRQ31."] + #[doc = "SmartDMA hijack NVIC IRQ32."] #[must_use] #[inline(always)] pub const fn int6(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ31."] + #[doc = "SmartDMA hijack NVIC IRQ32."] #[inline(always)] pub const fn set_int6(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } - #[doc = "SmartDMA hijack NVIC IRQ32."] + #[doc = "SmartDMA hijack NVIC IRQ33."] #[must_use] #[inline(always)] pub const fn int7(&self) -> bool { let val = (self.0 >> 7usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ32."] + #[doc = "SmartDMA hijack NVIC IRQ33."] #[inline(always)] pub const fn set_int7(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); } - #[doc = "SmartDMA hijack NVIC IRQ33."] + #[doc = "SmartDMA hijack NVIC IRQ34."] #[must_use] #[inline(always)] pub const fn int8(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ33."] + #[doc = "SmartDMA hijack NVIC IRQ34."] #[inline(always)] pub const fn set_int8(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } - #[doc = "SmartDMA hijack NVIC IRQ34."] + #[doc = "SmartDMA hijack NVIC IRQ35."] #[must_use] #[inline(always)] pub const fn int9(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ34."] + #[doc = "SmartDMA hijack NVIC IRQ35."] #[inline(always)] pub const fn set_int9(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); @@ -2845,138 +2968,162 @@ impl SmartDmaint { pub const fn set_int10(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } - #[doc = "SmartDMA hijack NVIC IRQ39."] + #[doc = "SmartDMA hijack NVIC IRQ37."] #[must_use] #[inline(always)] pub const fn int11(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ39."] + #[doc = "SmartDMA hijack NVIC IRQ37."] #[inline(always)] pub const fn set_int11(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } - #[doc = "SmartDMA hijack NVIC IRQ40."] + #[doc = "SmartDMA hijack NVIC IRQ38."] #[must_use] #[inline(always)] pub const fn int12(&self) -> bool { let val = (self.0 >> 12usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ40."] + #[doc = "SmartDMA hijack NVIC IRQ38."] #[inline(always)] pub const fn set_int12(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); } - #[doc = "SmartDMA hijack NVIC IRQ41."] + #[doc = "SmartDMA hijack NVIC IRQ39."] #[must_use] #[inline(always)] pub const fn int13(&self) -> bool { let val = (self.0 >> 13usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ41."] + #[doc = "SmartDMA hijack NVIC IRQ39."] #[inline(always)] pub const fn set_int13(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); } - #[doc = "SmartDMA hijack NVIC IRQ59."] + #[doc = "SmartDMA hijack NVIC IRQ40."] #[must_use] #[inline(always)] pub const fn int14(&self) -> bool { let val = (self.0 >> 14usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ59."] + #[doc = "SmartDMA hijack NVIC IRQ40."] #[inline(always)] pub const fn set_int14(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } - #[doc = "SmartDMA hijack NVIC IRQ62."] + #[doc = "SmartDMA hijack NVIC IRQ41."] #[must_use] #[inline(always)] pub const fn int15(&self) -> bool { let val = (self.0 >> 15usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ62."] + #[doc = "SmartDMA hijack NVIC IRQ41."] #[inline(always)] pub const fn set_int15(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); } - #[doc = "SmartDMA hijack NVIC IRQ64."] + #[doc = "SmartDMA hijack NVIC IRQ42."] #[must_use] #[inline(always)] pub const fn int16(&self) -> bool { let val = (self.0 >> 16usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ64."] + #[doc = "SmartDMA hijack NVIC IRQ42."] #[inline(always)] pub const fn set_int16(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "SmartDMA hijack NVIC IRQ71."] + #[doc = "SmartDMA hijack NVIC IRQ45."] #[must_use] #[inline(always)] pub const fn int17(&self) -> bool { let val = (self.0 >> 17usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ71."] + #[doc = "SmartDMA hijack NVIC IRQ45."] #[inline(always)] pub const fn set_int17(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } - #[doc = "SmartDMA hijack NVIC IRQ72."] + #[doc = "SmartDMA hijack NVIC IRQ47."] #[must_use] #[inline(always)] pub const fn int18(&self) -> bool { let val = (self.0 >> 18usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ72."] + #[doc = "SmartDMA hijack NVIC IRQ47."] #[inline(always)] pub const fn set_int18(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); } - #[doc = "SmartDMA hijack NVIC IRQ73."] + #[doc = "SmartDMA hijack NVIC IRQ50."] #[must_use] #[inline(always)] pub const fn int19(&self) -> bool { let val = (self.0 >> 19usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ73."] + #[doc = "SmartDMA hijack NVIC IRQ50."] #[inline(always)] pub const fn set_int19(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); } - #[doc = "SmartDMA hijack NVIC IRQ74."] + #[doc = "SmartDMA hijack NVIC IRQ51."] #[must_use] #[inline(always)] pub const fn int20(&self) -> bool { let val = (self.0 >> 20usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ74."] + #[doc = "SmartDMA hijack NVIC IRQ51."] #[inline(always)] pub const fn set_int20(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); } - #[doc = "SmartDMA hijack NVIC IRQ75."] + #[doc = "SmartDMA hijack NVIC IRQ66."] #[must_use] #[inline(always)] pub const fn int21(&self) -> bool { let val = (self.0 >> 21usize) & 0x01; val != 0 } - #[doc = "SmartDMA hijack NVIC IRQ75."] + #[doc = "SmartDMA hijack NVIC IRQ66."] #[inline(always)] pub const fn set_int21(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); } + #[doc = "SmartDMA hijack NVIC IRQ67."] + #[must_use] + #[inline(always)] + pub const fn int22(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SmartDMA hijack NVIC IRQ67."] + #[inline(always)] + pub const fn set_int22(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "SmartDMA hijack NVIC IRQ77."] + #[must_use] + #[inline(always)] + pub const fn int23(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "SmartDMA hijack NVIC IRQ77."] + #[inline(always)] + pub const fn set_int23(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } } impl Default for SmartDmaint { #[inline(always)] @@ -3009,6 +3156,8 @@ impl core::fmt::Debug for SmartDmaint { .field("int19", &self.int19()) .field("int20", &self.int20()) .field("int21", &self.int21()) + .field("int22", &self.int22()) + .field("int23", &self.int23()) .finish() } } @@ -3017,7 +3166,7 @@ impl defmt::Format for SmartDmaint { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "SmartDmaint {{ int0: {=bool:?}, int1: {=bool:?}, int2: {=bool:?}, int3: {=bool:?}, int4: {=bool:?}, int5: {=bool:?}, int6: {=bool:?}, int7: {=bool:?}, int8: {=bool:?}, int9: {=bool:?}, int10: {=bool:?}, int11: {=bool:?}, int12: {=bool:?}, int13: {=bool:?}, int14: {=bool:?}, int15: {=bool:?}, int16: {=bool:?}, int17: {=bool:?}, int18: {=bool:?}, int19: {=bool:?}, int20: {=bool:?}, int21: {=bool:?} }}", + "SmartDmaint {{ int0: {=bool:?}, int1: {=bool:?}, int2: {=bool:?}, int3: {=bool:?}, int4: {=bool:?}, int5: {=bool:?}, int6: {=bool:?}, int7: {=bool:?}, int8: {=bool:?}, int9: {=bool:?}, int10: {=bool:?}, int11: {=bool:?}, int12: {=bool:?}, int13: {=bool:?}, int14: {=bool:?}, int15: {=bool:?}, int16: {=bool:?}, int17: {=bool:?}, int18: {=bool:?}, int19: {=bool:?}, int20: {=bool:?}, int21: {=bool:?}, int22: {=bool:?}, int23: {=bool:?} }}", self.int0(), self.int1(), self.int2(), @@ -3039,7 +3188,9 @@ impl defmt::Format for SmartDmaint { self.int18(), self.int19(), self.int20(), - self.int21() + self.int21(), + self.int22(), + self.int23() ) } } @@ -3120,14 +3271,14 @@ impl SramXen { pub const fn set_ramc_xen(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] #[must_use] #[inline(always)] pub const fn lock(&self) -> SramXenLock { let val = (self.0 >> 31usize) & 0x01; SramXenLock::from_bits(val as u8) } - #[doc = "This 1-bit field provides a mechanism to limit writes to this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] + #[doc = "This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."] #[inline(always)] pub const fn set_lock(&mut self, val: SramXenLock) { self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); @@ -3322,9 +3473,9 @@ impl defmt::Format for SwdAccessCpu0 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl AhbclkdivUnstab { #[inline(always)] @@ -3353,13 +3504,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioCpu0Sbus { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioCpu0Sbus { #[inline(always)] @@ -3388,13 +3539,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioDma0 { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioDma0 { #[inline(always)] @@ -3423,9 +3574,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl BusclkdivHalt { #[inline(always)] @@ -3454,9 +3605,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl BusclkdivReset { #[inline(always)] @@ -3485,9 +3636,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl BusclkdivUnstab { #[inline(always)] @@ -3516,9 +3667,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClrLpcac { #[doc = "Unclears the cache."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Clears the cache."] - DISABLE = 0x01, + Disable = 0x01, } impl ClrLpcac { #[inline(always)] @@ -3547,13 +3698,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0Cbus { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu0Cbus { #[inline(always)] @@ -3582,9 +3733,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0lockup { #[doc = "CPU is not in lockup."] - AWAKE = 0x0, + Awake = 0x0, #[doc = "CPU is in lockup."] - SLEEPING = 0x01, + Sleeping = 0x01, } impl Cpu0lockup { #[inline(always)] @@ -3613,9 +3764,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0sleeping { #[doc = "CPU is not sleeping."] - AWAKE = 0x0, + Awake = 0x0, #[doc = "CPU is sleeping."] - SLEEPING = 0x01, + Sleeping = 0x01, } impl Cpu0sleeping { #[inline(always)] @@ -3644,13 +3795,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu1CbusSmartDmaI { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu1CbusSmartDmaI { #[inline(always)] @@ -3679,13 +3830,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu1SbusSmartDmaD { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu1SbusSmartDmaD { #[inline(always)] @@ -3715,9 +3866,9 @@ impl From for u8 { pub enum DebugFeaturesCpu0Dbgen { _RESERVED_0 = 0x0, #[doc = "Disables debug."] - DISABLE = 0x01, + Disable = 0x01, #[doc = "Enables debug."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl DebugFeaturesCpu0Dbgen { @@ -3748,9 +3899,9 @@ impl From for u8 { pub enum DebugFeaturesCpu0Niden { _RESERVED_0 = 0x0, #[doc = "Disables debug."] - DISABLE = 0x01, + Disable = 0x01, #[doc = "Enables debug."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl DebugFeaturesCpu0Niden { @@ -3781,9 +3932,9 @@ impl From for u8 { pub enum DebugFeaturesDpCpu0Dbgen { _RESERVED_0 = 0x0, #[doc = "Disables debug."] - DISABLE = 0x01, + Disable = 0x01, #[doc = "Enables debug."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl DebugFeaturesDpCpu0Dbgen { @@ -3814,9 +3965,9 @@ impl From for u8 { pub enum DebugFeaturesDpCpu0Niden { _RESERVED_0 = 0x0, #[doc = "Disables debug."] - DISABLE = 0x01, + Disable = 0x01, #[doc = "Enables debug."] - ENABLE = 0x02, + Enable = 0x02, _RESERVED_3 = 0x03, } impl DebugFeaturesDpCpu0Niden { @@ -3846,19 +3997,19 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DeviceTypePkg { #[doc = "HLQFP."] - HLQFP = 0x0, + Hlqfp = 0x0, #[doc = "HTQFP."] - HTQFP = 0x01, + Htqfp = 0x01, #[doc = "BGA."] - BGA = 0x02, + Bga = 0x02, #[doc = "HDQFP."] - HDQFP = 0x03, + Hdqfp = 0x03, #[doc = "QFN."] - QFN = 0x04, + Qfn = 0x04, #[doc = "CSP."] - CSP = 0x05, + Csp = 0x05, #[doc = "LQFP."] - LQFP = 0x06, + Lqfp = 0x06, _RESERVED_7 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, @@ -3896,9 +4047,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DeviceTypeSec { #[doc = "Non Secure."] - NON_SEC = 0x0, + NonSec = 0x0, #[doc = "Secure."] - SEC = 0x01, + Sec = 0x01, } impl DeviceTypeSec { #[inline(always)] @@ -3927,9 +4078,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisDataSpec { #[doc = "Enables data speculation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables data speculation."] - DISABLE = 0x01, + Disable = 0x01, } impl DisDataSpec { #[inline(always)] @@ -3958,9 +4109,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisFlashSpec { #[doc = "Enables flash speculation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables flash speculation."] - DISABLE = 0x01, + Disable = 0x01, } impl DisFlashSpec { #[inline(always)] @@ -3989,9 +4140,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisLpcac { #[doc = "Enabled."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disabled."] - DISABLE = 0x01, + Disable = 0x01, } impl DisLpcac { #[inline(always)] @@ -4020,9 +4171,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisMbeccErrData { #[doc = "Enables bus error on multi-bit ECC error for data."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables bus error on multi-bit ECC error for data."] - DISABLE = 0x01, + Disable = 0x01, } impl DisMbeccErrData { #[inline(always)] @@ -4051,9 +4202,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisMbeccErrInst { #[doc = "Enables bus error on multi-bit ECC error for instruction."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables bus error on multi-bit ECC error for instruction."] - DISABLE = 0x01, + Disable = 0x01, } impl DisMbeccErrInst { #[inline(always)] @@ -4082,23 +4233,23 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlashSize { #[doc = "32KB."] - SIZE_32KB = 0x0, + Size32kb = 0x0, #[doc = "64KB."] - SIZE_64KB = 0x01, + Size64kb = 0x01, #[doc = "128KB."] - SIZE_128KB = 0x02, + Size128kb = 0x02, #[doc = "256KB."] - SIZE_256KB = 0x03, + Size256kb = 0x03, #[doc = "512KB."] - SIZE_512KB = 0x04, + Size512kb = 0x04, #[doc = "768KB."] - SIZE_768KB = 0x05, + Size768kb = 0x05, #[doc = "1MB."] - SIZE_1MB = 0x06, + Size1mb = 0x06, #[doc = "1.5MB."] - SIZE_1P5MB = 0x07, + Size1p5mb = 0x07, #[doc = "2MB."] - SIZE_2MB = 0x08, + Size2mb = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, @@ -4134,9 +4285,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlashStallEn { #[doc = "No stall on FLASH busy."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Stall on FLASH busy."] - DISABLE = 0x01, + Disable = 0x01, } impl FlashStallEn { #[inline(always)] @@ -4165,9 +4316,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrcNoAlloc { #[doc = "Forces allocation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Forces no allocation."] - DISABLE = 0x01, + Disable = 0x01, } impl FrcNoAlloc { #[inline(always)] @@ -4196,9 +4347,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl FrohfdivHalt { #[inline(always)] @@ -4227,9 +4378,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl FrohfdivReset { #[inline(always)] @@ -4258,9 +4409,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl FrohfdivUnstab { #[inline(always)] @@ -4289,9 +4440,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl FrolfdivHalt { #[inline(always)] @@ -4320,9 +4471,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl FrolfdivReset { #[inline(always)] @@ -4351,9 +4502,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl FrolfdivUnstab { #[inline(always)] @@ -4382,9 +4533,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IfrEraseDis0 { #[doc = "Enable IFR sector erase."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable IFR sector erase, write one lock until a system reset."] - DISABLE = 0x01, + Disable = 0x01, } impl IfrEraseDis0 { #[inline(always)] @@ -4413,9 +4564,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IfrEraseDis1 { #[doc = "Enable IFR sector erase."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable IFR sector erase, write one lock until a system reset."] - DISABLE = 0x01, + Disable = 0x01, } impl IfrEraseDis1 { #[inline(always)] @@ -4444,9 +4595,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IfrEraseDis2 { #[doc = "Enable IFR sector erase."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable IFR sector erase, write one lock until a system reset."] - DISABLE = 0x01, + Disable = 0x01, } impl IfrEraseDis2 { #[inline(always)] @@ -4475,9 +4626,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum IfrEraseDis3 { #[doc = "Enable IFR sector erase."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable IFR sector erase, write one lock until a system reset."] - DISABLE = 0x01, + Disable = 0x01, } impl IfrEraseDis3 { #[inline(always)] @@ -4506,9 +4657,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Interleave { #[doc = "RAM access is consecutive."] - NORMAL = 0x0, + Normal = 0x0, #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] - INTERLEAVE = 0x01, + Interleave = 0x01, } impl Interleave { #[inline(always)] @@ -4535,9 +4686,44 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum KeySel { + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]."] + Duk0 = 0x0, + #[doc = "DUK: UID\\[127:0\\]^RTL_CONST1\\[127:0\\]."] + Duk1 = 0x01, + #[doc = "DeviceHSM."] + DeviceHsm = 0x02, + #[doc = "NXP_mRoT."] + NxpMRoT = 0x03, +} +impl KeySel { + #[inline(always)] + pub const fn from_bits(val: u8) -> KeySel { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for KeySel { + #[inline(always)] + fn from(val: u8) -> KeySel { + KeySel::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: KeySel) -> u8 { + KeySel::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum LockAll { #[doc = "Any other value than b1010: disables write access to all registers."] - DISABLE = 0x0, + Disable = 0x0, _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, @@ -4548,7 +4734,7 @@ pub enum LockAll { _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, #[doc = "Enables write access to all registers."] - ENABLE = 0x0a, + Enable = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, @@ -4582,9 +4768,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Locknsmpu { #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] - DISABLE = 0x01, + Disable = 0x01, } impl Locknsmpu { #[inline(always)] @@ -4613,9 +4799,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum MassEraseDis { #[doc = "Enables mass erase."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables mass erase, write one lock until a system reset."] - DISABLE = 0x01, + Disable = 0x01, } impl MassEraseDis { #[inline(always)] @@ -4644,9 +4830,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Noref { #[doc = "Reference clock is provided."] - YES_REF = 0x0, + YesRef = 0x0, #[doc = "No reference clock is provided."] - NO_REF = 0x01, + NoRef = 0x01, } impl Noref { #[inline(always)] @@ -4675,9 +4861,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pkc { #[doc = "RAMX0: alias space is disabled."] - PKC_0 = 0x0, + Pkc0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - PKC_1 = 0x01, + Pkc1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4708,13 +4894,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PkcEls { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl PkcEls { #[inline(always)] @@ -4743,9 +4929,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl Pll1clkdivHalt { #[inline(always)] @@ -4774,9 +4960,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl Pll1clkdivReset { #[inline(always)] @@ -4805,9 +4991,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl Pll1clkdivUnstab { #[inline(always)] @@ -4836,9 +5022,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ProtlvlLock { #[doc = "This register is not locked and can be altered."] - LOCK_0 = 0x0, + Lock0 = 0x0, #[doc = "This register is locked and cannot be altered until a system reset."] - LOCK_1 = 0x01, + Lock1 = 0x01, } impl ProtlvlLock { #[inline(always)] @@ -4867,29 +5053,29 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RamSize { #[doc = "8KB."] - SIZE_8KB = 0x0, + Size8kb = 0x0, #[doc = "16KB."] - SIZE_16KB = 0x01, + Size16kb = 0x01, #[doc = "32KB."] - SIZE_32KB = 0x02, + Size32kb = 0x02, #[doc = "64KB."] - SIZE_64KB = 0x03, + Size64kb = 0x03, #[doc = "96KB."] - SIZE_96KB = 0x04, + Size96kb = 0x04, #[doc = "128KB."] - SIZE_128KB = 0x05, + Size128kb = 0x05, #[doc = "160KB."] - SIZE_160KB = 0x06, + Size160kb = 0x06, #[doc = "192KB."] - SIZE_192KB = 0x07, + Size192kb = 0x07, #[doc = "256KB."] - SIZE_256KB = 0x08, + Size256kb = 0x08, #[doc = "288KB."] - SIZE_288KB = 0x09, + Size288kb = 0x09, #[doc = "352KB."] - SIZE_352KB = 0x0a, + Size352kb = 0x0a, #[doc = "512KB."] - SIZE_512KB = 0x0b, + Size512kb = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, @@ -4922,9 +5108,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapCpu0Sbus { #[doc = "RAMX0: alias space is disabled."] - CPU0_SBUS_0 = 0x0, + Cpu0Sbus0 = 0x0, #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] - CPU0_SBUS_1 = 0x01, + Cpu0Sbus1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4955,9 +5141,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapDma0 { #[doc = "RAMX0: alias space is disabled."] - DMA0_0 = 0x0, + Dma00 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - DMA0_1 = 0x01, + Dma01 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4988,9 +5174,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapLock { #[doc = "This register is not locked and can be altered."] - LOCK_0 = 0x0, + Lock0 = 0x0, #[doc = "This register is locked and cannot be altered until a system reset."] - LOCK_1 = 0x01, + Lock1 = 0x01, } impl RemapLock { #[inline(always)] @@ -5019,9 +5205,9 @@ impl From for u8 { pub struct SecCode(u32); impl SecCode { #[doc = "CPU0 DAP is not allowed. Reading back register is read as 0x5."] - pub const DISABLE: Self = Self(0x0); + pub const Disable: Self = Self(0x0); #[doc = "Value to write to enable CPU0 SWD access. Reading back register is read as 0xA."] - pub const ENABLE: Self = Self(0x1234_5678); + pub const Enable: Self = Self(0x1234_5678); } impl SecCode { pub const fn from_bits(val: u32) -> SecCode { @@ -5034,8 +5220,8 @@ impl SecCode { impl core::fmt::Debug for SecCode { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("DISABLE"), - 0x1234_5678 => f.write_str("ENABLE"), + 0x0 => f.write_str("Disable"), + 0x1234_5678 => f.write_str("Enable"), other => core::write!(f, "0x{:02X}", other), } } @@ -5044,8 +5230,8 @@ impl core::fmt::Debug for SecCode { impl defmt::Format for SecCode { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "DISABLE"), - 0x1234_5678 => defmt::write!(f, "ENABLE"), + 0x0 => defmt::write!(f, "Disable"), + 0x1234_5678 => defmt::write!(f, "Enable"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -5072,13 +5258,13 @@ pub enum Security { _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, #[doc = "Secure version."] - NON_SEC = 0x05, + NonSec = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, #[doc = "Non secure version."] - SECURITY_10 = 0x0a, + Security10 = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, @@ -5112,9 +5298,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Skew { #[doc = "TENMS value is exact."] - EXACT = 0x0, + Exact = 0x0, #[doc = "TENMS value is not exact or not given."] - INEXACT = 0x01, + Inexact = 0x01, } impl Skew { #[inline(always)] @@ -5143,9 +5329,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl SlowclkdivHalt { #[inline(always)] @@ -5174,9 +5360,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl SlowclkdivReset { #[inline(always)] @@ -5205,9 +5391,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl SlowclkdivUnstab { #[inline(always)] @@ -5236,9 +5422,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmartDmaD { #[doc = "RAMX0: alias space is disabled."] - SMART_DMA_D_0 = 0x0, + SmartDmaD0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - SMART_DMA_D_1 = 0x01, + SmartDmaD1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -5269,9 +5455,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmartDmaI { #[doc = "RAMX0: alias space is disabled."] - SMART_DMA_I_0 = 0x0, + SmartDmaI0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - SMART_DMA_I_1 = 0x01, + SmartDmaI1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -5302,9 +5488,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SramXenLock { #[doc = "This register is not locked and can be altered."] - LOCK_0 = 0x0, + Lock0 = 0x0, #[doc = "This register is locked and cannot be altered."] - LOCK_1 = 0x01, + Lock1 = 0x01, } impl SramXenLock { #[inline(always)] @@ -5331,11 +5517,99 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum UdfHidden { + _RESERVED_0 = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + #[doc = "Enable the access of UDF register from APB bus. All other value, disable the read/write of UDF register from UDF APB bus."] + UdfHidden = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl UdfHidden { + #[inline(always)] + pub const fn from_bits(val: u8) -> UdfHidden { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for UdfHidden { + #[inline(always)] + fn from(val: u8) -> UdfHidden { + UdfHidden::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: UdfHidden) -> u8 { + UdfHidden::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum UidHidden { + _RESERVED_0 = 0x0, + _RESERVED_1 = 0x01, + _RESERVED_2 = 0x02, + _RESERVED_3 = 0x03, + _RESERVED_4 = 0x04, + _RESERVED_5 = 0x05, + _RESERVED_6 = 0x06, + _RESERVED_7 = 0x07, + _RESERVED_8 = 0x08, + _RESERVED_9 = 0x09, + #[doc = "Enable the access of UID\\[127:0\\] register. All other value, disable the read/write of UID\\[127:0\\] register."] + UidHidden = 0x0a, + _RESERVED_b = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl UidHidden { + #[inline(always)] + pub const fn from_bits(val: u8) -> UidHidden { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for UidHidden { + #[inline(always)] + fn from(val: u8) -> UidHidden { + UidHidden::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: UidHidden) -> u8 { + UidHidden::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Unlock { #[doc = "Updates are allowed to all clock configuration registers."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Freezes all clock configuration registers update."] - FREEZE = 0x01, + Freeze = 0x01, } impl Unlock { #[inline(always)] @@ -5364,9 +5638,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Usb0 { #[doc = "RAMX0: alias space is disabled."] - USB0_0 = 0x0, + Usb00 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - USB0_1 = 0x01, + Usb01 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -5397,13 +5671,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum UsbFsEnet { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl UsbFsEnet { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/SYSCON5xx.rs b/nxp-pac/src/meta_peripherals/mcxa/SYSCON5xx.rs index efa3433..09f7e74 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/SYSCON5xx.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/SYSCON5xx.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "SYSCON."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Syscon { @@ -27,6 +28,13 @@ impl Syscon { pub const fn ahbmatprio(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x10usize) as _) } } + #[doc = "Buffering of write accesses on the Synchronous System configuration APB interface."] + #[inline(always)] + pub const fn bufferingahb2vpb0( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x20usize) as _) } + } #[doc = "NMI Source Select."] #[inline(always)] pub const fn nmisrc(self) -> crate::pac::common::Reg { @@ -124,6 +132,11 @@ impl Syscon { pub const fn nvm_ctrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0200usize) as _) } } + #[doc = "ROM Control and State."] + #[inline(always)] + pub const fn romcr(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0204usize) as _) } + } #[doc = "SmartDMA Interrupt Hijack."] #[inline(always)] pub const fn smart_dmaint( @@ -131,10 +144,19 @@ impl Syscon { ) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0214usize) as _) } } - #[doc = "Immediate cessation of execution following the completion of ROM execution."] + #[doc = "USB1-HS Need Clock Control."] + #[inline(always)] + pub const fn usb1needclkctrl( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0224usize) as _) } + } + #[doc = "USB1-HS Need Clock Status."] #[inline(always)] - pub const fn bootrom(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x023cusize) as _) } + pub const fn usb1needclkstat( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0228usize) as _) } } #[doc = "Controls Shared RAM Integration."] #[inline(always)] @@ -153,7 +175,7 @@ impl Syscon { pub const fn lpcac_ctrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0324usize) as _) } } - #[doc = "I3C Misc Control."] + #[doc = "Chip Special I3C Control."] #[inline(always)] pub const fn i3c_misc_ctrl( self, @@ -172,6 +194,37 @@ impl Syscon { pub const fn ram_ctrl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0444usize) as _) } } + #[doc = "FRO 48MHz Reference Clock Control."] + #[inline(always)] + pub const fn ref_clk_ctrl(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0660usize) as _) } + } + #[doc = "FRO 48MHz Reference Clock Control Set."] + #[inline(always)] + pub const fn ref_clk_ctrl_set( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0664usize) as _) } + } + #[doc = "FRO 48MHz Reference Clock Control Clear."] + #[inline(always)] + pub const fn ref_clk_ctrl_clr( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x0668usize) as _) } + } + #[doc = "Flash size configuration."] + #[inline(always)] + pub const fn flashsizecfg( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x07e0usize) as _) } + } + #[doc = "MISC Phantom control register."] + #[inline(always)] + pub const fn miscphantom(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x07e8usize) as _) } + } #[doc = "JTAG Chip ID."] #[inline(always)] pub const fn jtag_id(self) -> crate::pac::common::Reg { @@ -187,6 +240,11 @@ impl Syscon { pub const fn device_id0(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x07f8usize) as _) } } + #[doc = "Chip Revision ID and Number."] + #[inline(always)] + pub const fn dieid(self) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x07fcusize) as _) } + } } #[doc = "System Clock Divider."] #[repr(transparent)] @@ -492,6 +550,201 @@ impl defmt::Format for BinaryCodeMsb { ) } } +#[doc = "Buffering of write accesses on the Synchronous System configuration APB interface."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Bufferingahb2vpb0(pub u32); +impl Bufferingahb2vpb0 { + #[doc = "Enables buffering of write accesses on the peripheral input mux distribute APB interface:."] + #[must_use] + #[inline(always)] + pub const fn inputmux0(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on the peripheral input mux distribute APB interface:."] + #[inline(always)] + pub const fn set_inputmux0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Enables buffering of write accesses on I3C0 APB interface."] + #[must_use] + #[inline(always)] + pub const fn i3c0(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on I3C0 APB interface."] + #[inline(always)] + pub const fn set_i3c0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Enables buffering of write accesses on CTIMER0 APB interface."] + #[must_use] + #[inline(always)] + pub const fn ctimer0(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on CTIMER0 APB interface."] + #[inline(always)] + pub const fn set_ctimer0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Enables buffering of write accesses on CTIMER1 APB interface."] + #[must_use] + #[inline(always)] + pub const fn ctimer1(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on CTIMER1 APB interface."] + #[inline(always)] + pub const fn set_ctimer1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Enables buffering of write accesses on CTIMER2 APB interface."] + #[must_use] + #[inline(always)] + pub const fn ctimer2(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on CTIMER2 APB interface."] + #[inline(always)] + pub const fn set_ctimer2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Enables buffering of write accesses on CTIMER3 APB interface."] + #[must_use] + #[inline(always)] + pub const fn ctimer3(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on CTIMER3 APB interface."] + #[inline(always)] + pub const fn set_ctimer3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Enables buffering of write accesses on CTIMER4 APB interface."] + #[must_use] + #[inline(always)] + pub const fn ctimer4(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on CTIMER4 APB interface."] + #[inline(always)] + pub const fn set_ctimer4(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Enables buffering of write accesses on freqme APB interface."] + #[must_use] + #[inline(always)] + pub const fn freqme(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on freqme APB interface."] + #[inline(always)] + pub const fn set_freqme(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Enables buffering of write accesses on micro Tick APB interface."] + #[must_use] + #[inline(always)] + pub const fn utick(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on micro Tick APB interface."] + #[inline(always)] + pub const fn set_utick(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enables buffering of write accesses on wwdt0 APB interface."] + #[must_use] + #[inline(always)] + pub const fn wwdt0(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on wwdt0 APB interface."] + #[inline(always)] + pub const fn set_wwdt0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Enables buffering of write accesses on wwdt1 APB interface."] + #[must_use] + #[inline(always)] + pub const fn wwdt1(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on wwdt1 APB interface."] + #[inline(always)] + pub const fn set_wwdt1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Enables buffering of write accesses on SmartDMA0 APB interface."] + #[must_use] + #[inline(always)] + pub const fn smart_dma0(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Enables buffering of write accesses on SmartDMA0 APB interface."] + #[inline(always)] + pub const fn set_smart_dma0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } +} +impl Default for Bufferingahb2vpb0 { + #[inline(always)] + fn default() -> Bufferingahb2vpb0 { + Bufferingahb2vpb0(0) + } +} +impl core::fmt::Debug for Bufferingahb2vpb0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Bufferingahb2vpb0") + .field("inputmux0", &self.inputmux0()) + .field("i3c0", &self.i3c0()) + .field("ctimer0", &self.ctimer0()) + .field("ctimer1", &self.ctimer1()) + .field("ctimer2", &self.ctimer2()) + .field("ctimer3", &self.ctimer3()) + .field("ctimer4", &self.ctimer4()) + .field("freqme", &self.freqme()) + .field("utick", &self.utick()) + .field("wwdt0", &self.wwdt0()) + .field("wwdt1", &self.wwdt1()) + .field("smart_dma0", &self.smart_dma0()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Bufferingahb2vpb0 { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Bufferingahb2vpb0 {{ inputmux0: {=bool:?}, i3c0: {=bool:?}, ctimer0: {=bool:?}, ctimer1: {=bool:?}, ctimer2: {=bool:?}, ctimer3: {=bool:?}, ctimer4: {=bool:?}, freqme: {=bool:?}, utick: {=bool:?}, wwdt0: {=bool:?}, wwdt1: {=bool:?}, smart_dma0: {=bool:?} }}", + self.inputmux0(), + self.i3c0(), + self.ctimer0(), + self.ctimer1(), + self.ctimer2(), + self.ctimer3(), + self.ctimer4(), + self.freqme(), + self.utick(), + self.wwdt0(), + self.wwdt1(), + self.smart_dma0() + ) + } +} #[doc = "BUS_CLK Clock Divider."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -841,13 +1094,13 @@ impl DeviceId0 { #[doc = "Indicates the device's ram size."] #[must_use] #[inline(always)] - pub const fn ram_size(&self) -> RamSize { + pub const fn ram_size(&self) -> DeviceId0RamSize { let val = (self.0 >> 0usize) & 0x0f; - RamSize::from_bits(val as u8) + DeviceId0RamSize::from_bits(val as u8) } #[doc = "Indicates the device's ram size."] #[inline(always)] - pub const fn set_ram_size(&mut self, val: RamSize) { + pub const fn set_ram_size(&mut self, val: DeviceId0RamSize) { self.0 = (self.0 & !(0x0f << 0usize)) | (((val.to_bits() as u32) & 0x0f) << 0usize); } #[doc = "Indicates the device's flash size."] @@ -874,14 +1127,14 @@ impl DeviceId0 { pub const fn set_rom_rev_minor(&mut self, val: u8) { self.0 = (self.0 & !(0x0f << 20usize)) | (((val as u32) & 0x0f) << 20usize); } - #[doc = "no description available."] + #[doc = "CM33_SECURITY_EXTENSION_DISABLE\\[3:0\\], which is loaded from soctrim0\\[87:84\\]."] #[must_use] #[inline(always)] pub const fn security(&self) -> Security { let val = (self.0 >> 24usize) & 0x0f; Security::from_bits(val as u8) } - #[doc = "no description available."] + #[doc = "CM33_SECURITY_EXTENSION_DISABLE\\[3:0\\], which is loaded from soctrim0\\[87:84\\]."] #[inline(always)] pub const fn set_security(&mut self, val: Security) { self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize); @@ -999,6 +1252,75 @@ impl defmt::Format for DeviceType { ) } } +#[doc = "Chip Revision ID and Number."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Dieid(pub u32); +impl Dieid { + #[doc = "Chip minor revision."] + #[must_use] + #[inline(always)] + pub const fn minor_revision(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Chip minor revision."] + #[inline(always)] + pub const fn set_minor_revision(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "Chip major revision."] + #[must_use] + #[inline(always)] + pub const fn major_revision(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "Chip major revision."] + #[inline(always)] + pub const fn set_major_revision(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Chip number."] + #[must_use] + #[inline(always)] + pub const fn mco_num_in_die_id(&self) -> u32 { + let val = (self.0 >> 8usize) & 0x000f_ffff; + val as u32 + } + #[doc = "Chip number."] + #[inline(always)] + pub const fn set_mco_num_in_die_id(&mut self, val: u32) { + self.0 = (self.0 & !(0x000f_ffff << 8usize)) | (((val as u32) & 0x000f_ffff) << 8usize); + } +} +impl Default for Dieid { + #[inline(always)] + fn default() -> Dieid { + Dieid(0) + } +} +impl core::fmt::Debug for Dieid { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dieid") + .field("minor_revision", &self.minor_revision()) + .field("major_revision", &self.major_revision()) + .field("mco_num_in_die_id", &self.mco_num_in_die_id()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Dieid { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Dieid {{ minor_revision: {=u8:?}, major_revision: {=u8:?}, mco_num_in_die_id: {=u32:?} }}", + self.minor_revision(), + self.major_revision(), + self.mco_num_in_die_id() + ) + } +} #[doc = "Ethernet Control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1095,6 +1417,61 @@ impl defmt::Format for EnetSbdFlowCtrl { ) } } +#[doc = "Flash size configuration."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Flashsizecfg(pub u32); +impl Flashsizecfg { + #[doc = "Size of Flash Block 0."] + #[must_use] + #[inline(always)] + pub const fn maxaddr0(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Size of Flash Block 0."] + #[inline(always)] + pub const fn set_maxaddr0(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Size of Flash Block 1."] + #[must_use] + #[inline(always)] + pub const fn maxaddr1(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Size of Flash Block 1."] + #[inline(always)] + pub const fn set_maxaddr1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } +} +impl Default for Flashsizecfg { + #[inline(always)] + fn default() -> Flashsizecfg { + Flashsizecfg(0) + } +} +impl core::fmt::Debug for Flashsizecfg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Flashsizecfg") + .field("maxaddr0", &self.maxaddr0()) + .field("maxaddr1", &self.maxaddr1()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Flashsizecfg { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Flashsizecfg {{ maxaddr0: {=u8:?}, maxaddr1: {=u8:?} }}", + self.maxaddr0(), + self.maxaddr1() + ) + } +} #[doc = "FRO_HF_DIV Clock Divider."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -1343,7 +1720,7 @@ impl defmt::Format for GrayCodeMsb { ) } } -#[doc = "I3C Misc Control."] +#[doc = "Chip Special I3C Control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] pub struct I3cMiscCtrl(pub u32); @@ -1420,30 +1797,6 @@ impl I3cMiscCtrl { pub const fn set_i3c2_sda_filt(&mut self, val: I3c2SdaFilt) { self.0 = (self.0 & !(0x0f << 20usize)) | (((val.to_bits() as u32) & 0x0f) << 20usize); } - #[doc = "Disables/enables the I3C3 filter function on SCL pin."] - #[must_use] - #[inline(always)] - pub const fn i3c3_scl_filt(&self) -> I3c3SclFilt { - let val = (self.0 >> 24usize) & 0x0f; - I3c3SclFilt::from_bits(val as u8) - } - #[doc = "Disables/enables the I3C3 filter function on SCL pin."] - #[inline(always)] - pub const fn set_i3c3_scl_filt(&mut self, val: I3c3SclFilt) { - self.0 = (self.0 & !(0x0f << 24usize)) | (((val.to_bits() as u32) & 0x0f) << 24usize); - } - #[doc = "Disables/enables the I3C3 filter function on SDA pin."] - #[must_use] - #[inline(always)] - pub const fn i3c3_sda_filt(&self) -> I3c3SdaFilt { - let val = (self.0 >> 28usize) & 0x0f; - I3c3SdaFilt::from_bits(val as u8) - } - #[doc = "Disables/enables the I3C3 filter function on SDA pin."] - #[inline(always)] - pub const fn set_i3c3_sda_filt(&mut self, val: I3c3SdaFilt) { - self.0 = (self.0 & !(0x0f << 28usize)) | (((val.to_bits() as u32) & 0x0f) << 28usize); - } } impl Default for I3cMiscCtrl { #[inline(always)] @@ -1460,8 +1813,6 @@ impl core::fmt::Debug for I3cMiscCtrl { .field("i3c1_sda_filt", &self.i3c1_sda_filt()) .field("i3c2_scl_filt", &self.i3c2_scl_filt()) .field("i3c2_sda_filt", &self.i3c2_sda_filt()) - .field("i3c3_scl_filt", &self.i3c3_scl_filt()) - .field("i3c3_sda_filt", &self.i3c3_sda_filt()) .finish() } } @@ -1470,15 +1821,13 @@ impl defmt::Format for I3cMiscCtrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "I3cMiscCtrl {{ i3c0_scl_filt: {:?}, i3c0_sda_filt: {:?}, i3c1_scl_filt: {:?}, i3c1_sda_filt: {:?}, i3c2_scl_filt: {:?}, i3c2_sda_filt: {:?}, i3c3_scl_filt: {:?}, i3c3_sda_filt: {:?} }}", + "I3cMiscCtrl {{ i3c0_scl_filt: {:?}, i3c0_sda_filt: {:?}, i3c1_scl_filt: {:?}, i3c1_sda_filt: {:?}, i3c2_scl_filt: {:?}, i3c2_sda_filt: {:?} }}", self.i3c0_scl_filt(), self.i3c0_sda_filt(), self.i3c1_scl_filt(), self.i3c1_sda_filt(), self.i3c2_scl_filt(), - self.i3c2_sda_filt(), - self.i3c3_scl_filt(), - self.i3c3_sda_filt() + self.i3c2_sda_filt() ) } } @@ -1644,52 +1993,121 @@ impl defmt::Format for LpcacCtrl { ) } } -#[doc = "NMI Source Select."] +#[doc = "MISC Phantom control register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Nmisrc(pub u32); -impl Nmisrc { - #[doc = "The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] +pub struct Miscphantom(pub u32); +impl Miscphantom { + #[doc = "System RAM size phantom control."] #[must_use] #[inline(always)] - pub const fn irqcpu0(&self) -> u8 { - let val = (self.0 >> 0usize) & 0xff; - val as u8 + pub const fn ram_size(&self) -> MiscphantomRamSize { + let val = (self.0 >> 0usize) & 0x03; + MiscphantomRamSize::from_bits(val as u8) } - #[doc = "The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] + #[doc = "System RAM size phantom control."] #[inline(always)] - pub const fn set_irqcpu0(&mut self, val: u8) { - self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + pub const fn set_ram_size(&mut self, val: MiscphantomRamSize) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); } - #[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[doc = "RAMA ECC enable."] #[must_use] #[inline(always)] - pub const fn nmiencpu0(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; + pub const fn rama_ecc(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; val != 0 } - #[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[doc = "RAMA ECC enable."] #[inline(always)] - pub const fn set_nmiencpu0(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + pub const fn set_rama_ecc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FLEXCAN_FD enable."] + #[must_use] + #[inline(always)] + pub const fn flexcan_fd_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "FLEXCAN_FD enable."] + #[inline(always)] + pub const fn set_flexcan_fd_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); } } -impl Default for Nmisrc { +impl Default for Miscphantom { #[inline(always)] - fn default() -> Nmisrc { - Nmisrc(0) + fn default() -> Miscphantom { + Miscphantom(0) } } -impl core::fmt::Debug for Nmisrc { +impl core::fmt::Debug for Miscphantom { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Nmisrc") - .field("irqcpu0", &self.irqcpu0()) - .field("nmiencpu0", &self.nmiencpu0()) + f.debug_struct("Miscphantom") + .field("ram_size", &self.ram_size()) + .field("rama_ecc", &self.rama_ecc()) + .field("flexcan_fd_en", &self.flexcan_fd_en()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Nmisrc { +impl defmt::Format for Miscphantom { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Miscphantom {{ ram_size: {:?}, rama_ecc: {=bool:?}, flexcan_fd_en: {=bool:?} }}", + self.ram_size(), + self.rama_ecc(), + self.flexcan_fd_en() + ) + } +} +#[doc = "NMI Source Select."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Nmisrc(pub u32); +impl Nmisrc { + #[doc = "The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] + #[must_use] + #[inline(always)] + pub const fn irqcpu0(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."] + #[inline(always)] + pub const fn set_irqcpu0(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[must_use] + #[inline(always)] + pub const fn nmiencpu0(&self) -> bool { + let val = (self.0 >> 31usize) & 0x01; + val != 0 + } + #[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."] + #[inline(always)] + pub const fn set_nmiencpu0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); + } +} +impl Default for Nmisrc { + #[inline(always)] + fn default() -> Nmisrc { + Nmisrc(0) + } +} +impl core::fmt::Debug for Nmisrc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Nmisrc") + .field("irqcpu0", &self.irqcpu0()) + .field("nmiencpu0", &self.nmiencpu0()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Nmisrc { fn format(&self, f: defmt::Formatter) { defmt::write!( f, @@ -1728,6 +2146,18 @@ impl NvmCtrl { pub const fn set_dis_data_spec(&mut self, val: DisDataSpec) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); } + #[doc = "FLASH IFR1 lock access control."] + #[must_use] + #[inline(always)] + pub const fn lock_ifr1(&self) -> LockIfr1 { + let val = (self.0 >> 9usize) & 0x01; + LockIfr1::from_bits(val as u8) + } + #[doc = "FLASH IFR1 lock access control."] + #[inline(always)] + pub const fn set_lock_ifr1(&mut self, val: LockIfr1) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + } #[doc = "FLASH stall on busy control."] #[must_use] #[inline(always)] @@ -1776,6 +2206,7 @@ impl core::fmt::Debug for NvmCtrl { f.debug_struct("NvmCtrl") .field("dis_flash_spec", &self.dis_flash_spec()) .field("dis_data_spec", &self.dis_data_spec()) + .field("lock_ifr1", &self.lock_ifr1()) .field("flash_stall_en", &self.flash_stall_en()) .field("dis_mbecc_err_inst", &self.dis_mbecc_err_inst()) .field("dis_mbecc_err_data", &self.dis_mbecc_err_data()) @@ -1787,9 +2218,10 @@ impl defmt::Format for NvmCtrl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "NvmCtrl {{ dis_flash_spec: {:?}, dis_data_spec: {:?}, flash_stall_en: {:?}, dis_mbecc_err_inst: {:?}, dis_mbecc_err_data: {:?} }}", + "NvmCtrl {{ dis_flash_spec: {:?}, dis_data_spec: {:?}, lock_ifr1: {:?}, flash_stall_en: {:?}, dis_mbecc_err_inst: {:?}, dis_mbecc_err_data: {:?} }}", self.dis_flash_spec(), self.dis_data_spec(), + self.lock_ifr1(), self.flash_stall_en(), self.dis_mbecc_err_inst(), self.dis_mbecc_err_data() @@ -1884,14 +2316,14 @@ impl defmt::Format for Pll1clkdiv { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Protlvl(pub u32); impl Protlvl { - #[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG, DMA, ROMCP and Flexspi."] + #[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] #[must_use] #[inline(always)] pub const fn priv_(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; val != 0 } - #[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG, DMA, ROMCP and Flexspi."] + #[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG."] #[inline(always)] pub const fn set_priv_(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); @@ -2086,6 +2518,171 @@ impl defmt::Format for RamCtrl { ) } } +#[doc = "FRO 48MHz Reference Clock Control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RefClkCtrl(pub u32); +impl RefClkCtrl { + #[doc = "GDET reference clock enable bit."] + #[must_use] + #[inline(always)] + pub const fn gdet_refclk_en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "GDET reference clock enable bit."] + #[inline(always)] + pub const fn set_gdet_refclk_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "ELS TRNG reference clock enable bit."] + #[must_use] + #[inline(always)] + pub const fn trng_refclk_en(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "ELS TRNG reference clock enable bit."] + #[inline(always)] + pub const fn set_trng_refclk_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } +} +impl Default for RefClkCtrl { + #[inline(always)] + fn default() -> RefClkCtrl { + RefClkCtrl(0) + } +} +impl core::fmt::Debug for RefClkCtrl { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RefClkCtrl") + .field("gdet_refclk_en", &self.gdet_refclk_en()) + .field("trng_refclk_en", &self.trng_refclk_en()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for RefClkCtrl { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "RefClkCtrl {{ gdet_refclk_en: {=bool:?}, trng_refclk_en: {=bool:?} }}", + self.gdet_refclk_en(), + self.trng_refclk_en() + ) + } +} +#[doc = "FRO 48MHz Reference Clock Control Clear."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RefClkCtrlClr(pub u32); +impl RefClkCtrlClr { + #[doc = "GDET reference clock enable clear bit."] + #[must_use] + #[inline(always)] + pub const fn gdet_refclk_en_clr(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "GDET reference clock enable clear bit."] + #[inline(always)] + pub const fn set_gdet_refclk_en_clr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "ELS TRNG reference clock enable clear bit."] + #[must_use] + #[inline(always)] + pub const fn trng_refclk_en_clr(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "ELS TRNG reference clock enable clear bit."] + #[inline(always)] + pub const fn set_trng_refclk_en_clr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } +} +impl Default for RefClkCtrlClr { + #[inline(always)] + fn default() -> RefClkCtrlClr { + RefClkCtrlClr(0) + } +} +impl core::fmt::Debug for RefClkCtrlClr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RefClkCtrlClr") + .field("gdet_refclk_en_clr", &self.gdet_refclk_en_clr()) + .field("trng_refclk_en_clr", &self.trng_refclk_en_clr()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for RefClkCtrlClr { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "RefClkCtrlClr {{ gdet_refclk_en_clr: {=bool:?}, trng_refclk_en_clr: {=bool:?} }}", + self.gdet_refclk_en_clr(), + self.trng_refclk_en_clr() + ) + } +} +#[doc = "FRO 48MHz Reference Clock Control Set."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct RefClkCtrlSet(pub u32); +impl RefClkCtrlSet { + #[doc = "GDET reference clock enable set bit."] + #[must_use] + #[inline(always)] + pub const fn gdet_refclk_en_set(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "GDET reference clock enable set bit."] + #[inline(always)] + pub const fn set_gdet_refclk_en_set(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "ELS TRNG reference clock enable set bit."] + #[must_use] + #[inline(always)] + pub const fn trng_refclk_en_set(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "ELS TRNG reference clock enable set bit."] + #[inline(always)] + pub const fn set_trng_refclk_en_set(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } +} +impl Default for RefClkCtrlSet { + #[inline(always)] + fn default() -> RefClkCtrlSet { + RefClkCtrlSet(0) + } +} +impl core::fmt::Debug for RefClkCtrlSet { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RefClkCtrlSet") + .field("gdet_refclk_en_set", &self.gdet_refclk_en_set()) + .field("trng_refclk_en_set", &self.trng_refclk_en_set()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for RefClkCtrlSet { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "RefClkCtrlSet {{ gdet_refclk_en_set: {=bool:?}, trng_refclk_en_set: {=bool:?} }}", + self.gdet_refclk_en_set(), + self.trng_refclk_en_set() + ) + } +} #[doc = "AHB Matrix Remap Control."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2253,6 +2850,43 @@ impl defmt::Format for Remap { ) } } +#[doc = "ROM Control and State."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Romcr(pub u32); +impl Romcr { + #[doc = "ROM waiting Arm core and other masters for one cycle."] + #[must_use] + #[inline(always)] + pub const fn rom_wait(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "ROM waiting Arm core and other masters for one cycle."] + #[inline(always)] + pub const fn set_rom_wait(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } +} +impl Default for Romcr { + #[inline(always)] + fn default() -> Romcr { + Romcr(0) + } +} +impl core::fmt::Debug for Romcr { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Romcr") + .field("rom_wait", &self.rom_wait()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Romcr { + fn format(&self, f: defmt::Formatter) { + defmt::write!(f, "Romcr {{ rom_wait: {=bool:?} }}", self.rom_wait()) + } +} #[doc = "SLOW_CLK Clock Divider."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2685,14 +3319,166 @@ impl defmt::Format for SmartDmaint { ) } } +#[doc = "USB1-HS Need Clock Control."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Usb1needclkctrl(pub u32); +impl Usb1needclkctrl { + #[doc = "USB1-HS device need_clock signal control."] + #[must_use] + #[inline(always)] + pub const fn ap_hs_dev_needclk(&self) -> ApHsDevNeedclk { + let val = (self.0 >> 0usize) & 0x01; + ApHsDevNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS device need_clock signal control."] + #[inline(always)] + pub const fn set_ap_hs_dev_needclk(&mut self, val: ApHsDevNeedclk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt."] + #[must_use] + #[inline(always)] + pub const fn pol_hs_dev_needclk(&self) -> PolHsDevNeedclk { + let val = (self.0 >> 1usize) & 0x01; + PolHsDevNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt."] + #[inline(always)] + pub const fn set_pol_hs_dev_needclk(&mut self, val: PolHsDevNeedclk) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } + #[doc = "USB1-HS Host need clock signal control."] + #[must_use] + #[inline(always)] + pub const fn ap_hs_host_needclk(&self) -> ApHsHostNeedclk { + let val = (self.0 >> 2usize) & 0x01; + ApHsHostNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS Host need clock signal control."] + #[inline(always)] + pub const fn set_ap_hs_host_needclk(&mut self, val: ApHsHostNeedclk) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + } + #[doc = "USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt."] + #[must_use] + #[inline(always)] + pub const fn pol_hs_host_needclk(&self) -> PolHsHostNeedclk { + let val = (self.0 >> 3usize) & 0x01; + PolHsHostNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt."] + #[inline(always)] + pub const fn set_pol_hs_host_needclk(&mut self, val: PolHsHostNeedclk) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + } + #[doc = "Software override of device controller PHY wake up logic."] + #[must_use] + #[inline(always)] + pub const fn hs_dev_wakeup_n(&self) -> HsDevWakeupN { + let val = (self.0 >> 4usize) & 0x01; + HsDevWakeupN::from_bits(val as u8) + } + #[doc = "Software override of device controller PHY wake up logic."] + #[inline(always)] + pub const fn set_hs_dev_wakeup_n(&mut self, val: HsDevWakeupN) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + } +} +impl Default for Usb1needclkctrl { + #[inline(always)] + fn default() -> Usb1needclkctrl { + Usb1needclkctrl(0) + } +} +impl core::fmt::Debug for Usb1needclkctrl { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Usb1needclkctrl") + .field("ap_hs_dev_needclk", &self.ap_hs_dev_needclk()) + .field("pol_hs_dev_needclk", &self.pol_hs_dev_needclk()) + .field("ap_hs_host_needclk", &self.ap_hs_host_needclk()) + .field("pol_hs_host_needclk", &self.pol_hs_host_needclk()) + .field("hs_dev_wakeup_n", &self.hs_dev_wakeup_n()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Usb1needclkctrl { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Usb1needclkctrl {{ ap_hs_dev_needclk: {:?}, pol_hs_dev_needclk: {:?}, ap_hs_host_needclk: {:?}, pol_hs_host_needclk: {:?}, hs_dev_wakeup_n: {:?} }}", + self.ap_hs_dev_needclk(), + self.pol_hs_dev_needclk(), + self.ap_hs_host_needclk(), + self.pol_hs_host_needclk(), + self.hs_dev_wakeup_n() + ) + } +} +#[doc = "USB1-HS Need Clock Status."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct Usb1needclkstat(pub u32); +impl Usb1needclkstat { + #[doc = "USB1-HS device need_clock signal status."] + #[must_use] + #[inline(always)] + pub const fn dev_needclk(&self) -> DevNeedclk { + let val = (self.0 >> 0usize) & 0x01; + DevNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS device need_clock signal status."] + #[inline(always)] + pub const fn set_dev_needclk(&mut self, val: DevNeedclk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + } + #[doc = "USB1-HS Host need_clock signal status."] + #[must_use] + #[inline(always)] + pub const fn host_needclk(&self) -> HostNeedclk { + let val = (self.0 >> 1usize) & 0x01; + HostNeedclk::from_bits(val as u8) + } + #[doc = "USB1-HS Host need_clock signal status."] + #[inline(always)] + pub const fn set_host_needclk(&mut self, val: HostNeedclk) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + } +} +impl Default for Usb1needclkstat { + #[inline(always)] + fn default() -> Usb1needclkstat { + Usb1needclkstat(0) + } +} +impl core::fmt::Debug for Usb1needclkstat { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Usb1needclkstat") + .field("dev_needclk", &self.dev_needclk()) + .field("host_needclk", &self.host_needclk()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Usb1needclkstat { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Usb1needclkstat {{ dev_needclk: {:?}, host_needclk: {:?} }}", + self.dev_needclk(), + self.host_needclk() + ) + } +} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl AhbclkdivUnstab { #[inline(always)] @@ -2721,13 +3507,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioCoolfluxYEspi { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioCoolfluxYEspi { #[inline(always)] @@ -2756,13 +3542,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioCpu0Sbus { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioCpu0Sbus { #[inline(always)] @@ -2791,13 +3577,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioDma0 { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioDma0 { #[inline(always)] @@ -2826,13 +3612,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioDma1 { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioDma1 { #[inline(always)] @@ -2861,13 +3647,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioPkcEls { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl AhbmatprioPkcEls { #[inline(always)] @@ -2896,69 +3682,131 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum AhbmatprioUsbFsEnet { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, +} +impl AhbmatprioUsbFsEnet { + #[inline(always)] + pub const fn from_bits(val: u8) -> AhbmatprioUsbFsEnet { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for AhbmatprioUsbFsEnet { + #[inline(always)] + fn from(val: u8) -> AhbmatprioUsbFsEnet { + AhbmatprioUsbFsEnet::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: AhbmatprioUsbFsEnet) -> u8 { + AhbmatprioUsbFsEnet::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AhbmatprioUsbHs { + #[doc = "level 0."] + Level0 = 0x0, + #[doc = "level 1."] + Level1 = 0x01, + #[doc = "level 2."] + Level2 = 0x02, + #[doc = "level 3."] + Level3 = 0x03, +} +impl AhbmatprioUsbHs { + #[inline(always)] + pub const fn from_bits(val: u8) -> AhbmatprioUsbHs { + unsafe { core::mem::transmute(val & 0x03) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for AhbmatprioUsbHs { + #[inline(always)] + fn from(val: u8) -> AhbmatprioUsbHs { + AhbmatprioUsbHs::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: AhbmatprioUsbHs) -> u8 { + AhbmatprioUsbHs::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ApHsDevNeedclk { + #[doc = "HOST_NEEDCLK is under hardware control."] + HwCtrl = 0x0, + #[doc = "HOST_NEEDCLK is forced high."] + Forced = 0x01, } -impl AhbmatprioUsbFsEnet { +impl ApHsDevNeedclk { #[inline(always)] - pub const fn from_bits(val: u8) -> AhbmatprioUsbFsEnet { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> ApHsDevNeedclk { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for AhbmatprioUsbFsEnet { +impl From for ApHsDevNeedclk { #[inline(always)] - fn from(val: u8) -> AhbmatprioUsbFsEnet { - AhbmatprioUsbFsEnet::from_bits(val) + fn from(val: u8) -> ApHsDevNeedclk { + ApHsDevNeedclk::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: AhbmatprioUsbFsEnet) -> u8 { - AhbmatprioUsbFsEnet::to_bits(val) + fn from(val: ApHsDevNeedclk) -> u8 { + ApHsDevNeedclk::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum AhbmatprioUsbHs { - #[doc = "level 0."] - LEVEL0 = 0x0, - #[doc = "level 1."] - LEVEL1 = 0x01, - #[doc = "level 2."] - LEVEL2 = 0x02, - #[doc = "level 3."] - LEVEL3 = 0x03, +pub enum ApHsHostNeedclk { + #[doc = "HOST_NEEDCLK is under hardware control."] + HwCtrl = 0x0, + #[doc = "HOST_NEEDCLK is forced high."] + Forced = 0x01, } -impl AhbmatprioUsbHs { +impl ApHsHostNeedclk { #[inline(always)] - pub const fn from_bits(val: u8) -> AhbmatprioUsbHs { - unsafe { core::mem::transmute(val & 0x03) } + pub const fn from_bits(val: u8) -> ApHsHostNeedclk { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for AhbmatprioUsbHs { +impl From for ApHsHostNeedclk { #[inline(always)] - fn from(val: u8) -> AhbmatprioUsbHs { - AhbmatprioUsbHs::from_bits(val) + fn from(val: u8) -> ApHsHostNeedclk { + ApHsHostNeedclk::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: AhbmatprioUsbHs) -> u8 { - AhbmatprioUsbHs::to_bits(val) + fn from(val: ApHsHostNeedclk) -> u8 { + ApHsHostNeedclk::to_bits(val) } } #[repr(u8)] @@ -2966,9 +3814,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl BusclkdivHalt { #[inline(always)] @@ -2997,9 +3845,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl BusclkdivReset { #[inline(always)] @@ -3028,9 +3876,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum BusclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl BusclkdivUnstab { #[inline(always)] @@ -3059,9 +3907,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ClrLpcac { #[doc = "Unclears the cache."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Clears the cache."] - DISABLE = 0x01, + Disable = 0x01, } impl ClrLpcac { #[inline(always)] @@ -3090,13 +3938,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0Cbus { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu0Cbus { #[inline(always)] @@ -3125,9 +3973,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0lockup { #[doc = "CPU is not in lockup."] - AWAKE = 0x0, + Awake = 0x0, #[doc = "CPU is in lockup."] - SLEEPING = 0x01, + Sleeping = 0x01, } impl Cpu0lockup { #[inline(always)] @@ -3156,9 +4004,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu0sleeping { #[doc = "CPU is not sleeping."] - AWAKE = 0x0, + Awake = 0x0, #[doc = "CPU is sleeping."] - SLEEPING = 0x01, + Sleeping = 0x01, } impl Cpu0sleeping { #[inline(always)] @@ -3187,13 +4035,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu1CbusSmartDmaI { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu1CbusSmartDmaI { #[inline(always)] @@ -3222,13 +4070,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Cpu1SbusSmartDmaD { #[doc = "level 0."] - LEVEL0 = 0x0, + Level0 = 0x0, #[doc = "level 1."] - LEVEL1 = 0x01, + Level1 = 0x01, #[doc = "level 2."] - LEVEL2 = 0x02, + Level2 = 0x02, #[doc = "level 3."] - LEVEL3 = 0x03, + Level3 = 0x03, } impl Cpu1SbusSmartDmaD { #[inline(always)] @@ -3255,21 +4103,107 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DevNeedclk { + #[doc = "DEV_NEEDCLK is low."] + Low = 0x0, + #[doc = "DEV_NEEDCLK is high."] + High = 0x01, +} +impl DevNeedclk { + #[inline(always)] + pub const fn from_bits(val: u8) -> DevNeedclk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for DevNeedclk { + #[inline(always)] + fn from(val: u8) -> DevNeedclk { + DevNeedclk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: DevNeedclk) -> u8 { + DevNeedclk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DeviceId0RamSize { + #[doc = "8KB."] + Size8kb = 0x0, + #[doc = "16KB."] + Size16kb = 0x01, + #[doc = "32KB."] + Size32kb = 0x02, + #[doc = "64KB."] + Size64kb = 0x03, + #[doc = "96KB."] + Size96kb = 0x04, + #[doc = "128KB."] + Size128kb = 0x05, + #[doc = "160KB."] + Size160kb = 0x06, + #[doc = "192KB."] + Size192kb = 0x07, + #[doc = "256KB."] + Size256kb = 0x08, + #[doc = "288KB."] + Size288kb = 0x09, + #[doc = "352KB."] + Size352kb = 0x0a, + #[doc = "512KB."] + Size512kb = 0x0b, + _RESERVED_c = 0x0c, + _RESERVED_d = 0x0d, + _RESERVED_e = 0x0e, + _RESERVED_f = 0x0f, +} +impl DeviceId0RamSize { + #[inline(always)] + pub const fn from_bits(val: u8) -> DeviceId0RamSize { + unsafe { core::mem::transmute(val & 0x0f) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for DeviceId0RamSize { + #[inline(always)] + fn from(val: u8) -> DeviceId0RamSize { + DeviceId0RamSize::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: DeviceId0RamSize) -> u8 { + DeviceId0RamSize::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DeviceTypePkg { #[doc = "HLQFP."] - HLQFP = 0x0, + Hlqfp = 0x0, #[doc = "HTQFP."] - HTQFP = 0x01, + Htqfp = 0x01, #[doc = "BGA."] - BGA = 0x02, + Bga = 0x02, #[doc = "HDQFP."] - HDQFP = 0x03, + Hdqfp = 0x03, #[doc = "QFN."] - QFN = 0x04, + Qfn = 0x04, #[doc = "CSP."] - CSP = 0x05, + Csp = 0x05, #[doc = "LQFP."] - LQFP = 0x06, + Lqfp = 0x06, _RESERVED_7 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, @@ -3307,9 +4241,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DeviceTypeSec { #[doc = "Non Secure."] - NON_SEC = 0x0, + NonSec = 0x0, #[doc = "Secure."] - SEC = 0x01, + Sec = 0x01, } impl DeviceTypeSec { #[inline(always)] @@ -3338,9 +4272,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisDataSpec { #[doc = "Enables data speculation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables data speculation."] - DISABLE = 0x01, + Disable = 0x01, } impl DisDataSpec { #[inline(always)] @@ -3369,9 +4303,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisFlashSpec { #[doc = "Enables flash speculation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables flash speculation."] - DISABLE = 0x01, + Disable = 0x01, } impl DisFlashSpec { #[inline(always)] @@ -3400,9 +4334,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisLpcac { #[doc = "Enabled."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disabled."] - DISABLE = 0x01, + Disable = 0x01, } impl DisLpcac { #[inline(always)] @@ -3431,9 +4365,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisMbeccErrData { #[doc = "Enables bus error on multi-bit ECC error for data."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables bus error on multi-bit ECC error for data."] - DISABLE = 0x01, + Disable = 0x01, } impl DisMbeccErrData { #[inline(always)] @@ -3462,9 +4396,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DisMbeccErrInst { #[doc = "Enables bus error on multi-bit ECC error for instruction."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Disables bus error on multi-bit ECC error for instruction."] - DISABLE = 0x01, + Disable = 0x01, } impl DisMbeccErrInst { #[inline(always)] @@ -3493,23 +4427,23 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlashSize { #[doc = "32KB."] - SIZE_32KB = 0x0, + Size32kb = 0x0, #[doc = "64KB."] - SIZE_64KB = 0x01, + Size64kb = 0x01, #[doc = "128KB."] - SIZE_128KB = 0x02, + Size128kb = 0x02, #[doc = "256KB."] - SIZE_256KB = 0x03, + Size256kb = 0x03, #[doc = "512KB."] - SIZE_512KB = 0x04, + Size512kb = 0x04, #[doc = "768KB."] - SIZE_768KB = 0x05, + Size768kb = 0x05, #[doc = "1MB."] - SIZE_1MB = 0x06, + Size1mb = 0x06, #[doc = "1.5MB."] - SIZE_1P5MB = 0x07, + Size1p5mb = 0x07, #[doc = "2MB."] - SIZE_2MB = 0x08, + Size2mb = 0x08, _RESERVED_9 = 0x09, _RESERVED_a = 0x0a, _RESERVED_b = 0x0b, @@ -3545,9 +4479,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FlashStallEn { #[doc = "No stall on FLASH busy."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Stall on FLASH busy."] - DISABLE = 0x01, + Disable = 0x01, } impl FlashStallEn { #[inline(always)] @@ -3576,9 +4510,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrcNoAlloc { #[doc = "Forces allocation."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Forces no allocation."] - DISABLE = 0x01, + Disable = 0x01, } impl FrcNoAlloc { #[inline(always)] @@ -3607,9 +4541,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl FrohfdivHalt { #[inline(always)] @@ -3638,9 +4572,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl FrohfdivReset { #[inline(always)] @@ -3669,9 +4603,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrohfdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl FrohfdivUnstab { #[inline(always)] @@ -3700,9 +4634,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl FrolfdivHalt { #[inline(always)] @@ -3731,9 +4665,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl FrolfdivReset { #[inline(always)] @@ -3762,9 +4696,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FrolfdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl FrolfdivUnstab { #[inline(always)] @@ -3791,11 +4725,73 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum HostNeedclk { + #[doc = "HOST_NEEDCLK is low."] + Low = 0x0, + #[doc = "HOST_NEEDCLK is high."] + High = 0x01, +} +impl HostNeedclk { + #[inline(always)] + pub const fn from_bits(val: u8) -> HostNeedclk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for HostNeedclk { + #[inline(always)] + fn from(val: u8) -> HostNeedclk { + HostNeedclk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: HostNeedclk) -> u8 { + HostNeedclk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum HsDevWakeupN { + #[doc = "Forces USB1_PHY to wake-up."] + ForceWup = 0x0, + #[doc = "Normal USB1_PHY behavior."] + NormalWup = 0x01, +} +impl HsDevWakeupN { + #[inline(always)] + pub const fn from_bits(val: u8) -> HsDevWakeupN { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for HsDevWakeupN { + #[inline(always)] + fn from(val: u8) -> HsDevWakeupN { + HsDevWakeupN::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: HsDevWakeupN) -> u8 { + HsDevWakeupN::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c0SclFilt { #[doc = "Disabled filter function when I3C0 SDA_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT."] - FILT_CNT = 0x01, + FiltCnt = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3838,9 +4834,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c0SdaFilt { #[doc = "Disabled filter function when I3C0 SCL_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, + FiltNum = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3883,9 +4879,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c1SclFilt { #[doc = "Disabled filter function when SDA_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, + FiltNum = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3928,9 +4924,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c1SdaFilt { #[doc = "Disabled filter function when I3C1 SCL_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, + FiltNum = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -3973,9 +4969,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c2SclFilt { #[doc = "Disabled filter function when I3C2 SDA_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, + FiltNum = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -4018,9 +5014,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum I3c2SdaFilt { #[doc = "Disabled filter function when I3C2 SCL_FILT=0b0000."] - DISABLE = 0x0, + Disable = 0x0, #[doc = "Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, + FiltNum = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, @@ -4061,105 +5057,77 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum I3c3SclFilt { - #[doc = "Disabled filter function when I3C3 SDA_FILT=0b0000."] - DISABLE = 0x0, - #[doc = "Enable Spike filter on SCL input. Non_zero value means width of Glitch on SCL line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, +pub enum Interleave { + #[doc = "RAM access is consecutive."] + Normal = 0x0, + #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] + Interleave = 0x01, } -impl I3c3SclFilt { +impl Interleave { #[inline(always)] - pub const fn from_bits(val: u8) -> I3c3SclFilt { - unsafe { core::mem::transmute(val & 0x0f) } + pub const fn from_bits(val: u8) -> Interleave { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for I3c3SclFilt { +impl From for Interleave { #[inline(always)] - fn from(val: u8) -> I3c3SclFilt { - I3c3SclFilt::from_bits(val) + fn from(val: u8) -> Interleave { + Interleave::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: I3c3SclFilt) -> u8 { - I3c3SclFilt::to_bits(val) + fn from(val: Interleave) -> u8 { + Interleave::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum I3c3SdaFilt { - #[doc = "Disabled filter function when I3C3 SCL_FILT=0b0000."] - DISABLE = 0x0, - #[doc = "Enable Spike filter on SDA input. Non_zero value means width of Glitch on SDA line to be filtered in number of half cycles of CLK_FLT."] - FILT_NUM = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, - _RESERVED_4 = 0x04, - _RESERVED_5 = 0x05, - _RESERVED_6 = 0x06, - _RESERVED_7 = 0x07, - _RESERVED_8 = 0x08, - _RESERVED_9 = 0x09, - _RESERVED_a = 0x0a, - _RESERVED_b = 0x0b, - _RESERVED_c = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, +pub enum LockIfr1 { + #[doc = "No lock access to IFR1."] + Enable = 0x0, + #[doc = "Lock access to IFR1."] + Disable = 0x01, } -impl I3c3SdaFilt { +impl LockIfr1 { #[inline(always)] - pub const fn from_bits(val: u8) -> I3c3SdaFilt { - unsafe { core::mem::transmute(val & 0x0f) } + pub const fn from_bits(val: u8) -> LockIfr1 { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for I3c3SdaFilt { +impl From for LockIfr1 { #[inline(always)] - fn from(val: u8) -> I3c3SdaFilt { - I3c3SdaFilt::from_bits(val) + fn from(val: u8) -> LockIfr1 { + LockIfr1::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: I3c3SdaFilt) -> u8 { - I3c3SdaFilt::to_bits(val) + fn from(val: LockIfr1) -> u8 { + LockIfr1::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Interleave { - #[doc = "RAM access is consecutive."] - NORMAL = 0x0, - #[doc = "RAM access is interleaved. This setting is need for PKC L0 memory access."] - INTERLEAVE = 0x01, +pub enum Locknsmpu { + #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] + Enable = 0x0, + #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] + Disable = 0x01, } -impl Interleave { +impl Locknsmpu { #[inline(always)] - pub const fn from_bits(val: u8) -> Interleave { + pub const fn from_bits(val: u8) -> Locknsmpu { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -4167,47 +5135,50 @@ impl Interleave { unsafe { core::mem::transmute(self) } } } -impl From for Interleave { +impl From for Locknsmpu { #[inline(always)] - fn from(val: u8) -> Interleave { - Interleave::from_bits(val) + fn from(val: u8) -> Locknsmpu { + Locknsmpu::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Interleave) -> u8 { - Interleave::to_bits(val) + fn from(val: Locknsmpu) -> u8 { + Locknsmpu::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Locknsmpu { - #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."] - ENABLE = 0x0, - #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."] - DISABLE = 0x01, +pub enum MiscphantomRamSize { + #[doc = "256KB (RAMX0~X3, RAMA0~A7)."] + Size256kb = 0x0, + #[doc = "512KB (RAMX0~X3, RAMA0~A11, RAMB0~B3)."] + Size512kb = 0x01, + _RESERVED_2 = 0x02, + #[doc = "640KB."] + SizeMax = 0x03, } -impl Locknsmpu { +impl MiscphantomRamSize { #[inline(always)] - pub const fn from_bits(val: u8) -> Locknsmpu { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> MiscphantomRamSize { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for Locknsmpu { +impl From for MiscphantomRamSize { #[inline(always)] - fn from(val: u8) -> Locknsmpu { - Locknsmpu::from_bits(val) + fn from(val: u8) -> MiscphantomRamSize { + MiscphantomRamSize::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Locknsmpu) -> u8 { - Locknsmpu::to_bits(val) + fn from(val: MiscphantomRamSize) -> u8 { + MiscphantomRamSize::to_bits(val) } } #[repr(u8)] @@ -4215,9 +5186,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Noref { #[doc = "Reference clock is provided."] - YES_REF = 0x0, + YesRef = 0x0, #[doc = "No reference clock is provided."] - NO_REF = 0x01, + NoRef = 0x01, } impl Noref { #[inline(always)] @@ -4246,9 +5217,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PhyIntf { #[doc = "Selects MII PHY Interface."] - MII = 0x0, + Mii = 0x0, #[doc = "Selects RMII PHY Interface."] - RMII = 0x01, + Rmii = 0x01, } impl PhyIntf { #[inline(always)] @@ -4277,9 +5248,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum PhySel { #[doc = "Selects external PHY."] - PHY = 0x0, + Phy = 0x0, #[doc = "Selects on-chip 10BASE-T1S."] - T1S = 0x01, + T1s = 0x01, } impl PhySel { #[inline(always)] @@ -4308,9 +5279,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl Pll1clkdivHalt { #[inline(always)] @@ -4339,9 +5310,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl Pll1clkdivReset { #[inline(always)] @@ -4370,9 +5341,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pll1clkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl Pll1clkdivUnstab { #[inline(always)] @@ -4399,15 +5370,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum ProtlvlLock { - #[doc = "This register is not locked and can be altered."] - ENABLE = 0x0, - #[doc = "This register is locked and cannot be altered until a system reset."] - DISABLE = 0x01, +pub enum PolHsDevNeedclk { + #[doc = "Falling edge of DEV_NEEDCLK triggers wake-up."] + Falling = 0x0, + #[doc = "Rising edge of DEV_NEEDCLK triggers wake-up."] + Rising = 0x01, } -impl ProtlvlLock { +impl PolHsDevNeedclk { #[inline(always)] - pub const fn from_bits(val: u8) -> ProtlvlLock { + pub const fn from_bits(val: u8) -> PolHsDevNeedclk { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -4415,72 +5386,78 @@ impl ProtlvlLock { unsafe { core::mem::transmute(self) } } } -impl From for ProtlvlLock { +impl From for PolHsDevNeedclk { #[inline(always)] - fn from(val: u8) -> ProtlvlLock { - ProtlvlLock::from_bits(val) + fn from(val: u8) -> PolHsDevNeedclk { + PolHsDevNeedclk::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: ProtlvlLock) -> u8 { - ProtlvlLock::to_bits(val) + fn from(val: PolHsDevNeedclk) -> u8 { + PolHsDevNeedclk::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RamSize { - #[doc = "8KB."] - SIZE_8KB = 0x0, - #[doc = "16KB."] - SIZE_16KB = 0x01, - #[doc = "32KB."] - SIZE_32KB = 0x02, - #[doc = "64KB."] - SIZE_64KB = 0x03, - #[doc = "96KB."] - SIZE_96KB = 0x04, - #[doc = "128KB."] - SIZE_128KB = 0x05, - #[doc = "160KB."] - SIZE_160KB = 0x06, - #[doc = "192KB."] - SIZE_192KB = 0x07, - #[doc = "256KB."] - SIZE_256KB = 0x08, - #[doc = "288KB."] - SIZE_288KB = 0x09, - #[doc = "352KB."] - SIZE_352KB = 0x0a, - #[doc = "512KB."] - SIZE_512KB = 0x0b, - #[doc = "640KB."] - SIZE_640KB = 0x0c, - _RESERVED_d = 0x0d, - _RESERVED_e = 0x0e, - _RESERVED_f = 0x0f, +pub enum PolHsHostNeedclk { + #[doc = "Falling edge of HOST_NEEDCLK triggers wake-up."] + Falling = 0x0, + #[doc = "Rising edge of HOST_NEEDCLK triggers wake-up."] + Rising = 0x01, } -impl RamSize { +impl PolHsHostNeedclk { #[inline(always)] - pub const fn from_bits(val: u8) -> RamSize { - unsafe { core::mem::transmute(val & 0x0f) } + pub const fn from_bits(val: u8) -> PolHsHostNeedclk { + unsafe { core::mem::transmute(val & 0x01) } + } + #[inline(always)] + pub const fn to_bits(self) -> u8 { + unsafe { core::mem::transmute(self) } + } +} +impl From for PolHsHostNeedclk { + #[inline(always)] + fn from(val: u8) -> PolHsHostNeedclk { + PolHsHostNeedclk::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: PolHsHostNeedclk) -> u8 { + PolHsHostNeedclk::to_bits(val) + } +} +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ProtlvlLock { + #[doc = "This register is not locked and can be altered."] + Lock0 = 0x0, + #[doc = "This register is locked and cannot be altered until a system reset."] + Lock1 = 0x01, +} +impl ProtlvlLock { + #[inline(always)] + pub const fn from_bits(val: u8) -> ProtlvlLock { + unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for RamSize { +impl From for ProtlvlLock { #[inline(always)] - fn from(val: u8) -> RamSize { - RamSize::from_bits(val) + fn from(val: u8) -> ProtlvlLock { + ProtlvlLock::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: RamSize) -> u8 { - RamSize::to_bits(val) + fn from(val: ProtlvlLock) -> u8 { + ProtlvlLock::to_bits(val) } } #[repr(u8)] @@ -4488,9 +5465,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapCoolfluxYEspi { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + CoolfluxYEspi0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + CoolfluxYEspi1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4521,9 +5498,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapCpu0Sbus { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + Cpu0Sbus0 = 0x0, #[doc = "RAMX0: alias space is enabled. It's linear address space from bottom of system ram. The start address is 0x20000000 + (system ram size - RAMX size)*1024."] - ENABLE = 0x01, + Cpu0Sbus1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4554,9 +5531,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapDma0 { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + Dma00 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + Dma01 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4587,9 +5564,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapDma1 { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + Dma10 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + Dma11 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4620,9 +5597,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapLock { #[doc = "This register is not locked and can be altered."] - ENABLE = 0x0, + Lock0 = 0x0, #[doc = "This register is locked and cannot be altered until a system reset."] - DISABLE = 0x01, + Lock1 = 0x01, } impl RemapLock { #[inline(always)] @@ -4651,9 +5628,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapPkcEls { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + PkcEls0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + PkcEls1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4684,9 +5661,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapUsbFsEnet { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + UsbFsEnet0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + UsbFsEnet1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4717,9 +5694,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum RemapUsbHs { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + UsbHs0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + UsbHs1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4754,14 +5731,14 @@ pub enum Security { _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, _RESERVED_4 = 0x04, - #[doc = "Secure version. (All values other than 1010b represent the secure version.)."] - SEC = 0x05, + #[doc = "Secure version."] + NonSec = 0x05, _RESERVED_6 = 0x06, _RESERVED_7 = 0x07, _RESERVED_8 = 0x08, _RESERVED_9 = 0x09, #[doc = "Non secure version."] - NON_SEC = 0x0a, + Security10 = 0x0a, _RESERVED_b = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, @@ -4795,9 +5772,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Skew { #[doc = "TENMS value is exact."] - EXACT = 0x0, + Exact = 0x0, #[doc = "TENMS value is not exact or not given."] - INEXACT = 0x01, + Inexact = 0x01, } impl Skew { #[inline(always)] @@ -4826,9 +5803,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivHalt { #[doc = "Divider clock is running."] - RUN = 0x0, + Run = 0x0, #[doc = "Divider clock is stopped."] - HALT = 0x01, + Halt = 0x01, } impl SlowclkdivHalt { #[inline(always)] @@ -4857,9 +5834,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivReset { #[doc = "Divider is not reset."] - RELEASED = 0x0, + Released = 0x0, #[doc = "Divider is reset."] - ASSERTED = 0x01, + Asserted = 0x01, } impl SlowclkdivReset { #[inline(always)] @@ -4888,9 +5865,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SlowclkdivUnstab { #[doc = "Divider clock is stable."] - STABLE = 0x0, + Stable = 0x0, #[doc = "Clock frequency is not stable."] - ONGOING = 0x01, + Ongoing = 0x01, } impl SlowclkdivUnstab { #[inline(always)] @@ -4919,9 +5896,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmartDmaD { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + SmartDmaD0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + SmartDmaD1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4952,9 +5929,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum SmartDmaI { #[doc = "RAMX0: alias space is disabled."] - DISABLE = 0x0, + SmartDmaI0 = 0x0, #[doc = "RAMX0: same alias space as CPU0_SBUS."] - ENABLE = 0x01, + SmartDmaI1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, } @@ -4985,9 +5962,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Unlock { #[doc = "Updates are allowed to all clock configuration registers."] - ENABLE = 0x0, + Enable = 0x0, #[doc = "Freezes all clock configuration registers update."] - FREEZE = 0x01, + Freeze = 0x01, } impl Unlock { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/TRNG.rs b/nxp-pac/src/meta_peripherals/mcxa/TRNG.rs index 75e01bd..8cc2830 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/TRNG.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/TRNG.rs @@ -1,7 +1,8 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] -#[doc = "TRNG."] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] +#[doc = "pd_main.trng0."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Trng { ptr: *mut u8, @@ -64,7 +65,7 @@ impl Trng { } #[doc = "Oscillator-2 Frequency Count Register."] #[inline(always)] - pub const fn osc2_frqcnt(self) -> crate::pac::common::Reg { + pub const fn osc2_frqcnt(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x18usize) as _) } } #[doc = "Frequency Count Register."] @@ -152,9 +153,9 @@ impl Trng { pub const fn status(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x3cusize) as _) } } - #[doc = "Entropy Read Register."] + #[doc = "Entropy Read Register"] #[inline(always)] - pub const fn ent(self, n: usize) -> crate::pac::common::Reg { + pub const fn ent(self, n: usize) -> crate::pac::common::Reg { assert!(n < 8usize); unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0x40usize + n * 4usize) as _) @@ -220,19 +221,9 @@ impl Trng { pub const fn int_status(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xacusize) as _) } } - #[doc = "Common Security Error Register."] - #[inline(always)] - pub const fn cser(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xb0usize) as _) } - } - #[doc = "Common Security Clear Register."] - #[inline(always)] - pub const fn csclr(self) -> crate::pac::common::Reg { - unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xb4usize) as _) } - } #[doc = "TRNG Oscillator 2 Control Register."] #[inline(always)] - pub const fn osc2_ctl(self) -> crate::pac::common::Reg { + pub const fn osc2_ctl(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xecusize) as _) } } #[doc = "Version ID Register (MS)."] @@ -245,171 +236,12 @@ impl Trng { pub const fn vid2(self) -> crate::pac::common::Reg { unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf4usize) as _) } } -} -#[doc = "Common Security Clear Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Csclr(pub u32); -impl Csclr { - #[doc = "Redundant Signals error/fault Detected."] - #[must_use] - #[inline(always)] - pub const fn red_sigs_clr(&self) -> RedSigsClr { - let val = (self.0 >> 0usize) & 0x01; - RedSigsClr::from_bits(val as u8) - } - #[doc = "Redundant Signals error/fault Detected."] - #[inline(always)] - pub const fn set_red_sigs_clr(&mut self, val: RedSigsClr) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); - } - #[doc = "Read only: Redundant FSM error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn red_fsm_clr(&self) -> RedFsmClr { - let val = (self.0 >> 1usize) & 0x01; - RedFsmClr::from_bits(val as u8) - } - #[doc = "Read only: Redundant FSM error/fault detected."] - #[inline(always)] - pub const fn set_red_fsm_clr(&mut self, val: RedFsmClr) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); - } - #[doc = "Read only: Local-EDC error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn local_edc_clr(&self) -> LocalEdcClr { - let val = (self.0 >> 2usize) & 0x01; - LocalEdcClr::from_bits(val as u8) - } - #[doc = "Read only: Local-EDC error/fault detected."] - #[inline(always)] - pub const fn set_local_edc_clr(&mut self, val: LocalEdcClr) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); - } - #[doc = "Read only: Bus-EDC error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn bus_edc_clr(&self) -> BusEdcClr { - let val = (self.0 >> 3usize) & 0x01; - BusEdcClr::from_bits(val as u8) - } - #[doc = "Read only: Bus-EDC error/fault detected."] - #[inline(always)] - pub const fn set_bus_edc_clr(&mut self, val: BusEdcClr) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); - } -} -impl Default for Csclr { - #[inline(always)] - fn default() -> Csclr { - Csclr(0) - } -} -impl core::fmt::Debug for Csclr { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Csclr") - .field("red_sigs_clr", &self.red_sigs_clr()) - .field("red_fsm_clr", &self.red_fsm_clr()) - .field("local_edc_clr", &self.local_edc_clr()) - .field("bus_edc_clr", &self.bus_edc_clr()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Csclr { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Csclr {{ red_sigs_clr: {:?}, red_fsm_clr: {:?}, local_edc_clr: {:?}, bus_edc_clr: {:?} }}", - self.red_sigs_clr(), - self.red_fsm_clr(), - self.local_edc_clr(), - self.bus_edc_clr() - ) - } -} -#[doc = "Common Security Error Register."] -#[repr(transparent)] -#[derive(Copy, Clone, Eq, PartialEq)] -pub struct Cser(pub u32); -impl Cser { - #[doc = "Redundant Signals error/fault Detected."] - #[must_use] - #[inline(always)] - pub const fn red_sigs(&self) -> RedSigs { - let val = (self.0 >> 0usize) & 0x01; - RedSigs::from_bits(val as u8) - } - #[doc = "Redundant Signals error/fault Detected."] - #[inline(always)] - pub const fn set_red_sigs(&mut self, val: RedSigs) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); - } - #[doc = "Redundant FSM error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn red_fsm(&self) -> RedFsm { - let val = (self.0 >> 1usize) & 0x01; - RedFsm::from_bits(val as u8) - } - #[doc = "Redundant FSM error/fault detected."] + #[doc = "Oscillator Inverter Chain Length Register."] #[inline(always)] - pub const fn set_red_fsm(&mut self, val: RedFsm) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); - } - #[doc = "Local-EDC error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn local_edc(&self) -> LocalEdc { - let val = (self.0 >> 2usize) & 0x01; - LocalEdc::from_bits(val as u8) - } - #[doc = "Local-EDC error/fault detected."] - #[inline(always)] - pub const fn set_local_edc(&mut self, val: LocalEdc) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); - } - #[doc = "Bus-EDC error/fault detected."] - #[must_use] - #[inline(always)] - pub const fn bus_edc(&self) -> BusEdc { - let val = (self.0 >> 3usize) & 0x01; - BusEdc::from_bits(val as u8) - } - #[doc = "Bus-EDC error/fault detected."] - #[inline(always)] - pub const fn set_bus_edc(&mut self, val: BusEdc) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); - } -} -impl Default for Cser { - #[inline(always)] - fn default() -> Cser { - Cser(0) - } -} -impl core::fmt::Debug for Cser { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Cser") - .field("red_sigs", &self.red_sigs()) - .field("red_fsm", &self.red_fsm()) - .field("local_edc", &self.local_edc()) - .field("bus_edc", &self.bus_edc()) - .finish() - } -} -#[cfg(feature = "defmt")] -impl defmt::Format for Cser { - fn format(&self, f: defmt::Formatter) { - defmt::write!( - f, - "Cser {{ red_sigs: {:?}, red_fsm: {:?}, local_edc: {:?}, bus_edc: {:?} }}", - self.red_sigs(), - self.red_fsm(), - self.local_edc(), - self.bus_edc() - ) + pub const fn osc_inv_chain_len( + self, + ) -> crate::pac::common::Reg { + unsafe { crate::pac::common::Reg::from_ptr(self.ptr.wrapping_add(0xf8usize) as _) } } } #[doc = "Entropy Read Register."] @@ -599,14 +431,14 @@ impl IntCtrl { pub const fn set_frq_ct_fail(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Clear the INTG_FLT interrupt."] + #[doc = "Clear the INTG_FLT interrupt"] #[must_use] #[inline(always)] pub const fn intg_flt(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Clear the INTG_FLT interrupt."] + #[doc = "Clear the INTG_FLT interrupt"] #[inline(always)] pub const fn set_intg_flt(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); @@ -682,14 +514,14 @@ impl IntMask { pub const fn set_frq_ct_fail(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } - #[doc = "Mask the INTG_FLT interrupt."] + #[doc = "Mask the INTG_FLT interrupt"] #[must_use] #[inline(always)] pub const fn intg_flt(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; val != 0 } - #[doc = "Mask the INTG_FLT interrupt."] + #[doc = "Mask the INTG_FLT interrupt"] #[inline(always)] pub const fn set_intg_flt(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); @@ -744,14 +576,14 @@ impl IntStatus { #[doc = "Entropy Valid."] #[must_use] #[inline(always)] - pub const fn ent_val(&self) -> IntStatusEntVal { + pub const fn ent_val(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - IntStatusEntVal::from_bits(val as u8) + val != 0 } #[doc = "Entropy Valid."] #[inline(always)] - pub const fn set_ent_val(&mut self, val: IntStatusEntVal) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_ent_val(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "Frequency Count Fail."] #[must_use] @@ -799,7 +631,7 @@ impl defmt::Format for IntStatus { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "IntStatus {{ hw_err: {=bool:?}, ent_val: {:?}, frq_ct_fail: {=bool:?}, intg_flt: {=bool:?} }}", + "IntStatus {{ hw_err: {=bool:?}, ent_val: {=bool:?}, frq_ct_fail: {=bool:?}, intg_flt: {=bool:?} }}", self.hw_err(), self.ent_val(), self.frq_ct_fail(), @@ -812,6 +644,18 @@ impl defmt::Format for IntStatus { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Mctl(pub u32); impl Mctl { + #[doc = "Sample Mode."] + #[must_use] + #[inline(always)] + pub const fn samp_mode(&self) -> SampMode { + let val = (self.0 >> 0usize) & 0x03; + SampMode::from_bits(val as u8) + } + #[doc = "Sample Mode."] + #[inline(always)] + pub const fn set_samp_mode(&mut self, val: SampMode) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize); + } #[doc = "Oscillator1 Divide."] #[must_use] #[inline(always)] @@ -860,6 +704,18 @@ impl Mctl { pub const fn set_rst_def(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } + #[doc = "Force System Clock."] + #[must_use] + #[inline(always)] + pub const fn for_sclk(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Force System Clock."] + #[inline(always)] + pub const fn set_for_sclk(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } #[doc = "Frequency Count Fail."] #[must_use] #[inline(always)] @@ -944,18 +800,6 @@ impl Mctl { pub const fn set_prgm(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); } - #[doc = "Integrity Error."] - #[must_use] - #[inline(always)] - pub const fn intg_err(&self) -> bool { - let val = (self.0 >> 31usize) & 0x01; - val != 0 - } - #[doc = "Integrity Error."] - #[inline(always)] - pub const fn set_intg_err(&mut self, val: bool) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); - } } impl Default for Mctl { #[inline(always)] @@ -966,10 +810,12 @@ impl Default for Mctl { impl core::fmt::Debug for Mctl { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Mctl") + .field("samp_mode", &self.samp_mode()) .field("osc_div", &self.osc_div()) .field("dis_slf_tst", &self.dis_slf_tst()) .field("trng_acc", &self.trng_acc()) .field("rst_def", &self.rst_def()) + .field("for_sclk", &self.for_sclk()) .field("fct_fail", &self.fct_fail()) .field("fct_val", &self.fct_val()) .field("ent_val", &self.ent_val()) @@ -977,7 +823,6 @@ impl core::fmt::Debug for Mctl { .field("tstop_ok", &self.tstop_ok()) .field("osc2_fail", &self.osc2_fail()) .field("prgm", &self.prgm()) - .field("intg_err", &self.intg_err()) .finish() } } @@ -986,27 +831,28 @@ impl defmt::Format for Mctl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mctl {{ osc_div: {:?}, dis_slf_tst: {=bool:?}, trng_acc: {=bool:?}, rst_def: {=bool:?}, fct_fail: {=bool:?}, fct_val: {=bool:?}, ent_val: {=bool:?}, err: {=bool:?}, tstop_ok: {=bool:?}, osc2_fail: {=bool:?}, prgm: {=bool:?}, intg_err: {=bool:?} }}", + "Mctl {{ samp_mode: {:?}, osc_div: {:?}, dis_slf_tst: {=bool:?}, trng_acc: {=bool:?}, rst_def: {=bool:?}, for_sclk: {=bool:?}, fct_fail: {=bool:?}, fct_val: {=bool:?}, ent_val: {=bool:?}, err: {=bool:?}, tstop_ok: {=bool:?}, osc2_fail: {=bool:?}, prgm: {=bool:?} }}", + self.samp_mode(), self.osc_div(), self.dis_slf_tst(), self.trng_acc(), self.rst_def(), + self.for_sclk(), self.fct_fail(), self.fct_val(), self.ent_val(), self.err(), self.tstop_ok(), self.osc2_fail(), - self.prgm(), - self.intg_err() + self.prgm() ) } } #[doc = "TRNG Oscillator 2 Control Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Osc2ctl(pub u32); -impl Osc2ctl { +pub struct Osc2Ctl(pub u32); +impl Osc2Ctl { #[doc = "TRNG entropy generation control."] #[must_use] #[inline(always)] @@ -1022,25 +868,25 @@ impl Osc2ctl { #[doc = "Oscillator 2 Divide."] #[must_use] #[inline(always)] - pub const fn osc2_div(&self) -> Osc2div { + pub const fn osc2_div(&self) -> Osc2Div { let val = (self.0 >> 2usize) & 0x03; - Osc2div::from_bits(val as u8) + Osc2Div::from_bits(val as u8) } #[doc = "Oscillator 2 Divide."] #[inline(always)] - pub const fn set_osc2_div(&mut self, val: Osc2div) { + pub const fn set_osc2_div(&mut self, val: Osc2Div) { self.0 = (self.0 & !(0x03 << 2usize)) | (((val.to_bits() as u32) & 0x03) << 2usize); } #[doc = "Oscillator 2 Clock Output Enable."] #[must_use] #[inline(always)] - pub const fn osc2_out_en(&self) -> Osc2outEn { + pub const fn osc2_out_en(&self) -> Osc2OutEn { let val = (self.0 >> 4usize) & 0x01; - Osc2outEn::from_bits(val as u8) + Osc2OutEn::from_bits(val as u8) } #[doc = "Oscillator 2 Clock Output Enable."] #[inline(always)] - pub const fn set_osc2_out_en(&mut self, val: Osc2outEn) { + pub const fn set_osc2_out_en(&mut self, val: Osc2OutEn) { self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); } #[doc = "TRNG Oscillator 2 Frequency Count Valid."] @@ -1080,15 +926,15 @@ impl Osc2ctl { self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); } } -impl Default for Osc2ctl { +impl Default for Osc2Ctl { #[inline(always)] - fn default() -> Osc2ctl { - Osc2ctl(0) + fn default() -> Osc2Ctl { + Osc2Ctl(0) } } -impl core::fmt::Debug for Osc2ctl { +impl core::fmt::Debug for Osc2Ctl { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Osc2ctl") + f.debug_struct("Osc2Ctl") .field("trng_ent_ctl", &self.trng_ent_ctl()) .field("osc2_div", &self.osc2_div()) .field("osc2_out_en", &self.osc2_out_en()) @@ -1099,11 +945,11 @@ impl core::fmt::Debug for Osc2ctl { } } #[cfg(feature = "defmt")] -impl defmt::Format for Osc2ctl { +impl defmt::Format for Osc2Ctl { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Osc2ctl {{ trng_ent_ctl: {:?}, osc2_div: {:?}, osc2_out_en: {:?}, osc2_fct_val: {=bool:?}, osc_failsafe_lmt: {:?}, osc_failsafe_test: {=bool:?} }}", + "Osc2Ctl {{ trng_ent_ctl: {:?}, osc2_div: {:?}, osc2_out_en: {:?}, osc2_fct_val: {=bool:?}, osc_failsafe_lmt: {:?}, osc_failsafe_test: {=bool:?} }}", self.trng_ent_ctl(), self.osc2_div(), self.osc2_out_en(), @@ -1116,8 +962,8 @@ impl defmt::Format for Osc2ctl { #[doc = "Oscillator-2 Frequency Count Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] -pub struct Osc2frqcnt(pub u32); -impl Osc2frqcnt { +pub struct Osc2Frqcnt(pub u32); +impl Osc2Frqcnt { #[doc = "Frequency Count."] #[must_use] #[inline(always)] @@ -1131,29 +977,84 @@ impl Osc2frqcnt { self.0 = (self.0 & !(0x003f_ffff << 0usize)) | (((val as u32) & 0x003f_ffff) << 0usize); } } -impl Default for Osc2frqcnt { +impl Default for Osc2Frqcnt { #[inline(always)] - fn default() -> Osc2frqcnt { - Osc2frqcnt(0) + fn default() -> Osc2Frqcnt { + Osc2Frqcnt(0) } } -impl core::fmt::Debug for Osc2frqcnt { +impl core::fmt::Debug for Osc2Frqcnt { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Osc2frqcnt") + f.debug_struct("Osc2Frqcnt") .field("osc2_frq_ct", &self.osc2_frq_ct()) .finish() } } #[cfg(feature = "defmt")] -impl defmt::Format for Osc2frqcnt { +impl defmt::Format for Osc2Frqcnt { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Osc2frqcnt {{ osc2_frq_ct: {=u32:?} }}", + "Osc2Frqcnt {{ osc2_frq_ct: {=u32:?} }}", self.osc2_frq_ct() ) } } +#[doc = "Oscillator Inverter Chain Length Register."] +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq)] +pub struct OscInvChainLen(pub u32); +impl OscInvChainLen { + #[doc = "Shows the even number of inverters set/chosen for the oscillator 1."] + #[must_use] + #[inline(always)] + pub const fn osc1_inv_chain_len(&self) -> Osc1InvChainLen { + let val = (self.0 >> 0usize) & 0xff; + Osc1InvChainLen::from_bits(val as u8) + } + #[doc = "Shows the even number of inverters set/chosen for the oscillator 1."] + #[inline(always)] + pub const fn set_osc1_inv_chain_len(&mut self, val: Osc1InvChainLen) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val.to_bits() as u32) & 0xff) << 0usize); + } + #[doc = "Shows the even number of inverters set/chosen for the oscillator 2."] + #[must_use] + #[inline(always)] + pub const fn osc2_inv_chain_len(&self) -> Osc2InvChainLen { + let val = (self.0 >> 8usize) & 0xff; + Osc2InvChainLen::from_bits(val as u8) + } + #[doc = "Shows the even number of inverters set/chosen for the oscillator 2."] + #[inline(always)] + pub const fn set_osc2_inv_chain_len(&mut self, val: Osc2InvChainLen) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val.to_bits() as u32) & 0xff) << 8usize); + } +} +impl Default for OscInvChainLen { + #[inline(always)] + fn default() -> OscInvChainLen { + OscInvChainLen(0) + } +} +impl core::fmt::Debug for OscInvChainLen { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OscInvChainLen") + .field("osc1_inv_chain_len", &self.osc1_inv_chain_len()) + .field("osc2_inv_chain_len", &self.osc2_inv_chain_len()) + .finish() + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for OscInvChainLen { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "OscInvChainLen {{ osc1_inv_chain_len: {:?}, osc2_inv_chain_len: {:?} }}", + self.osc1_inv_chain_len(), + self.osc2_inv_chain_len() + ) + } +} #[doc = "Statistical Check Poker Count 1 and 0 Register."] #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq)] @@ -2609,14 +2510,14 @@ impl defmt::Format for Sdctl { #[derive(Copy, Clone, Eq, PartialEq)] pub struct SecCfg(pub u32); impl SecCfg { - #[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed."] + #[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Poker Range Register (PKRRNG) TRNG Poker Maximum Limit Register (PKRMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Statistical Check Run Length 4 Limit Register (SCR4L) TRNG Statistical Check Run Length 5 Limit Register (SCR5L) TRNG Statistical Check Run Length 6 Limit Register (SCR6PL) TRNG Sparse Bit Limit Register (SBLIM) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed."] #[must_use] #[inline(always)] pub const fn no_prgm(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; val != 0 } - #[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed."] + #[doc = "If set, below mentioned TRNG configuration registers cannot be programmed: Oscillator 2 Control Register (OSC2_CTL): TRNG Entropy Generation Control \\[1:0\\] Oscillator 2 Divider \\[3:2\\] Oscillator Fail Safe Limit \\[13:12\\] Oscillator Fail Safe Test \\[14\\] TRNG Seed Control Register (SDCTL) TRNG Frequency Count Minimum Limit Register (FRQMIN) TRNG Frequency Count Maximum Limit Register (FRQMAX) TRNG Poker Range Register (PKRRNG) TRNG Poker Maximum Limit Register (PKRMAX) TRNG Statistical Check Monobit Limit Register (SCML) TRNG Statistical Check Run Length 1 Limit Register (SCR1L) TRNG Statistical Check Run Length 2 Limit Register (SCR2L) TRNG Statistical Check Run Length 3 Limit Register (SCR3L) TRNG Statistical Check Run Length 4 Limit Register (SCR4L) TRNG Statistical Check Run Length 5 Limit Register (SCR5L) TRNG Statistical Check Run Length 6 Limit Register (SCR6PL) TRNG Sparse Bit Limit Register (SBLIM) TRNG Miscellaneous Control Register (MCTL): Sample Mode \\[1:0\\] Oscillator Divider \\[3:2\\] Reset Defaults \\[6\\] Force System Clock \\[7\\] Long Runs Continuation Mode \\[14\\] After this bit has been written to a 1, it cannot be changed."] #[inline(always)] pub const fn set_no_prgm(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); @@ -3041,14 +2942,14 @@ impl Vid2 { pub const fn set_eco_rev(&mut self, val: EcoRev) { self.0 = (self.0 & !(0xff << 8usize)) | (((val.to_bits() as u32) & 0xff) << 8usize); } - #[doc = "Shows the integration options for the TRNG."] + #[doc = "Shows the integration options for the TRNG. (For 2019 or newer SoCs)."] #[must_use] #[inline(always)] pub const fn intg_opt(&self) -> IntgOpt { let val = (self.0 >> 16usize) & 0xff; IntgOpt::from_bits(val as u8) } - #[doc = "Shows the integration options for the TRNG."] + #[doc = "Shows the integration options for the TRNG. (For 2019 or newer SoCs)."] #[inline(always)] pub const fn set_intg_opt(&mut self, val: IntgOpt) { self.0 = (self.0 & !(0xff << 16usize)) | (((val.to_bits() as u32) & 0xff) << 16usize); @@ -3095,74 +2996,12 @@ impl defmt::Format for Vid2 { ) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum BusEdc { - #[doc = "No Bus-EDC error/fault detected."] - BUS_EDC_NOERR = 0x0, - #[doc = "Bus-EDC error/fault detected."] - BUS_EDC_ERR = 0x01, -} -impl BusEdc { - #[inline(always)] - pub const fn from_bits(val: u8) -> BusEdc { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for BusEdc { - #[inline(always)] - fn from(val: u8) -> BusEdc { - BusEdc::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: BusEdc) -> u8 { - BusEdc::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum BusEdcClr { - #[doc = "No effect, ignored."] - BUS_EDC_NOEFFECT = 0x0, - #[doc = "Clears the CSER\\[BUS_EDC\\] bit."] - BUS_EDC_CLEAR = 0x01, -} -impl BusEdcClr { - #[inline(always)] - pub const fn from_bits(val: u8) -> BusEdcClr { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for BusEdcClr { - #[inline(always)] - fn from(val: u8) -> BusEdcClr { - BusEdcClr::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: BusEdcClr) -> u8 { - BusEdcClr::to_bits(val) - } -} #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct ConfigOpt(u8); impl ConfigOpt { #[doc = "TRNG_CONFIG_OPT for TRNG."] - pub const CONFIG_OPT_VAL: Self = Self(0x0); + pub const ConfigOptVal: Self = Self(0x0); } impl ConfigOpt { pub const fn from_bits(val: u8) -> ConfigOpt { @@ -3175,7 +3014,7 @@ impl ConfigOpt { impl core::fmt::Debug for ConfigOpt { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("CONFIG_OPT_VAL"), + 0x0 => f.write_str("ConfigOptVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3184,7 +3023,7 @@ impl core::fmt::Debug for ConfigOpt { impl defmt::Format for ConfigOpt { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "CONFIG_OPT_VAL"), + 0x0 => defmt::write!(f, "ConfigOptVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3206,7 +3045,7 @@ impl From for u8 { pub struct EcoRev(u8); impl EcoRev { #[doc = "TRNG_ECO_REV for TRNG."] - pub const ECO_REV_VAL: Self = Self(0x0); + pub const EcoRevVal: Self = Self(0x0); } impl EcoRev { pub const fn from_bits(val: u8) -> EcoRev { @@ -3219,7 +3058,7 @@ impl EcoRev { impl core::fmt::Debug for EcoRev { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0 => f.write_str("ECO_REV_VAL"), + 0x0 => f.write_str("EcoRevVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3228,7 +3067,7 @@ impl core::fmt::Debug for EcoRev { impl defmt::Format for EcoRev { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0 => defmt::write!(f, "ECO_REV_VAL"), + 0x0 => defmt::write!(f, "EcoRevVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3250,7 +3089,7 @@ impl From for u8 { pub struct Era(u8); impl Era { #[doc = "ERA of the TRNG."] - pub const ERA_VAL: Self = Self(0x0c); + pub const EraVal: Self = Self(0x0c); } impl Era { pub const fn from_bits(val: u8) -> Era { @@ -3263,7 +3102,7 @@ impl Era { impl core::fmt::Debug for Era { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0c => f.write_str("ERA_VAL"), + 0x0c => f.write_str("EraVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3272,7 +3111,7 @@ impl core::fmt::Debug for Era { impl defmt::Format for Era { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0c => defmt::write!(f, "ERA_VAL"), + 0x0c => defmt::write!(f, "EraVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3289,43 +3128,12 @@ impl From for u8 { Era::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IntStatusEntVal { - #[doc = "Busy generating entropy. Any value read from the Entropy registers is invalid."] - ENT_VAL_INVALID = 0x0, - #[doc = "Values read from the Entropy registers are valid."] - ENT_VAL_VALID = 0x01, -} -impl IntStatusEntVal { - #[inline(always)] - pub const fn from_bits(val: u8) -> IntStatusEntVal { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for IntStatusEntVal { - #[inline(always)] - fn from(val: u8) -> IntStatusEntVal { - IntStatusEntVal::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: IntStatusEntVal) -> u8 { - IntStatusEntVal::to_bits(val) - } -} #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct IntgOpt(u8); impl IntgOpt { #[doc = "INTG_OPT for TRNG."] - pub const INTG_OPT_VAL: Self = Self(0x0a); + pub const IntgOptVal: Self = Self(0x0a); } impl IntgOpt { pub const fn from_bits(val: u8) -> IntgOpt { @@ -3338,7 +3146,7 @@ impl IntgOpt { impl core::fmt::Debug for IntgOpt { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0a => f.write_str("INTG_OPT_VAL"), + 0x0a => f.write_str("IntgOptVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3347,7 +3155,7 @@ impl core::fmt::Debug for IntgOpt { impl defmt::Format for IntgOpt { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0a => defmt::write!(f, "INTG_OPT_VAL"), + 0x0a => defmt::write!(f, "IntgOptVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3369,7 +3177,7 @@ impl From for u8 { pub struct IpId(u16); impl IpId { #[doc = "ID for TRNG."] - pub const IP_ID_VAL: Self = Self(0x30); + pub const IpIdVal: Self = Self(0x30); } impl IpId { pub const fn from_bits(val: u16) -> IpId { @@ -3382,7 +3190,7 @@ impl IpId { impl core::fmt::Debug for IpId { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x30 => f.write_str("IP_ID_VAL"), + 0x30 => f.write_str("IpIdVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3391,7 +3199,7 @@ impl core::fmt::Debug for IpId { impl defmt::Format for IpId { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x30 => defmt::write!(f, "IP_ID_VAL"), + 0x30 => defmt::write!(f, "IpIdVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3408,74 +3216,12 @@ impl From for u16 { IpId::to_bits(val) } } -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LocalEdc { - #[doc = "No Local-EDC error/fault detected."] - LOCAL_EDC_NOERR = 0x0, - #[doc = "Local-EDC error/fault detected."] - LOCAL_EDC_ERR = 0x01, -} -impl LocalEdc { - #[inline(always)] - pub const fn from_bits(val: u8) -> LocalEdc { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for LocalEdc { - #[inline(always)] - fn from(val: u8) -> LocalEdc { - LocalEdc::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: LocalEdc) -> u8 { - LocalEdc::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LocalEdcClr { - #[doc = "No effect, ignored."] - LOCAL_EDC_NOEFFECT = 0x0, - #[doc = "Clears the CSER\\[LOCAL_EDC\\] bit."] - LOCAL_EDC_CLEAR = 0x01, -} -impl LocalEdcClr { - #[inline(always)] - pub const fn from_bits(val: u8) -> LocalEdcClr { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for LocalEdcClr { - #[inline(always)] - fn from(val: u8) -> LocalEdcClr { - LocalEdcClr::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: LocalEdcClr) -> u8 { - LocalEdcClr::to_bits(val) - } -} #[repr(transparent)] #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] pub struct MajRev(u8); impl MajRev { #[doc = "Major revision number for TRNG."] - pub const MAJ_REV_VAL: Self = Self(0x14); + pub const MajRevVal: Self = Self(0x11); } impl MajRev { pub const fn from_bits(val: u8) -> MajRev { @@ -3488,7 +3234,7 @@ impl MajRev { impl core::fmt::Debug for MajRev { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x14 => f.write_str("MAJ_REV_VAL"), + 0x11 => f.write_str("MajRevVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3497,7 +3243,7 @@ impl core::fmt::Debug for MajRev { impl defmt::Format for MajRev { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x14 => defmt::write!(f, "MAJ_REV_VAL"), + 0x11 => defmt::write!(f, "MajRevVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3519,7 +3265,7 @@ impl From for u8 { pub struct MinRev(u8); impl MinRev { #[doc = "Minor revision number for TRNG."] - pub const MIN_REV_VAL: Self = Self(0x0c); + pub const MinRevVal: Self = Self(0x0c); } impl MinRev { pub const fn from_bits(val: u8) -> MinRev { @@ -3532,7 +3278,7 @@ impl MinRev { impl core::fmt::Debug for MinRev { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { match self.0 { - 0x0c => f.write_str("MIN_REV_VAL"), + 0x0c => f.write_str("MinRevVal"), other => core::write!(f, "0x{:02X}", other), } } @@ -3541,7 +3287,7 @@ impl core::fmt::Debug for MinRev { impl defmt::Format for MinRev { fn format(&self, f: defmt::Formatter) { match self.0 { - 0x0c => defmt::write!(f, "MIN_REV_VAL"), + 0x0c => defmt::write!(f, "MinRevVal"), other => defmt::write!(f, "0x{:02X}", other), } } @@ -3558,22 +3304,66 @@ impl From for u8 { MinRev::to_bits(val) } } +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Osc1InvChainLen(u8); +impl Osc1InvChainLen { + #[doc = "Adding 1 to this count are the total number of inversions occurring in ring oscillator 1."] + pub const Osc1InvLen: Self = Self(0x28); +} +impl Osc1InvChainLen { + pub const fn from_bits(val: u8) -> Osc1InvChainLen { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for Osc1InvChainLen { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x28 => f.write_str("Osc1InvLen"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Osc1InvChainLen { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x28 => defmt::write!(f, "Osc1InvLen"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Osc1InvChainLen { + #[inline(always)] + fn from(val: u8) -> Osc1InvChainLen { + Osc1InvChainLen::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Osc1InvChainLen) -> u8 { + Osc1InvChainLen::to_bits(val) + } +} #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Osc2div { +pub enum Osc2Div { #[doc = "Use ring oscillator 2 with no divide."] - OSC2_DIV_DIV1 = 0x0, + Osc2DivDiv1 = 0x0, #[doc = "Use ring oscillator 2 divided-by-2."] - OSC2_DIV_DIV2 = 0x01, + Osc2DivDiv2 = 0x01, #[doc = "Use ring oscillator 2 divided-by-4."] - OSC2_DIV_DIV4 = 0x02, + Osc2DivDiv4 = 0x02, #[doc = "Use ring oscillator 2 divided-by-8."] - OSC2_DIV_DIV8 = 0x03, + Osc2DivDiv8 = 0x03, } -impl Osc2div { +impl Osc2Div { #[inline(always)] - pub const fn from_bits(val: u8) -> Osc2div { + pub const fn from_bits(val: u8) -> Osc2Div { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -3581,30 +3371,74 @@ impl Osc2div { unsafe { core::mem::transmute(self) } } } -impl From for Osc2div { +impl From for Osc2Div { #[inline(always)] - fn from(val: u8) -> Osc2div { - Osc2div::from_bits(val) + fn from(val: u8) -> Osc2Div { + Osc2Div::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Osc2div) -> u8 { - Osc2div::to_bits(val) + fn from(val: Osc2Div) -> u8 { + Osc2Div::to_bits(val) + } +} +#[repr(transparent)] +#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] +pub struct Osc2InvChainLen(u8); +impl Osc2InvChainLen { + #[doc = "Adding 1 to this count are the total number of inversions occurring in ring oscillator 2."] + pub const Osc2InvLen: Self = Self(0x36); +} +impl Osc2InvChainLen { + pub const fn from_bits(val: u8) -> Osc2InvChainLen { + Self(val & 0xff) + } + pub const fn to_bits(self) -> u8 { + self.0 + } +} +impl core::fmt::Debug for Osc2InvChainLen { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + match self.0 { + 0x36 => f.write_str("Osc2InvLen"), + other => core::write!(f, "0x{:02X}", other), + } + } +} +#[cfg(feature = "defmt")] +impl defmt::Format for Osc2InvChainLen { + fn format(&self, f: defmt::Formatter) { + match self.0 { + 0x36 => defmt::write!(f, "Osc2InvLen"), + other => defmt::write!(f, "0x{:02X}", other), + } + } +} +impl From for Osc2InvChainLen { + #[inline(always)] + fn from(val: u8) -> Osc2InvChainLen { + Osc2InvChainLen::from_bits(val) + } +} +impl From for u8 { + #[inline(always)] + fn from(val: Osc2InvChainLen) -> u8 { + Osc2InvChainLen::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Osc2outEn { +pub enum Osc2OutEn { #[doc = "Ring oscillator 2 output is gated to an output pad."] - OSC2_OUT_EN_0 = 0x0, + Osc2OutEn0 = 0x0, #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."] - OSC2_OUT_EN_1 = 0x01, + Osc2OutEn1 = 0x01, } -impl Osc2outEn { +impl Osc2OutEn { #[inline(always)] - pub const fn from_bits(val: u8) -> Osc2outEn { + pub const fn from_bits(val: u8) -> Osc2OutEn { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -3612,16 +3446,16 @@ impl Osc2outEn { unsafe { core::mem::transmute(self) } } } -impl From for Osc2outEn { +impl From for Osc2OutEn { #[inline(always)] - fn from(val: u8) -> Osc2outEn { - Osc2outEn::from_bits(val) + fn from(val: u8) -> Osc2OutEn { + Osc2OutEn::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Osc2outEn) -> u8 { - Osc2outEn::to_bits(val) + fn from(val: Osc2OutEn) -> u8 { + Osc2OutEn::to_bits(val) } } #[repr(u8)] @@ -3629,13 +3463,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum OscDiv { #[doc = "use ring oscillator with no divide."] - OSC_DIV_DIV1 = 0x0, + OscDivDiv1 = 0x0, #[doc = "use ring oscillator divided-by-2."] - OSC_DIV_DIV2 = 0x01, + OscDivDiv2 = 0x01, #[doc = "use ring oscillator divided-by-4."] - OSC_DIV_DIV4 = 0x02, + OscDivDiv4 = 0x02, #[doc = "use ring oscillator divided-by-8."] - OSC_DIV_DIV8 = 0x03, + OscDivDiv8 = 0x03, } impl OscDiv { #[inline(always)] @@ -3664,13 +3498,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum OscFailsafeLmt { #[doc = "The limit N is 4096 (2^12) system clocks."] - OSC_FAILSAFE_LMT_4K = 0x0, + OscFailsafeLmt4k = 0x0, #[doc = "The limit N is 65536 (2^16) system clocks. (default)."] - OSC_FAILSAFE_LMT_64K = 0x01, + OscFailsafeLmt64k = 0x01, #[doc = "N is 2^20 system clocks."] - OSC_FAILSAFE_LMT_1M = 0x02, + OscFailsafeLmt1m = 0x02, #[doc = "N is 2^22 system clocks (full range of the counter being used)."] - OSC_FAILSAFE_LMT_4M = 0x03, + OscFailsafeLmt4m = 0x03, } impl OscFailsafeLmt { #[inline(always)] @@ -3697,125 +3531,36 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RedFsm { - #[doc = "No redundant FSM error/fault."] - RED_FSM_NOERR = 0x0, - #[doc = "Redundant FSM error/fault detected."] - RED_FSM_ERR = 0x01, -} -impl RedFsm { - #[inline(always)] - pub const fn from_bits(val: u8) -> RedFsm { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for RedFsm { - #[inline(always)] - fn from(val: u8) -> RedFsm { - RedFsm::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: RedFsm) -> u8 { - RedFsm::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RedFsmClr { - #[doc = "No effect, ignored."] - RED_FSM_NOEFFECT = 0x0, - #[doc = "Clears the CSER\\[RED_FSM\\] bit."] - RED_FSM_CLEAR = 0x01, -} -impl RedFsmClr { - #[inline(always)] - pub const fn from_bits(val: u8) -> RedFsmClr { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for RedFsmClr { - #[inline(always)] - fn from(val: u8) -> RedFsmClr { - RedFsmClr::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: RedFsmClr) -> u8 { - RedFsmClr::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RedSigs { - #[doc = "No redundant signal error/fault."] - RED_SIGS_NOERR = 0x0, - #[doc = "Redundant signal error/fault detected."] - RED_SIGS_ERR = 0x01, -} -impl RedSigs { - #[inline(always)] - pub const fn from_bits(val: u8) -> RedSigs { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for RedSigs { - #[inline(always)] - fn from(val: u8) -> RedSigs { - RedSigs::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: RedSigs) -> u8 { - RedSigs::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RedSigsClr { - #[doc = "No effect, ignored."] - RED_SIGS_NOEFFECT = 0x0, - #[doc = "Clears the CSER\\[RED_SIGS\\] bit."] - RED_SIGS_CLEAR = 0x01, -} -impl RedSigsClr { - #[inline(always)] - pub const fn from_bits(val: u8) -> RedSigsClr { - unsafe { core::mem::transmute(val & 0x01) } +pub enum SampMode { + #[doc = "undefined/reserved."] + SampModeVonBoth = 0x0, + #[doc = "use raw data into both Entropy shifter and Statistical Checker."] + SampModeRawBoth = 0x01, + #[doc = "undefined/reserved."] + SampModeVonEnt = 0x02, + #[doc = "undefined/reserved."] + SampModeUndef = 0x03, +} +impl SampMode { + #[inline(always)] + pub const fn from_bits(val: u8) -> SampMode { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for RedSigsClr { +impl From for SampMode { #[inline(always)] - fn from(val: u8) -> RedSigsClr { - RedSigsClr::from_bits(val) + fn from(val: u8) -> SampMode { + SampMode::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: RedSigsClr) -> u8 { - RedSigsClr::to_bits(val) + fn from(val: SampMode) -> u8 { + SampMode::to_bits(val) } } #[repr(u8)] @@ -3823,13 +3568,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TrngEntCtl { #[doc = "Single oscillator mode, using OSC1 (default)."] - TRNG_ENT_CTL_SINGLE_OSC1 = 0x0, + TrngEntCtlSingleOsc1 = 0x0, #[doc = "Dual oscillator mode."] - TRNG_ENT_CTL_DUAL_OSCS = 0x01, + TrngEntCtlDualOscs = 0x01, #[doc = "Single oscillator mode, using OSC2."] - TRNG_ENT_CTL_SINGLE_OSC2 = 0x02, + TrngEntCtlSingleOsc2 = 0x02, #[doc = "Unused, (bit field cannot be written to this value)."] - OSC2_DIV_DIV8 = 0x03, + Osc2DivDiv8 = 0x03, } impl TrngEntCtl { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/VBAT.rs b/nxp-pac/src/meta_peripherals/mcxa/VBAT.rs index e9b2521..0743db2 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/VBAT.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/VBAT.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "VBAT."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Vbat { @@ -382,14 +383,14 @@ impl Irqena { #[doc = "POR Detect."] #[must_use] #[inline(always)] - pub const fn por_det(&self) -> IrqenaPorDet { + pub const fn por_det(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - IrqenaPorDet::from_bits(val as u8) + val != 0 } #[doc = "POR Detect."] #[inline(always)] - pub const fn set_por_det(&mut self, val: IrqenaPorDet) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_por_det(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Wakeup Pin Flag."] #[must_use] @@ -406,50 +407,50 @@ impl Irqena { #[doc = "Bandgap Timer 0."] #[must_use] #[inline(always)] - pub const fn timer0_flag(&self) -> IrqenaTimer0Flag { + pub const fn timer0_flag(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - IrqenaTimer0Flag::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timer 0."] #[inline(always)] - pub const fn set_timer0_flag(&mut self, val: IrqenaTimer0Flag) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_timer0_flag(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } #[doc = "Bandgap Timer 2."] #[must_use] #[inline(always)] - pub const fn timer1_flag(&self) -> IrqenaTimer1Flag { + pub const fn timer1_flag(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - IrqenaTimer1Flag::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timer 2."] #[inline(always)] - pub const fn set_timer1_flag(&mut self, val: IrqenaTimer1Flag) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_timer1_flag(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } #[doc = "LDO Ready."] #[must_use] #[inline(always)] - pub const fn ldo_rdy(&self) -> IrqenaLdoRdy { + pub const fn ldo_rdy(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - IrqenaLdoRdy::from_bits(val as u8) + val != 0 } #[doc = "LDO Ready."] #[inline(always)] - pub const fn set_ldo_rdy(&mut self, val: IrqenaLdoRdy) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_ldo_rdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } #[doc = "OSC32k Ready."] #[must_use] #[inline(always)] - pub const fn osc_rdy(&self) -> IrqenaOscRdy { + pub const fn osc_rdy(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; - IrqenaOscRdy::from_bits(val as u8) + val != 0 } #[doc = "OSC32k Ready."] #[inline(always)] - pub const fn set_osc_rdy(&mut self, val: IrqenaOscRdy) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_osc_rdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } } impl Default for Irqena { @@ -475,7 +476,7 @@ impl defmt::Format for Irqena { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Irqena {{ por_det: {:?}, wakeup_flag: {:?}, timer0_flag: {:?}, timer1_flag: {:?}, ldo_rdy: {:?}, osc_rdy: {:?} }}", + "Irqena {{ por_det: {=bool:?}, wakeup_flag: {:?}, timer0_flag: {=bool:?}, timer1_flag: {=bool:?}, ldo_rdy: {=bool:?}, osc_rdy: {=bool:?} }}", self.por_det(), self.wakeup_flag(), self.timer0_flag(), @@ -682,74 +683,74 @@ impl Ldoramc { #[doc = "Isolate SRAM."] #[must_use] #[inline(always)] - pub const fn iso(&self) -> Iso { + pub const fn iso(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - Iso::from_bits(val as u8) + val != 0 } #[doc = "Isolate SRAM."] #[inline(always)] - pub const fn set_iso(&mut self, val: Iso) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_iso(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Switch SRAM."] #[must_use] #[inline(always)] - pub const fn swi(&self) -> Swi { + pub const fn swi(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - Swi::from_bits(val as u8) + val != 0 } #[doc = "Switch SRAM."] #[inline(always)] - pub const fn set_swi(&mut self, val: Swi) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_swi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "Retention."] #[must_use] #[inline(always)] - pub const fn ret0(&self) -> Ret0 { + pub const fn ret0(&self) -> bool { let val = (self.0 >> 8usize) & 0x01; - Ret0::from_bits(val as u8) + val != 0 } #[doc = "Retention."] #[inline(always)] - pub const fn set_ret0(&mut self, val: Ret0) { - self.0 = (self.0 & !(0x01 << 8usize)) | (((val.to_bits() as u32) & 0x01) << 8usize); + pub const fn set_ret0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); } #[doc = "Retention."] #[must_use] #[inline(always)] - pub const fn ret1(&self) -> Ret1 { + pub const fn ret1(&self) -> bool { let val = (self.0 >> 9usize) & 0x01; - Ret1::from_bits(val as u8) + val != 0 } #[doc = "Retention."] #[inline(always)] - pub const fn set_ret1(&mut self, val: Ret1) { - self.0 = (self.0 & !(0x01 << 9usize)) | (((val.to_bits() as u32) & 0x01) << 9usize); + pub const fn set_ret1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); } #[doc = "Retention."] #[must_use] #[inline(always)] - pub const fn ret2(&self) -> Ret2 { + pub const fn ret2(&self) -> bool { let val = (self.0 >> 10usize) & 0x01; - Ret2::from_bits(val as u8) + val != 0 } #[doc = "Retention."] #[inline(always)] - pub const fn set_ret2(&mut self, val: Ret2) { - self.0 = (self.0 & !(0x01 << 10usize)) | (((val.to_bits() as u32) & 0x01) << 10usize); + pub const fn set_ret2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); } #[doc = "Retention."] #[must_use] #[inline(always)] - pub const fn ret3(&self) -> Ret3 { + pub const fn ret3(&self) -> bool { let val = (self.0 >> 11usize) & 0x01; - Ret3::from_bits(val as u8) + val != 0 } #[doc = "Retention."] #[inline(always)] - pub const fn set_ret3(&mut self, val: Ret3) { - self.0 = (self.0 & !(0x01 << 11usize)) | (((val.to_bits() as u32) & 0x01) << 11usize); + pub const fn set_ret3(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); } } impl Default for Ldoramc { @@ -775,7 +776,7 @@ impl defmt::Format for Ldoramc { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ldoramc {{ iso: {:?}, swi: {:?}, ret0: {:?}, ret1: {:?}, ret2: {:?}, ret3: {:?} }}", + "Ldoramc {{ iso: {=bool:?}, swi: {=bool:?}, ret0: {=bool:?}, ret1: {=bool:?}, ret2: {=bool:?}, ret3: {=bool:?} }}", self.iso(), self.swi(), self.ret0(), @@ -805,14 +806,14 @@ impl Ldotimer0 { #[doc = "Bandgap Timeout Period Enable."] #[must_use] #[inline(always)] - pub const fn timen(&self) -> Ldotimer0Timen { + pub const fn timen(&self) -> bool { let val = (self.0 >> 31usize) & 0x01; - Ldotimer0Timen::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timeout Period Enable."] #[inline(always)] - pub const fn set_timen(&mut self, val: Ldotimer0Timen) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_timen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } impl Default for Ldotimer0 { @@ -834,7 +835,7 @@ impl defmt::Format for Ldotimer0 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ldotimer0 {{ timcfg: {:?}, timen: {:?} }}", + "Ldotimer0 {{ timcfg: {:?}, timen: {=bool:?} }}", self.timcfg(), self.timen() ) @@ -860,14 +861,14 @@ impl Ldotimer1 { #[doc = "Bandgap Timeout Period Enable."] #[must_use] #[inline(always)] - pub const fn timen(&self) -> Ldotimer1Timen { + pub const fn timen(&self) -> bool { let val = (self.0 >> 31usize) & 0x01; - Ldotimer1Timen::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timeout Period Enable."] #[inline(always)] - pub const fn set_timen(&mut self, val: Ldotimer1Timen) { - self.0 = (self.0 & !(0x01 << 31usize)) | (((val.to_bits() as u32) & 0x01) << 31usize); + pub const fn set_timen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize); } } impl Default for Ldotimer1 { @@ -889,7 +890,7 @@ impl defmt::Format for Ldotimer1 { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Ldotimer1 {{ timcfg: {=u32:?}, timen: {:?} }}", + "Ldotimer1 {{ timcfg: {=u32:?}, timen: {=bool:?} }}", self.timcfg(), self.timen() ) @@ -1132,14 +1133,14 @@ impl Oscctla { #[doc = "Crystal Oscillator Bypass Enable."] #[must_use] #[inline(always)] - pub const fn osc_byp_en(&self) -> OscBypEn { + pub const fn osc_byp_en(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - OscBypEn::from_bits(val as u8) + val != 0 } #[doc = "Crystal Oscillator Bypass Enable."] #[inline(always)] - pub const fn set_osc_byp_en(&mut self, val: OscBypEn) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_osc_byp_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } #[doc = "Amplifier Gain Coarse Adjustment."] #[must_use] @@ -1168,14 +1169,14 @@ impl Oscctla { #[doc = "Output Hysteresis Select."] #[must_use] #[inline(always)] - pub const fn hyst_sel(&self) -> HystSel { + pub const fn hyst_sel(&self) -> bool { let val = (self.0 >> 6usize) & 0x01; - HystSel::from_bits(val as u8) + val != 0 } #[doc = "Output Hysteresis Select."] #[inline(always)] - pub const fn set_hyst_sel(&mut self, val: HystSel) { - self.0 = (self.0 & !(0x01 << 6usize)) | (((val.to_bits() as u32) & 0x01) << 6usize); + pub const fn set_hyst_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); } #[doc = "Crystal Load Capacitance Selection Enable."] #[must_use] @@ -1265,7 +1266,7 @@ impl defmt::Format for Oscctla { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Oscctla {{ osc_en: {=bool:?}, osc_byp_en: {:?}, coarse_amp_gain: {:?}, fine_amp_gain: {:?}, hyst_sel: {:?}, cap_sel_en: {=bool:?}, extal_cap_sel: {:?}, xtal_cap_sel: {:?}, mode_en: {:?}, supply_det: {:?} }}", + "Oscctla {{ osc_en: {=bool:?}, osc_byp_en: {=bool:?}, coarse_amp_gain: {:?}, fine_amp_gain: {:?}, hyst_sel: {=bool:?}, cap_sel_en: {=bool:?}, extal_cap_sel: {:?}, xtal_cap_sel: {:?}, mode_en: {:?}, supply_det: {:?} }}", self.osc_en(), self.osc_byp_en(), self.coarse_amp_gain(), @@ -1504,26 +1505,26 @@ impl Swictla { #[doc = "Switch Enable."] #[must_use] #[inline(always)] - pub const fn swi_en(&self) -> SwiEn { + pub const fn swi_en(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - SwiEn::from_bits(val as u8) + val != 0 } #[doc = "Switch Enable."] #[inline(always)] - pub const fn set_swi_en(&mut self, val: SwiEn) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_swi_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Low Power Enable."] #[must_use] #[inline(always)] - pub const fn lp_en(&self) -> LpEn { + pub const fn lp_en(&self) -> bool { let val = (self.0 >> 1usize) & 0x01; - LpEn::from_bits(val as u8) + val != 0 } #[doc = "Low Power Enable."] #[inline(always)] - pub const fn set_lp_en(&mut self, val: LpEn) { - self.0 = (self.0 & !(0x01 << 1usize)) | (((val.to_bits() as u32) & 0x01) << 1usize); + pub const fn set_lp_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); } } impl Default for Swictla { @@ -1545,7 +1546,7 @@ impl defmt::Format for Swictla { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Swictla {{ swi_en: {:?}, lp_en: {:?} }}", + "Swictla {{ swi_en: {=bool:?}, lp_en: {=bool:?} }}", self.swi_en(), self.lp_en() ) @@ -1559,14 +1560,14 @@ impl Swilcka { #[doc = "Lock."] #[must_use] #[inline(always)] - pub const fn lock(&self) -> SwilckaLock { + pub const fn lock(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - SwilckaLock::from_bits(val as u8) + val != 0 } #[doc = "Lock."] #[inline(always)] - pub const fn set_lock(&mut self, val: SwilckaLock) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } impl Default for Swilcka { @@ -1585,7 +1586,7 @@ impl core::fmt::Debug for Swilcka { #[cfg(feature = "defmt")] impl defmt::Format for Swilcka { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Swilcka {{ lock: {:?} }}", self.lock()) + defmt::write!(f, "Swilcka {{ lock: {=bool:?} }}", self.lock()) } } #[doc = "Version ID."] @@ -1700,14 +1701,14 @@ impl Wakena { #[doc = "POR Detect."] #[must_use] #[inline(always)] - pub const fn por_det(&self) -> WakenaPorDet { + pub const fn por_det(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - WakenaPorDet::from_bits(val as u8) + val != 0 } #[doc = "POR Detect."] #[inline(always)] - pub const fn set_por_det(&mut self, val: WakenaPorDet) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_por_det(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } #[doc = "Wake-up Pin Flag."] #[must_use] @@ -1724,50 +1725,50 @@ impl Wakena { #[doc = "Bandgap Timer 0."] #[must_use] #[inline(always)] - pub const fn timer0_flag(&self) -> WakenaTimer0Flag { + pub const fn timer0_flag(&self) -> bool { let val = (self.0 >> 2usize) & 0x01; - WakenaTimer0Flag::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timer 0."] #[inline(always)] - pub const fn set_timer0_flag(&mut self, val: WakenaTimer0Flag) { - self.0 = (self.0 & !(0x01 << 2usize)) | (((val.to_bits() as u32) & 0x01) << 2usize); + pub const fn set_timer0_flag(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); } #[doc = "Bandgap Timer 2."] #[must_use] #[inline(always)] - pub const fn timer1_flag(&self) -> WakenaTimer1Flag { + pub const fn timer1_flag(&self) -> bool { let val = (self.0 >> 3usize) & 0x01; - WakenaTimer1Flag::from_bits(val as u8) + val != 0 } #[doc = "Bandgap Timer 2."] #[inline(always)] - pub const fn set_timer1_flag(&mut self, val: WakenaTimer1Flag) { - self.0 = (self.0 & !(0x01 << 3usize)) | (((val.to_bits() as u32) & 0x01) << 3usize); + pub const fn set_timer1_flag(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); } #[doc = "LDO Ready."] #[must_use] #[inline(always)] - pub const fn ldo_rdy(&self) -> WakenaLdoRdy { + pub const fn ldo_rdy(&self) -> bool { let val = (self.0 >> 4usize) & 0x01; - WakenaLdoRdy::from_bits(val as u8) + val != 0 } #[doc = "LDO Ready."] #[inline(always)] - pub const fn set_ldo_rdy(&mut self, val: WakenaLdoRdy) { - self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize); + pub const fn set_ldo_rdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); } #[doc = "OSC32K Ready."] #[must_use] #[inline(always)] - pub const fn osc_rdy(&self) -> WakenaOscRdy { + pub const fn osc_rdy(&self) -> bool { let val = (self.0 >> 5usize) & 0x01; - WakenaOscRdy::from_bits(val as u8) + val != 0 } #[doc = "OSC32K Ready."] #[inline(always)] - pub const fn set_osc_rdy(&mut self, val: WakenaOscRdy) { - self.0 = (self.0 & !(0x01 << 5usize)) | (((val.to_bits() as u32) & 0x01) << 5usize); + pub const fn set_osc_rdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } } impl Default for Wakena { @@ -1793,7 +1794,7 @@ impl defmt::Format for Wakena { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Wakena {{ por_det: {:?}, wakeup_flag: {:?}, timer0_flag: {:?}, timer1_flag: {:?}, ldo_rdy: {:?}, osc_rdy: {:?} }}", + "Wakena {{ por_det: {=bool:?}, wakeup_flag: {:?}, timer0_flag: {=bool:?}, timer1_flag: {=bool:?}, ldo_rdy: {=bool:?}, osc_rdy: {=bool:?} }}", self.por_det(), self.wakeup_flag(), self.timer0_flag(), @@ -1846,14 +1847,14 @@ impl Waklcka { #[doc = "Lock."] #[must_use] #[inline(always)] - pub const fn lock(&self) -> WaklckaLock { + pub const fn lock(&self) -> bool { let val = (self.0 >> 0usize) & 0x01; - WaklckaLock::from_bits(val as u8) + val != 0 } #[doc = "Lock."] #[inline(always)] - pub const fn set_lock(&mut self, val: WaklckaLock) { - self.0 = (self.0 & !(0x01 << 0usize)) | (((val.to_bits() as u32) & 0x01) << 0usize); + pub const fn set_lock(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); } } impl Default for Waklcka { @@ -1872,7 +1873,7 @@ impl core::fmt::Debug for Waklcka { #[cfg(feature = "defmt")] impl defmt::Format for Waklcka { fn format(&self, f: defmt::Formatter) { - defmt::write!(f, "Waklcka {{ lock: {:?} }}", self.lock()) + defmt::write!(f, "Waklcka {{ lock: {=bool:?} }}", self.lock()) } } #[repr(u8)] @@ -1880,13 +1881,13 @@ impl defmt::Format for Waklcka { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CapTrim { #[doc = "Default (when CAP2_TRIM = 0 and CAP_TRIM\\[1:0\\] = 00 )."] - VAL0 = 0x0, + Val0 = 0x0, #[doc = "-1us (when CAP2_TRIM = 0 and CAP_TRIM\\[1:0\\] = 01)."] - VAL1 = 0x01, + Val1 = 0x01, #[doc = "-2us (when CAP2_TRIM = 0 and CAP_TRIM\\[1:0\\] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM\\[1:0\\] = 10)."] - VAL2 = 0x02, + Val2 = 0x02, #[doc = "-2.5us (when CAP2_TRIM = 0 and CAP_TRIM\\[1:0\\] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM\\[1:0\\] = 11)."] - VAL3 = 0x03, + Val3 = 0x03, } impl CapTrim { #[inline(always)] @@ -1915,12 +1916,12 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CmpTrim { #[doc = "760 mV."] - CMP_760 = 0x0, + Cmp760 = 0x0, #[doc = "770 mV."] - CMP_770 = 0x01, + Cmp770 = 0x01, _RESERVED_2 = 0x02, #[doc = "740 mV."] - CMP_740 = 0x03, + Cmp740 = 0x03, } impl CmpTrim { #[inline(always)] @@ -1949,13 +1950,13 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum CoarseAmpGain { #[doc = "ESR Range 0."] - GAIN05 = 0x0, + Gain05 = 0x0, #[doc = "ESR Range 1."] - GAIN10 = 0x01, + Gain10 = 0x01, #[doc = "ESR Range 2."] - GAIN18 = 0x02, + Gain18 = 0x02, #[doc = "ESR Range 3."] - GAIN33 = 0x03, + Gain33 = 0x03, } impl CoarseAmpGain { #[inline(always)] @@ -1984,26 +1985,26 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum DlyTrim { #[doc = "P current 9(nA) and N Current 6(nA)."] - DLY_9_6 = 0x0, + Dly96 = 0x0, #[doc = "P current 13(nA) and N Current 6(nA)."] - DLY_13_6 = 0x01, + Dly136 = 0x01, _RESERVED_2 = 0x02, #[doc = "P current 4(nA) and N Current 6(nA)."] - DLY_4_6 = 0x03, + Dly46 = 0x03, #[doc = "P current 9(nA) and N Current 4(nA)."] - DLY_9_4 = 0x04, + Dly94 = 0x04, #[doc = "P current 13(nA) and N Current 4(nA)."] - DLY_13_4 = 0x05, + Dly134 = 0x05, _RESERVED_6 = 0x06, #[doc = "P current 4(nA) and N Current 4(nA)."] - DLY_4_4 = 0x07, + Dly44 = 0x07, #[doc = "P current 9(nA) and N Current 2(nA)."] - DLY_9_2 = 0x08, + Dly92 = 0x08, #[doc = "P current 13(nA) and N Current 2(nA)."] - DLY_13_2 = 0x09, + Dly132 = 0x09, _RESERVED_a = 0x0a, #[doc = "P current 4(nA) and N Current 2(nA)."] - DLY_4_2 = 0x0b, + Dly42 = 0x0b, _RESERVED_c = 0x0c, _RESERVED_d = 0x0d, _RESERVED_e = 0x0e, @@ -2036,37 +2037,37 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ExtalCapSel { #[doc = "0 pF."] - SEL0 = 0x0, + Sel0 = 0x0, #[doc = "2 pF."] - SEL2 = 0x01, + Sel2 = 0x01, #[doc = "4 pF."] - SEL4 = 0x02, + Sel4 = 0x02, #[doc = "6 pF."] - SEL6 = 0x03, + Sel6 = 0x03, #[doc = "8 pF."] - SEL8 = 0x04, + Sel8 = 0x04, #[doc = "10 pF."] - SEL10 = 0x05, + Sel10 = 0x05, #[doc = "12 pF."] - SEL12 = 0x06, + Sel12 = 0x06, #[doc = "14 pF."] - SEL14 = 0x07, + Sel14 = 0x07, #[doc = "16 pF."] - SEL16 = 0x08, + Sel16 = 0x08, #[doc = "18 pF."] - SEL18 = 0x09, + Sel18 = 0x09, #[doc = "20 pF."] - SEL20 = 0x0a, + Sel20 = 0x0a, #[doc = "22 pF."] - SEL22 = 0x0b, + Sel22 = 0x0b, #[doc = "24 pF."] - SEL24 = 0x0c, + Sel24 = 0x0c, #[doc = "26 pF."] - SEL26 = 0x0d, + Sel26 = 0x0d, #[doc = "28 pF."] - SEL28 = 0x0e, + Sel28 = 0x0e, #[doc = "30 pF."] - SEL30 = 0x0f, + Sel30 = 0x0f, } impl ExtalCapSel { #[inline(always)] @@ -2095,7 +2096,7 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum FineAmpGain { #[doc = "200 mV."] - AGC200 = 0x0, + Agc200 = 0x0, _RESERVED_1 = 0x01, _RESERVED_2 = 0x02, _RESERVED_3 = 0x03, @@ -2125,54 +2126,23 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum HystSel { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl HystSel { - #[inline(always)] - pub const fn from_bits(val: u8) -> HystSel { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for HystSel { - #[inline(always)] - fn from(val: u8) -> HystSel { - HystSel::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: HystSel) -> u8 { - HystSel::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum InitTrim { #[doc = "8 s."] - SEL0 = 0x0, + Sel0 = 0x0, #[doc = "4 s."] - SEL1 = 0x01, + Sel1 = 0x01, #[doc = "2 s."] - SEL2 = 0x02, + Sel2 = 0x02, #[doc = "1 s."] - SEL3 = 0x03, + Sel3 = 0x03, #[doc = "0.5 s."] - SEL4 = 0x04, + Sel4 = 0x04, #[doc = "0.25 s."] - SEL5 = 0x05, + Sel5 = 0x05, #[doc = "0.125 s."] - SEL6 = 0x06, + Sel6 = 0x06, #[doc = "0.5 ms."] - SEL7 = 0x07, + Sel7 = 0x07, } impl InitTrim { #[inline(always)] @@ -2199,15 +2169,15 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaLdoRdy { +pub enum IrqenaWakeupFlag { #[doc = "Disable."] - DISABLE = 0x0, + Clr = 0x0, #[doc = "Enable."] - ENABLE = 0x01, + Set = 0x01, } -impl IrqenaLdoRdy { +impl IrqenaWakeupFlag { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaLdoRdy { + pub const fn from_bits(val: u8) -> IrqenaWakeupFlag { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2215,61 +2185,64 @@ impl IrqenaLdoRdy { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaLdoRdy { +impl From for IrqenaWakeupFlag { #[inline(always)] - fn from(val: u8) -> IrqenaLdoRdy { - IrqenaLdoRdy::from_bits(val) + fn from(val: u8) -> IrqenaWakeupFlag { + IrqenaWakeupFlag::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaLdoRdy) -> u8 { - IrqenaLdoRdy::to_bits(val) + fn from(val: IrqenaWakeupFlag) -> u8 { + IrqenaWakeupFlag::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaOscRdy { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum ModeEn { + #[doc = "Normal mode."] + Hp = 0x0, + #[doc = "Startup mode."] + Lp = 0x01, + _RESERVED_2 = 0x02, + #[doc = "Low power mode."] + Sw = 0x03, } -impl IrqenaOscRdy { +impl ModeEn { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaOscRdy { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> ModeEn { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaOscRdy { +impl From for ModeEn { #[inline(always)] - fn from(val: u8) -> IrqenaOscRdy { - IrqenaOscRdy::from_bits(val) + fn from(val: u8) -> ModeEn { + ModeEn::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaOscRdy) -> u8 { - IrqenaOscRdy::to_bits(val) + fn from(val: ModeEn) -> u8 { + ModeEn::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaPorDet { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum Out { + #[doc = "Logic zero (asserted)."] + On = 0x0, + #[doc = "Logic one."] + Off = 0x01, } -impl IrqenaPorDet { +impl Out { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaPorDet { + pub const fn from_bits(val: u8) -> Out { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2277,61 +2250,65 @@ impl IrqenaPorDet { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaPorDet { +impl From for Out { #[inline(always)] - fn from(val: u8) -> IrqenaPorDet { - IrqenaPorDet::from_bits(val) + fn from(val: u8) -> Out { + Out::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaPorDet) -> u8 { - IrqenaPorDet::to_bits(val) + fn from(val: Out) -> u8 { + Out::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaTimer0Flag { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum RefreshTrim { + #[doc = "Refresh every 7.8125 ms."] + Sel7 = 0x0, + #[doc = "Refresh every 15.625 ms."] + Sel15 = 0x01, + #[doc = "Refresh every 31.25 ms."] + Sel31 = 0x02, + #[doc = "Refresh every 62.5 ms."] + Sel62 = 0x03, } -impl IrqenaTimer0Flag { +impl RefreshTrim { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaTimer0Flag { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> RefreshTrim { + unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaTimer0Flag { +impl From for RefreshTrim { #[inline(always)] - fn from(val: u8) -> IrqenaTimer0Flag { - IrqenaTimer0Flag::from_bits(val) + fn from(val: u8) -> RefreshTrim { + RefreshTrim::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaTimer0Flag) -> u8 { - IrqenaTimer0Flag::to_bits(val) + fn from(val: RefreshTrim) -> u8 { + RefreshTrim::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaTimer1Flag { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum StatusaLdoRdy { + #[doc = "Disabled (not ready)."] + Clr = 0x0, + #[doc = "Enabled (ready)."] + Set = 0x01, } -impl IrqenaTimer1Flag { +impl StatusaLdoRdy { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaTimer1Flag { + pub const fn from_bits(val: u8) -> StatusaLdoRdy { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2339,30 +2316,30 @@ impl IrqenaTimer1Flag { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaTimer1Flag { +impl From for StatusaLdoRdy { #[inline(always)] - fn from(val: u8) -> IrqenaTimer1Flag { - IrqenaTimer1Flag::from_bits(val) + fn from(val: u8) -> StatusaLdoRdy { + StatusaLdoRdy::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaTimer1Flag) -> u8 { - IrqenaTimer1Flag::to_bits(val) + fn from(val: StatusaLdoRdy) -> u8 { + StatusaLdoRdy::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum IrqenaWakeupFlag { - #[doc = "Disable."] - CLR = 0x0, - #[doc = "Enable."] - SET = 0x01, +pub enum StatusaOscRdy { + #[doc = "Disabled (clock not ready)."] + Clr = 0x0, + #[doc = "Enabled (clock ready)."] + Set = 0x01, } -impl IrqenaWakeupFlag { +impl StatusaOscRdy { #[inline(always)] - pub const fn from_bits(val: u8) -> IrqenaWakeupFlag { + pub const fn from_bits(val: u8) -> StatusaOscRdy { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2370,30 +2347,30 @@ impl IrqenaWakeupFlag { unsafe { core::mem::transmute(self) } } } -impl From for IrqenaWakeupFlag { +impl From for StatusaOscRdy { #[inline(always)] - fn from(val: u8) -> IrqenaWakeupFlag { - IrqenaWakeupFlag::from_bits(val) + fn from(val: u8) -> StatusaOscRdy { + StatusaOscRdy::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: IrqenaWakeupFlag) -> u8 { - IrqenaWakeupFlag::to_bits(val) + fn from(val: StatusaOscRdy) -> u8 { + StatusaOscRdy::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Iso { - #[doc = "State follows the chip power modes."] - DISABLE = 0x0, - #[doc = "Isolates SRAM and places it in Low-Power Retention mode."] - ENABLE = 0x01, +pub enum StatusaPorDet { + #[doc = "Not reset."] + Clr = 0x0, + #[doc = "Reset."] + Set = 0x01, } -impl Iso { +impl StatusaPorDet { #[inline(always)] - pub const fn from_bits(val: u8) -> Iso { + pub const fn from_bits(val: u8) -> StatusaPorDet { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2401,30 +2378,30 @@ impl Iso { unsafe { core::mem::transmute(self) } } } -impl From for Iso { +impl From for StatusaPorDet { #[inline(always)] - fn from(val: u8) -> Iso { - Iso::from_bits(val) + fn from(val: u8) -> StatusaPorDet { + StatusaPorDet::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Iso) -> u8 { - Iso::to_bits(val) + fn from(val: StatusaPorDet) -> u8 { + StatusaPorDet::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ldotimer0Timen { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum StatusaTimer0Flag { + #[doc = "Not reached."] + Clr = 0x0, + #[doc = "Reached."] + Set = 0x01, } -impl Ldotimer0Timen { +impl StatusaTimer0Flag { #[inline(always)] - pub const fn from_bits(val: u8) -> Ldotimer0Timen { + pub const fn from_bits(val: u8) -> StatusaTimer0Flag { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2432,30 +2409,30 @@ impl Ldotimer0Timen { unsafe { core::mem::transmute(self) } } } -impl From for Ldotimer0Timen { +impl From for StatusaTimer0Flag { #[inline(always)] - fn from(val: u8) -> Ldotimer0Timen { - Ldotimer0Timen::from_bits(val) + fn from(val: u8) -> StatusaTimer0Flag { + StatusaTimer0Flag::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Ldotimer0Timen) -> u8 { - Ldotimer0Timen::to_bits(val) + fn from(val: StatusaTimer0Flag) -> u8 { + StatusaTimer0Flag::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ldotimer1Timen { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, +pub enum StatusaTimer1Flag { + #[doc = "Not reached."] + Clr = 0x0, + #[doc = "Reached."] + Set = 0x01, } -impl Ldotimer1Timen { +impl StatusaTimer1Flag { #[inline(always)] - pub const fn from_bits(val: u8) -> Ldotimer1Timen { + pub const fn from_bits(val: u8) -> StatusaTimer1Flag { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2463,30 +2440,30 @@ impl Ldotimer1Timen { unsafe { core::mem::transmute(self) } } } -impl From for Ldotimer1Timen { +impl From for StatusaTimer1Flag { #[inline(always)] - fn from(val: u8) -> Ldotimer1Timen { - Ldotimer1Timen::from_bits(val) + fn from(val: u8) -> StatusaTimer1Flag { + StatusaTimer1Flag::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: Ldotimer1Timen) -> u8 { - Ldotimer1Timen::to_bits(val) + fn from(val: StatusaTimer1Flag) -> u8 { + StatusaTimer1Flag::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum LpEn { - #[doc = "VDD_BAT always supplies VBAT modules in low-power modes."] - DISABLE = 0x0, - #[doc = "VDD_SYS always supplies VBAT modules if SWI_EN is also 1."] - ENABLE = 0x01, +pub enum StatusaWakeupFlag { + #[doc = "Not asserted."] + Clr = 0x0, + #[doc = "Asserted."] + Set = 0x01, } -impl LpEn { +impl StatusaWakeupFlag { #[inline(always)] - pub const fn from_bits(val: u8) -> LpEn { + pub const fn from_bits(val: u8) -> StatusaWakeupFlag { unsafe { core::mem::transmute(val & 0x01) } } #[inline(always)] @@ -2494,33 +2471,32 @@ impl LpEn { unsafe { core::mem::transmute(self) } } } -impl From for LpEn { +impl From for StatusaWakeupFlag { #[inline(always)] - fn from(val: u8) -> LpEn { - LpEn::from_bits(val) + fn from(val: u8) -> StatusaWakeupFlag { + StatusaWakeupFlag::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: LpEn) -> u8 { - LpEn::to_bits(val) + fn from(val: StatusaWakeupFlag) -> u8 { + StatusaWakeupFlag::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum ModeEn { - #[doc = "Normal mode."] - HP = 0x0, - #[doc = "Startup mode."] - LP = 0x01, +pub enum SupplyDet { + #[doc = "VBAT supply is less than 3V."] + L3vsupply = 0x0, + #[doc = "VBAT supply is greater than 3V."] + G3vsupply = 0x01, _RESERVED_2 = 0x02, - #[doc = "Low power mode."] - SW = 0x03, + _RESERVED_3 = 0x03, } -impl ModeEn { +impl SupplyDet { #[inline(always)] - pub const fn from_bits(val: u8) -> ModeEn { + pub const fn from_bits(val: u8) -> SupplyDet { unsafe { core::mem::transmute(val & 0x03) } } #[inline(always)] @@ -2528,583 +2504,50 @@ impl ModeEn { unsafe { core::mem::transmute(self) } } } -impl From for ModeEn { +impl From for SupplyDet { #[inline(always)] - fn from(val: u8) -> ModeEn { - ModeEn::from_bits(val) + fn from(val: u8) -> SupplyDet { + SupplyDet::from_bits(val) } } -impl From for u8 { +impl From for u8 { #[inline(always)] - fn from(val: ModeEn) -> u8 { - ModeEn::to_bits(val) + fn from(val: SupplyDet) -> u8 { + SupplyDet::to_bits(val) } } #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum OscBypEn { - #[doc = "Does not bypass."] - DISABLE = 0x0, - #[doc = "Bypass."] - ENABLE = 0x01, +pub enum Timcfg { + #[doc = "1 s."] + Cfg1000 = 0x0, + #[doc = "500 ms."] + Cfg500 = 0x01, + #[doc = "250 ms."] + Cfg250 = 0x02, + #[doc = "125 ms."] + Cfg125 = 0x03, + #[doc = "62.5 ms."] + Cfg62 = 0x04, + #[doc = "31.25 ms."] + Cfg31 = 0x05, + #[doc = "15.625 ms."] + Cfg15 = 0x06, + #[doc = "7.8125 ms."] + Cfg7 = 0x07, } -impl OscBypEn { +impl Timcfg { #[inline(always)] - pub const fn from_bits(val: u8) -> OscBypEn { - unsafe { core::mem::transmute(val & 0x01) } + pub const fn from_bits(val: u8) -> Timcfg { + unsafe { core::mem::transmute(val & 0x07) } } #[inline(always)] pub const fn to_bits(self) -> u8 { unsafe { core::mem::transmute(self) } } } -impl From for OscBypEn { - #[inline(always)] - fn from(val: u8) -> OscBypEn { - OscBypEn::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: OscBypEn) -> u8 { - OscBypEn::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Out { - #[doc = "Logic zero (asserted)."] - ON = 0x0, - #[doc = "Logic one."] - OFF = 0x01, -} -impl Out { - #[inline(always)] - pub const fn from_bits(val: u8) -> Out { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Out { - #[inline(always)] - fn from(val: u8) -> Out { - Out::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Out) -> u8 { - Out::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum RefreshTrim { - #[doc = "Refresh every 7.8125 ms."] - SEL7 = 0x0, - #[doc = "Refresh every 15.625 ms."] - SEL15 = 0x01, - #[doc = "Refresh every 31.25 ms."] - SEL31 = 0x02, - #[doc = "Refresh every 62.5 ms."] - SEL62 = 0x03, -} -impl RefreshTrim { - #[inline(always)] - pub const fn from_bits(val: u8) -> RefreshTrim { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for RefreshTrim { - #[inline(always)] - fn from(val: u8) -> RefreshTrim { - RefreshTrim::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: RefreshTrim) -> u8 { - RefreshTrim::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ret0 { - #[doc = "Corresponding SRAM array is retained in low-power modes."] - DISABLE = 0x0, - #[doc = "Corresponding SRAM array is not retained in low-power modes."] - ENABLE = 0x01, -} -impl Ret0 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ret0 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ret0 { - #[inline(always)] - fn from(val: u8) -> Ret0 { - Ret0::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ret0) -> u8 { - Ret0::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ret1 { - #[doc = "Corresponding SRAM array is retained in low-power modes."] - DISABLE = 0x0, - #[doc = "Corresponding SRAM array is not retained in low-power modes."] - ENABLE = 0x01, -} -impl Ret1 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ret1 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ret1 { - #[inline(always)] - fn from(val: u8) -> Ret1 { - Ret1::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ret1) -> u8 { - Ret1::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ret2 { - #[doc = "Corresponding SRAM array is retained in low-power modes."] - DISABLE = 0x0, - #[doc = "Corresponding SRAM array is not retained in low-power modes."] - ENABLE = 0x01, -} -impl Ret2 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ret2 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ret2 { - #[inline(always)] - fn from(val: u8) -> Ret2 { - Ret2::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ret2) -> u8 { - Ret2::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Ret3 { - #[doc = "Corresponding SRAM array is retained in low-power modes."] - DISABLE = 0x0, - #[doc = "Corresponding SRAM array is not retained in low-power modes."] - ENABLE = 0x01, -} -impl Ret3 { - #[inline(always)] - pub const fn from_bits(val: u8) -> Ret3 { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Ret3 { - #[inline(always)] - fn from(val: u8) -> Ret3 { - Ret3::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Ret3) -> u8 { - Ret3::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaLdoRdy { - #[doc = "Disabled (not ready)."] - CLR = 0x0, - #[doc = "Enabled (ready)."] - SET = 0x01, -} -impl StatusaLdoRdy { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaLdoRdy { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaLdoRdy { - #[inline(always)] - fn from(val: u8) -> StatusaLdoRdy { - StatusaLdoRdy::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaLdoRdy) -> u8 { - StatusaLdoRdy::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaOscRdy { - #[doc = "Disabled (clock not ready)."] - CLR = 0x0, - #[doc = "Enabled (clock ready)."] - SET = 0x01, -} -impl StatusaOscRdy { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaOscRdy { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaOscRdy { - #[inline(always)] - fn from(val: u8) -> StatusaOscRdy { - StatusaOscRdy::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaOscRdy) -> u8 { - StatusaOscRdy::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaPorDet { - #[doc = "Not reset."] - CLR = 0x0, - #[doc = "Reset."] - SET = 0x01, -} -impl StatusaPorDet { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaPorDet { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaPorDet { - #[inline(always)] - fn from(val: u8) -> StatusaPorDet { - StatusaPorDet::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaPorDet) -> u8 { - StatusaPorDet::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaTimer0Flag { - #[doc = "Not reached."] - CLR = 0x0, - #[doc = "Reached."] - SET = 0x01, -} -impl StatusaTimer0Flag { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaTimer0Flag { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaTimer0Flag { - #[inline(always)] - fn from(val: u8) -> StatusaTimer0Flag { - StatusaTimer0Flag::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaTimer0Flag) -> u8 { - StatusaTimer0Flag::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaTimer1Flag { - #[doc = "Not reached."] - CLR = 0x0, - #[doc = "Reached."] - SET = 0x01, -} -impl StatusaTimer1Flag { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaTimer1Flag { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaTimer1Flag { - #[inline(always)] - fn from(val: u8) -> StatusaTimer1Flag { - StatusaTimer1Flag::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaTimer1Flag) -> u8 { - StatusaTimer1Flag::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum StatusaWakeupFlag { - #[doc = "Not asserted."] - CLR = 0x0, - #[doc = "Asserted."] - SET = 0x01, -} -impl StatusaWakeupFlag { - #[inline(always)] - pub const fn from_bits(val: u8) -> StatusaWakeupFlag { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for StatusaWakeupFlag { - #[inline(always)] - fn from(val: u8) -> StatusaWakeupFlag { - StatusaWakeupFlag::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: StatusaWakeupFlag) -> u8 { - StatusaWakeupFlag::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum SupplyDet { - #[doc = "VBAT supply is less than 3V."] - L3VSUPPLY = 0x0, - #[doc = "VBAT supply is greater than 3V."] - G3VSUPPLY = 0x01, - _RESERVED_2 = 0x02, - _RESERVED_3 = 0x03, -} -impl SupplyDet { - #[inline(always)] - pub const fn from_bits(val: u8) -> SupplyDet { - unsafe { core::mem::transmute(val & 0x03) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SupplyDet { - #[inline(always)] - fn from(val: u8) -> SupplyDet { - SupplyDet::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SupplyDet) -> u8 { - SupplyDet::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Swi { - #[doc = "Supply follows the chip power modes."] - DISABLE = 0x0, - #[doc = "LDO_RAM powers the array."] - ENABLE = 0x01, -} -impl Swi { - #[inline(always)] - pub const fn from_bits(val: u8) -> Swi { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Swi { - #[inline(always)] - fn from(val: u8) -> Swi { - Swi::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: Swi) -> u8 { - Swi::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum SwiEn { - #[doc = "VDD_BAT."] - DISABLE = 0x0, - #[doc = "VDD_SYS."] - ENABLE = 0x01, -} -impl SwiEn { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwiEn { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwiEn { - #[inline(always)] - fn from(val: u8) -> SwiEn { - SwiEn::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwiEn) -> u8 { - SwiEn::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum SwilckaLock { - #[doc = "Do not block."] - DISABLE = 0x0, - #[doc = "Block."] - ENABLE = 0x01, -} -impl SwilckaLock { - #[inline(always)] - pub const fn from_bits(val: u8) -> SwilckaLock { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for SwilckaLock { - #[inline(always)] - fn from(val: u8) -> SwilckaLock { - SwilckaLock::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: SwilckaLock) -> u8 { - SwilckaLock::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum Timcfg { - #[doc = "1 s."] - CFG1000 = 0x0, - #[doc = "500 ms."] - CFG500 = 0x01, - #[doc = "250 ms."] - CFG250 = 0x02, - #[doc = "125 ms."] - CFG125 = 0x03, - #[doc = "62.5 ms."] - CFG62 = 0x04, - #[doc = "31.25 ms."] - CFG31 = 0x05, - #[doc = "15.625 ms."] - CFG15 = 0x06, - #[doc = "7.8125 ms."] - CFG7 = 0x07, -} -impl Timcfg { - #[inline(always)] - pub const fn from_bits(val: u8) -> Timcfg { - unsafe { core::mem::transmute(val & 0x07) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for Timcfg { +impl From for Timcfg { #[inline(always)] fn from(val: u8) -> Timcfg { Timcfg::from_bits(val) @@ -3119,166 +2562,11 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakenaLdoRdy { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl WakenaLdoRdy { - #[inline(always)] - pub const fn from_bits(val: u8) -> WakenaLdoRdy { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WakenaLdoRdy { - #[inline(always)] - fn from(val: u8) -> WakenaLdoRdy { - WakenaLdoRdy::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WakenaLdoRdy) -> u8 { - WakenaLdoRdy::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakenaOscRdy { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl WakenaOscRdy { - #[inline(always)] - pub const fn from_bits(val: u8) -> WakenaOscRdy { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WakenaOscRdy { - #[inline(always)] - fn from(val: u8) -> WakenaOscRdy { - WakenaOscRdy::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WakenaOscRdy) -> u8 { - WakenaOscRdy::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakenaPorDet { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl WakenaPorDet { - #[inline(always)] - pub const fn from_bits(val: u8) -> WakenaPorDet { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WakenaPorDet { - #[inline(always)] - fn from(val: u8) -> WakenaPorDet { - WakenaPorDet::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WakenaPorDet) -> u8 { - WakenaPorDet::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakenaTimer0Flag { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl WakenaTimer0Flag { - #[inline(always)] - pub const fn from_bits(val: u8) -> WakenaTimer0Flag { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WakenaTimer0Flag { - #[inline(always)] - fn from(val: u8) -> WakenaTimer0Flag { - WakenaTimer0Flag::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WakenaTimer0Flag) -> u8 { - WakenaTimer0Flag::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WakenaTimer1Flag { - #[doc = "Disable."] - DISABLE = 0x0, - #[doc = "Enable."] - ENABLE = 0x01, -} -impl WakenaTimer1Flag { - #[inline(always)] - pub const fn from_bits(val: u8) -> WakenaTimer1Flag { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WakenaTimer1Flag { - #[inline(always)] - fn from(val: u8) -> WakenaTimer1Flag { - WakenaTimer1Flag::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WakenaTimer1Flag) -> u8 { - WakenaTimer1Flag::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum WakenaWakeupFlag { #[doc = "Disable."] - CLR = 0x0, + Clr = 0x0, #[doc = "Enable."] - SET = 0x01, + Set = 0x01, } impl WakenaWakeupFlag { #[inline(always)] @@ -3305,70 +2593,39 @@ impl From for u8 { #[repr(u8)] #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum WaklckaLock { - #[doc = "Lock is disabled."] - DISABLE = 0x0, - #[doc = "Lock is enabled."] - ENABLE = 0x01, -} -impl WaklckaLock { - #[inline(always)] - pub const fn from_bits(val: u8) -> WaklckaLock { - unsafe { core::mem::transmute(val & 0x01) } - } - #[inline(always)] - pub const fn to_bits(self) -> u8 { - unsafe { core::mem::transmute(self) } - } -} -impl From for WaklckaLock { - #[inline(always)] - fn from(val: u8) -> WaklckaLock { - WaklckaLock::from_bits(val) - } -} -impl From for u8 { - #[inline(always)] - fn from(val: WaklckaLock) -> u8 { - WaklckaLock::to_bits(val) - } -} -#[repr(u8)] -#[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum XtalCapSel { #[doc = "0 pF."] - SEL0 = 0x0, + Sel0 = 0x0, #[doc = "2 pF."] - SEL2 = 0x01, + Sel2 = 0x01, #[doc = "4 pF."] - SEL4 = 0x02, + Sel4 = 0x02, #[doc = "6 pF."] - SEL6 = 0x03, + Sel6 = 0x03, #[doc = "8 pF."] - SEL8 = 0x04, + Sel8 = 0x04, #[doc = "10 pF."] - SEL10 = 0x05, + Sel10 = 0x05, #[doc = "12 pF."] - SEL12 = 0x06, + Sel12 = 0x06, #[doc = "14 pF."] - SEL14 = 0x07, + Sel14 = 0x07, #[doc = "16 pF."] - SEL16 = 0x08, + Sel16 = 0x08, #[doc = "18 pF."] - SEL18 = 0x09, + Sel18 = 0x09, #[doc = "20 pF."] - SEL20 = 0x0a, + Sel20 = 0x0a, #[doc = "22 pF."] - SEL22 = 0x0b, + Sel22 = 0x0b, #[doc = "24 pF."] - SEL24 = 0x0c, + Sel24 = 0x0c, #[doc = "26 pF."] - SEL26 = 0x0d, + Sel26 = 0x0d, #[doc = "28 pF."] - SEL28 = 0x0e, + Sel28 = 0x0e, #[doc = "30 pF."] - SEL30 = 0x0f, + Sel30 = 0x0f, } impl XtalCapSel { #[inline(always)] diff --git a/nxp-pac/src/meta_peripherals/mcxa/WWDT.rs b/nxp-pac/src/meta_peripherals/mcxa/WWDT.rs index a53d50e..1cee50e 100644 --- a/nxp-pac/src/meta_peripherals/mcxa/WWDT.rs +++ b/nxp-pac/src/meta_peripherals/mcxa/WWDT.rs @@ -1,6 +1,7 @@ #![allow(non_camel_case_types)] #![allow(non_snake_case)] -#![doc = "Peripheral access API (generated using chiptool v0.1.0 (2fd28c5 2026-04-02))"] +#![allow(non_upper_case_globals)] +#![doc = "Peripheral access API (generated using chiptool v0.1.0 (859f02b 2026-04-15))"] #[doc = "Windowed Watchdog Timer."] #[derive(Copy, Clone, Eq, PartialEq)] pub struct Wwdt { @@ -160,6 +161,18 @@ impl Mod { pub const fn set_lock(&mut self, val: bool) { self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); } + #[doc = "Debug Enable."] + #[must_use] + #[inline(always)] + pub const fn debug_en(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Debug Enable."] + #[inline(always)] + pub const fn set_debug_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } } impl Default for Mod { #[inline(always)] @@ -176,6 +189,7 @@ impl core::fmt::Debug for Mod { .field("wdint", &self.wdint()) .field("wdprotect", &self.wdprotect()) .field("lock", &self.lock()) + .field("debug_en", &self.debug_en()) .finish() } } @@ -184,13 +198,14 @@ impl defmt::Format for Mod { fn format(&self, f: defmt::Formatter) { defmt::write!( f, - "Mod {{ wden: {:?}, wdreset: {:?}, wdtof: {=bool:?}, wdint: {=bool:?}, wdprotect: {:?}, lock: {=bool:?} }}", + "Mod {{ wden: {:?}, wdreset: {:?}, wdtof: {=bool:?}, wdint: {=bool:?}, wdprotect: {:?}, lock: {=bool:?}, debug_en: {=bool:?} }}", self.wden(), self.wdreset(), self.wdtof(), self.wdint(), self.wdprotect(), - self.lock() + self.lock(), + self.debug_en() ) } } @@ -343,9 +358,9 @@ impl defmt::Format for Window { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Wden { #[doc = "Timer stopped."] - STOP = 0x0, + Stop = 0x0, #[doc = "Timer running."] - RUN = 0x01, + Run = 0x01, } impl Wden { #[inline(always)] @@ -374,9 +389,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Wdprotect { #[doc = "Flexible."] - FLEXIBLE = 0x0, + Flexible = 0x0, #[doc = "Threshold."] - THRESHOLD = 0x01, + Threshold = 0x01, } impl Wdprotect { #[inline(always)] @@ -405,9 +420,9 @@ impl From for u8 { #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Wdreset { #[doc = "Interrupt."] - INTERRUPT = 0x0, + Interrupt = 0x0, #[doc = "Reset."] - RESET = 0x01, + Reset = 0x01, } impl Wdreset { #[inline(always)]