[PW_SID:1095073] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support

Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml

@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 Pin Controller
+maintainers:
+  - Jia Wang <wangjia@ultrarisc.com>
+
+description: |
+  UltraRISC RISC-V SoC DP1000 pin controller.
+
+  The binding supports two child node styles under the same controller
+  compatible:
+
+  - legacy DP1000-specific nodes using phandle-array properties
+    `pinctrl-pins` and `pinconf-pins`
+  - generic pinctrl nodes using `pins`, `function` and generic pin
+    configuration properties
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pinctrl
+
+  reg:
+    maxItems: 1
+
+  "#pinctrl-cells":
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+  '.*-pins$':
+    type: object
+    allOf:
+      - $ref: /schemas/pinctrl/pincfg-node.yaml#
+      - $ref: /schemas/pinctrl/pinmux-node.yaml#
+    additionalProperties: false
+    properties:
+      pinctrl-pins:
+        description: |
+          The list of pins and their mux settings that properties in the node
+          apply to. The format: `PORT  PIN  FUNCTION`.
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        minItems: 1
+        maxItems: 32
+      pinconf-pins:
+        description: |
+          The list of pins and their pad configuration that properties in the
+          node apply to. The format: `PORT  PIN  CONF`.
+          CONF is a DP1000-specific encoding of pull and drive strength as
+          defined in dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h.
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        minItems: 1
+        maxItems: 32
+      pins:
+        description: List of pins affected by this state node.
+        minItems: 1
+        uniqueItems: true
+        items:
+          type: string
+          pattern: '^(PA([0-9]|1[0-5])|P[BCD][0-7]|LPC([0-9]|1[0-2]))$'
+
+      function:
+        description: |
+          Mux function to select for the listed pins.
+          gpio maps to the hardware default mode. The default mode is
+          GPIO for PA/PB/PC/PD pins and LPC for LPC pins.
+          func1 is not supported on LPC pins.
+        enum:
+          - gpio
+          - func0
+          - func1
+
+      bias-disable: true
+      bias-high-impedance: true
+      bias-pull-up: true
+      bias-pull-down: true
+
+      drive-strength:
+        description: Output drive strength in mA.
+        enum: [20, 27, 33, 40]
+
+    oneOf:
+      - allOf:
+          - anyOf:
+              - required: [pinctrl-pins]
+              - required: [pinconf-pins]
+          - not:
+              required: [pins]
+      - allOf:
+          - required: [pins]
+          - not:
+              anyOf:
+                - required: [pinctrl-pins]
+                - required: [pinconf-pins]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pinmux@11081000 {
+        compatible = "ultrarisc,dp1000-pinctrl";
+        reg = <0x0 0x11081000  0x0 0x1000>;
+        #pinctrl-cells = <2>;
+
+        i2c0-pins {
+          pins = "PA12", "PA13";
+          function = "func0";
+          bias-pull-up;
+          drive-strength = <33>;
+        };
+
+        uart0-pins {
+          pins = "PA8", "PA9";
+          function = "func1";
+          bias-pull-up;
+          drive-strength = <33>;
+        };
+      };
+    };
+
+  - |
+    /* Legacy example */
+    #include <dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pinmux@11081000 {
+        compatible = "ultrarisc,dp1000-pinctrl";
+        reg = <0x0 0x11081000  0x0 0x1000>;
+        #pinctrl-cells = <2>;
+
+        i2c0-pins {
+          pinctrl-pins = <
+            UR_DP1000_IOMUX_A  12  UR_DP1000_FUNC0
+            UR_DP1000_IOMUX_A  13  UR_DP1000_FUNC0
+          >;
+
+          pinconf-pins = <
+            UR_DP1000_IOMUX_A  12  UR_DP1000_BIAS(UR_DP1000_PULL_UP,
+                                                  UR_DP1000_DRIVE_DEF)
+            UR_DP1000_IOMUX_A  13  UR_DP1000_BIAS(UR_DP1000_PULL_UP,
+                                                  UR_DP1000_DRIVE_DEF)
+          >;
+        };
+
+        uart0-pins {
+          pinctrl-pins = <
+            UR_DP1000_IOMUX_A  8  UR_DP1000_FUNC1
+            UR_DP1000_IOMUX_A  9  UR_DP1000_FUNC1
+          >;
+
+          pinconf-pins = <
+            UR_DP1000_IOMUX_A  8   UR_DP1000_BIAS(UR_DP1000_PULL_UP,
+                                                  UR_DP1000_DRIVE_DEF)
+            UR_DP1000_IOMUX_A  9   UR_DP1000_BIAS(UR_DP1000_PULL_UP,
+                                                  UR_DP1000_DRIVE_DEF)
+          >;
+        };
+      };
+    };

Documentation/devicetree/bindings/riscv/cpus.yaml

@@ -67,6 +67,7 @@ properties:
               - thead,c908
               - thead,c910
               - thead,c920
+              - ultrarisc,cp100
           - const: riscv
       - items:
           - enum:

Documentation/devicetree/bindings/riscv/ultrarisc.yaml

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/ultrarisc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC SoC-based boards
+
+maintainers:
+  - Jia Wang <wangjia@ultrarisc.com>
+
+description:
+  UltraRISC DP1000 SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - rongda,m0
+              - milkv,titan
+          - const: ultrarisc,dp1000
+
+additionalProperties: true
+...

Documentation/devicetree/bindings/vendor-prefixes.yaml

@@ -1407,6 +1407,8 @@ patternProperties:
     description: Rockchip Electronics Co., Ltd.
   "^rocktech,.*":
     description: ROCKTECH DISPLAYS LIMITED
+  "^rongda,.*":
+    description: Shenzhen Rongda Computer Co., Ltd.
   "^rohm,.*":
     description: ROHM Semiconductor Co., Ltd
   "^ronbo,.*":

MAINTAINERS

@@ -23044,6 +23044,13 @@ F:	include/dt-bindings/power/thead,th1520-power.h
 F:	include/dt-bindings/reset/thead,th1520-reset.h
 F:	include/linux/firmware/thead/thead,th1520-aon.h
 
+RISC-V ULTRARISC SoC SUPPORT
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/ultrarisc.yaml
+F:	arch/riscv/boot/dts/ultrarisc/
+
 RNBD BLOCK DRIVERS
 M:	Md. Haris Iqbal <haris.iqbal@ionos.com>
 M:	Jack Wang <jinpu.wang@ionos.com>
@@ -27312,6 +27319,14 @@ S:	Maintained
 F:	drivers/usb/common/ulpi.c
 F:	include/linux/ulpi/
 
+ULTRARISC DP1000 PINCTRL DRIVER
+M:	Jia Wang <wangjia@ultrarisc.com>
+L:	linux-gpio@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml
+F:	drivers/pinctrl/ultrarisc/*
+F:	include/dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h
+
 ULTRATRONIK BOARD SUPPORT
 M:	Goran Rađenović <goran.radni@gmail.com>
 M:	Börge Strümpfel <boerge.struempfel@gmail.com>

arch/riscv/boot/dts/Makefile

@@ -12,3 +12,4 @@ subdir-y += spacemit
 subdir-y += starfive
 subdir-y += tenstorrent
 subdir-y += thead
+subdir-y += ultrarisc

arch/riscv/boot/dts/ultrarisc/Makefile

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-milkv-titan.dtb
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb

arch/riscv/boot/dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi

@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000.dtsi"
+
+&pmx0 {
+	i2c0_pins: i2c0-pins {
+		pins = "PA12", "PA13";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c1_pins: i2c1-pins {
+		pins = "PB6", "PB7";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c2_pins: i2c2-pins {
+		pins = "PC0", "PC1";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	i2c3_pins: i2c3-pins {
+		pins = "PC2", "PC3";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	io_pins: io-pins {
+		pins = "PA10", "PA15", "PB0", "PB1", "PB2", "PD6", "PD7";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	gpio_keys_pins: gpio-keys-pins {
+		pins = "PA4", "PA11", "PA14";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	mux_dcdc_pins: mux-dcdc-pins {
+		pins = "PA5";
+		function = "gpio";
+	};
+
+	mux_i2c3_pins: mux-i2c3-pins {
+		pins = "PA6";
+		function = "gpio";
+	};
+
+	mux_uart0_pins: mux-uart0-pins {
+		pins = "PA7";
+		function = "gpio";
+	};
+
+	spi0_pins: spi0-pins {
+		pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
+		function = "func1";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	spi1_pins: spi1-pins {
+		pins = "PA0", "PA1", "PA2", "PA3";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart0_pins: uart0-pins {
+		pins = "PA8", "PA9";
+		function = "func1";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart1_pins: uart1-pins {
+		pins = "PB4", "PB5";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart2_pins: uart2-pins {
+		pins = "PC4", "PC5";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+
+	uart3_pins: uart3-pins {
+		pins = "PC6", "PC7";
+		function = "func0";
+		bias-pull-up;
+		drive-strength = <33>;
+	};
+};