Linux Buildroot Errors/Warnings

[PietDelaney]

I still don't have Wally Booting after it jumps into OpenSBI mechanism.

I tried building Linux with just "Make' and wonder why there are so many warnings
When I maintained linux, BuoldRoot and BusyBox for Tensilica's Xtensa FPGA builds
I don't recall allowing any weird stuff in the build process.

Example:
cpio -id -D buildroot/output/images/disassembly/rootfs -F buildroot/output/images/rootfs.cpio
cpio: dev/console: Cannot mknod: Operation not permitted
cpio: buildroot/output/images/disassembly/rootfs: Cannot change mode to rwxrwxr-x: No such file or directory
143364 blocks
make: [Makefile:95: buildroot/output/images/disassembly/rootfs] Error 2 (ignored)_

[rosethompson]

Hi Piet. I would really like to resolve your issues with the Wally's FPGA boot. I have more available time now. If we cannot resolve this over text, I can meet over video chat.

After you built using just 'Make' what command did you use to flash the sd card?

I get the same cpio error, but I successfully boot into Linux. The cpio error will have to a separate investigation.

Here are the exact commands I'm running to boot the Arty A7. I ran on the latest version of the repo. Can you confirm any differences?

cd cvw
source ./setup.sh
cd linux
make
cd sdcard
./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-artya7.dtb /dev/sda
cd ../../fpga/generator

Plug in the Arty A7.
In another terminal. The specific ttyUSB may be different.
screen /dev/ttyUSB1 115200
On the first terminal
vivado &
Open the project
Open Hardware Manger
Open Target
Auto Connect
Program Device
xc7a100t_0
Program

[PietDelaney]

I think I;m using the same proceedure as you just mentioned.
One difference is I didn't use my alias to burn the sdcard from the sdcard directory.
All of the aruments to the sdcard command are provided with complete paths.

I used this alias with and without the -z option:

  # alias Flash_sd="$WALLY/linux/sdcard/flash-sd.sh -z -d wally-artya7.dtb -b $RISCV/buildroot /dev/sda"
  alias   Flash_sd="$WALLY/linux/sdcard/flash-sd.sh    -d $RISCV/buildroot/output/images/wally-artya7.dtb -b $RISCV/buildroot /dev/sda"

i do the setup.sh in my bashrc:

if [ -f /src/piet/cvw/cvw/setup.sh ]; then
source /src/piet/cvw/cvw/setup.sh
printenv
fi

The only difference I see is my not being the sdcard directory when i use the flash-sd.sh script.

why can't we enable debug in the OpenSBI code? At Tensilica we didn't use OpenSBI.
So far I don't see the need for it.

-PIET

[rosethompson]

I can't see why any of that would cause an issue. We can certainly enable OpenSBI debug mode. Since you didn't use OpenSBI at Tensilica, what did you use for the firmware?

One thing which will probably be useful to add is the in-circuit logic analyzer (ILA) debugger with probes in the UART device so we can see the characters transmitted to the serial console in the hardware. There is already a debugger script, but we'll need a to add a few signals to it, fpga/constraints/small-debug-uart.xdc. You'll need to change fpga/generator/wally.tcl line 101 to source this file.
Then move fpga/constraints/marked_debug_uart.txt to fpga/constraints/marked_debug.txt.

I'll update the xdc and marked_debug file. You'll need to resynthesize the fpga after to have these in the ILA.

Rose

[PietDelaney]

Ill try your suggestions this evening and try again...

At Tensilica I liked debugging with JTAG. One way to boot was to install the linux kernel with jtag and boot
the root filesystem made by Buildroot. Im interested in adding JTAG support to Wally.

I think one approach was installing Buildroot into the Flash memory, booting UBoot and fetching the Linux kernel
via TFTP. As I recall it was convenient to run the Linux kernel and use NFS. It's been a long time since I did this.
Here's a web page on a my support for a Transwitch FPGA that I worked on:

https://wiki.linux-xtensa.org/index.php?title=Transwitch_A2000_Development_Board

https://wiki.linux-xtensa.org/index.php?title=Linux_Kernel

https://wiki.linux-xtensa.org/index.php?title=Boot_Loader

A lot of my work was on a Xilinx ML605 FPGA board and my debugging Linux to support multi-processing, SMP support.
The ML605 boards are only about $100 on Ebay but the software isn't provided a cheap enought price (Yet?) to use them.
Would be great to get Wally up to this state of debugging with JTAG a SMP linux system on FPGA boards.

Here was the wiki describing installing a Xtensa ISA with HIFI extensions. The HIFI extensions supported saturated math processing, that minimizes clicks on numbers getting to large and overflowing to huge negitive numbers. The kernel booted
quicker than Wally. SMP would be an interesting addition to WALLY as well as JTAG. I got tensilicas JTAG to be 100x faster by using a ASYNC hack, a bit like OpenOCD but with much better tracing.

https://wiki.linux-xtensa.org/index.php?title=SMP_HiFi_2_Development_Board

It was a lot of fun. It would be nice to see Wally like this, Tensilica work.
As I recall, Buildroot, Linux Kernel, and Busybox were all building without errors. So it was easy for users to get it working. I don't recall the Transwitch customer being as enthusiastic as I was when I was helping them with the A2000 development.

Sigh

-piet

-piet

[PietDelaney]

Wondering what you meant by "I'll update the xdc and marked_debug file".

What is the XDC?

[PietDelaney]

I looked over your debug changes. Maybe a git branch with these changes and an example of before and after screen
so I know what to expect. You said some new signals need to be added to fpga/constraints/small-debug-uart.xdc

I've used git branches for experimentation. I don't see any precedent in your git branches for debug hacks.

[PietDelaney]

Rose: I could pull from your Git repo on github and use a debug branch with your uart changes for debugging.

https://github.com/rosethompson/cvw

Curious why debugging OpenSBI requires changes like this. I pulled a copy of OpenSBI and took a look.
It has a DEBUG=1 option but it seems to be mostly just enabling gdb debugging or core file analysis.
Doubt that helps without JTAG.

The device tree was started after the 2.69 kernel I worked on at Tensilica .

Buildroot just had to put it in memory and it was a stand alone program; debuggable with gdb.

I use to use jtag and gdb on the buildroot code and then switch objects just as buildroot was jumping to the linux kernel.
So I never lost control.

-piet

[rosethompson]

Wally does not implement the RISC-V debug (D) extension yet. This is how we would extract data through JTAG. A about a year ago a grad student was working on the D extension but he graduated and the work was unfinished. Dr. James Stine is hoping to continue this with another student this summer.

Presently we use the ILA (in-circuit logic analyzer) to debug FPGA issues. It is similar to a bench top logic analyzer were you would connect probes into the circuit, except this is built into the FPGA itself. You then set triggers to capture the internal probes. The xdc defines which signals (Wally buses, registers, etc) are captured by the ILA. We aren't modifying OpenSBI, just the FPGA implementation. By adding specific UART registers, such as the transmit buffer register, the status and control registers we can see what is happening when the UART scrambles the messages.

1. To use the ILA first program the FPGA.
2. Then in the hardware manager, go to the box labeled "Hardware". There will be a hierarchy labeled "localhost (1)", "xilinx_tcf/Digilent/....", "xc7a100t_0", ...
3. Click on the second level, "xilinx_tcf/Digilent/...."
4. In the box below labeled, "Hardware Target Properties", Click "Properties" at the bottom of the box.
5. Then Click the arrow next to "PARAM" and set FREQUENCY to "7500000"

This makes the ILA functional for the Arty A7, the frequency has to be less than 50% of the main clock (20MHz).
Now you can use the box to the right labeled "hw_ila_1". The double arrow ">>" triggers now. Pressing will capture the CPU state immediately. The single arrow ">" will capture on a specific trigger set the "Trigger Setup" box in the lower right corner.

You're idea of a branch on my repo is a good one, https://github.com/rosethompson/cvw/tree/uart-discussion-1361. Using the ILA is bit convoluted. We need to set the trigger to a write to the UART's transmit buffer, write to physical address 0x1000_0000. Set the trigger condition to be IEUAdrM = 10000000 and MemRWM = 1, InstrValidM = 1. Then press the single arrow ">" to set the trigger while OpenSBI is outputting the mangled messages.

Beyond this, I would love to have a HIFI Wally. Let's see if we can get past the current issue.

[PietDelaney]

I was looking over the git repo that Mathew Otto did for the JTAG support.
It's quite a lot of code. I get the impression it's including the ARM RVI device. Is that related to RVVI?

Seems RVI supports SMP debugging with JTAG. That interesting. At Tensilica our JTAG didn't support SMP hardly at all.
I did work on a HP debugger that I was able to make breakpoints specific to a linug process.

You were heavenly involved in the git commits from Matthew Otto. I was wonder if anyone wrote up a design spec for this Wally extension. Perhaps a design spec from Dr. James Stine for Matthew.

I've tried the mainline Wally/CVW repo and I'm getting problem with the top level Make.
I'm going to try the fpga part of the build and see it it's working as well as your git repo.

Are you having any trouble with the top level Makefile in your repo and or the default cvw repo?

-piet

[jordancarlin]

I've tried the mainline Wally/CVW repo and I'm getting problem with the top level Make.
I'm going to try the fpga part of the build and see it it's working as well as your git repo.

Can you share the error message/output that you’re getting? I haven’t had issues with the top level Makefile.

[PietDelaney]

(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make clean
make clean -C sim
make clean -C /src/piet/cvw/cvw/tests/riscof
rm -f config??.ini
rm -rf ./riscof_work
rm -rf ./work/wally-riscv-arch-test
rm -rf ./work/riscv-arch-test
rm -rf
make clean -C /src/piet/cvw/cvw/tests/fp
make -C /src/piet/cvw/cvw/tests/fp/vectors clean
rm -f .tv
rm -f sed
make -C /src/piet/cvw/cvw/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC clean
rm -f s_eq128.o s_le128.o s_lt128.o s_shortShiftLeft128.o s_shortShiftRight128.o s_shortShiftRightJam64.o s_shortShiftRightJam64Extra.o s_shortShiftRightJam128.o s_shortShiftRightJam128Extra.o s_shiftRightJam32.o s_shiftRightJam64.o s_shiftRightJam64Extra.o s_shiftRightJam128.o s_shiftRightJam128Extra.o s_shiftRightJam256M.o s_countLeadingZeros8.o s_countLeadingZeros16.o s_countLeadingZeros32.o s_countLeadingZeros64.o s_add128.o s_add256M.o s_sub128.o s_sub256M.o s_mul64ByShifted32To128.o s_mul64To128.o s_mul128By32.o s_mul128To256M.o s_approxRecip_1Ks.o s_approxRecip32_1.o s_approxRecipSqrt_1Ks.o s_approxRecipSqrt32_1.o softfloat_raiseFlags.o s_f16UIToCommonNaN.o s_commonNaNToF16UI.o s_propagateNaNF16UI.o s_bf16UIToCommonNaN.o s_commonNaNToBF16UI.o s_f32UIToCommonNaN.o s_commonNaNToF32UI.o s_propagateNaNF32UI.o s_f64UIToCommonNaN.o s_commonNaNToF64UI.o s_propagateNaNF64UI.o extF80M_isSignalingNaN.o s_extF80UIToCommonNaN.o s_commonNaNToExtF80UI.o s_propagateNaNExtF80UI.o f128M_isSignalingNaN.o s_f128UIToCommonNaN.o s_commonNaNToF128UI.o s_propagateNaNF128UI.o s_roundToUI32.o s_roundToUI64.o s_roundToI32.o s_roundToI64.o s_normSubnormalBF16Sig.o s_roundPackToBF16.o s_normSubnormalF16Sig.o s_roundPackToF16.o s_normRoundPackToF16.o s_addMagsF16.o s_subMagsF16.o s_mulAddF16.o s_normSubnormalF32Sig.o s_roundPackToF32.o s_normRoundPackToF32.o s_addMagsF32.o s_subMagsF32.o s_mulAddF32.o s_normSubnormalF64Sig.o s_roundPackToF64.o s_normRoundPackToF64.o s_addMagsF64.o s_subMagsF64.o s_mulAddF64.o s_normSubnormalExtF80Sig.o s_roundPackToExtF80.o s_normRoundPackToExtF80.o s_addMagsExtF80.o s_subMagsExtF80.o s_normSubnormalF128Sig.o s_roundPackToF128.o s_normRoundPackToF128.o s_addMagsF128.o s_subMagsF128.o s_mulAddF128.o softfloat_state.o ui32_to_f16.o ui32_to_f32.o ui32_to_f64.o ui32_to_extF80.o ui32_to_extF80M.o ui32_to_f128.o ui32_to_f128M.o ui64_to_f16.o ui64_to_f32.o ui64_to_f64.o ui64_to_extF80.o ui64_to_extF80M.o ui64_to_f128.o ui64_to_f128M.o i32_to_f16.o i32_to_f32.o i32_to_f64.o i32_to_extF80.o i32_to_extF80M.o i32_to_f128.o i32_to_f128M.o i64_to_f16.o i64_to_f32.o i64_to_f64.o i64_to_extF80.o i64_to_extF80M.o i64_to_f128.o i64_to_f128M.o bf16_isSignalingNaN.o bf16_to_f32.o f16_to_ui32.o f16_to_ui64.o f16_to_i32.o f16_to_i64.o f16_to_ui32_r_minMag.o f16_to_ui64_r_minMag.o f16_to_i32_r_minMag.o f16_to_i64_r_minMag.o f16_to_f32.o f16_to_f64.o f16_to_extF80.o f16_to_extF80M.o f16_to_f128.o f16_to_f128M.o f16_roundToInt.o f16_add.o f16_sub.o f16_mul.o f16_mulAdd.o f16_div.o f16_rem.o f16_sqrt.o f16_eq.o f16_le.o f16_lt.o f16_eq_signaling.o f16_le_quiet.o f16_lt_quiet.o f16_isSignalingNaN.o f32_to_ui32.o f32_to_ui64.o f32_to_i32.o f32_to_i64.o f32_to_ui32_r_minMag.o f32_to_ui64_r_minMag.o f32_to_i32_r_minMag.o f32_to_i64_r_minMag.o f32_to_bf16.o f32_to_f16.o f32_to_f64.o f32_to_extF80.o f32_to_extF80M.o f32_to_f128.o f32_to_f128M.o f32_roundToInt.o f32_add.o f32_sub.o f32_mul.o f32_mulAdd.o f32_div.o f32_rem.o f32_sqrt.o f32_eq.o f32_le.o f32_lt.o f32_eq_signaling.o f32_le_quiet.o f32_lt_quiet.o f32_isSignalingNaN.o f64_to_ui32.o f64_to_ui64.o f64_to_i32.o f64_to_i64.o f64_to_ui32_r_minMag.o f64_to_ui64_r_minMag.o f64_to_i32_r_minMag.o f64_to_i64_r_minMag.o f64_to_f16.o f64_to_f32.o f64_to_extF80.o f64_to_extF80M.o f64_to_f128.o f64_to_f128M.o f64_roundToInt.o f64_add.o f64_sub.o f64_mul.o f64_mulAdd.o f64_div.o f64_rem.o f64_sqrt.o f64_eq.o f64_le.o f64_lt.o f64_eq_signaling.o f64_le_quiet.o f64_lt_quiet.o f64_isSignalingNaN.o extF80_to_ui32.o extF80_to_ui64.o extF80_to_i32.o extF80_to_i64.o extF80_to_ui32_r_minMag.o extF80_to_ui64_r_minMag.o extF80_to_i32_r_minMag.o extF80_to_i64_r_minMag.o extF80_to_f16.o extF80_to_f32.o extF80_to_f64.o extF80_to_f128.o extF80_roundToInt.o extF80_add.o extF80_sub.o extF80_mul.o extF80_div.o extF80_rem.o extF80_sqrt.o extF80_eq.o extF80_le.o extF80_lt.o extF80_eq_signaling.o extF80_le_quiet.o extF80_lt_quiet.o extF80_isSignalingNaN.o extF80M_to_ui32.o extF80M_to_ui64.o extF80M_to_i32.o extF80M_to_i64.o extF80M_to_ui32_r_minMag.o extF80M_to_ui64_r_minMag.o extF80M_to_i32_r_minMag.o extF80M_to_i64_r_minMag.o extF80M_to_f16.o extF80M_to_f32.o extF80M_to_f64.o extF80M_to_f128M.o extF80M_roundToInt.o extF80M_add.o extF80M_sub.o extF80M_mul.o extF80M_div.o extF80M_rem.o extF80M_sqrt.o extF80M_eq.o extF80M_le.o extF80M_lt.o extF80M_eq_signaling.o extF80M_le_quiet.o extF80M_lt_quiet.o f128_to_ui32.o f128_to_ui64.o f128_to_i32.o f128_to_i64.o f128_to_ui32_r_minMag.o f128_to_ui64_r_minMag.o f128_to_i32_r_minMag.o f128_to_i64_r_minMag.o f128_to_f16.o f128_to_f32.o f128_to_extF80.o f128_to_f64.o f128_roundToInt.o f128_add.o f128_sub.o f128_mul.o f128_mulAdd.o f128_div.o f128_rem.o f128_sqrt.o f128_eq.o f128_le.o f128_lt.o f128_eq_signaling.o f128_le_quiet.o f128_lt_quiet.o f128_isSignalingNaN.o f128M_to_ui32.o f128M_to_ui64.o f128M_to_i32.o f128M_to_i64.o f128M_to_ui32_r_minMag.o f128M_to_ui64_r_minMag.o f128M_to_i32_r_minMag.o f128M_to_i64_r_minMag.o f128M_to_f16.o f128M_to_f32.o f128M_to_extF80M.o f128M_to_f64.o f128M_roundToInt.o f128M_add.o f128M_sub.o f128M_mul.o f128M_mulAdd.o f128M_div.o f128M_rem.o f128M_sqrt.o f128M_eq.o f128M_le.o f128M_lt.o f128M_eq_signaling.o f128M_le_quiet.o f128M_lt_quiet.o softfloat.a
make -C /src/piet/cvw/cvw/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC clean
rm -f uint128_inline.o uint128.o fail.o functions_common.o functionInfos.o standardFunctionInfos.o random.o genCases_common.o genCases_ui32.o genCases_ui64.o genCases_i32.o genCases_i64.o genCases_f16.o genCases_bf16.o genCases_f32.o genCases_f64.o genCases_extF80.o genCases_f128.o genCases_writeTestsTotal.o verCases_inline.o verCases_common.o verCases_writeFunctionName.o readHex.o writeHex.o writeCase_a_ui32.o writeCase_a_ui64.o writeCase_a_f16.o writeCase_a_bf16.o writeCase_ab_f16.o writeCase_abc_f16.o writeCase_a_f32.o writeCase_ab_f32.o writeCase_abc_f32.o writeCase_a_f64.o writeCase_ab_f64.o writeCase_abc_f64.o writeCase_a_extF80M.o writeCase_ab_extF80M.o writeCase_a_f128M.o writeCase_ab_f128M.o writeCase_abc_f128M.o writeCase_z_bool.o writeCase_z_ui32.o writeCase_z_ui64.o writeCase_z_bf16.o writeCase_z_f16.o writeCase_z_f32.o writeCase_z_f64.o writeCase_z_extF80M.o writeCase_z_f128M.o testLoops_common.o test_a_ui32_z_f16.o test_a_ui32_z_f32.o test_a_ui32_z_f64.o test_a_ui32_z_extF80.o test_a_ui32_z_f128.o test_a_ui64_z_f16.o test_a_ui64_z_f32.o test_a_ui64_z_f64.o test_a_ui64_z_extF80.o test_a_ui64_z_f128.o test_a_i32_z_f16.o test_a_i32_z_f32.o test_a_i32_z_f64.o test_a_i32_z_extF80.o test_a_i32_z_f128.o test_a_i64_z_f16.o test_a_i64_z_f32.o test_a_i64_z_f64.o test_a_i64_z_extF80.o test_a_i64_z_f128.o test_a_f16_z_ui32_rx.o test_a_f16_z_ui64_rx.o test_a_f16_z_i32_rx.o test_a_f16_z_i64_rx.o test_a_f16_z_ui32_x.o test_a_f16_z_ui64_x.o test_a_f16_z_i32_x.o test_a_f16_z_i64_x.o test_a_f16_z_f32.o test_a_bf16_z_f32.o test_a_f32_z_bf16.o test_a_f16_z_f64.o test_a_f16_z_extF80.o test_a_f16_z_f128.o test_az_f16.o test_az_f16_rx.o test_abz_f16.o test_abcz_f16.o test_ab_f16_z_bool.o test_a_f32_z_ui32_rx.o test_a_f32_z_ui64_rx.o test_a_f32_z_i32_rx.o test_a_f32_z_i64_rx.o test_a_f32_z_ui32_x.o test_a_f32_z_ui64_x.o test_a_f32_z_i32_x.o test_a_f32_z_i64_x.o test_a_f32_z_f16.o test_a_f32_z_f64.o test_a_f32_z_extF80.o test_a_f32_z_f128.o test_az_f32.o test_az_f32_rx.o test_abz_f32.o test_abcz_f32.o test_ab_f32_z_bool.o test_a_f64_z_ui32_rx.o test_a_f64_z_ui64_rx.o test_a_f64_z_i32_rx.o test_a_f64_z_i64_rx.o test_a_f64_z_ui32_x.o test_a_f64_z_ui64_x.o test_a_f64_z_i32_x.o test_a_f64_z_i64_x.o test_a_f64_z_f16.o test_a_f64_z_f32.o test_a_f64_z_extF80.o test_a_f64_z_f128.o test_az_f64.o test_az_f64_rx.o test_abz_f64.o test_abcz_f64.o test_ab_f64_z_bool.o test_a_extF80_z_ui32_rx.o test_a_extF80_z_ui64_rx.o test_a_extF80_z_i32_rx.o test_a_extF80_z_i64_rx.o test_a_extF80_z_ui32_x.o test_a_extF80_z_ui64_x.o test_a_extF80_z_i32_x.o test_a_extF80_z_i64_x.o test_a_extF80_z_f16.o test_a_extF80_z_f32.o test_a_extF80_z_f64.o test_a_extF80_z_f128.o test_az_extF80.o test_az_extF80_rx.o test_abz_extF80.o test_ab_extF80_z_bool.o test_a_f128_z_ui32_rx.o test_a_f128_z_ui64_rx.o test_a_f128_z_i32_rx.o test_a_f128_z_i64_rx.o test_a_f128_z_ui32_x.o test_a_f128_z_ui64_x.o test_a_f128_z_i32_x.o test_a_f128_z_i64_x.o test_a_f128_z_f16.o test_a_f128_z_f32.o test_a_f128_z_f64.o test_a_f128_z_extF80.o test_az_f128.o test_az_f128_rx.o test_abz_f128.o test_abcz_f128.o test_ab_f128_z_bool.o testfloat.a
rm -f slowfloat.o testsoftfloat.o testsoftfloat
rm -f timesoftfloat.o timesoftfloat
rm -f genLoops.o testfloat_gen.o testfloat_gen
rm -f verLoops.o testfloat_ver.o testfloat_ver
rm -f subjfloat.o subjfloat_functions.o testfloat.o testfloat
rm -f /src/piet/cvw/cvw/tests/fp/combined_IF_vectors/IF_vectors/.tv
make clean -C /src/piet/cvw/cvw/tests/coverage
rm -f *.elf *.objdump *.signature.output .addr .lab .memfile .o .s
make clean -C /src/piet/cvw/cvw/addins/cvw-arch-verif
rm -rf fcov/unpriv/
rm -rf tests/lockstep/rv64 tests/lockstep/rv32 tests/lockstep/priv/headers tests/lockstep/priv/rv64 tests/lockstep/priv/rv32 work
rm -rf tests/selfchecking/
rm -rf tests/signature/
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make
make -C sim
make -C /src/piet/cvw/cvw/tests/riscof
mkdir -p riscof_work
mkdir -p work/riscv-arch-test
sed 's,{0},/src/piet/cvw/cvw/tests/riscof,g;s,{1},32e,g;s,{2},27,g' config.ini > config32e.ini
riscof run --work-dir=./riscof_work/arch32e --config=config32e.ini --suite=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/ --env=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env --no-browser
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.18.3
INFO | Reading configuration from: /src/piet/cvw/cvw/tests/riscof/config32e.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | ISACheck: Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_rv32e_isa.yaml
INFO | ISACheck: Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | ISACheck: Processing Hart:0
INFO | ISACheck: Initiating Validation for Hart:0
INFO | ISACheck: No errors for Hart:0
INFO | ISACheck: Updating fields node for each CSR in Hart:0
INFO | ISACheck: Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_rv32e_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_platform.yaml
INFO | Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_platform_checked.yaml
INFO | Generating database for suite: /src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite
INFO | Database File Generated: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/database.yaml
INFO | Env path set to/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
ERROR | make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:53: TARGET12] Error 1
make[3]: *** Waiting for unfinished jobs....
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:21: TARGET4] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:25: TARGET5] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:57: TARGET13] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:61: TARGET14] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:65: TARGET15] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:69: TARGET16] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:73: TARGET17] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:77: TARGET18] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:81: TARGET19] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:89: TARGET21] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:93: TARGET22] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:97: TARGET23] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:105: TARGET25] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:109: TARGET26] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:45: TARGET10] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:49: TARGET11] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:37: TARGET8] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:41: TARGET9] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:9: TARGET1] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:5: TARGET0] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:33: TARGET7] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:17: TARGET3] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:13: TARGET2] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:29: TARGET6] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:85: TARGET20] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:101: TARGET24] Error 1
INFO | Initiating signature checking.
Traceback (most recent call last):
File "/opt/riscv/riscv-python/bin/riscof", line 8, in
sys.exit(cli())
^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1161, in call
return self.main(args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1082, in main
rv = self.invoke(ctx)
^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1697, in invoke
return _process_result(sub_ctx.command.invoke(sub_ctx))
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1443, in invoke
return ctx.invoke(self.callback, **ctx.params)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 788(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make clean
make clean -C sim
make clean -C /src/piet/cvw/cvw/tests/riscof
rm -f config??.ini
rm -rf ./riscof_work
rm -rf ./work/wally-riscv-arch-test
rm -rf ./work/riscv-arch-test
rm -rf
make clean -C /src/piet/cvw/cvw/tests/fp
make -C /src/piet/cvw/cvw/tests/fp/vectors clean
rm -f .tv
rm -f sed
make -C /src/piet/cvw/cvw/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC clean
rm -f s_eq128.o s_le128.o s_lt128.o s_shortShiftLeft128.o s_shortShiftRight128.o s_shortShiftRightJam64.o s_shortShiftRightJam64Extra.o s_shortShiftRightJam128.o s_shortShiftRightJam128Extra.o s_shiftRightJam32.o s_shiftRightJam64.o s_shiftRightJam64Extra.o s_shiftRightJam128.o s_shiftRightJam128Extra.o s_shiftRightJam256M.o s_countLeadingZeros8.o s_countLeadingZeros16.o s_countLeadingZeros32.o s_countLeadingZeros64.o s_add128.o s_add256M.o s_sub128.o s_sub256M.o s_mul64ByShifted32To128.o s_mul64To128.o s_mul128By32.o s_mul128To256M.o s_approxRecip_1Ks.o s_approxRecip32_1.o s_approxRecipSqrt_1Ks.o s_approxRecipSqrt32_1.o softfloat_raiseFlags.o s_f16UIToCommonNaN.o s_commonNaNToF16UI.o s_propagateNaNF16UI.o s_bf16UIToCommonNaN.o s_commonNaNToBF16UI.o s_f32UIToCommonNaN.o s_commonNaNToF32UI.o s_propagateNaNF32UI.o s_f64UIToCommonNaN.o s_commonNaNToF64UI.o s_propagateNaNF64UI.o extF80M_isSignalingNaN.o s_extF80UIToCommonNaN.o s_commonNaNToExtF80UI.o s_propagateNaNExtF80UI.o f128M_isSignalingNaN.o s_f128UIToCommonNaN.o s_commonNaNToF128UI.o s_propagateNaNF128UI.o s_roundToUI32.o s_roundToUI64.o s_roundToI32.o s_roundToI64.o s_normSubnormalBF16Sig.o s_roundPackToBF16.o s_normSubnormalF16Sig.o s_roundPackToF16.o s_normRoundPackToF16.o s_addMagsF16.o s_subMagsF16.o s_mulAddF16.o s_normSubnormalF32Sig.o s_roundPackToF32.o s_normRoundPackToF32.o s_addMagsF32.o s_subMagsF32.o s_mulAddF32.o s_normSubnormalF64Sig.o s_roundPackToF64.o s_normRoundPackToF64.o s_addMagsF64.o s_subMagsF64.o s_mulAddF64.o s_normSubnormalExtF80Sig.o s_roundPackToExtF80.o s_normRoundPackToExtF80.o s_addMagsExtF80.o s_subMagsExtF80.o s_normSubnormalF128Sig.o s_roundPackToF128.o s_normRoundPackToF128.o s_addMagsF128.o s_subMagsF128.o s_mulAddF128.o softfloat_state.o ui32_to_f16.o ui32_to_f32.o ui32_to_f64.o ui32_to_extF80.o ui32_to_extF80M.o ui32_to_f128.o ui32_to_f128M.o ui64_to_f16.o ui64_to_f32.o ui64_to_f64.o ui64_to_extF80.o ui64_to_extF80M.o ui64_to_f128.o ui64_to_f128M.o i32_to_f16.o i32_to_f32.o i32_to_f64.o i32_to_extF80.o i32_to_extF80M.o i32_to_f128.o i32_to_f128M.o i64_to_f16.o i64_to_f32.o i64_to_f64.o i64_to_extF80.o i64_to_extF80M.o i64_to_f128.o i64_to_f128M.o bf16_isSignalingNaN.o bf16_to_f32.o f16_to_ui32.o f16_to_ui64.o f16_to_i32.o f16_to_i64.o f16_to_ui32_r_minMag.o f16_to_ui64_r_minMag.o f16_to_i32_r_minMag.o f16_to_i64_r_minMag.o f16_to_f32.o f16_to_f64.o f16_to_extF80.o f16_to_extF80M.o f16_to_f128.o f16_to_f128M.o f16_roundToInt.o f16_add.o f16_sub.o f16_mul.o f16_mulAdd.o f16_div.o f16_rem.o f16_sqrt.o f16_eq.o f16_le.o f16_lt.o f16_eq_signaling.o f16_le_quiet.o f16_lt_quiet.o f16_isSignalingNaN.o f32_to_ui32.o f32_to_ui64.o f32_to_i32.o f32_to_i64.o f32_to_ui32_r_minMag.o f32_to_ui64_r_minMag.o f32_to_i32_r_minMag.o f32_to_i64_r_minMag.o f32_to_bf16.o f32_to_f16.o f32_to_f64.o f32_to_extF80.o f32_to_extF80M.o f32_to_f128.o f32_to_f128M.o f32_roundToInt.o f32_add.o f32_sub.o f32_mul.o f32_mulAdd.o f32_div.o f32_rem.o f32_sqrt.o f32_eq.o f32_le.o f32_lt.o f32_eq_signaling.o f32_le_quiet.o f32_lt_quiet.o f32_isSignalingNaN.o f64_to_ui32.o f64_to_ui64.o f64_to_i32.o f64_to_i64.o f64_to_ui32_r_minMag.o f64_to_ui64_r_minMag.o f64_to_i32_r_minMag.o f64_to_i64_r_minMag.o f64_to_f16.o f64_to_f32.o f64_to_extF80.o f64_to_extF80M.o f64_to_f128.o f64_to_f128M.o f64_roundToInt.o f64_add.o f64_sub.o f64_mul.o f64_mulAdd.o f64_div.o f64_rem.o f64_sqrt.o f64_eq.o f64_le.o f64_lt.o f64_eq_signaling.o f64_le_quiet.o f64_lt_quiet.o f64_isSignalingNaN.o extF80_to_ui32.o extF80_to_ui64.o extF80_to_i32.o extF80_to_i64.o extF80_to_ui32_r_minMag.o extF80_to_ui64_r_minMag.o extF80_to_i32_r_minMag.o extF80_to_i64_r_minMag.o extF80_to_f16.o extF80_to_f32.o extF80_to_f64.o extF80_to_f128.o extF80_roundToInt.o extF80_add.o extF80_sub.o extF80_mul.o extF80_div.o extF80_rem.o extF80_sqrt.o extF80_eq.o extF80_le.o extF80_lt.o extF80_eq_signaling.o extF80_le_quiet.o extF80_lt_quiet.o extF80_isSignalingNaN.o extF80M_to_ui32.o extF80M_to_ui64.o extF80M_to_i32.o extF80M_to_i64.o extF80M_to_ui32_r_minMag.o extF80M_to_ui64_r_minMag.o extF80M_to_i32_r_minMag.o extF80M_to_i64_r_minMag.o extF80M_to_f16.o extF80M_to_f32.o extF80M_to_f64.o extF80M_to_f128M.o extF80M_roundToInt.o extF80M_add.o extF80M_sub.o extF80M_mul.o extF80M_div.o extF80M_rem.o extF80M_sqrt.o extF80M_eq.o extF80M_le.o extF80M_lt.o extF80M_eq_signaling.o extF80M_le_quiet.o extF80M_lt_quiet.o f128_to_ui32.o f128_to_ui64.o f128_to_i32.o f128_to_i64.o f128_to_ui32_r_minMag.o f128_to_ui64_r_minMag.o f128_to_i32_r_minMag.o f128_to_i64_r_minMag.o f128_to_f16.o f128_to_f32.o f128_to_extF80.o f128_to_f64.o f128_roundToInt.o f128_add.o f128_sub.o f128_mul.o f128_mulAdd.o f128_div.o f128_rem.o f128_sqrt.o f128_eq.o f128_le.o f128_lt.o f128_eq_signaling.o f128_le_quiet.o f128_lt_quiet.o f128_isSignalingNaN.o f128M_to_ui32.o f128M_to_ui64.o f128M_to_i32.o f128M_to_i64.o f128M_to_ui32_r_minMag.o f128M_to_ui64_r_minMag.o f128M_to_i32_r_minMag.o f128M_to_i64_r_minMag.o f128M_to_f16.o f128M_to_f32.o f128M_to_extF80M.o f128M_to_f64.o f128M_roundToInt.o f128M_add.o f128M_sub.o f128M_mul.o f128M_mulAdd.o f128M_div.o f128M_rem.o f128M_sqrt.o f128M_eq.o f128M_le.o f128M_lt.o f128M_eq_signaling.o f128M_le_quiet.o f128M_lt_quiet.o softfloat.a
make -C /src/piet/cvw/cvw/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC clean
rm -f uint128_inline.o uint128.o fail.o functions_common.o functionInfos.o standa(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make clean
make clean -C sim
make clean -C /src/piet/cvw/cvw/tests/riscof
rm -f config??.ini
rm -rf ./riscof_work
rm -rf ./work/wally-riscv-arch-test
rm -rf ./work/riscv-arch-test
rm -rf
make clean -C /src/piet/cvw/cvw/tests/fp
make -C /src/piet/cvw/cvw/tests/fp/vectors clean
rm -f .tv
rm -f sed
make -C /src/piet/cvw/cvw/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC clean
rm -f s_eq128.o s_le128.o s_lt128.o s_shortShiftLeft128.o s_shortShiftRight128.o s_shortShiftRightJam64.o s_shortShiftRightJam64Extra.o s_shortShiftRightJam128.o s_shortShiftRightJam128Extra.o s_shiftRightJam32.o s_shiftRightJam64.o s_shiftRightJam64Extra.o s_shiftRightJam128.o s_shiftRightJam128Extra.o s_shiftRightJam256M.o s_countLeadingZeros8.o s_countLeadingZeros16.o s_countLeadingZeros32.o s_countLeadingZeros64.o s_add128.o s_add256M.o s_sub128.o s_sub256M.o s_mul64ByShifted32To128.o s_mul64To128.o s_mul128By32.o s_mul128To256M.o s_approxRecip_1Ks.o s_approxRecip32_1.o s_approxRecipSqrt_1Ks.o s_approxRecipSqrt32_1.o softfloat_raiseFlags.o s_f16UIToCommonNaN.o s_commonNaNToF16UI.o s_propagateNaNF16UI.o s_bf16UIToCommonNaN.o s_commonNaNToBF16UI.o s_f32UIToCommonNaN.o s_commonNaNToF32UI.o s_propagateNaNF32UI.o s_f64UIToCommonNaN.o s_commonNaNToF64UI.o s_propagateNaNF64UI.o extF80M_isSignalingNaN.o s_extF80UIToCommonNaN.o s_commonNaNToExtF80UI.o s_propagateNaNExtF80UI.o f128M_isSignalingNaN.o s_f128UIToCommonNaN.o s_commonNaNToF128UI.o s_propagateNaNF128UI.o s_roundToUI32.o s_roundToUI64.o s_roundToI32.o s_roundToI64.o s_normSubnormalBF16Sig.o s_roundPackToBF16.o s_normSubnormalF16Sig.o s_roundPackToF16.o s_normRoundPackToF16.o s_addMagsF16.o s_subMagsF16.o s_mulAddF16.o s_normSubnormalF32Sig.o s_roundPackToF32.o s_normRoundPackToF32.o s_addMagsF32.o s_subMagsF32.o s_mulAddF32.o s_normSubnormalF64Sig.o s_roundPackToF64.o s_normRoundPackToF64.o s_addMagsF64.o s_subMagsF64.o s_mulAddF64.o s_normSubnormalExtF80Sig.o s_roundPackToExtF80.o s_normRoundPackToExtF80.o s_addMagsExtF80.o s_subMagsExtF80.o s_normSubnormalF128Sig.o s_roundPackToF128.o s_normRoundPackToF128.o s_addMagsF128.o s_subMagsF128.o s_mulAddF128.o softfloat_state.o ui32_to_f16.o ui32_to_f32.o ui32_to_f64.o ui32_to_extF80.o ui32_to_extF80M.o ui32_to_f128.o ui32_to_f128M.o ui64_to_f16.o ui64_to_f32.o ui64_to_f64.o ui64_to_extF80.o ui64_to_extF80M.o ui64_to_f128.o ui64_to_f128M.o i32_to_f16.o i32_to_f32.o i32_to_f64.o i32_to_extF80.o i32_to_extF80M.o i32_to_f128.o i32_to_f128M.o i64_to_f16.o i64_to_f32.o i64_to_f64.o i64_to_extF80.o i64_to_extF80M.o i64_to_f128.o i64_to_f128M.o bf16_isSignalingNaN.o bf16_to_f32.o f16_to_ui32.o f16_to_ui64.o f16_to_i32.o f16_to_i64.o f16_to_ui32_r_minMag.o f16_to_ui64_r_minMag.o f16_to_i32_r_minMag.o f16_to_i64_r_minMag.o f16_to_f32.o f16_to_f64.o f16_to_extF80.o f16_to_extF80M.o f16_to_f128.o f16_to_f128M.o f16_roundToInt.o f16_add.o f16_sub.o f16_mul.o f16_mulAdd.o f16_div.o f16_rem.o f16_sqrt.o f16_eq.o f16_le.o f16_lt.o f16_eq_signaling.o f16_le_quiet.o f16_lt_quiet.o f16_isSignalingNaN.o f32_to_ui32.o f32_to_ui64.o f32_to_i32.o f32_to_i64.o f32_to_ui32_r_minMag.o f32_to_ui64_r_minMag.o f32_to_i32_r_minMag.o f32_to_i64_r_minMag.o f32_to_bf16.o f32_to_f16.o f32_to_f64.o f32_to_extF80.o f32_to_extF80M.o f32_to_f128.o f32_to_f128M.o f32_roundToInt.o f32_add.o f32_sub.o f32_mul.o f32_mulAdd.o f32_div.o f32_rem.o f32_sqrt.o f32_eq.o f32_le.o f32_lt.o f32_eq_signaling.o f32_le_quiet.o f32_lt_quiet.o f32_isSignalingNaN.o f64_to_ui32.o f64_to_ui64.o f64_to_i32.o f64_to_i64.o f64_to_ui32_r_minMag.o f64_to_ui64_r_minMag.o f64_to_i32_r_minMag.o f64_to_i64_r_minMag.o f64_to_f16.o f64_to_f32.o f64_to_extF80.o f64_to_extF80M.o f64_to_f128.o f64_to_f128M.o f64_roundToInt.o f64_add.o f64_sub.o f64_mul.o f64_mulAdd.o f64_div.o f64_rem.o f64_sqrt.o f64_eq.o f64_le.o f64_lt.o f64_eq_signaling.o f64_le_quiet.o f64_lt_quiet.o f64_isSignalingNaN.o extF80_to_ui32.o extF80_to_ui64.o extF80_to_i32.o extF80_to_i64.o extF80_to_ui32_r_minMag.o extF80_to_ui64_r_minMag.o extF80_to_i32_r_minMag.o extF80_to_i64_r_minMag.o extF80_to_f16.o extF80_to_f32.o extF80_to_f64.o extF80_to_f128.o extF80_roundToInt.o extF80_add.o extF80_sub.o extF80_mul.o extF80_div.o extF80_rem.o extF80_sqrt.o extF80_eq.o extF80_le.o extF80_lt.o extF80_eq_signaling.o extF80_le_quiet.o extF80_lt_quiet.o extF80_isSignalingNaN.o extF80M_to_ui32.o extF80M_to_ui64.o extF80M_to_i32.o extF80M_to_i64.o extF80M_to_ui32_r_minMag.o extF80M_to_ui64_r_minMag.o extF80M_to_i32_r_minMag.o extF80M_to_i64_r_minMag.o extF80M_to_f16.o extF80M_to_f32.o extF80M_to_f64.o extF80M_to_f128M.o extF80M_roundToInt.o extF80M_add.o extF80M_sub.o extF80M_mul.o extF80M_div.o extF80M_rem.o extF80M_sqrt.o extF80M_eq.o extF80M_le.o extF80M_lt.o extF80M_eq_signaling.o extF80M_le_quiet.o extF80M_lt_quiet.o f128_to_ui32.o f128_to_ui64.o f128_to_i32.o f128_to_i64.o f128_to_ui32_r_minMag.o f128_to_ui64_r_minMag.o f128_to_i32_r_minMag.o f128_to_i64_r_minMag.o f128_to_f16.o f128_to_f32.o f128_to_extF80.o f128_to_f64.o f128_roundToInt.o f128_add.o f128_sub.o f128_mul.o f128_mulAdd.o f128_div.o f128_rem.o f128_sqrt.o f128_eq.o f128_le.o f128_lt.o f128_eq_signaling.o f128_le_quiet.o f128_lt_quiet.o f128_isSignalingNaN.o f128M_to_ui32.o f128M_to_ui64.o f128M_to_i32.o f128M_to_i64.o f128M_to_ui32_r_minMag.o f128M_to_ui64_r_minMag.o f128M_to_i32_r_minMag.o f128M_to_i64_r_minMag.o f128M_to_f16.o f128M_to_f32.o f128M_to_extF80M.o f128M_to_f64.o f128M_roundToInt.o f128M_add.o f128M_sub.o f128M_mul.o f128M_mulAdd.o f128M_div.o f128M_rem.o f128M_sqrt.o f128M_eq.o f128M_le.o f128M_lt.o f128M_eq_signaling.o f128M_le_quiet.o f128M_lt_quiet.o softfloat.a
make -C /src/piet/cvw/cvw/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC clean
rm -f uint128_inline.o uint128.o fail.o functions_common.o functionInfos.o standardFunctionInfos.o random.o genCases_common.o genCases_ui32.o genCases_ui64.o genCases_i32.o genCases_i64.o genCases_f16.o genCases_bf16.o genCases_f32.o genCases_f64.o genCases_extF80.o genCases_f128.o genCases_writeTestsTotal.o verCases_inline.o verCases_common.o verCases_writeFunctionName.o readHex.o writeHex.o writeCase_a_ui32.o writeCase_a_ui64.o writeCase_a_f16.o writeCase_a_bf16.o writeCase_ab_f16.o writeCase_abc_f16.o writeCase_a_f32.o writeCase_ab_f32.o writeCase_abc_f32.o writeCase_a_f64.o writeCase_ab_f64.o writeCase_abc_f64.o writeCase_a_extF80M.o writeCase_ab_extF80M.o writeCase_a_f128M.o writeCase_ab_f128M.o writeCase_abc_f128M.o writeCase_z_bool.o writeCase_z_ui32.o writeCase_z_ui64.o writeCase_z_bf16.o writeCase_z_f16.o writeCase_z_f32.o writeCase_z_f64.o writeCase_z_extF80M.o writeCase_z_f128M.o testLoops_common.o test_a_ui32_z_f16.o test_a_ui32_z_f32.o test_a_ui32_z_f64.o test_a_ui32_z_extF80.o test_a_ui32_z_f128.o test_a_ui64_z_f16.o test_a_ui64_z_f32.o test_a_ui64_z_f64.o test_a_ui64_z_extF80.o test_a_ui64_z_f128.o test_a_i32_z_f16.o test_a_i32_z_f32.o test_a_i32_z_f64.o test_a_i32_z_extF80.o test_a_i32_z_f128.o test_a_i64_z_f16.o test_a_i64_z_f32.o test_a_i64_z_f64.o test_a_i64_z_extF80.o test_a_i64_z_f128.o test_a_f16_z_ui32_rx.o test_a_f16_z_ui64_rx.o test_a_f16_z_i32_rx.o test_a_f16_z_i64_rx.o test_a_f16_z_ui32_x.o test_a_f16_z_ui64_x.o test_a_f16_z_i32_x.o test_a_f16_z_i64_x.o test_a_f16_z_f32.o test_a_bf16_z_f32.o test_a_f32_z_bf16.o test_a_f16_z_f64.o test_a_f16_z_extF80.o test_a_f16_z_f128.o test_az_f16.o test_az_f16_rx.o test_abz_f16.o test_abcz_f16.o test_ab_f16_z_bool.o test_a_f32_z_ui32_rx.o test_a_f32_z_ui64_rx.o test_a_f32_z_i32_rx.o test_a_f32_z_i64_rx.o test_a_f32_z_ui32_x.o test_a_f32_z_ui64_x.o test_a_f32_z_i32_x.o test_a_f32_z_i64_x.o test_a_f32_z_f16.o test_a_f32_z_f64.o test_a_f32_z_extF80.o test_a_f32_z_f128.o test_az_f32.o test_az_f32_rx.o test_abz_f32.o test_abcz_f32.o test_ab_f32_z_bool.o test_a_f64_z_ui32_rx.o test_a_f64_z_ui64_rx.o test_a_f64_z_i32_rx.o test_a_f64_z_i64_rx.o test_a_f64_z_ui32_x.o test_a_f64_z_ui64_x.o test_a_f64_z_i32_x.o test_a_f64_z_i64_x.o test_a_f64_z_f16.o test_a_f64_z_f32.o test_a_f64_z_extF80.o test_a_f64_z_f128.o test_az_f64.o test_az_f64_rx.o test_abz_f64.o test_abcz_f64.o test_ab_f64_z_bool.o test_a_extF80_z_ui32_rx.o test_a_extF80_z_ui64_rx.o test_a_extF80_z_i32_rx.o test_a_extF80_z_i64_rx.o test_a_extF80_z_ui32_x.o test_a_extF80_z_ui64_x.o test_a_extF80_z_i32_x.o test_a_extF80_z_i64_x.o test_a_extF80_z_f16.o test_a_extF80_z_f32.o test_a_extF80_z_f64.o test_a_extF80_z_f128.o test_az_extF80.o test_az_extF80_rx.o test_abz_extF80.o test_ab_extF80_z_bool.o test_a_f128_z_ui32_rx.o test_a_f128_z_ui64_rx.o test_a_f128_z_i32_rx.o test_a_f128_z_i64_rx.o test_a_f128_z_ui32_x.o test_a_f128_z_ui64_x.o test_a_f128_z_i32_x.o test_a_f128_z_i64_x.o test_a_f128_z_f16.o test_a_f128_z_f32.o test_a_f128_z_f64.o test_a_f128_z_extF80.o test_az_f128.o test_az_f128_rx.o test_abz_f128.o test_abcz_f128.o test_ab_f128_z_bool.o testfloat.a
rm -f slowfloat.o testsoftfloat.o testsoftfloat
rm -f timesoftfloat.o timesoftfloat
rm -f genLoops.o testfloat_gen.o testfloat_gen
rm -f verLoops.o testfloat_ver.o testfloat_ver
rm -f subjfloat.o subjfloat_functions.o testfloat.o testfloat
rm -f /src/piet/cvw/cvw/tests/fp/combined_IF_vectors/IF_vectors/.tv
make clean -C /src/piet/cvw/cvw/tests/coverage
rm -f *.elf *.objdump *.signature.output *.addr *.lab .memfile .o .s
make clean -C /src/piet/cvw/cvw/addins/cvw-arch-verif
rm -rf fcov/unpriv/
rm -rf tests/lockstep/rv64 tests/lockstep/rv32 tests/lockstep/priv/headers tests/lockstep/priv/rv64 tests/lockstep/priv/rv32 work
rm -rf tests/selfchecking/
rm -rf tests/signature/
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make
make -C sim
make -C /src/piet/cvw/cvw/tests/riscof
mkdir -p riscof_work
mkdir -p work/riscv-arch-test
sed 's,{0},/src/piet/cvw/cvw/tests/riscof,g;s,{1},32e,g;s,{2},27,g' config.ini > config32e.ini
riscof run --work-dir=./riscof_work/arch32e --config=config32e.ini --suite=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/ --env=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env --no-browser
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.18.3
INFO | Reading configuration from: /src/piet/cvw/cvw/tests/riscof/config32e.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | ISACheck: Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_rv32e_isa.yaml
INFO | ISACheck: Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | ISACheck: Processing Hart:0
INFO | ISACheck: Initiating Validation for Hart:0
INFO | ISACheck: No errors for Hart:0
INFO | ISACheck: Updating fields node for each CSR in Hart:0
INFO | ISACheck: Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_rv32e_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_platform.yaml
INFO | Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_platform_checked.yaml
INFO | Generating database for suite: /src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite
INFO | Database File Generated: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/database.yaml
INFO | Env path set to/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
ERROR | make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:53: TARGET12] Error 1
make[3]: *** Waiting for unfinished jobs....
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:21: TARGET4] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:25: TARGET5] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:57: TARGET13] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:61: TARGET14] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:65: TARGET15] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:69: TARGET16] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:73: TARGET17] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:77: TARGET18] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:81: TARGET19] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:89: TARGET21] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:93: TARGET22] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:97: TARGET23] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:105: TARGET25] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:109: TARGET26] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:45: TARGET10] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:49: TARGET11] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:37: TARGET8] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:41: TARGET9] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:9: TARGET1] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:5: TARGET0] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:33: TARGET7] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:17: TARGET3] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:13: TARGET2] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:29: TARGET6] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:85: TARGET20] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:101: TARGET24] Error 1
INFO | Initiating signature checking.
Traceback (most recent call last):
File "/opt/riscv/riscv-python/bin/riscof", line 8, in
sys.exit(cli())
^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1161, in call
return self.main(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1082, in main
rv = self.invoke(ctx)
^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1697, in invoke
return _process_result(sub_ctx.command.invoke(sub_ctx))
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1443, in invoke
return ctx.invoke(self.callback, **ctx.params)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 788, in invoke
return __callback(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/decorators.py", line 33, in new_func
return f(get_current_context(), *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/cli.py", line 321, in run
report_objects['results'] = framework.run(dut, base, ctx.obj.isa_file,
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/main.py", line 209, in run
results = test.run_tests(dut, base, ispec['hart0'], pspec, work_dir, cntr_args)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 458, in run_tests
result, diff = compare_signature(res, ref)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 46, in compare_signature
file2_lines = open(file2, "r").readlines()
^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/rv32e_m/B/src/clmul-01.S/ref/Reference-sail_c_simulator.signature'
make[2]: *** [Makefile:27: arch32e] Error 1
rm config32e.ini
make[1]: *** [Makefile:16: riscoftests] Error 2
make: *** [Makefile:15: riscof] Error 2
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$

rdFunctionInfos.o random.o genCases_common.o genCases_ui32.o genCases_ui64.o genCases_i32.o genCases_i64.o genCases_f16.o genCases_bf16.o genCases_f32.o genCases_f64.o genCases_extF80.o genCases_f128.o genCases_writeTestsTotal.o verCases_inline.o verCases_common.o verCases_writeFunctionName.o readHex.o writeHex.o writeCase_a_ui32.o writeCase_a_ui64.o writeCase_a_f16.o writeCase_a_bf16.o writeCase_ab_f16.o writeCase_abc_f16.o writeCase_a_f32.o writeCase_ab_f32.o writeCase_abc_f32.o writeCase_a_f64.o writeCase_ab_f64.o writeCase_abc_f64.o writeCase_a_extF80M.o writeCase_ab_extF80M.o writeCase_a_f128M.o writeCase_ab_f128M.o writeCase_abc_f128M.o writeCase_z_bool.o writeCase_z_ui32.o writeCase_z_ui64.o writeCase_z_bf16.o writeCase_z_f16.o writeCase_z_f32.o writeCase_z_f64.o writeCase_z_extF80M.o writeCase_z_f128M.o testLoops_common.o test_a_ui32_z_f16.o test_a_ui32_z_f32.o test_a_ui32_z_f64.o test_a_ui32_z_extF80.o test_a_ui32_z_f128.o test_a_ui64_z_f16.o test_a_ui64_z_f32.o test_a_ui64_z_f64.o test_a_ui64_z_extF80.o test_a_ui64_z_f128.o test_a_i32_z_f16.o test_a_i32_z_f32.o test_a_i32_z_f64.o test_a_i32_z_extF80.o test_a_i32_z_f128.o test_a_i64_z_f16.o test_a_i64_z_f32.o test_a_i64_z_f64.o test_a_i64_z_extF80.o test_a_i64_z_f128.o test_a_f16_z_ui32_rx.o test_a_f16_z_ui64_rx.o test_a_f16_z_i32_rx.o test_a_f16_z_i64_rx.o test_a_f16_z_ui32_x.o test_a_f16_z_ui64_x.o test_a_f16_z_i32_x.o test_a_f16_z_i64_x.o test_a_f16_z_f32.o test_a_bf16_z_f32.o test_a_f32_z_bf16.o test_a_f16_z_f64.o test_a_f16_z_extF80.o test_a_f16_z_f128.o test_az_f16.o test_az_f16_rx.o test_abz_f16.o test_abcz_f16.o test_ab_f16_z_bool.o test_a_f32_z_ui32_rx.o test_a_f32_z_ui64_rx.o test_a_f32_z_i32_rx.o test_a_f32_z_i64_rx.o test_a_f32_z_ui32_x.o test_a_f32_z_ui64_x.o test_a_f32_z_i32_x.o test_a_f32_z_i64_x.o test_a_f32_z_f16.o test_a_f32_z_f64.o test_a_f32_z_extF80.o test_a_f32_z_f128.o test_az_f32.o test_az_f32_rx.o test_abz_f32.o test_abcz_f32.o test_ab_f32_z_bool.o test_a_f64_z_ui32_rx.o test_a_f64_z_ui64_rx.o test_a_f64_z_i32_rx.o test_a_f64_z_i64_rx.o test_a_f64_z_ui32_x.o test_a_f64_z_ui64_x.o test_a_f64_z_i32_x.o test_a_f64_z_i64_x.o test_a_f64_z_f16.o test_a_f64_z_f32.o test_a_f64_z_extF80.o test_a_f64_z_f128.o test_az_f64.o test_az_f64_rx.o test_abz_f64.o test_abcz_f64.o test_ab_f64_z_bool.o test_a_extF80_z_ui32_rx.o test_a_extF80_z_ui64_rx.o test_a_extF80_z_i32_rx.o test_a_extF80_z_i64_rx.o test_a_extF80_z_ui32_x.o test_a_extF80_z_ui64_x.o test_a_extF80_z_i32_x.o test_a_extF80_z_i64_x.o test_a_extF80_z_f16.o test_a_extF80_z_f32.o test_a_extF80_z_f64.o test_a_extF80_z_f128.o test_az_extF80.o test_az_extF80_rx.o test_abz_extF80.o test_ab_extF80_z_bool.o test_a_f128_z_ui32_rx.o test_a_f128_z_ui64_rx.o test_a_f128_z_i32_rx.o test_a_f128_z_i64_rx.o test_a_f128_z_ui32_x.o test_a_f128_z_ui64_x.o test_a_f128_z_i32_x.o test_a_f128_z_i64_x.o test_a_f128_z_f16.o test_a_f128_z_f32.o test_a_f128_z_f64.o test_a_f128_z_extF80.o test_az_f128.o test_az_f128_rx.o test_abz_f128.o test_abcz_f128.o test_ab_f128_z_bool.o testfloat.a
rm -f slowfloat.o testsoftfloat.o testsoftfloat
rm -f timesoftfloat.o timesoftfloat
rm -f genLoops.o testfloat_gen.o testfloat_gen
rm -f verLoops.o testfloat_ver.o testfloat_ver
rm -f subjfloat.o subjfloat_functions.o testfloat.o testfloat
rm -f /src/piet/cvw/cvw/tests/fp/combined_IF_vectors/IF_vectors/*.tv
make clean -C /src/piet/cvw/cvw/tests/coverage
rm -f *.elf *.objdump *.signature.output *.addr *.lab .memfile .o .s
make clean -C /src/piet/cvw/cvw/addins/cvw-arch-verif
rm -rf fcov/unpriv/
rm -rf tests/lockstep/rv64 tests/lockstep/rv32 tests/lockstep/priv/headers tests/lockstep/priv/rv64 tests/lockstep/priv/rv32 work
rm -rf tests/selfchecking/
rm -rf tests/signature/
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$ make
make -C sim
make -C /src/piet/cvw/cvw/tests/riscof
mkdir -p riscof_work
mkdir -p work/riscv-arch-test
sed 's,{0},/src/piet/cvw/cvw/tests/riscof,g;s,{1},32e,g;s,{2},27,g' config.ini > config32e.ini
riscof run --work-dir=./riscof_work/arch32e --config=config32e.ini --suite=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/ --env=/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env --no-browser
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.18.3
INFO | Reading configuration from: /src/piet/cvw/cvw/tests/riscof/config32e.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | ISACheck: Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_rv32e_isa.yaml
INFO | ISACheck: Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | ISACheck: Processing Hart:0
INFO | ISACheck: Initiating Validation for Hart:0
INFO | ISACheck: No errors for Hart:0
INFO | ISACheck: Updating fields node for each CSR in Hart:0
INFO | ISACheck: Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_rv32e_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /src/piet/cvw/cvw/tests/riscof/spike/spike_platform.yaml
INFO | Load Schema /opt/riscv/riscv-python/lib/python3.12/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/spike_platform_checked.yaml
INFO | Generating database for suite: /src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite
INFO | Database File Generated: /src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/database.yaml
INFO | Env path set to/src/piet/cvw/cvw/addins/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
ERROR | make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:53: TARGET12] Error 1
make[3]: *** Waiting for unfinished jobs....
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:21: TARGET4] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:25: TARGET5] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:57: TARGET13] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:61: TARGET14] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:65: TARGET15] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:69: TARGET16] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:73: TARGET17] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:77: TARGET18] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:81: TARGET19] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:89: TARGET21] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:93: TARGET22] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:97: TARGET23] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:105: TARGET25] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:109: TARGET26] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:45: TARGET10] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:49: TARGET11] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:37: TARGET8] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:41: TARGET9] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:9: TARGET1] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:5: TARGET0] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:33: TARGET7] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:17: TARGET3] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:13: TARGET2] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:29: TARGET6] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:85: TARGET20] Error 1
make[3]: *** [/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/Makefile.Reference-sail_c_simulator:101: TARGET24] Error 1
INFO | Initiating signature checking.
Traceback (most recent call last):
File "/opt/riscv/riscv-python/bin/riscof", line 8, in
sys.exit(cli())
^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1161, in call
return self.main(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1082, in main
rv = self.invoke(ctx)
^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1697, in invoke
return _process_result(sub_ctx.command.invoke(sub_ctx))
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 1443, in invoke
return ctx.invoke(self.callback, **ctx.params)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/core.py", line 788, in invoke
return __callback(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/decorators.py", line 33, in new_func
return f(get_current_context(), *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/cli.py", line 321, in run
report_objects['results'] = framework.run(dut, base, ctx.obj.isa_file,
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/main.py", line 209, in run
results = test.run_tests(dut, base, ispec['hart0'], pspec, work_dir, cntr_args)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 458, in run_tests
result, diff = compare_signature(res, ref)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 46, in compare_signature
file2_lines = open(file2, "r").readlines()
^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/rv32e_m/B/src/clmul-01.S/ref/Reference-sail_c_simulator.signature'
make[2]: *** [Makefile:27: arch32e] Error 1
rm config32e.ini
make[1]: *** [Makefile:16: riscoftests] Error 2
make: *** [Makefile:15: riscof] Error 2
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$

, in invoke
return __callback(*args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/click/decorators.py", line 33, in new_func
return f(get_current_context(), *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/cli.py", line 321, in run
report_objects['results'] = framework.run(dut, base, ctx.obj.isa_file,
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/main.py", line 209, in run
results = test.run_tests(dut, base, ispec['hart0'], pspec, work_dir, cntr_args)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 458, in run_tests
result, diff = compare_signature(res, ref)
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/opt/riscv/riscv-python/lib/python3.12/site-packages/riscof/framework/test.py", line 46, in compare_signature
file2_lines = open(file2, "r").readlines()
^^^^^^^^^^^^^^^^
FileNotFoundError: [Errno 2] No such file or directory: '/src/piet/cvw/cvw/tests/riscof/riscof_work/arch32e/rv32e_m/B/src/clmul-01.S/ref/Reference-sail_c_simulator.signature'
make[2]: *** [Makefile:27: arch32e] Error 1
rm config32e.ini
make[1]: *** [Makefile:16: riscoftests] Error 2
make: *** [Makefile:15: riscof] Error 2
(cvw) piet@piet-Precision-7780:/src/piet/cvw/cvw$

[jordancarlin]

Looks like that is a result of #1381. I'll try to get a fix in for that soon.

[PietDelaney]

Seems like a very long time for the build to be broken. No?

[PietDelaney]

Buildroot stopped after an error timing out on a WGET.
As I recall, starting the build again will delete the buildroot directory.
This is rather a silly build environment.

Sigh.

[PietDelaney]

When I looked at the makefile, it looked like the clean was only supposed to occur after a successful complete build.
It failed again, likely due to hibernation. Disabled it....

[PietDelaney]

Ramspeed is having trouble.

--2025-04-18 21:59:57-- http://www.alasir.com/software/ramspeed/ramspeed-2.6.0.tar.gz
Resolving www.alasir.com (www.alasir.com)... 2607:f130:0:ee::f7d9:915f, 74.48.183.199
Connecting to www.alasir.com (www.alasir.com)|2607:f130:0:ee::f7d9:915f|:80... failed: Connection timed out.
Connecting to www.alasir.com (www.alasir.com)|74.48.183.199|:80... ^[[Afailed: Connection timed out.
Retrying.

--2025-04-18 22:04:27-- (try: 2) http://www.alasir.com/software/ramspeed/ramspeed-2.6.0.tar.gz
Connecting to www.alasir.com (www.alasir.com)|2607:f130:0:ee::f7d9:915f|:80... failed: Connection timed out.
Connecting to www.alasir.com (www.alasir.com)|74.48.183.199|:80...

[PietDelaney]

Wondered about this possible fix:

The version combination of pip=20.2.4 and pip-tools=6.6.0 is not compatible. Either upgrade pip to >=21.2, or downgrade pip-tools to 5version combination of pip=20.2.4 and pip-tools=6.6.0 is not compatible. Either upgrade pip to >=21.2, or downgrade pip-tools to 5.5.

[PietDelaney]

Looks like Im using the version of python installed by the setup scripts:

(cvw) piet@piet-Precision-7780:/opt/riscv$ find . -name pip -print
./riscv-python/bin/pip
./riscv-python/lib/python3.12/site-packages/pip
./qemu/build/pyvenv/bin/pip
./qemu/build/pyvenv/lib/python3.12/site-packages/pip
./buildroot/output/build/host-python3-3.12.10/Tools/msi/pip
./buildroot/output/build/host-qemu-9.1.0/build/pyvenv/bin/pip
./buildroot/output/build/host-qemu-9.1.0/build/pyvenv/lib/python3.12/site-packages/pip
(cvw) piet@piet-Precision-7780:/opt/riscv$ python
python python3.12-config pythonflow-bpfcc
python3 python3-config pythongc-bpfcc
python3.12 pythoncalls-bpfcc pythonstat-bpfcc
(cvw) piet@piet-Precision-7780:/opt/riscv$ python
Python 3.12.3 (main, Feb 4 2025, 14:48:35) [GCC 13.3.0] on linux
Type "help", "copyright", "credits" or "license" for more information.

KeyboardInterrupt

quit
Use quit() or Ctrl-D (i.e. EOF) to exit

[PietDelaney]

Good News Rose, you repo builds Linux and boots fine. I didn't try the:

 Click the arrow next to "PARAM" and set FREQUENCY to "7500000"Click the arrow next to "PARAM" and set FREQUENCY to "7500000"

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

minicom

Welcome to minicom 2.9

OPTIONS: I18n
Port /dev/ttyUSB1, 21:00:13

Press CTRL-A Z for help on special keys

---

---

** Avnet/Digilent Arty Evaluation Board **
** LEDs and switches GPIO Demonstration **

---

---

**
Choose Task:
BTN0: Print PWM value.
BTN1: 'Cylon' LED display.
BTN2: Scrolling LED display.
BTN3: Return to this menu.

█▀█ █▀█ █▀█ █▀▀ █ █
█ █ █ █▄▀ █▄▄ ▄▄▄ █ █
█▄█ █▄█ █ █ █▄▄ ▀▄▀

---

\ \ / / / \ | | | | \ \ / /
\ \ __ / / / \ | | | | \ / /
\ / / / / /\ \ | | | | \ /
\ / / ____ \ | |___ | |___ | |
_/_/ // _|||| |__|

[0.05343] Initializing SPI Controller.
[0.05703] Initializing SD Card in SPI mode.
[0.06125] CMD0: Success, r = 0x01
[0.06435] CMD8: Success, 0x01000001AA
[0.06797] ACMD41: Success, r = 0x00
[0.30273] New clock frequency: 5000000
[0.30651] SD card is initialized.
[0.30968] Getting GPT information.
Blocks loaded: 1/1
[0.32238] Getting partition entries.
Blocks loaded: 1/1
[0.33526] Loading device tree at: 0x8F000000
Blocks loaded: 5/5
[0.35263] Loading OpenSBI at: 0x80000000
Blocks loaded: 535/535
[0.89596] Loading Linux Kernel at: 0x80200000
Blocks loaded: 169318/169318
[170.14144] Done! Flashing LEDs and jumping to OpenSBI...

OpenSBI v1.6

---

/ __ \ / | _ _ |
| | | | __ ___ _ __ | ( | |) || |
| | | | '_ \ / _ \ '_ \ ___ | _ < | |
| || | |) | __/ | | |) | |) || |
_/| ./ _|| ||/|____/|
| |
|_|

Platform Name : wally-virt,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 20000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform PMU Device : ---
Platform Reboot Device : ---
Platform Shutdown Device : ---
Platform Suspend Device : ---
Platform CPPC Device : ---
Firmware Base : 0x80000000
Firmware Size : 325 KB
Firmware RW Offset : 0x40000
Firmware RW Size : 69 KB
Firmware Heap Offset : 0x48000
Firmware Heap Size : 37 KB (total), 2 KB (reserved), 11 KB (used), 23 )
Firmware Scratch Size : 4096 B (total), 432 B (used), 3664 B (free)
Runtime SBI Version : 2.0
Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy
Experimental SBI Extensions : fwft,sse

Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000010000000-0x0000000010000fff M: (I,R,W) )
Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) )
Domain0 Region02 : 0x000000000c200000-0x000000000c20ffff M: (I,R,W) )
Domain0 Region03 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/)
Domain0 Region04 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/)
Domain0 Region05 : 0x000000000c000000-0x000000000c1fffff M: (I,R,W) )
Domain0 Region06 : 0x0000000000000000-0xffffffffffffffff M: () S/U: )
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x0000000082200000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Domain0 SysSuspend : yes

Boot HART ID : 0
Boot HART Domain : root
Boot HART Priv Version : v1.12
Boot HART Base ISA : rv64imafdcb
Boot HART ISA Extensions : sstc,zicntr,zihpm,zicboz,zicbom,svpbmt,svade,svadu
Boot HART PMP Count : 16
Boot HART PMP Granularity : 2 bits
Boot HART PMP Address Bits : 54
Boot HART MHPM Info : 18 (0xfff0d230)
Boot HART Debug Triggers : 0 triggers
Boot HART MIDELEG : 0x0000000000000222
Boot HART MEDELEG : 0x000000000000b108
[ 0.000000] Linux version 6.12.8 (piet@piet-Precision-7780) (riscv64-buildro5
[ 0.000000] Machine model: wally-virt,qemu
[ 0.000000] SBI specification v2.0 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x10006
[ 0.000000] SBI TIME extension detected
[ 0.000000] SBI IPI extension detected
[ 0.000000] SBI RFENCE extension detected
[ 0.000000] SBI DBCN extension detected
[ 0.000000] efi: UEFI not found.
[ 0.000000] INITRD: 0x84200000+0x01a44000 overlaps in-use memory region
[ 0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 Ki0
[ 0.000000] OF: reserved mem: 0x0000000080040000..0x000000008005ffff (128 Ki0
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000080000000-0x000000008fffffff]
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x000000008005ffff]
[ 0.000000] node 0: [mem 0x0000000080060000-0x000000008fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff]
[ 0.000000] riscv: base ISA extensions acdfim
[ 0.000000] riscv: ELF capabilities acdfim
[ 0.000000] Kernel command line: root=/dev/vda ro console=ttyS0,115200 logl7
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, )
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, l)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 65536
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 0MB
[ 0.000000] software IO TLB: area num 1.
[ 0.000000] software IO TLB: mapped [mem 0x000000008fbcd000-0x000000008fc0d0)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] fixmap : 0xffff8d7ffea00000 - 0xffff8d7fff000000 (6144 k)
[ 0.000000] pci io : 0xffff8d7fff000000 - 0xffff8d8000000000 ( 16 M)
[ 0.000000] vmemmap : 0xffff8d8000000000 - 0xffff8f8000000000 (2048 G)
[ 0.000000] vmalloc : 0xffff8f8000000000 - 0xffffaf8000000000 ( 32 T)
[ 0.000000] modules : 0xffffffff052ee000 - 0xffffffff80000000 (1965 M)
[ 0.000000] lowmem : 0xffffaf8000000000 - 0xffffaf8010000000 ( 256 M)
[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 M)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] riscv-intc: 64 local interrupts mapped
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycs
[ 0.000044] sched_clock: 64 bits at 20MHz, resolution 50ns, wraps every 4398s
[ 0.000691] riscv-timer: Timer interrupt in S-mode is available via sstc extn
[ 0.007911] Console: colour dummy device 80x25
[ 0.010087] Calibrating delay loop (skipped), value calculated using timer f)
[ 0.011302] pid_max: default: 32768 minimum: 301
[ 0.016460] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linea)
[ 0.017278] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, )
[ 0.117111] riscv: ELF compat mode unsupported
[ 0.118776] ASID allocator using 16 bits (65536 entries)
[ 0.132609] EFI services will not be available.
[ 0.134988] Memory: 170404K/262144K available (2790K kernel code, 4696K rwda)
[ 0.154389] devtmpfs: initialized
[ 0.221392] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ms
[ 0.223253] futex hash table entries: 256 (order: 1, 12288 bytes, linear)
[ 0.238462] DMI not present or invalid.
[ 0.244332] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
[ 0.247085] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic as
[ 0.292577] cpu0: Ratio of byte access time to unaligned word access is 7.92t
[ 0.491407] clocksource: Switched to clocksource riscv_clocksource
[ 1.256402] workingset: timestamp_bits=62 max_order=16 bucket_order=0
[ 1.332611] io scheduler mq-deadline registered
[ 1.333112] io scheduler kyber registered
[ 1.335049] io scheduler bfq registered
[ 1.824601] riscv-plic: plic@c000000: mapped 53 interrupts with 1 handlers f.
[ 9.417539] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[ 9.529538] printk: legacy console [ttyS0] disabled
[ 9.551113] 10000000.uart: ttyS0 at MMIO 0x10000000 (irq = 2, base_baud = 12A
[ 9.553455] printk: legacy console [ttyS0] enabled
[ 10.670434] sifive_spi 13000.spi: mapped; irq=3, cs=4
[ 10.854940] mmc_spi spi0.0: SD/MMC host mmc0, no WP, no poweroff, cd polling
[ 11.688402] debug_vm_pgtable: [debug_vm_pgtable ]: Validating archits
[ 12.626342] clk: Disabling unused clocks
[ 12.816791] mmc0: host does not support reading read-only switch, assuming we
[ 12.827139] mmc0: new SDXC card on SPI
[ 12.928277] mmcblk0: mmc0:0000 SR64G 59.5 GiB
[ 18.926134] mmcblk0: p1 p2 p3 p4
[ 45.541414] Freeing unused kernel image (initmem) memory: 73816K
[ 45.550200] Run /init as init process

init started: BusyBox v1.36.1 (2025-04-18 21:53:45 PDT)
Saving 256 bits of non-creditable seed for next boot
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Starting network: /etc/init.d/S40network: line 12: /sbin/ifup: not found
FAIL
Starting crond: OK
crond[61]: can't change directory to '/var/spool/cron/crontabs': No such file oy

BusyBox v1.36.1 (2025-04-18 21:53:45 PDT) built-in shell (ash)
Enter 'help' for a list of built-in commands.

Hello this ~/.profile is meant to demonstrate running some basic commands on Wa.
I am root
And I am on WallyHostname
Created myFile.txt and moved it to myDir. It contains:
Hello World!
And farewell!
Created myScript.sh. Running it yields:
Hello this is another example script
Created symLinkToMyScript.sh. Running it yields:
Hello this is another example script
Now let's remove all these example files and scripts
Here is disk usage:
Filesystem Size Used Available Use% Mounted on
devtmpfs 83.7M 0 83.7M 0% /dev
tmpfs 119.8M 0 119.8M 0% /dev/shm
tmpfs 119.8M 0 119.8M 0% /tmp
tmpfs 119.8M 12.0K 119.7M 0% /run
And here are the current processes:
PID USER VSZ STAT COMMAND
1 root 2160 S init
2 root 0 SW [kthreadd]
3 root 0 SW [pool_workqueue_]
4 root 0 IW< [kworker/R-slub_]
5 root 0 IW [kworker/0:0-eve]
6 root 0 IW< [kworker/0:0H]
7 root 0 IW [kworker/0:1-eve]
8 root 0 IW [kworker/u4:0-ev]
9 root 0 IW< [kworker/R-mm_pe]
10 root 0 SW [ksoftirqd/0]
11 root 0 SW [kdevtmpfs]
12 root 0 SW [khungtaskd]
13 root 0 SW [oom_reaper]
14 root 0 IW< [kworker/R-write]
15 root 0 SW [kcompactd0]
16 root 0 IW< [kworker/R-kbloc]
17 root 0 SW [kswapd0]
18 root 0 IW [kworker/u4:1-ev]
19 root 0 SW [spi0]
20 root 0 IW [kworker/u4:2-ev]
21 root 0 IW [kworker/0:2-eve]
22 root 0 IW< [kworker/R-mmc_c]
23 root 0 IW< [kworker/0:1H-kb]
46 root 2160 S /sbin/klogd -n
62 root 2160 S -/bin/sh
78 root 2160 R ps
And finally a login prompt.
WallyHostname login:
WallyHostname login: root
login[79]: root login on 'console'

BusyBox v1.36.1 (2025-04-18 21:53:45 PDT) built-in shell (ash)
Enter 'help' for a list of built-in commands.

ps

PID USER VSZ STAT COMMAND
1 root 2160 S init
2 root 0 SW [kthreadd]
3 root 0 SW [pool_workqueue_]
4 root 0 IW< [kworker/R-slub_]
5 root 0 IW [kworker/0:0-eve]
6 root 0 IW< [kworker/0:0H]
7 root 0 IW [kworker/0:1-eve]
8 root 0 IW [kworker/u4:0-ev]
9 root 0 IW< [kworker/R-mm_pe]
10 root 0 SW [ksoftirqd/0]
11 root 0 SW [kdevtmpfs]
12 root 0 SW [khungtaskd]
13 root 0 SW [oom_reaper]
14 root 0 IW< [kworker/R-write]
15 root 0 SW [kcompactd0]
16 root 0 IW< [kworker/R-kbloc]
17 root 0 SW [kswapd0]
18 root 0 IW [kworker/u4:1-ev]
19 root 0 SW [spi0]
20 root 0 IW [kworker/u4:2-ev]
21 root 0 IW [kworker/0:2-eve]
22 root 0 IW< [kworker/R-mmc_c]
23 root 0 IW< [kworker/0:1H-kb]
46 root 2160 S /sbin/klogd -n
62 root 2160 S -/bin/sh
79 root 2160 S -sh
81 root 2160 R ps

[ 199.206106] random: crng init done

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

[PietDelaney]

Wonder why your repo boots fine but the std repo isn't or wasnt.

I looked over the ILA documentation on line a bit.

Looks like a usefull tool, though JTAG and GDB seem like a more likely matched took as the processor was running fine.
Guess putting in breakpoints as you transistion between programs would take some practice.

I'll give your ILA debug suggestion a try now. Thanks.

[rosethompson]

Piet,

I am very pleased you got it working. I think @JacobPease might know why the standard repo won't work, but our custom one does. I know there are configuration options which are specific to Wally, but I thought everything was set by the device tree. Sounds like there is more to it.

Again, we currently don't support JTAG because Wally does not currently implement the Debug extension. This is something we wish to add in the future. Your struggles highlight just how important the D extension will be for software developers.

In the meantime you have a great deal more experience with Linux and the software environment than any of the hardware developers on our team. You've mentioned a few changes including JTAG, not using OpenSBI, and something with init ramfs (I can't recall what it was). Other than the D extension (JTAG), could you briefly summarize what you think should be changed and why?

[PietDelaney]

Most successful software projects I worked on put a higher priority with comments in the git commit messages as I recall. I liked the Gerrit commit code review protocol with robots testing builds during a commit. I really like the extensive documentation with Wally. Back in 1980 we had a book with line by line explanation of the complete version 6 UNIX kernel. I cut my teeth with a solo version 6 upgrade to v7 UNIX . Documentation is great. Thanks.

Saw a risc-v workstation recently released, 64 CPUs.
I found MMU and cache coherency very interesting.
I didn't notice a SMP risc-v extension. Wonder if Wally will
Eventually be complete enough for being a commercial basis.

I.have found FTrace important to be enabled in the kernel and working correctly.

Rose I pulled your repo but the sub-modules weren't included. So I updated the .git/config to include the sub-modules from the common tree. I got build problems with the top level
Make. The FPGA code compiled and ran fine. you have your git on a branch of the common git repo.

It would be nice if one or two of Yuri's class got more interested in Wally. The more fault free we can make the environment the more likely one of the guys will get more interested. Coming from a FPGA work environment he wasn't comfortable yet with the size of the projects framework. I'll try to understand the difference between your git repo and the common git repo.

-pete