diff --git a/README.md b/README.md index cefa9312..710eda9c 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ orpsoc-cores ============ -Core description files for ORPSoCv3 +Core description files for ORPSoCv3. +Support for Altera DE2 board added (alpha, written by Tran Cong Nam). diff --git a/cores/elf-loader/vpi_wrapper.c b/cores/elf-loader/vpi_wrapper.c index d5be84a4..b43e7dbf 100644 --- a/cores/elf-loader/vpi_wrapper.c +++ b/cores/elf-loader/vpi_wrapper.c @@ -1,3 +1,5 @@ +#include +#include #include #include "elf-loader.h" diff --git a/systems/de2/backend/rtl/verilog/pll.v b/systems/de2/backend/rtl/verilog/pll.v new file mode 100755 index 00000000..c3f34d76 --- /dev/null +++ b/systems/de2/backend/rtl/verilog/pll.v @@ -0,0 +1,377 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 11.0 Build 157 04/27/2011 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2011 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [5:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 1, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 5, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 1, + altpll_component.clk2_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.gate_lock_signal = "NO", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone II", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/systems/de2/data/de2.sdc b/systems/de2/data/de2.sdc new file mode 100755 index 00000000..aad4ab21 --- /dev/null +++ b/systems/de2/data/de2.sdc @@ -0,0 +1,8 @@ +# Main system clock (50 Mhz) +create_clock -name "sys_clk_pad_i" -period 20.000ns [get_ports {sys_clk_pad_i}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/systems/de2/data/options.tcl b/systems/de2/data/options.tcl new file mode 100755 index 00000000..2b66c97e --- /dev/null +++ b/systems/de2/data/options.tcl @@ -0,0 +1,17 @@ +# See Cyclone II FPGA Family Errata, needed for ddual-port dual-clock mode M4K +# (http://www.altera.com/support/kdb/solutions/fb27180.html) + +set_parameter -name CYCLONEII_SAFE_WRITE "VERIFIED_SAFE" + +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS_INPUT_TRI_STATED" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" + +# Make it pass STA + +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED diff --git a/systems/de2/data/pinmap.tcl b/systems/de2/data/pinmap.tcl new file mode 100755 index 00000000..440485a2 --- /dev/null +++ b/systems/de2/data/pinmap.tcl @@ -0,0 +1,208 @@ +# Clock / Reset + +set_location_assignment PIN_G26 -to rst_n_pad_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pad_i +set_location_assignment PIN_N2 -to sys_clk_pad_i +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i + +# SD card +#set_location_assignment PIN_V20 -to sd_clk_pad_o + +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_clk_pad_o +#set_location_assignment PIN_Y20 -to sd_cmd_pad_o +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_cmd_pad_o +#set_location_assignment PIN_W20 -to sd_dat_pad_i +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat_pad_i +#set_location_assignment PIN_U20 -to sd_dat3_pad_o +#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_dat3_pad_o + +# UART +set_location_assignment PIN_C25 -to uart0_srx_pad_i + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i +set_location_assignment PIN_B25 -to uart0_stx_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o + +# SDRAM +set_location_assignment PIN_T6 -to sdram_a_pad_o[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[0] +set_location_assignment PIN_V4 -to sdram_a_pad_o[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[1] +set_location_assignment PIN_V3 -to sdram_a_pad_o[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[2] +set_location_assignment PIN_W2 -to sdram_a_pad_o[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[3] +set_location_assignment PIN_W1 -to sdram_a_pad_o[4] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[4] +set_location_assignment PIN_U6 -to sdram_a_pad_o[5] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[5] +set_location_assignment PIN_U7 -to sdram_a_pad_o[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[6] +set_location_assignment PIN_U5 -to sdram_a_pad_o[7] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[7] +set_location_assignment PIN_W4 -to sdram_a_pad_o[8] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[8] +set_location_assignment PIN_W3 -to sdram_a_pad_o[9] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[9] +set_location_assignment PIN_Y1 -to sdram_a_pad_o[10] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[10] +set_location_assignment PIN_V5 -to sdram_a_pad_o[11] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_a_pad_o[11] + +set_location_assignment PIN_V6 -to sdram_dq_pad_io[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[0] +set_location_assignment PIN_AA2 -to sdram_dq_pad_io[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[1] +set_location_assignment PIN_AA1 -to sdram_dq_pad_io[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[2] +set_location_assignment PIN_Y3 -to sdram_dq_pad_io[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[3] +set_location_assignment PIN_Y4 -to sdram_dq_pad_io[4] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[4] +set_location_assignment PIN_R8 -to sdram_dq_pad_io[5] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[5] +set_location_assignment PIN_T8 -to sdram_dq_pad_io[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[6] +set_location_assignment PIN_V7 -to sdram_dq_pad_io[7] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[7] +set_location_assignment PIN_W6 -to sdram_dq_pad_io[8] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[8] +set_location_assignment PIN_AB2 -to sdram_dq_pad_io[9] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[9] +set_location_assignment PIN_AB1 -to sdram_dq_pad_io[10] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[10] +set_location_assignment PIN_AA4 -to sdram_dq_pad_io[11] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[11] +set_location_assignment PIN_AA3 -to sdram_dq_pad_io[12] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[12] +set_location_assignment PIN_AC2 -to sdram_dq_pad_io[13] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[13] +set_location_assignment PIN_AC1 -to sdram_dq_pad_io[14] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[14] +set_location_assignment PIN_AA5 -to sdram_dq_pad_io[15] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq_pad_io[15] + +set_location_assignment PIN_AD2 -to sdram_dqm_pad_o[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[0] +set_location_assignment PIN_Y5 -to sdram_dqm_pad_o[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm_pad_o[1] + +set_location_assignment PIN_AE2 -to sdram_ba_pad_o[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[0] +set_location_assignment PIN_AE3 -to sdram_ba_pad_o[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba_pad_o[1] + +set_location_assignment PIN_AB3 -to sdram_cas_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_pad_o + +set_location_assignment PIN_AA6 -to sdram_cke_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke_pad_o + +set_location_assignment PIN_AC3 -to sdram_cs_n_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n_pad_o + +set_location_assignment PIN_AB4 -to sdram_ras_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_pad_o + +set_location_assignment PIN_AD3 -to sdram_we_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o + +set_location_assignment PIN_AA7 -to sdram_clk_pad_o + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o + +# RED LED +set_location_assignment PIN_AE23 -to led_r_pad_o[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[0] +set_location_assignment PIN_AF23 -to led_r_pad_o[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[1] +set_location_assignment PIN_AB21 -to led_r_pad_o[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[2] +set_location_assignment PIN_AC22 -to led_r_pad_o[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[3] +set_location_assignment PIN_AD22 -to led_r_pad_o[4] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[4] +set_location_assignment PIN_AD23 -to led_r_pad_o[5] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[5] +set_location_assignment PIN_AD21 -to led_r_pad_o[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[6] +set_location_assignment PIN_AC21 -to led_r_pad_o[7] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[7] +set_location_assignment PIN_AA14 -to led_r_pad_o[8] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[8] +set_location_assignment PIN_Y13 -to led_r_pad_o[9] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_r_pad_o[9] + +# GREEN LED +set_location_assignment PIN_AE22 -to gpio0_io[0] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[0] +set_location_assignment PIN_AF22 -to gpio0_io[1] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[1] +set_location_assignment PIN_W19 -to gpio0_io[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[2] +set_location_assignment PIN_V18 -to gpio0_io[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[3] +set_location_assignment PIN_U18 -to gpio0_io[4] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[4] +set_location_assignment PIN_U17 -to gpio0_io[5] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[5] +set_location_assignment PIN_AA20 -to gpio0_io[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[6] +set_location_assignment PIN_Y18 -to gpio0_io[7] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio0_io[7] diff --git a/systems/de2/data/wb_intercon.conf b/systems/de2/data/wb_intercon.conf new file mode 100755 index 00000000..0fe144fc --- /dev/null +++ b/systems/de2/data/wb_intercon.conf @@ -0,0 +1,43 @@ +; or1k instruction bus master +[master or1k_i] +slaves = + sdram_ibus + rom0 + +; or1k data bus master +[master or1k_d] +slaves = + sdram_dbus + uart0 + gpio0 + +; debug master +[master dbg] +slaves = + sdram_dbus + uart0 + gpio0 + +[slave uart0] +datawidth=8 +offset=0x90000000 +size=32 + +[slave gpio0] +datawidth=8 +offset=0x91000000 +size=2 + +[slave rom0] +offset=0xf0000100 +size=64 + +; SDRAM +; Have several ports with buffering features, +; so we split each port into a seperate slave +[slave sdram_dbus] +offset=0 +size=0x2000000 ; 32MB +[slave sdram_ibus] +offset=0 +size=0x2000000 ; 32MB diff --git a/systems/generic/generic.core b/systems/de2/de2.core old mode 100644 new mode 100755 similarity index 53% rename from systems/generic/generic.core rename to systems/de2/de2.core index 63fbd072..db833b2c --- a/systems/generic/generic.core +++ b/systems/de2/de2.core @@ -1,16 +1,20 @@ CAPI=1 [main] -depend = - adv_debug_sys - dbg +depend = jtag_tap - jtag_vpi + wb_intercon + adv_debug_sys or1200 - elf-loader - ram_wb uart16550 + elf-loader vlog_tb_utils - wb_utils + jtag_vpi + wiredelay + wb_sdram_ctrl + mor1kx + mt48lc16m16a2 + gpio + altera_virtual_jtag simulators = icarus @@ -19,16 +23,22 @@ simulators = [verilog] src_files = rtl/verilog/clkgen.v - rtl/verilog/intgen.v - rtl/verilog/rom.v rtl/verilog/orpsoc_top.v + backend/rtl/verilog/pll.v + rtl/verilog/rom.v + rtl/verilog/wb_intercon.v + + include_files = rtl/verilog/include/or1200_defines.v rtl/verilog/include/orpsoc-defines.v - rtl/verilog/include/orpsoc-params.v rtl/verilog/include/timescale.v rtl/verilog/include/uart_defines.v + rtl/verilog/wb_intercon.vh + +[icarus] +iverilog_options = -DICARUS_SIM -DSIM -tb_src_files = - bench/uart_decoder.v - bench/orpsoc_tb.v +[modelsim] +vlog_options = +define+SIM +define+MODELSIM_SIM +vsim_options = -L altera_mf_ver -L altera_mf diff --git a/systems/de2/de2.core~origin_master b/systems/de2/de2.core~origin_master new file mode 100755 index 00000000..918bf988 --- /dev/null +++ b/systems/de2/de2.core~origin_master @@ -0,0 +1,44 @@ +CAPI=1 +[main] +depend = + jtag_tap + wb_intercon + adv_debug_sys + or1200 + uart16550 + or1k-elf-loader + vlog_tb_utils + jtag_vpi + wiredelay + wb_sdram_ctrl + mor1kx + mt48lc16m16a2 + gpio + altera_virtual_jtag + +simulators = + icarus + modelsim + +[verilog] +src_files = + rtl/verilog/clkgen.v + rtl/verilog/orpsoc_top.v + backend/rtl/verilog/pll.v + rtl/verilog/rom.v + rtl/verilog/wb_intercon.v + + +include_files = + rtl/verilog/include/or1200_defines.v + rtl/verilog/include/orpsoc-defines.v + rtl/verilog/include/timescale.v + rtl/verilog/include/uart_defines.v + rtl/verilog/wb_intercon.vh + +[icarus] +iverilog_options = -DICARUS_SIM -DSIM + +[modelsim] +vlog_options = +define+SIM +define+MODELSIM_SIM +vsim_options = -L altera_mf_ver -L altera_mf diff --git a/systems/de2/de2.system b/systems/de2/de2.system new file mode 100755 index 00000000..7d48909b --- /dev/null +++ b/systems/de2/de2.system @@ -0,0 +1,15 @@ +SAPI=1 +[main] +name = de2 +description = "Altera de2 board OpenRISC system" + +backend = quartus + +[quartus] +family = "Cyclone II" +device = EP2C35F672C6 +sdc_files = data/de2.sdc +tcl_files = data/pinmap.tcl + data/options.tcl + + diff --git a/systems/generic/rtl/verilog/clkgen.v b/systems/de2/rtl/verilog/clkgen.v old mode 100644 new mode 100755 similarity index 56% rename from systems/generic/rtl/verilog/clkgen.v rename to systems/de2/rtl/verilog/clkgen.v index d4606b00..08dd6278 --- a/systems/generic/rtl/verilog/clkgen.v +++ b/systems/de2/rtl/verilog/clkgen.v @@ -31,88 +31,98 @@ //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// -// -// A simple implementation for the main generic ORPSoC simulations -// `include "timescale.v" `include "orpsoc-defines.v" module clkgen - ( - // Main clocks in, depending on board - clk_pad_i, - - // Input reset - through a buffer, asynchronous - async_rst_o, - // Wishbone clock and reset out - wb_clk_o, - wb_rst_o, - - // JTAG clock -`ifdef JTAG_DEBUG - tck_pad_i, - dbg_tck_o, -`endif - - // Asynchronous, active low reset in - rst_n_pad_i - - ); - - input clk_pad_i; - - output async_rst_o; - - output wb_rst_o; - output wb_clk_o; - -`ifdef JTAG_DEBUG - input tck_pad_i; - output dbg_tck_o; -`endif - - // Asynchronous, active low reset (pushbutton, typically) - input rst_n_pad_i; - - // First, deal with the asychronous reset - wire async_rst_n; - - // An input buffer is usually instantiated here - assign async_rst_n = rst_n_pad_i; - - // Everyone likes active-high reset signals... - assign async_rst_o = ~async_rst_n; - -`ifdef JTAG_DEBUG - assign dbg_tck_o = tck_pad_i; +( + // Main clocks in, depending on board + input sys_clk_pad_i, + // Asynchronous, active low reset in + input rst_n_pad_i, + // Input reset - through a buffer, asynchronous + output async_rst_o, + + // Wishbone clock and reset out + output wb_clk_o, + output wb_rst_o, + + // JTAG clock +`ifdef SIM + input tck_pad_i, + output dbg_tck_o, +`endif + + // Main memory clocks + output sdram_clk_o, + output sdram_rst_o +); + +// First, deal with the asychronous reset +wire async_rst; +wire async_rst_n; + +assign async_rst_n = rst_n_pad_i; +assign async_rst = ~async_rst_n; + +// Everyone likes active-high reset signals... +assign async_rst_o = ~async_rst_n; + +`ifdef SIM +assign dbg_tck_o = tck_pad_i; +`endif + +// +// Declare synchronous reset wires here +// + +// An active-low synchronous reset signal (usually a PLL lock signal) +wire sync_rst_n; + +wire pll_lock; + +`ifndef SIM +pll pll0 ( + .areset (async_rst), + .inclk0 (sys_clk_pad_i), + .c0 (sdram_clk_o), + .c1 (wb_clk_o), + .locked (pll_lock) +); +`else +assign sdram_clk_o = sys_clk_pad_i; +assign wb_clk_o = sys_clk_pad_i; +assign pll_lock = 1'b1; `endif - // - // Declare synchronous reset wires here - // - - // An active-low synchronous reset signal (usually a PLL lock signal) - wire sync_rst_n; - assign sync_rst_n = async_rst_n; // Pretend it's somehow synchronous now - - - // Here we just assign "board" clock (really test) to wishbone clock - assign wb_clk_o = clk_pad_i; - - // - // Reset generation - // - // - - // Reset generation for wishbone - reg [15:0] wb_rst_shr; - always @(posedge wb_clk_o or posedge async_rst_o) - if (async_rst_o) - wb_rst_shr <= 16'hffff; - else - wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)}; - - assign wb_rst_o = wb_rst_shr[15]; - +assign sync_rst_n = pll_lock; + +// +// Reset generation +// +// + +// Reset generation for wishbone +reg [15:0] wb_rst_shr; + +always @(posedge wb_clk_o or posedge async_rst) + if (async_rst) + wb_rst_shr <= 16'hffff; + else + wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)}; + +assign wb_rst_o = wb_rst_shr[15]; + +// Reset generation for SDRAM controller +reg [15:0] sdram_rst_shr; + +always @(posedge sdram_clk_o or posedge async_rst) + if (async_rst) + sdram_rst_shr <= 16'hffff; + else + sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)}; + +assign sdram_rst_o = sdram_rst_shr[15]; + endmodule // clkgen diff --git a/systems/generic/rtl/verilog/include/or1200_defines.v b/systems/de2/rtl/verilog/include/or1200_defines.v old mode 100644 new mode 100755 similarity index 99% rename from systems/generic/rtl/verilog/include/or1200_defines.v rename to systems/de2/rtl/verilog/include/or1200_defines.v index bdfcc838..840f66f6 --- a/systems/generic/rtl/verilog/include/or1200_defines.v +++ b/systems/de2/rtl/verilog/include/or1200_defines.v @@ -119,14 +119,14 @@ // // Target FPGA memories // -//`define OR1200_ALTERA_LPM +`define OR1200_ALTERA_LPM //`define OR1200_XILINX_RAMB16 //`define OR1200_XILINX_RAMB4 //`define OR1200_XILINX_RAM32X1D //`define OR1200_USE_RAM16X1D_FOR_RAM32X1D // Generic models should infer RAM blocks at synthesis time (not only effects // single port ram.) -`define OR1200_GENERIC +//`define OR1200_GENERIC // // Do not implement Data cache @@ -299,7 +299,7 @@ // If you don't use them, then disable implementation // to save area. // -`define OR1200_IMPL_ADDC +//`define OR1200_IMPL_ADDC // // Implement l.sub instruction @@ -321,7 +321,7 @@ // instructions and if these three insns are not // implemented there is not much point having SR[CY]. // -`define OR1200_IMPL_CY +//`define OR1200_IMPL_CY // // Implement carry bit SR[OV] @@ -329,7 +329,7 @@ // Compiler doesn't use this, but other code may like // to. // -`define OR1200_IMPL_OV +//`define OR1200_IMPL_OV // // Implement carry bit SR[OVE] @@ -337,7 +337,7 @@ // Overflow interrupt indicator. When enabled, SR[OV] flag // does not remain asserted after exception. // -`define OR1200_IMPL_OVE +//`define OR1200_IMPL_OVE // @@ -359,12 +359,12 @@ // // Type of ALU compare to implement // -// Try to find which synthesizes with -// most efficient logic use or highest speed. +// Try either one to find what yields +// higher clock frequencyin your case. // //`define OR1200_IMPL_ALU_COMP1 -//`define OR1200_IMPL_ALU_COMP2 -`define OR1200_IMPL_ALU_COMP3 +`define OR1200_IMPL_ALU_COMP2 +//`define OR1200_IMPL_ALU_COMP3 // // Implement Find First/Last '1' @@ -379,7 +379,7 @@ // // Implement l.extXs and l.extXz instructions // -`define OR1200_IMPL_ALU_EXT +//`define OR1200_IMPL_ALU_EXT // // Implement multiplier @@ -395,7 +395,7 @@ // implement MAC, multiplier (non-serial) needs to be // implemented. // -`define OR1200_MAC_IMPLEMENTED +//`define OR1200_MAC_IMPLEMENTED // // Implement optional l.div/l.divu instructions @@ -409,7 +409,7 @@ // // Serial multiplier. // -//`define OR1200_MULT_SERIAL +`define OR1200_MULT_SERIAL // // Serial divider. @@ -421,7 +421,7 @@ // // Implement HW Single Precision FPU // -`define OR1200_FPU_IMPLEMENTED +//`define OR1200_FPU_IMPLEMENTED // // Clock ratio RISC clock versus WB clock @@ -1069,7 +1069,7 @@ `define OR1200_PIC_IMPLEMENTED // Define number of interrupt inputs (2-31) -`define OR1200_PIC_INTS 20 +`define OR1200_PIC_INTS 31 // Address offsets of PIC registers inside PIC group `define OR1200_PIC_OFS_PICMR 2'd0 @@ -1820,5 +1820,5 @@ //`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f //`define OR1200_BOOT_ADR 32'hf0000100 // Boot from 0x100 - `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f - `define OR1200_BOOT_ADR 32'h00000100 +`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f +`define OR1200_BOOT_ADR 32'h00000100 diff --git a/systems/generic/rtl/verilog/include/orpsoc-defines.v b/systems/de2/rtl/verilog/include/orpsoc-defines.v old mode 100644 new mode 100755 similarity index 97% rename from systems/generic/rtl/verilog/include/orpsoc-defines.v rename to systems/de2/rtl/verilog/include/orpsoc-defines.v index 57c5c497..af1605e8 --- a/systems/generic/rtl/verilog/include/orpsoc-defines.v +++ b/systems/de2/rtl/verilog/include/orpsoc-defines.v @@ -34,9 +34,6 @@ ////////////////////////////////////////////////////////////////////// // Included modules: define to include -`define JTAG_DEBUG -`define UART0 -`define RAM_WB -`define INTGEN `define BOOTROM +`define OR1200_CPU // end of included module defines - keep this comment line here diff --git a/systems/de2/rtl/verilog/include/timescale.v b/systems/de2/rtl/verilog/include/timescale.v new file mode 100755 index 00000000..e66f979c --- /dev/null +++ b/systems/de2/rtl/verilog/include/timescale.v @@ -0,0 +1 @@ +`timescale 1ns/1ps diff --git a/systems/generic/rtl/verilog/include/uart_defines.v b/systems/de2/rtl/verilog/include/uart_defines.v old mode 100644 new mode 100755 similarity index 99% rename from systems/generic/rtl/verilog/include/uart_defines.v rename to systems/de2/rtl/verilog/include/uart_defines.v index d67b3b4a..f9c567a1 --- a/systems/generic/rtl/verilog/include/uart_defines.v +++ b/systems/de2/rtl/verilog/include/uart_defines.v @@ -240,11 +240,11 @@ `define FAST_TEST 1 // 64/1024 packets are sent // Defines hard baud prescaler register - uncomment to enable -`define PRESCALER_PRESET_HARD +//`define PRESCALER_PRESET_HARD // 115200 baud preset values // 20MHz: prescaler 10.8 (11, rounded up) //`define PRESCALER_HIGH_PRESET 8'd0 //`define PRESCALER_LOW_PRESET 8'd11 // 50MHz: prescaler 27.1 -`define PRESCALER_HIGH_PRESET 8'd0 -`define PRESCALER_LOW_PRESET 8'd27 +//`define PRESCALER_HIGH_PRESET 8'd0 +//`define PRESCALER_LOW_PRESET 8'd27 diff --git a/systems/de2/rtl/verilog/orpsoc_top.v b/systems/de2/rtl/verilog/orpsoc_top.v new file mode 100755 index 00000000..4975e096 --- /dev/null +++ b/systems/de2/rtl/verilog/orpsoc_top.v @@ -0,0 +1,705 @@ +////////////////////////////////////////////////////////////////////// +/// //// +/// ORPSoC top for Altera de1 board //// +/// //// +/// Franck Jullien, franck.jullien@gmail.com //// +/// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "orpsoc-defines.v" + +module orpsoc_top #( + parameter rom0_aw = 6, + parameter uart0_aw = 3 +) +( + input sys_clk_pad_i, + input rst_n_pad_i, + + output [9:0] led_r_pad_o, + inout [7:0] gpio0_io, + +`ifdef SIM + output tdo_pad_o, + input tms_pad_i, + input tck_pad_i, + input tdi_pad_i, +`endif + + output [1:0] sdram_ba_pad_o, + output [11:0] sdram_a_pad_o, + output sdram_cs_n_pad_o, + output sdram_ras_pad_o, + output sdram_cas_pad_o, + output sdram_we_pad_o, + inout [15:0] sdram_dq_pad_io, + output [1:0] sdram_dqm_pad_o, + output sdram_cke_pad_o, + output sdram_clk_pad_o, + + input uart0_srx_pad_i, + output uart0_stx_pad_o +); + +parameter IDCODE_VALUE = 32'h14951185; + +//////////////////////////////////////////////////////////////////////// +// +// Clock and reset generation module +// +//////////////////////////////////////////////////////////////////////// + +wire async_rst; +wire wb_clk, wb_rst; +wire dbg_tck; +wire sdram_clk; +wire sdram_rst; + +assign sdram_clk_pad_o = sdram_clk; + +clkgen clkgen0 ( + .sys_clk_pad_i (sys_clk_pad_i), + .rst_n_pad_i (rst_n_pad_i), + .async_rst_o (async_rst), + .wb_clk_o (wb_clk), + .wb_rst_o (wb_rst), +`ifdef SIM + .tck_pad_i (tck_pad_i), + .dbg_tck_o (dbg_tck), +`endif + .sdram_clk_o (sdram_clk), + .sdram_rst_o (sdram_rst) +); + +//////////////////////////////////////////////////////////////////////// +// +// Modules interconnections +// +//////////////////////////////////////////////////////////////////////// + +`include "wb_intercon.vh" + +`ifdef SIM +//////////////////////////////////////////////////////////////////////// +// +// GENERIC JTAG TAP +// +//////////////////////////////////////////////////////////////////////// + +wire dbg_if_select; +wire dbg_if_tdo; +wire jtag_tap_tdo; +wire jtag_tap_shift_dr; +wire jtag_tap_pause_dr; +wire jtag_tap_update_dr; +wire jtag_tap_capture_dr; + +tap_top #(.IDCODE_VALUE(IDCODE_VALUE)) +jtag_tap0 ( + .tdo_pad_o (tdo_pad_o), + .tms_pad_i (tms_pad_i), + .tck_pad_i (dbg_tck), + .trst_pad_i (async_rst), + .tdi_pad_i (tdi_pad_i), + + .tdo_padoe_o (tdo_padoe_o), + + .tdo_o (jtag_tap_tdo), + + .shift_dr_o (jtag_tap_shift_dr), + .pause_dr_o (jtag_tap_pause_dr), + .update_dr_o (jtag_tap_update_dr), + .capture_dr_o (jtag_tap_capture_dr), + + .extest_select_o (), + .sample_preload_select_o (), + .mbist_select_o (), + .debug_select_o (dbg_if_select), + + + .bs_chain_tdi_i (1'b0), + .mbist_tdi_i (1'b0), + .debug_tdi_i (dbg_if_tdo) +); + +`else +//////////////////////////////////////////////////////////////////////// +// +// ALTERA Virtual JTAG TAP +// +//////////////////////////////////////////////////////////////////////// + +wire dbg_if_select; +wire dbg_if_tdo; +wire jtag_tap_tdo; +wire jtag_tap_shift_dr; +wire jtag_tap_pause_dr; +wire jtag_tap_update_dr; +wire jtag_tap_capture_dr; + +altera_virtual_jtag jtag_tap0 ( + .tck_o (dbg_tck), + .debug_tdo_i (dbg_if_tdo), + .tdi_o (jtag_tap_tdo), + .test_logic_reset_o (), + .run_test_idle_o (), + .shift_dr_o (jtag_tap_shift_dr), + .capture_dr_o (jtag_tap_capture_dr), + .pause_dr_o (jtag_tap_pause_dr), + .update_dr_o (jtag_tap_update_dr), + .debug_select_o (dbg_if_select) +); +`endif + +//////////////////////////////////////////////////////////////////////// +// +// OR1K CPU +// +//////////////////////////////////////////////////////////////////////// + +wire [31:0] or1k_irq; + +wire [31:0] or1k_dbg_dat_i; +wire [31:0] or1k_dbg_adr_i; +wire or1k_dbg_we_i; +wire or1k_dbg_stb_i; +wire or1k_dbg_ack_o; +wire [31:0] or1k_dbg_dat_o; + +wire or1k_dbg_stall_i; +wire or1k_dbg_ewt_i; +wire [3:0] or1k_dbg_lss_o; +wire [1:0] or1k_dbg_is_o; +wire [10:0] or1k_dbg_wp_o; +wire or1k_dbg_bp_o; +wire or1k_dbg_rst; + +wire sig_tick; +wire or1k_rst; + +assign or1k_rst = wb_rst | or1k_dbg_rst; + +`ifdef OR1200_CPU + +or1200_top #(.boot_adr(32'hf0000100)) +or1200_top0 ( + // Instruction bus, clocks, reset + .iwb_clk_i (wb_clk), + .iwb_rst_i (wb_rst), + .iwb_ack_i (wb_s2m_or1k_i_ack), + .iwb_err_i (wb_s2m_or1k_i_err), + .iwb_rty_i (wb_s2m_or1k_i_rty), + .iwb_dat_i (wb_s2m_or1k_i_dat), + + .iwb_cyc_o (wb_m2s_or1k_i_cyc), + .iwb_adr_o (wb_m2s_or1k_i_adr), + .iwb_stb_o (wb_m2s_or1k_i_stb), + .iwb_we_o (wb_m2s_or1k_i_we), + .iwb_sel_o (wb_m2s_or1k_i_sel), + .iwb_dat_o (wb_m2s_or1k_i_dat), + .iwb_cti_o (wb_m2s_or1k_i_cti), + .iwb_bte_o (wb_m2s_or1k_i_bte), + + // Data bus, clocks, reset + .dwb_clk_i (wb_clk), + .dwb_rst_i (wb_rst), + .dwb_ack_i (wb_s2m_or1k_d_ack), + .dwb_err_i (wb_s2m_or1k_d_err), + .dwb_rty_i (wb_s2m_or1k_d_rty), + .dwb_dat_i (wb_s2m_or1k_d_dat), + + .dwb_cyc_o (wb_m2s_or1k_d_cyc), + .dwb_adr_o (wb_m2s_or1k_d_adr), + .dwb_stb_o (wb_m2s_or1k_d_stb), + .dwb_we_o (wb_m2s_or1k_d_we), + .dwb_sel_o (wb_m2s_or1k_d_sel), + .dwb_dat_o (wb_m2s_or1k_d_dat), + .dwb_cti_o (wb_m2s_or1k_d_cti), + .dwb_bte_o (wb_m2s_or1k_d_bte), + + // Debug interface ports + .dbg_stall_i (or1k_dbg_stall_i), + .dbg_ewt_i (1'b0), + .dbg_lss_o (or1k_dbg_lss_o), + .dbg_is_o (or1k_dbg_is_o), + .dbg_wp_o (or1k_dbg_wp_o), + .dbg_bp_o (or1k_dbg_bp_o), + + .dbg_adr_i (or1k_dbg_adr_i), + .dbg_we_i (or1k_dbg_we_i), + .dbg_stb_i (or1k_dbg_stb_i), + .dbg_dat_i (or1k_dbg_dat_i), + .dbg_dat_o (or1k_dbg_dat_o), + .dbg_ack_o (or1k_dbg_ack_o), + + .pm_clksd_o (), + .pm_dc_gate_o (), + .pm_ic_gate_o (), + .pm_dmmu_gate_o (), + .pm_immu_gate_o (), + .pm_tt_gate_o (), + .pm_cpu_gate_o (), + .pm_wakeup_o (), + .pm_lvolt_o (), + + // Core clocks, resets + .clk_i (wb_clk), + .rst_i (or1k_rst), + + .clmode_i (2'b00), + + // Interrupts + .pic_ints_i (or1k_irq[30:0]), + .sig_tick (sig_tick), + + .pm_cpustall_i (1'b0) +); + +`else + +mor1kx #( + .FEATURE_DEBUGUNIT ("ENABLED"), + .FEATURE_CMOV ("ENABLED"), + .FEATURE_INSTRUCTIONCACHE ("ENABLED"), + .OPTION_ICACHE_BLOCK_WIDTH (5), + .OPTION_ICACHE_SET_WIDTH (3), + .OPTION_ICACHE_WAYS (2), + .OPTION_ICACHE_LIMIT_WIDTH (32), + .FEATURE_IMMU ("ENABLED"), + .FEATURE_DATACACHE ("ENABLED"), + .OPTION_DCACHE_BLOCK_WIDTH (5), + .OPTION_DCACHE_SET_WIDTH (3), + .OPTION_DCACHE_WAYS (2), + .OPTION_DCACHE_LIMIT_WIDTH (31), + .FEATURE_DMMU ("ENABLED"), + .OPTION_PIC_TRIGGER ("LATCHED_LEVEL"), + + .IBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"), + .DBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"), + .OPTION_CPU0 ("CAPPUCCINO"), + .OPTION_RESET_PC (32'hf0000100) +) mor1kx0 ( + .iwbm_adr_o (wb_m2s_or1k_i_adr), + .iwbm_stb_o (wb_m2s_or1k_i_stb), + .iwbm_cyc_o (wb_m2s_or1k_i_cyc), + .iwbm_sel_o (wb_m2s_or1k_i_sel), + .iwbm_we_o (wb_m2s_or1k_i_we), + .iwbm_cti_o (wb_m2s_or1k_i_cti), + .iwbm_bte_o (wb_m2s_or1k_i_bte), + .iwbm_dat_o (wb_m2s_or1k_i_dat), + + .dwbm_adr_o (wb_m2s_or1k_d_adr), + .dwbm_stb_o (wb_m2s_or1k_d_stb), + .dwbm_cyc_o (wb_m2s_or1k_d_cyc), + .dwbm_sel_o (wb_m2s_or1k_d_sel), + .dwbm_we_o (wb_m2s_or1k_d_we ), + .dwbm_cti_o (wb_m2s_or1k_d_cti), + .dwbm_bte_o (wb_m2s_or1k_d_bte), + .dwbm_dat_o (wb_m2s_or1k_d_dat), + + .clk (wb_clk), + .rst (or1k_rst), + + .iwbm_err_i (wb_s2m_or1k_i_err), + .iwbm_ack_i (wb_s2m_or1k_i_ack), + .iwbm_dat_i (wb_s2m_or1k_i_dat), + .iwbm_rty_i (wb_s2m_or1k_i_rty), + + .dwbm_err_i (wb_s2m_or1k_d_err), + .dwbm_ack_i (wb_s2m_or1k_d_ack), + .dwbm_dat_i (wb_s2m_or1k_d_dat), + .dwbm_rty_i (wb_s2m_or1k_d_rty), + + .irq_i (or1k_irq), + + .du_addr_i (or1k_dbg_adr_i[15:0]), + .du_stb_i (or1k_dbg_stb_i), + .du_dat_i (or1k_dbg_dat_i), + .du_we_i (or1k_dbg_we_i), + .du_dat_o (or1k_dbg_dat_o), + .du_ack_o (or1k_dbg_ack_o), + .du_stall_i (or1k_dbg_stall_i), + .du_stall_o (or1k_dbg_bp_o) +); +`endif + +//////////////////////////////////////////////////////////////////////// +// +// Debug Interface +// +//////////////////////////////////////////////////////////////////////// + +adbg_top dbg_if0 ( + // OR1K interface + .cpu0_clk_i (wb_clk), + .cpu0_rst_o (or1k_dbg_rst), + .cpu0_addr_o (or1k_dbg_adr_i), + .cpu0_data_o (or1k_dbg_dat_i), + .cpu0_stb_o (or1k_dbg_stb_i), + .cpu0_we_o (or1k_dbg_we_i), + .cpu0_data_i (or1k_dbg_dat_o), + .cpu0_ack_i (or1k_dbg_ack_o), + .cpu0_stall_o (or1k_dbg_stall_i), + .cpu0_bp_i (or1k_dbg_bp_o), + + // TAP interface + .tck_i (dbg_tck), + .tdi_i (jtag_tap_tdo), + .tdo_o (dbg_if_tdo), + .rst_i (wb_rst), + .capture_dr_i (jtag_tap_capture_dr), + .shift_dr_i (jtag_tap_shift_dr), + .pause_dr_i (jtag_tap_pause_dr), + .update_dr_i (jtag_tap_update_dr), + .debug_select_i (dbg_if_select), + + // Wishbone debug master + .wb_clk_i (wb_clk), + .wb_dat_i (wb_s2m_dbg_dat), + .wb_ack_i (wb_s2m_dbg_ack), + .wb_err_i (wb_s2m_dbg_err), + + .wb_adr_o (wb_m2s_dbg_adr), + .wb_dat_o (wb_m2s_dbg_dat), + .wb_cyc_o (wb_m2s_dbg_cyc), + .wb_stb_o (wb_m2s_dbg_stb), + .wb_sel_o (wb_m2s_dbg_sel), + .wb_we_o (wb_m2s_dbg_we), + .wb_cti_o (wb_m2s_dbg_cti), + .wb_bte_o (wb_m2s_dbg_bte) +); + +//////////////////////////////////////////////////////////////////////// +// +// ROM +// +//////////////////////////////////////////////////////////////////////// + +assign wb_s2m_rom0_err = 1'b0; +assign wb_s2m_rom0_rty = 1'b0; + +`ifdef BOOTROM +rom #(.ADDR_WIDTH(rom0_aw)) +rom0 ( + .wb_clk (wb_clk), + .wb_rst (wb_rst), + .wb_adr_i (wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]), + .wb_cyc_i (wb_m2s_rom0_cyc), + .wb_stb_i (wb_m2s_rom0_stb), + .wb_cti_i (wb_m2s_rom0_cti), + .wb_bte_i (wb_m2s_rom0_bte), + .wb_dat_o (wb_s2m_rom0_dat), + .wb_ack_o (wb_s2m_rom0_ack) +); +`else +assign wb_s2m_rom0_dat_o = 0; +assign wb_s2m_rom0_ack_o = 0; +`endif + +//////////////////////////////////////////////////////////////////////// +// +// SDRAM Memory Controller +// +//////////////////////////////////////////////////////////////////////// + +wire [15:0] sdram_dq_i; +wire [15:0] sdram_dq_o; +wire sdram_dq_oe; + +assign sdram_dq_i = sdram_dq_pad_io; +assign sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz; +assign sdram_clk_pad_o = sdram_clk; + +assign wb_s2m_sdram_ibus_err = 0; +assign wb_s2m_sdram_ibus_rty = 0; + +assign wb_s2m_sdram_dbus_err = 0; +assign wb_s2m_sdram_dbus_rty = 0; + +wb_sdram_ctrl #( +`ifdef ICARUS_SIM + .TECHNOLOGY ("GENERIC"), +`else + .TECHNOLOGY ("ALTERA"), +`endif + .CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ +`ifdef SIM + .POWERUP_DELAY (1), // power up delay in us +`endif + .WB_PORTS (2), // Number of wishbone ports + .BUF_WIDTH (3), + .BURST_LENGTH (8), + .ROW_WIDTH (12), // Row width + .COL_WIDTH (8), // Column width + .BA_WIDTH (2), // Ba width + .tCAC (3), // CAS Latency + .tRAC (5), // RAS Latency + .tRP (3), // Command Period (PRE to ACT) + .tRC (7), // Command Period (REF to REF / ACT to ACT) + .tMRD (2) // Mode Register Set To Command Delay time +) + +wb_sdram_ctrl0 ( + // External SDRAM interface + .ba_pad_o (sdram_ba_pad_o[1:0]), + .a_pad_o (sdram_a_pad_o[11:0]), + .cs_n_pad_o (sdram_cs_n_pad_o), + .ras_pad_o (sdram_ras_pad_o), + .cas_pad_o (sdram_cas_pad_o), + .we_pad_o (sdram_we_pad_o), + .dq_i (sdram_dq_i[15:0]), + .dq_o (sdram_dq_o[15:0]), + .dqm_pad_o (sdram_dqm_pad_o[1:0]), + .dq_oe (sdram_dq_oe), + .cke_pad_o (sdram_cke_pad_o), + + .sdram_clk (sdram_clk), + .sdram_rst (sdram_rst), + + .wb_clk (wb_clk), + .wb_rst (wb_rst), + + .wb_adr_i ({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}), + .wb_stb_i ({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}), + .wb_cyc_i ({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}), + .wb_cti_i ({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}), + .wb_bte_i ({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}), + .wb_we_i ({wb_m2s_sdram_ibus_we, wb_m2s_sdram_dbus_we }), + .wb_sel_i ({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}), + .wb_dat_i ({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}), + .wb_dat_o ({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}), + .wb_ack_o ({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack}) +); + +//////////////////////////////////////////////////////////////////////// +// +// UART0 +// +//////////////////////////////////////////////////////////////////////// + +wire uart0_irq; + +wire [31:0] wb8_m2s_uart0_adr; +wire [1:0] wb8_m2s_uart0_bte; +wire [2:0] wb8_m2s_uart0_cti; +wire wb8_m2s_uart0_cyc; +wire [7:0] wb8_m2s_uart0_dat; +wire wb8_m2s_uart0_stb; +wire wb8_m2s_uart0_we; +wire [7:0] wb8_s2m_uart0_dat; +wire wb8_s2m_uart0_ack; +wire wb8_s2m_uart0_err; +wire wb8_s2m_uart0_rty; + +assign wb8_s2m_uart0_err = 0; +assign wb8_s2m_uart0_rty = 0; + +uart_top uart16550_0 ( + // Wishbone slave interface + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_adr_i (wb8_m2s_uart0_adr[uart0_aw-1:0]), + .wb_dat_i (wb8_m2s_uart0_dat), + .wb_we_i (wb8_m2s_uart0_we), + .wb_stb_i (wb8_m2s_uart0_stb), + .wb_cyc_i (wb8_m2s_uart0_cyc), + .wb_sel_i (4'b0), // Not used in 8-bit mode + .wb_dat_o (wb8_s2m_uart0_dat), + .wb_ack_o (wb8_s2m_uart0_ack), + + // Outputs + .int_o (uart0_irq), + .stx_pad_o (uart0_stx_pad_o), + .rts_pad_o (), + .dtr_pad_o (), + + // Inputs + .srx_pad_i (uart0_srx_pad_i), + .cts_pad_i (1'b0), + .dsr_pad_i (1'b0), + .ri_pad_i (1'b0), + .dcd_pad_i (1'b0) +); + +// 32-bit to 8-bit wishbone bus resize +wb_data_resize wb_data_resize_uart0 ( + // Wishbone Master interface + .wbm_adr_i (wb_m2s_uart0_adr), + .wbm_dat_i (wb_m2s_uart0_dat), + .wbm_sel_i (wb_m2s_uart0_sel), + .wbm_we_i (wb_m2s_uart0_we ), + .wbm_cyc_i (wb_m2s_uart0_cyc), + .wbm_stb_i (wb_m2s_uart0_stb), + .wbm_cti_i (wb_m2s_uart0_cti), + .wbm_bte_i (wb_m2s_uart0_bte), + .wbm_dat_o (wb_s2m_uart0_dat), + .wbm_ack_o (wb_s2m_uart0_ack), + .wbm_err_o (wb_s2m_uart0_err), + .wbm_rty_o (wb_s2m_uart0_rty), + + // Wishbone Slave interface + .wbs_adr_o (wb8_m2s_uart0_adr), + .wbs_dat_o (wb8_m2s_uart0_dat), + .wbs_we_o (wb8_m2s_uart0_we ), + .wbs_cyc_o (wb8_m2s_uart0_cyc), + .wbs_stb_o (wb8_m2s_uart0_stb), + .wbs_cti_o (wb8_m2s_uart0_cti), + .wbs_bte_o (wb8_m2s_uart0_bte), + .wbs_dat_i (wb8_s2m_uart0_dat), + .wbs_ack_i (wb8_s2m_uart0_ack), + .wbs_err_i (wb8_s2m_uart0_err), + .wbs_rty_i (wb8_s2m_uart0_rty) +); + +//////////////////////////////////////////////////////////////////////// +// +// GPIO 0 +// +//////////////////////////////////////////////////////////////////////// + +wire [7:0] gpio0_in; +wire [7:0] gpio0_out; +wire [7:0] gpio0_dir; + +wire [31:0] wb8_m2s_gpio0_adr; +wire [1:0] wb8_m2s_gpio0_bte; +wire [2:0] wb8_m2s_gpio0_cti; +wire wb8_m2s_gpio0_cyc; +wire [7:0] wb8_m2s_gpio0_dat; +wire wb8_m2s_gpio0_stb; +wire wb8_m2s_gpio0_we; +wire [7:0] wb8_s2m_gpio0_dat; +wire wb8_s2m_gpio0_ack; +wire wb8_s2m_gpio0_err; +wire wb8_s2m_gpio0_rty; + +// Tristate logic for IO +// 0 = input, 1 = output +genvar i; +generate + for (i = 0; i < 8; i = i+1) begin: gpio0_tris + assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz; + assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i]; + end +endgenerate + +gpio gpio0 ( + // GPIO bus + .gpio_i (gpio0_in), + .gpio_o (gpio0_out), + .gpio_dir_o (gpio0_dir), + + // Wishbone slave interface + .wb_adr_i (wb8_m2s_gpio0_adr[0]), + .wb_dat_i (wb8_m2s_gpio0_dat), + .wb_we_i (wb8_m2s_gpio0_we), + .wb_cyc_i (wb8_m2s_gpio0_cyc), + .wb_stb_i (wb8_m2s_gpio0_stb), + .wb_cti_i (wb8_m2s_gpio0_cti), + .wb_bte_i (wb8_m2s_gpio0_bte), + .wb_dat_o (wb8_s2m_gpio0_dat), + .wb_ack_o (wb8_s2m_gpio0_ack), + .wb_err_o (wb8_s2m_gpio0_err), + .wb_rty_o (wb8_s2m_gpio0_rty), + + .wb_clk (wb_clk), + .wb_rst (wb_rst) +); + +// 32-bit to 8-bit wishbone bus resize +wb_data_resize wb_data_resize_gpio0 ( + // Wishbone Master interface + .wbm_adr_i (wb_m2s_gpio0_adr), + .wbm_dat_i (wb_m2s_gpio0_dat), + .wbm_sel_i (wb_m2s_gpio0_sel), + .wbm_we_i (wb_m2s_gpio0_we ), + .wbm_cyc_i (wb_m2s_gpio0_cyc), + .wbm_stb_i (wb_m2s_gpio0_stb), + .wbm_cti_i (wb_m2s_gpio0_cti), + .wbm_bte_i (wb_m2s_gpio0_bte), + .wbm_dat_o (wb_s2m_gpio0_dat), + .wbm_ack_o (wb_s2m_gpio0_ack), + .wbm_err_o (wb_s2m_gpio0_err), + .wbm_rty_o (wb_s2m_gpio0_rty), + + // Wishbone Slave interface + .wbs_adr_o (wb8_m2s_gpio0_adr), + .wbs_dat_o (wb8_m2s_gpio0_dat), + .wbs_we_o (wb8_m2s_gpio0_we ), + .wbs_cyc_o (wb8_m2s_gpio0_cyc), + .wbs_stb_o (wb8_m2s_gpio0_stb), + .wbs_cti_o (wb8_m2s_gpio0_cti), + .wbs_bte_o (wb8_m2s_gpio0_bte), + .wbs_dat_i (wb8_s2m_gpio0_dat), + .wbs_ack_i (wb8_s2m_gpio0_ack), + .wbs_err_i (wb8_s2m_gpio0_err), + .wbs_rty_i (wb8_s2m_gpio0_rty) +); + +//////////////////////////////////////////////////////////////////////// +// +// Interrupt assignment +// +//////////////////////////////////////////////////////////////////////// + +assign or1k_irq[0] = 0; // Non-maskable inside OR1K +assign or1k_irq[1] = 0; // Non-maskable inside OR1K +assign or1k_irq[2] = uart0_irq; +assign or1k_irq[3] = 0; +assign or1k_irq[4] = 0; +assign or1k_irq[5] = 0; +assign or1k_irq[6] = 0; +assign or1k_irq[7] = 0; +assign or1k_irq[8] = 0; +assign or1k_irq[9] = 0; +assign or1k_irq[10] = 0; +assign or1k_irq[11] = 0; +assign or1k_irq[12] = 0; +assign or1k_irq[13] = 0; +assign or1k_irq[14] = 0; +assign or1k_irq[15] = 0; +assign or1k_irq[16] = 0; +assign or1k_irq[17] = 0; +assign or1k_irq[18] = 0; +assign or1k_irq[19] = 0; +assign or1k_irq[20] = 0; +assign or1k_irq[21] = 0; +assign or1k_irq[22] = 0; +assign or1k_irq[23] = 0; +assign or1k_irq[24] = 0; +assign or1k_irq[25] = 0; +assign or1k_irq[26] = 0; +assign or1k_irq[27] = 0; +assign or1k_irq[28] = 0; +assign or1k_irq[29] = 0; +assign or1k_irq[30] = 0; +assign or1k_irq[31] = 0; + +endmodule // orpsoc_top + + diff --git a/systems/generic/rtl/verilog/rom.v b/systems/de2/rtl/verilog/rom.v old mode 100644 new mode 100755 similarity index 53% rename from systems/generic/rtl/verilog/rom.v rename to systems/de2/rtl/verilog/rom.v index af1b6ddc..b653029c --- a/systems/generic/rtl/verilog/rom.v +++ b/systems/de2/rtl/verilog/rom.v @@ -33,94 +33,95 @@ //// //// ////////////////////////////////////////////////////////////////////// -module rom - #(parameter addr_width = 5, - parameter b3_burst = 0) - ( - input wb_clk, - input wb_rst, - input [(addr_width+2)-1:2] wb_adr_i, - input wb_stb_i, - input wb_cyc_i, - input [2:0] wb_cti_i, - input [1:0] wb_bte_i, - output reg [31:0] wb_dat_o, - output reg wb_ack_o); - - reg [addr_width-1:0] adr; +module rom #( + parameter ADDR_WIDTH = 5, + parameter B3_BURST = 0 +) +( + input wb_clk, + input wb_rst, + input [(ADDR_WIDTH + 2) - 1:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + input [2:0] wb_cti_i, + input [1:0] wb_bte_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o +); - always @ (posedge wb_clk or posedge wb_rst) - if (wb_rst) - wb_dat_o <= 32'h15000000; - else - case (adr) - // Zero r0 and jump to 0x00000100 - 0 : wb_dat_o <= 32'h18000000; - 1 : wb_dat_o <= 32'hA8200000; - 2 : wb_dat_o <= 32'hA8C00100; - 3 : wb_dat_o <= 32'h44003000; - 4 : wb_dat_o <= 32'h15000000; - - default: - wb_dat_o <= 32'h00000000; - endcase // case (wb_adr_i) +reg [ADDR_WIDTH-1:0] adr; + +always @ (posedge wb_clk or posedge wb_rst) +if (wb_rst) + wb_dat_o <= 32'h15000000; +else + case (adr) + // Zero r0 and jump to 0x00000100 + 0 : wb_dat_o <= 32'h18000000; + 1 : wb_dat_o <= 32'hA8200000; + 2 : wb_dat_o <= 32'hA8C00100; + 3 : wb_dat_o <= 32'h44003000; + 4 : wb_dat_o <= 32'h15000000; + default: wb_dat_o <= 32'h00000000; + endcase // case (wb_adr_i) generate -if(b3_burst) begin : gen_b3_burst - reg wb_stb_i_r; - reg new_access_r; - reg burst_r; - - wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111)); - wire new_access = (wb_stb_i & !wb_stb_i_r); - wire new_burst = (burst & !burst_r); +if (B3_BURST) begin : gen_B3_BURST + reg wb_stb_i_r; + reg new_access_r; + reg burst_r; + + wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111)); + wire new_access = (wb_stb_i & !wb_stb_i_r); + wire new_burst = (burst & !burst_r); + + always @(posedge wb_clk) begin + new_access_r <= new_access; + burst_r <= burst; + wb_stb_i_r <= wb_stb_i; + end + + always @(posedge wb_clk) + if (wb_rst) + adr <= 0; + else if (new_access) + // New access, register address, ack a cycle later + adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2]; + else if (burst) begin + if (wb_cti_i == 3'b010) + case (wb_bte_i) + 2'b00: adr <= adr + 1; + 2'b01: adr[1:0] <= adr[1:0] + 1; + 2'b10: adr[2:0] <= adr[2:0] + 1; + 2'b11: adr[3:0] <= adr[3:0] + 1; + endcase // case (wb_bte_i) + else + adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2]; + end // if (burst) - always @(posedge wb_clk) begin - new_access_r <= new_access; - burst_r <= burst; - wb_stb_i_r <= wb_stb_i; - end - - - always @(posedge wb_clk) - if (wb_rst) - adr <= 0; - else if (new_access) - // New access, register address, ack a cycle later - adr <= wb_adr_i[(addr_width+2)-1:2]; - else if (burst) begin - if (wb_cti_i == 3'b010) - case (wb_bte_i) - 2'b00: adr <= adr + 1; - 2'b01: adr[1:0] <= adr[1:0] + 1; - 2'b10: adr[2:0] <= adr[2:0] + 1; - 2'b11: adr[3:0] <= adr[3:0] + 1; - endcase // case (wb_bte_i) - else - adr <= wb_adr_i[(addr_width+2)-1:2]; - end // if (burst) - - - always @(posedge wb_clk) - if (wb_rst) - wb_ack_o <= 0; - else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111))) - wb_ack_o <= 0; - else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r))) - wb_ack_o <= 1; - else - wb_ack_o <= 0; - end else begin + always @(posedge wb_clk) + if (wb_rst) + wb_ack_o <= 0; + else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111))) + wb_ack_o <= 0; + else if (wb_stb_i & ((!burst & !new_access & new_access_r) | + (burst & burst_r))) + wb_ack_o <= 1; + else + wb_ack_o <= 0; + +end else begin always @(wb_adr_i) - adr <= wb_adr_i; - + adr <= wb_adr_i; + always @ (posedge wb_clk or posedge wb_rst) - if (wb_rst) - wb_ack_o <= 1'b0; - else - wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; - - end -endgenerate -endmodule + if (wb_rst) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; +end + +endgenerate + +endmodule diff --git a/systems/de2/rtl/verilog/wb_intercon.old.v b/systems/de2/rtl/verilog/wb_intercon.old.v new file mode 100755 index 00000000..aa04cde6 --- /dev/null +++ b/systems/de2/rtl/verilog/wb_intercon.old.v @@ -0,0 +1,360 @@ +module wb_intercon + (input wb_clk_i, + input wb_rst_i, + input [31:0] wb_or1k_i_adr_i, + input [31:0] wb_or1k_i_dat_i, + input [3:0] wb_or1k_i_sel_i, + input wb_or1k_i_we_i, + input wb_or1k_i_cyc_i, + input wb_or1k_i_stb_i, + input [2:0] wb_or1k_i_cti_i, + input [1:0] wb_or1k_i_bte_i, + output [31:0] wb_or1k_i_dat_o, + output wb_or1k_i_ack_o, + output wb_or1k_i_err_o, + output wb_or1k_i_rty_o, + input [31:0] wb_or1k_d_adr_i, + input [31:0] wb_or1k_d_dat_i, + input [3:0] wb_or1k_d_sel_i, + input wb_or1k_d_we_i, + input wb_or1k_d_cyc_i, + input wb_or1k_d_stb_i, + input [2:0] wb_or1k_d_cti_i, + input [1:0] wb_or1k_d_bte_i, + output [31:0] wb_or1k_d_dat_o, + output wb_or1k_d_ack_o, + output wb_or1k_d_err_o, + output wb_or1k_d_rty_o, + input [31:0] wb_dbg_adr_i, + input [31:0] wb_dbg_dat_i, + input [3:0] wb_dbg_sel_i, + input wb_dbg_we_i, + input wb_dbg_cyc_i, + input wb_dbg_stb_i, + input [2:0] wb_dbg_cti_i, + input [1:0] wb_dbg_bte_i, + output [31:0] wb_dbg_dat_o, + output wb_dbg_ack_o, + output wb_dbg_err_o, + output wb_dbg_rty_o, + output [31:0] wb_uart0_adr_o, + output [31:0] wb_uart0_dat_o, + output [3:0] wb_uart0_sel_o, + output wb_uart0_we_o, + output wb_uart0_cyc_o, + output wb_uart0_stb_o, + output [2:0] wb_uart0_cti_o, + output [1:0] wb_uart0_bte_o, + input [31:0] wb_uart0_dat_i, + input wb_uart0_ack_i, + input wb_uart0_err_i, + input wb_uart0_rty_i, + output [31:0] wb_sdram_dbus_adr_o, + output [31:0] wb_sdram_dbus_dat_o, + output [3:0] wb_sdram_dbus_sel_o, + output wb_sdram_dbus_we_o, + output wb_sdram_dbus_cyc_o, + output wb_sdram_dbus_stb_o, + output [2:0] wb_sdram_dbus_cti_o, + output [1:0] wb_sdram_dbus_bte_o, + input [31:0] wb_sdram_dbus_dat_i, + input wb_sdram_dbus_ack_i, + input wb_sdram_dbus_err_i, + input wb_sdram_dbus_rty_i, + output [31:0] wb_gpio0_adr_o, + output [31:0] wb_gpio0_dat_o, + output [3:0] wb_gpio0_sel_o, + output wb_gpio0_we_o, + output wb_gpio0_cyc_o, + output wb_gpio0_stb_o, + output [2:0] wb_gpio0_cti_o, + output [1:0] wb_gpio0_bte_o, + input [31:0] wb_gpio0_dat_i, + input wb_gpio0_ack_i, + input wb_gpio0_err_i, + input wb_gpio0_rty_i, + output [31:0] wb_rom0_adr_o, + output [31:0] wb_rom0_dat_o, + output [3:0] wb_rom0_sel_o, + output wb_rom0_we_o, + output wb_rom0_cyc_o, + output wb_rom0_stb_o, + output [2:0] wb_rom0_cti_o, + output [1:0] wb_rom0_bte_o, + input [31:0] wb_rom0_dat_i, + input wb_rom0_ack_i, + input wb_rom0_err_i, + input wb_rom0_rty_i, + output [31:0] wb_sdram_ibus_adr_o, + output [31:0] wb_sdram_ibus_dat_o, + output [3:0] wb_sdram_ibus_sel_o, + output wb_sdram_ibus_we_o, + output wb_sdram_ibus_cyc_o, + output wb_sdram_ibus_stb_o, + output [2:0] wb_sdram_ibus_cti_o, + output [1:0] wb_sdram_ibus_bte_o, + input [31:0] wb_sdram_ibus_dat_i, + input wb_sdram_ibus_ack_i, + input wb_sdram_ibus_err_i, + input wb_sdram_ibus_rty_i); + +wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr; +wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat; +wire [3:0] wb_m2s_or1k_d_sdram_dbus_sel; +wire wb_m2s_or1k_d_sdram_dbus_we; +wire wb_m2s_or1k_d_sdram_dbus_cyc; +wire wb_m2s_or1k_d_sdram_dbus_stb; +wire [2:0] wb_m2s_or1k_d_sdram_dbus_cti; +wire [1:0] wb_m2s_or1k_d_sdram_dbus_bte; +wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat; +wire wb_s2m_or1k_d_sdram_dbus_ack; +wire wb_s2m_or1k_d_sdram_dbus_err; +wire wb_s2m_or1k_d_sdram_dbus_rty; +wire [31:0] wb_m2s_or1k_d_uart0_adr; +wire [31:0] wb_m2s_or1k_d_uart0_dat; +wire [3:0] wb_m2s_or1k_d_uart0_sel; +wire wb_m2s_or1k_d_uart0_we; +wire wb_m2s_or1k_d_uart0_cyc; +wire wb_m2s_or1k_d_uart0_stb; +wire [2:0] wb_m2s_or1k_d_uart0_cti; +wire [1:0] wb_m2s_or1k_d_uart0_bte; +wire [31:0] wb_s2m_or1k_d_uart0_dat; +wire wb_s2m_or1k_d_uart0_ack; +wire wb_s2m_or1k_d_uart0_err; +wire wb_s2m_or1k_d_uart0_rty; +wire [31:0] wb_m2s_or1k_d_gpio0_adr; +wire [31:0] wb_m2s_or1k_d_gpio0_dat; +wire [3:0] wb_m2s_or1k_d_gpio0_sel; +wire wb_m2s_or1k_d_gpio0_we; +wire wb_m2s_or1k_d_gpio0_cyc; +wire wb_m2s_or1k_d_gpio0_stb; +wire [2:0] wb_m2s_or1k_d_gpio0_cti; +wire [1:0] wb_m2s_or1k_d_gpio0_bte; +wire [31:0] wb_s2m_or1k_d_gpio0_dat; +wire wb_s2m_or1k_d_gpio0_ack; +wire wb_s2m_or1k_d_gpio0_err; +wire wb_s2m_or1k_d_gpio0_rty; +wire [31:0] wb_m2s_dbg_sdram_dbus_adr; +wire [31:0] wb_m2s_dbg_sdram_dbus_dat; +wire [3:0] wb_m2s_dbg_sdram_dbus_sel; +wire wb_m2s_dbg_sdram_dbus_we; +wire wb_m2s_dbg_sdram_dbus_cyc; +wire wb_m2s_dbg_sdram_dbus_stb; +wire [2:0] wb_m2s_dbg_sdram_dbus_cti; +wire [1:0] wb_m2s_dbg_sdram_dbus_bte; +wire [31:0] wb_s2m_dbg_sdram_dbus_dat; +wire wb_s2m_dbg_sdram_dbus_ack; +wire wb_s2m_dbg_sdram_dbus_err; +wire wb_s2m_dbg_sdram_dbus_rty; +wire [31:0] wb_m2s_dbg_uart0_adr; +wire [31:0] wb_m2s_dbg_uart0_dat; +wire [3:0] wb_m2s_dbg_uart0_sel; +wire wb_m2s_dbg_uart0_we; +wire wb_m2s_dbg_uart0_cyc; +wire wb_m2s_dbg_uart0_stb; +wire [2:0] wb_m2s_dbg_uart0_cti; +wire [1:0] wb_m2s_dbg_uart0_bte; +wire [31:0] wb_s2m_dbg_uart0_dat; +wire wb_s2m_dbg_uart0_ack; +wire wb_s2m_dbg_uart0_err; +wire wb_s2m_dbg_uart0_rty; +wire [31:0] wb_m2s_dbg_gpio0_adr; +wire [31:0] wb_m2s_dbg_gpio0_dat; +wire [3:0] wb_m2s_dbg_gpio0_sel; +wire wb_m2s_dbg_gpio0_we; +wire wb_m2s_dbg_gpio0_cyc; +wire wb_m2s_dbg_gpio0_stb; +wire [2:0] wb_m2s_dbg_gpio0_cti; +wire [1:0] wb_m2s_dbg_gpio0_bte; +wire [31:0] wb_s2m_dbg_gpio0_dat; +wire wb_s2m_dbg_gpio0_ack; +wire wb_s2m_dbg_gpio0_err; +wire wb_s2m_dbg_gpio0_rty; + +wb_mux + #(.num_slaves (2), + .MATCH_ADDR ({32'h00000000, 32'hf0000100}), + .MATCH_MASK ({32'hfe000000, 32'hffffffc0})) + wb_mux_or1k_i + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_or1k_i_adr_i), + .wbm_dat_i (wb_or1k_i_dat_i), + .wbm_sel_i (wb_or1k_i_sel_i), + .wbm_we_i (wb_or1k_i_we_i), + .wbm_cyc_i (wb_or1k_i_cyc_i), + .wbm_stb_i (wb_or1k_i_stb_i), + .wbm_cti_i (wb_or1k_i_cti_i), + .wbm_bte_i (wb_or1k_i_bte_i), + .wbm_dat_o (wb_or1k_i_dat_o), + .wbm_ack_o (wb_or1k_i_ack_o), + .wbm_err_o (wb_or1k_i_err_o), + .wbm_rty_o (wb_or1k_i_rty_o), + .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}), + .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}), + .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}), + .wbs_we_o ({wb_sdram_ibus_we_o, wb_rom0_we_o}), + .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}), + .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}), + .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}), + .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}), + .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}), + .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}), + .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}), + .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i})); + +wb_mux + #(.num_slaves (3), + .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}), + .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe})) + wb_mux_or1k_d + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_or1k_d_adr_i), + .wbm_dat_i (wb_or1k_d_dat_i), + .wbm_sel_i (wb_or1k_d_sel_i), + .wbm_we_i (wb_or1k_d_we_i), + .wbm_cyc_i (wb_or1k_d_cyc_i), + .wbm_stb_i (wb_or1k_d_stb_i), + .wbm_cti_i (wb_or1k_d_cti_i), + .wbm_bte_i (wb_or1k_d_bte_i), + .wbm_dat_o (wb_or1k_d_dat_o), + .wbm_ack_o (wb_or1k_d_ack_o), + .wbm_err_o (wb_or1k_d_err_o), + .wbm_rty_o (wb_or1k_d_rty_o), + .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}), + .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}), + .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}), + .wbs_we_o ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}), + .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}), + .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}), + .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}), + .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}), + .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}), + .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}), + .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}), + .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty})); + +wb_mux + #(.num_slaves (3), + .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}), + .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe})) + wb_mux_dbg + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_dbg_adr_i), + .wbm_dat_i (wb_dbg_dat_i), + .wbm_sel_i (wb_dbg_sel_i), + .wbm_we_i (wb_dbg_we_i), + .wbm_cyc_i (wb_dbg_cyc_i), + .wbm_stb_i (wb_dbg_stb_i), + .wbm_cti_i (wb_dbg_cti_i), + .wbm_bte_i (wb_dbg_bte_i), + .wbm_dat_o (wb_dbg_dat_o), + .wbm_ack_o (wb_dbg_ack_o), + .wbm_err_o (wb_dbg_err_o), + .wbm_rty_o (wb_dbg_rty_o), + .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}), + .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}), + .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}), + .wbs_we_o ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}), + .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}), + .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}), + .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}), + .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}), + .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}), + .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}), + .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}), + .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty})); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_uart0 + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}), + .wbm_we_i ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}), + .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}), + .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}), + .wbs_adr_o (wb_uart0_adr_o), + .wbs_dat_o (wb_uart0_dat_o), + .wbs_sel_o (wb_uart0_sel_o), + .wbs_we_o (wb_uart0_we_o), + .wbs_cyc_o (wb_uart0_cyc_o), + .wbs_stb_o (wb_uart0_stb_o), + .wbs_cti_o (wb_uart0_cti_o), + .wbs_bte_o (wb_uart0_bte_o), + .wbs_dat_i (wb_uart0_dat_i), + .wbs_ack_i (wb_uart0_ack_i), + .wbs_err_i (wb_uart0_err_i), + .wbs_rty_i (wb_uart0_rty_i)); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_sdram_dbus + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}), + .wbm_we_i ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}), + .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}), + .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}), + .wbs_adr_o (wb_sdram_dbus_adr_o), + .wbs_dat_o (wb_sdram_dbus_dat_o), + .wbs_sel_o (wb_sdram_dbus_sel_o), + .wbs_we_o (wb_sdram_dbus_we_o), + .wbs_cyc_o (wb_sdram_dbus_cyc_o), + .wbs_stb_o (wb_sdram_dbus_stb_o), + .wbs_cti_o (wb_sdram_dbus_cti_o), + .wbs_bte_o (wb_sdram_dbus_bte_o), + .wbs_dat_i (wb_sdram_dbus_dat_i), + .wbs_ack_i (wb_sdram_dbus_ack_i), + .wbs_err_i (wb_sdram_dbus_err_i), + .wbs_rty_i (wb_sdram_dbus_rty_i)); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_gpio0 + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}), + .wbm_we_i ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}), + .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}), + .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}), + .wbs_adr_o (wb_gpio0_adr_o), + .wbs_dat_o (wb_gpio0_dat_o), + .wbs_sel_o (wb_gpio0_sel_o), + .wbs_we_o (wb_gpio0_we_o), + .wbs_cyc_o (wb_gpio0_cyc_o), + .wbs_stb_o (wb_gpio0_stb_o), + .wbs_cti_o (wb_gpio0_cti_o), + .wbs_bte_o (wb_gpio0_bte_o), + .wbs_dat_i (wb_gpio0_dat_i), + .wbs_ack_i (wb_gpio0_ack_i), + .wbs_err_i (wb_gpio0_err_i), + .wbs_rty_i (wb_gpio0_rty_i)); + +endmodule diff --git a/systems/de2/rtl/verilog/wb_intercon.old.vh b/systems/de2/rtl/verilog/wb_intercon.old.vh new file mode 100755 index 00000000..e81420ee --- /dev/null +++ b/systems/de2/rtl/verilog/wb_intercon.old.vh @@ -0,0 +1,197 @@ +wire [31:0] wb_m2s_or1k_i_adr; +wire [31:0] wb_m2s_or1k_i_dat; +wire [3:0] wb_m2s_or1k_i_sel; +wire wb_m2s_or1k_i_we; +wire wb_m2s_or1k_i_cyc; +wire wb_m2s_or1k_i_stb; +wire [2:0] wb_m2s_or1k_i_cti; +wire [1:0] wb_m2s_or1k_i_bte; +wire [31:0] wb_s2m_or1k_i_dat; +wire wb_s2m_or1k_i_ack; +wire wb_s2m_or1k_i_err; +wire wb_s2m_or1k_i_rty; +wire [31:0] wb_m2s_or1k_d_adr; +wire [31:0] wb_m2s_or1k_d_dat; +wire [3:0] wb_m2s_or1k_d_sel; +wire wb_m2s_or1k_d_we; +wire wb_m2s_or1k_d_cyc; +wire wb_m2s_or1k_d_stb; +wire [2:0] wb_m2s_or1k_d_cti; +wire [1:0] wb_m2s_or1k_d_bte; +wire [31:0] wb_s2m_or1k_d_dat; +wire wb_s2m_or1k_d_ack; +wire wb_s2m_or1k_d_err; +wire wb_s2m_or1k_d_rty; +wire [31:0] wb_m2s_dbg_adr; +wire [31:0] wb_m2s_dbg_dat; +wire [3:0] wb_m2s_dbg_sel; +wire wb_m2s_dbg_we; +wire wb_m2s_dbg_cyc; +wire wb_m2s_dbg_stb; +wire [2:0] wb_m2s_dbg_cti; +wire [1:0] wb_m2s_dbg_bte; +wire [31:0] wb_s2m_dbg_dat; +wire wb_s2m_dbg_ack; +wire wb_s2m_dbg_err; +wire wb_s2m_dbg_rty; +wire [31:0] wb_m2s_uart0_adr; +wire [31:0] wb_m2s_uart0_dat; +wire [3:0] wb_m2s_uart0_sel; +wire wb_m2s_uart0_we; +wire wb_m2s_uart0_cyc; +wire wb_m2s_uart0_stb; +wire [2:0] wb_m2s_uart0_cti; +wire [1:0] wb_m2s_uart0_bte; +wire [31:0] wb_s2m_uart0_dat; +wire wb_s2m_uart0_ack; +wire wb_s2m_uart0_err; +wire wb_s2m_uart0_rty; +wire [31:0] wb_m2s_sdram_dbus_adr; +wire [31:0] wb_m2s_sdram_dbus_dat; +wire [3:0] wb_m2s_sdram_dbus_sel; +wire wb_m2s_sdram_dbus_we; +wire wb_m2s_sdram_dbus_cyc; +wire wb_m2s_sdram_dbus_stb; +wire [2:0] wb_m2s_sdram_dbus_cti; +wire [1:0] wb_m2s_sdram_dbus_bte; +wire [31:0] wb_s2m_sdram_dbus_dat; +wire wb_s2m_sdram_dbus_ack; +wire wb_s2m_sdram_dbus_err; +wire wb_s2m_sdram_dbus_rty; +wire [31:0] wb_m2s_gpio0_adr; +wire [31:0] wb_m2s_gpio0_dat; +wire [3:0] wb_m2s_gpio0_sel; +wire wb_m2s_gpio0_we; +wire wb_m2s_gpio0_cyc; +wire wb_m2s_gpio0_stb; +wire [2:0] wb_m2s_gpio0_cti; +wire [1:0] wb_m2s_gpio0_bte; +wire [31:0] wb_s2m_gpio0_dat; +wire wb_s2m_gpio0_ack; +wire wb_s2m_gpio0_err; +wire wb_s2m_gpio0_rty; +wire [31:0] wb_m2s_rom0_adr; +wire [31:0] wb_m2s_rom0_dat; +wire [3:0] wb_m2s_rom0_sel; +wire wb_m2s_rom0_we; +wire wb_m2s_rom0_cyc; +wire wb_m2s_rom0_stb; +wire [2:0] wb_m2s_rom0_cti; +wire [1:0] wb_m2s_rom0_bte; +wire [31:0] wb_s2m_rom0_dat; +wire wb_s2m_rom0_ack; +wire wb_s2m_rom0_err; +wire wb_s2m_rom0_rty; +wire [31:0] wb_m2s_sdram_ibus_adr; +wire [31:0] wb_m2s_sdram_ibus_dat; +wire [3:0] wb_m2s_sdram_ibus_sel; +wire wb_m2s_sdram_ibus_we; +wire wb_m2s_sdram_ibus_cyc; +wire wb_m2s_sdram_ibus_stb; +wire [2:0] wb_m2s_sdram_ibus_cti; +wire [1:0] wb_m2s_sdram_ibus_bte; +wire [31:0] wb_s2m_sdram_ibus_dat; +wire wb_s2m_sdram_ibus_ack; +wire wb_s2m_sdram_ibus_err; +wire wb_s2m_sdram_ibus_rty; + +wb_intercon wb_intercon0 + (.wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_or1k_i_adr_i (wb_m2s_or1k_i_adr), + .wb_or1k_i_dat_i (wb_m2s_or1k_i_dat), + .wb_or1k_i_sel_i (wb_m2s_or1k_i_sel), + .wb_or1k_i_we_i (wb_m2s_or1k_i_we), + .wb_or1k_i_cyc_i (wb_m2s_or1k_i_cyc), + .wb_or1k_i_stb_i (wb_m2s_or1k_i_stb), + .wb_or1k_i_cti_i (wb_m2s_or1k_i_cti), + .wb_or1k_i_bte_i (wb_m2s_or1k_i_bte), + .wb_or1k_i_dat_o (wb_s2m_or1k_i_dat), + .wb_or1k_i_ack_o (wb_s2m_or1k_i_ack), + .wb_or1k_i_err_o (wb_s2m_or1k_i_err), + .wb_or1k_i_rty_o (wb_s2m_or1k_i_rty), + .wb_or1k_d_adr_i (wb_m2s_or1k_d_adr), + .wb_or1k_d_dat_i (wb_m2s_or1k_d_dat), + .wb_or1k_d_sel_i (wb_m2s_or1k_d_sel), + .wb_or1k_d_we_i (wb_m2s_or1k_d_we), + .wb_or1k_d_cyc_i (wb_m2s_or1k_d_cyc), + .wb_or1k_d_stb_i (wb_m2s_or1k_d_stb), + .wb_or1k_d_cti_i (wb_m2s_or1k_d_cti), + .wb_or1k_d_bte_i (wb_m2s_or1k_d_bte), + .wb_or1k_d_dat_o (wb_s2m_or1k_d_dat), + .wb_or1k_d_ack_o (wb_s2m_or1k_d_ack), + .wb_or1k_d_err_o (wb_s2m_or1k_d_err), + .wb_or1k_d_rty_o (wb_s2m_or1k_d_rty), + .wb_dbg_adr_i (wb_m2s_dbg_adr), + .wb_dbg_dat_i (wb_m2s_dbg_dat), + .wb_dbg_sel_i (wb_m2s_dbg_sel), + .wb_dbg_we_i (wb_m2s_dbg_we), + .wb_dbg_cyc_i (wb_m2s_dbg_cyc), + .wb_dbg_stb_i (wb_m2s_dbg_stb), + .wb_dbg_cti_i (wb_m2s_dbg_cti), + .wb_dbg_bte_i (wb_m2s_dbg_bte), + .wb_dbg_dat_o (wb_s2m_dbg_dat), + .wb_dbg_ack_o (wb_s2m_dbg_ack), + .wb_dbg_err_o (wb_s2m_dbg_err), + .wb_dbg_rty_o (wb_s2m_dbg_rty), + .wb_uart0_adr_o (wb_m2s_uart0_adr), + .wb_uart0_dat_o (wb_m2s_uart0_dat), + .wb_uart0_sel_o (wb_m2s_uart0_sel), + .wb_uart0_we_o (wb_m2s_uart0_we), + .wb_uart0_cyc_o (wb_m2s_uart0_cyc), + .wb_uart0_stb_o (wb_m2s_uart0_stb), + .wb_uart0_cti_o (wb_m2s_uart0_cti), + .wb_uart0_bte_o (wb_m2s_uart0_bte), + .wb_uart0_dat_i (wb_s2m_uart0_dat), + .wb_uart0_ack_i (wb_s2m_uart0_ack), + .wb_uart0_err_i (wb_s2m_uart0_err), + .wb_uart0_rty_i (wb_s2m_uart0_rty), + .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr), + .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat), + .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel), + .wb_sdram_dbus_we_o (wb_m2s_sdram_dbus_we), + .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc), + .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb), + .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti), + .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte), + .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat), + .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack), + .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err), + .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty), + .wb_gpio0_adr_o (wb_m2s_gpio0_adr), + .wb_gpio0_dat_o (wb_m2s_gpio0_dat), + .wb_gpio0_sel_o (wb_m2s_gpio0_sel), + .wb_gpio0_we_o (wb_m2s_gpio0_we), + .wb_gpio0_cyc_o (wb_m2s_gpio0_cyc), + .wb_gpio0_stb_o (wb_m2s_gpio0_stb), + .wb_gpio0_cti_o (wb_m2s_gpio0_cti), + .wb_gpio0_bte_o (wb_m2s_gpio0_bte), + .wb_gpio0_dat_i (wb_s2m_gpio0_dat), + .wb_gpio0_ack_i (wb_s2m_gpio0_ack), + .wb_gpio0_err_i (wb_s2m_gpio0_err), + .wb_gpio0_rty_i (wb_s2m_gpio0_rty), + .wb_rom0_adr_o (wb_m2s_rom0_adr), + .wb_rom0_dat_o (wb_m2s_rom0_dat), + .wb_rom0_sel_o (wb_m2s_rom0_sel), + .wb_rom0_we_o (wb_m2s_rom0_we), + .wb_rom0_cyc_o (wb_m2s_rom0_cyc), + .wb_rom0_stb_o (wb_m2s_rom0_stb), + .wb_rom0_cti_o (wb_m2s_rom0_cti), + .wb_rom0_bte_o (wb_m2s_rom0_bte), + .wb_rom0_dat_i (wb_s2m_rom0_dat), + .wb_rom0_ack_i (wb_s2m_rom0_ack), + .wb_rom0_err_i (wb_s2m_rom0_err), + .wb_rom0_rty_i (wb_s2m_rom0_rty), + .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr), + .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat), + .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel), + .wb_sdram_ibus_we_o (wb_m2s_sdram_ibus_we), + .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc), + .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb), + .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti), + .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte), + .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat), + .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack), + .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err), + .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty)); + diff --git a/systems/de2/rtl/verilog/wb_intercon.v b/systems/de2/rtl/verilog/wb_intercon.v new file mode 100644 index 00000000..5358c2c6 --- /dev/null +++ b/systems/de2/rtl/verilog/wb_intercon.v @@ -0,0 +1,442 @@ +module wb_intercon + (input wb_clk_i, + input wb_rst_i, + input [31:0] wb_or1k_i_adr_i, + input [31:0] wb_or1k_i_dat_i, + input [3:0] wb_or1k_i_sel_i, + input wb_or1k_i_we_i, + input wb_or1k_i_cyc_i, + input wb_or1k_i_stb_i, + input [2:0] wb_or1k_i_cti_i, + input [1:0] wb_or1k_i_bte_i, + output [31:0] wb_or1k_i_dat_o, + output wb_or1k_i_ack_o, + output wb_or1k_i_err_o, + output wb_or1k_i_rty_o, + input [31:0] wb_or1k_d_adr_i, + input [31:0] wb_or1k_d_dat_i, + input [3:0] wb_or1k_d_sel_i, + input wb_or1k_d_we_i, + input wb_or1k_d_cyc_i, + input wb_or1k_d_stb_i, + input [2:0] wb_or1k_d_cti_i, + input [1:0] wb_or1k_d_bte_i, + output [31:0] wb_or1k_d_dat_o, + output wb_or1k_d_ack_o, + output wb_or1k_d_err_o, + output wb_or1k_d_rty_o, + input [31:0] wb_dbg_adr_i, + input [31:0] wb_dbg_dat_i, + input [3:0] wb_dbg_sel_i, + input wb_dbg_we_i, + input wb_dbg_cyc_i, + input wb_dbg_stb_i, + input [2:0] wb_dbg_cti_i, + input [1:0] wb_dbg_bte_i, + output [31:0] wb_dbg_dat_o, + output wb_dbg_ack_o, + output wb_dbg_err_o, + output wb_dbg_rty_o, + output [31:0] wb_uart0_adr_o, + output [31:0] wb_uart0_dat_o, + output [3:0] wb_uart0_sel_o, + output wb_uart0_we_o, + output wb_uart0_cyc_o, + output wb_uart0_stb_o, + output [2:0] wb_uart0_cti_o, + output [1:0] wb_uart0_bte_o, + input [31:0] wb_uart0_dat_i, + input wb_uart0_ack_i, + input wb_uart0_err_i, + input wb_uart0_rty_i, + output [31:0] wb_gpio0_adr_o, + output [31:0] wb_gpio0_dat_o, + output [3:0] wb_gpio0_sel_o, + output wb_gpio0_we_o, + output wb_gpio0_cyc_o, + output wb_gpio0_stb_o, + output [2:0] wb_gpio0_cti_o, + output [1:0] wb_gpio0_bte_o, + input [31:0] wb_gpio0_dat_i, + input wb_gpio0_ack_i, + input wb_gpio0_err_i, + input wb_gpio0_rty_i, + output [31:0] wb_sdram_dbus_adr_o, + output [31:0] wb_sdram_dbus_dat_o, + output [3:0] wb_sdram_dbus_sel_o, + output wb_sdram_dbus_we_o, + output wb_sdram_dbus_cyc_o, + output wb_sdram_dbus_stb_o, + output [2:0] wb_sdram_dbus_cti_o, + output [1:0] wb_sdram_dbus_bte_o, + input [31:0] wb_sdram_dbus_dat_i, + input wb_sdram_dbus_ack_i, + input wb_sdram_dbus_err_i, + input wb_sdram_dbus_rty_i, + output [31:0] wb_rom0_adr_o, + output [31:0] wb_rom0_dat_o, + output [3:0] wb_rom0_sel_o, + output wb_rom0_we_o, + output wb_rom0_cyc_o, + output wb_rom0_stb_o, + output [2:0] wb_rom0_cti_o, + output [1:0] wb_rom0_bte_o, + input [31:0] wb_rom0_dat_i, + input wb_rom0_ack_i, + input wb_rom0_err_i, + input wb_rom0_rty_i, + output [31:0] wb_sdram_ibus_adr_o, + output [31:0] wb_sdram_ibus_dat_o, + output [3:0] wb_sdram_ibus_sel_o, + output wb_sdram_ibus_we_o, + output wb_sdram_ibus_cyc_o, + output wb_sdram_ibus_stb_o, + output [2:0] wb_sdram_ibus_cti_o, + output [1:0] wb_sdram_ibus_bte_o, + input [31:0] wb_sdram_ibus_dat_i, + input wb_sdram_ibus_ack_i, + input wb_sdram_ibus_err_i, + input wb_sdram_ibus_rty_i); + +wire [31:0] wb_m2s_or1k_d_sdram_dbus_adr; +wire [31:0] wb_m2s_or1k_d_sdram_dbus_dat; +wire [3:0] wb_m2s_or1k_d_sdram_dbus_sel; +wire wb_m2s_or1k_d_sdram_dbus_we; +wire wb_m2s_or1k_d_sdram_dbus_cyc; +wire wb_m2s_or1k_d_sdram_dbus_stb; +wire [2:0] wb_m2s_or1k_d_sdram_dbus_cti; +wire [1:0] wb_m2s_or1k_d_sdram_dbus_bte; +wire [31:0] wb_s2m_or1k_d_sdram_dbus_dat; +wire wb_s2m_or1k_d_sdram_dbus_ack; +wire wb_s2m_or1k_d_sdram_dbus_err; +wire wb_s2m_or1k_d_sdram_dbus_rty; +wire [31:0] wb_m2s_or1k_d_uart0_adr; +wire [31:0] wb_m2s_or1k_d_uart0_dat; +wire [3:0] wb_m2s_or1k_d_uart0_sel; +wire wb_m2s_or1k_d_uart0_we; +wire wb_m2s_or1k_d_uart0_cyc; +wire wb_m2s_or1k_d_uart0_stb; +wire [2:0] wb_m2s_or1k_d_uart0_cti; +wire [1:0] wb_m2s_or1k_d_uart0_bte; +wire [31:0] wb_s2m_or1k_d_uart0_dat; +wire wb_s2m_or1k_d_uart0_ack; +wire wb_s2m_or1k_d_uart0_err; +wire wb_s2m_or1k_d_uart0_rty; +wire [31:0] wb_m2s_or1k_d_gpio0_adr; +wire [31:0] wb_m2s_or1k_d_gpio0_dat; +wire [3:0] wb_m2s_or1k_d_gpio0_sel; +wire wb_m2s_or1k_d_gpio0_we; +wire wb_m2s_or1k_d_gpio0_cyc; +wire wb_m2s_or1k_d_gpio0_stb; +wire [2:0] wb_m2s_or1k_d_gpio0_cti; +wire [1:0] wb_m2s_or1k_d_gpio0_bte; +wire [31:0] wb_s2m_or1k_d_gpio0_dat; +wire wb_s2m_or1k_d_gpio0_ack; +wire wb_s2m_or1k_d_gpio0_err; +wire wb_s2m_or1k_d_gpio0_rty; +wire [31:0] wb_m2s_dbg_sdram_dbus_adr; +wire [31:0] wb_m2s_dbg_sdram_dbus_dat; +wire [3:0] wb_m2s_dbg_sdram_dbus_sel; +wire wb_m2s_dbg_sdram_dbus_we; +wire wb_m2s_dbg_sdram_dbus_cyc; +wire wb_m2s_dbg_sdram_dbus_stb; +wire [2:0] wb_m2s_dbg_sdram_dbus_cti; +wire [1:0] wb_m2s_dbg_sdram_dbus_bte; +wire [31:0] wb_s2m_dbg_sdram_dbus_dat; +wire wb_s2m_dbg_sdram_dbus_ack; +wire wb_s2m_dbg_sdram_dbus_err; +wire wb_s2m_dbg_sdram_dbus_rty; +wire [31:0] wb_m2s_dbg_uart0_adr; +wire [31:0] wb_m2s_dbg_uart0_dat; +wire [3:0] wb_m2s_dbg_uart0_sel; +wire wb_m2s_dbg_uart0_we; +wire wb_m2s_dbg_uart0_cyc; +wire wb_m2s_dbg_uart0_stb; +wire [2:0] wb_m2s_dbg_uart0_cti; +wire [1:0] wb_m2s_dbg_uart0_bte; +wire [31:0] wb_s2m_dbg_uart0_dat; +wire wb_s2m_dbg_uart0_ack; +wire wb_s2m_dbg_uart0_err; +wire wb_s2m_dbg_uart0_rty; +wire [31:0] wb_m2s_dbg_gpio0_adr; +wire [31:0] wb_m2s_dbg_gpio0_dat; +wire [3:0] wb_m2s_dbg_gpio0_sel; +wire wb_m2s_dbg_gpio0_we; +wire wb_m2s_dbg_gpio0_cyc; +wire wb_m2s_dbg_gpio0_stb; +wire [2:0] wb_m2s_dbg_gpio0_cti; +wire [1:0] wb_m2s_dbg_gpio0_bte; +wire [31:0] wb_s2m_dbg_gpio0_dat; +wire wb_s2m_dbg_gpio0_ack; +wire wb_s2m_dbg_gpio0_err; +wire wb_s2m_dbg_gpio0_rty; +wire [31:0] wb_m2s_resize_uart0_adr; +wire [31:0] wb_m2s_resize_uart0_dat; +wire [3:0] wb_m2s_resize_uart0_sel; +wire wb_m2s_resize_uart0_we; +wire wb_m2s_resize_uart0_cyc; +wire wb_m2s_resize_uart0_stb; +wire [2:0] wb_m2s_resize_uart0_cti; +wire [1:0] wb_m2s_resize_uart0_bte; +wire [31:0] wb_s2m_resize_uart0_dat; +wire wb_s2m_resize_uart0_ack; +wire wb_s2m_resize_uart0_err; +wire wb_s2m_resize_uart0_rty; +wire [31:0] wb_m2s_resize_gpio0_adr; +wire [31:0] wb_m2s_resize_gpio0_dat; +wire [3:0] wb_m2s_resize_gpio0_sel; +wire wb_m2s_resize_gpio0_we; +wire wb_m2s_resize_gpio0_cyc; +wire wb_m2s_resize_gpio0_stb; +wire [2:0] wb_m2s_resize_gpio0_cti; +wire [1:0] wb_m2s_resize_gpio0_bte; +wire [31:0] wb_s2m_resize_gpio0_dat; +wire wb_s2m_resize_gpio0_ack; +wire wb_s2m_resize_gpio0_err; +wire wb_s2m_resize_gpio0_rty; + +wb_mux + #(.num_slaves (2), + .MATCH_ADDR ({32'h00000000, 32'hf0000100}), + .MATCH_MASK ({32'hfe000000, 32'hffffffc0})) + wb_mux_or1k_i + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_or1k_i_adr_i), + .wbm_dat_i (wb_or1k_i_dat_i), + .wbm_sel_i (wb_or1k_i_sel_i), + .wbm_we_i (wb_or1k_i_we_i), + .wbm_cyc_i (wb_or1k_i_cyc_i), + .wbm_stb_i (wb_or1k_i_stb_i), + .wbm_cti_i (wb_or1k_i_cti_i), + .wbm_bte_i (wb_or1k_i_bte_i), + .wbm_dat_o (wb_or1k_i_dat_o), + .wbm_ack_o (wb_or1k_i_ack_o), + .wbm_err_o (wb_or1k_i_err_o), + .wbm_rty_o (wb_or1k_i_rty_o), + .wbs_adr_o ({wb_sdram_ibus_adr_o, wb_rom0_adr_o}), + .wbs_dat_o ({wb_sdram_ibus_dat_o, wb_rom0_dat_o}), + .wbs_sel_o ({wb_sdram_ibus_sel_o, wb_rom0_sel_o}), + .wbs_we_o ({wb_sdram_ibus_we_o, wb_rom0_we_o}), + .wbs_cyc_o ({wb_sdram_ibus_cyc_o, wb_rom0_cyc_o}), + .wbs_stb_o ({wb_sdram_ibus_stb_o, wb_rom0_stb_o}), + .wbs_cti_o ({wb_sdram_ibus_cti_o, wb_rom0_cti_o}), + .wbs_bte_o ({wb_sdram_ibus_bte_o, wb_rom0_bte_o}), + .wbs_dat_i ({wb_sdram_ibus_dat_i, wb_rom0_dat_i}), + .wbs_ack_i ({wb_sdram_ibus_ack_i, wb_rom0_ack_i}), + .wbs_err_i ({wb_sdram_ibus_err_i, wb_rom0_err_i}), + .wbs_rty_i ({wb_sdram_ibus_rty_i, wb_rom0_rty_i})); + +wb_mux + #(.num_slaves (3), + .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}), + .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe})) + wb_mux_or1k_d + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_or1k_d_adr_i), + .wbm_dat_i (wb_or1k_d_dat_i), + .wbm_sel_i (wb_or1k_d_sel_i), + .wbm_we_i (wb_or1k_d_we_i), + .wbm_cyc_i (wb_or1k_d_cyc_i), + .wbm_stb_i (wb_or1k_d_stb_i), + .wbm_cti_i (wb_or1k_d_cti_i), + .wbm_bte_i (wb_or1k_d_bte_i), + .wbm_dat_o (wb_or1k_d_dat_o), + .wbm_ack_o (wb_or1k_d_ack_o), + .wbm_err_o (wb_or1k_d_err_o), + .wbm_rty_o (wb_or1k_d_rty_o), + .wbs_adr_o ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_or1k_d_uart0_adr, wb_m2s_or1k_d_gpio0_adr}), + .wbs_dat_o ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_or1k_d_uart0_dat, wb_m2s_or1k_d_gpio0_dat}), + .wbs_sel_o ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_or1k_d_uart0_sel, wb_m2s_or1k_d_gpio0_sel}), + .wbs_we_o ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_or1k_d_uart0_we, wb_m2s_or1k_d_gpio0_we}), + .wbs_cyc_o ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_or1k_d_uart0_cyc, wb_m2s_or1k_d_gpio0_cyc}), + .wbs_stb_o ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_or1k_d_uart0_stb, wb_m2s_or1k_d_gpio0_stb}), + .wbs_cti_o ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_or1k_d_uart0_cti, wb_m2s_or1k_d_gpio0_cti}), + .wbs_bte_o ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_or1k_d_uart0_bte, wb_m2s_or1k_d_gpio0_bte}), + .wbs_dat_i ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_or1k_d_uart0_dat, wb_s2m_or1k_d_gpio0_dat}), + .wbs_ack_i ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_or1k_d_uart0_ack, wb_s2m_or1k_d_gpio0_ack}), + .wbs_err_i ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_or1k_d_uart0_err, wb_s2m_or1k_d_gpio0_err}), + .wbs_rty_i ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_or1k_d_uart0_rty, wb_s2m_or1k_d_gpio0_rty})); + +wb_mux + #(.num_slaves (3), + .MATCH_ADDR ({32'h00000000, 32'h90000000, 32'h91000000}), + .MATCH_MASK ({32'hfe000000, 32'hffffffe0, 32'hfffffffe})) + wb_mux_dbg + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_dbg_adr_i), + .wbm_dat_i (wb_dbg_dat_i), + .wbm_sel_i (wb_dbg_sel_i), + .wbm_we_i (wb_dbg_we_i), + .wbm_cyc_i (wb_dbg_cyc_i), + .wbm_stb_i (wb_dbg_stb_i), + .wbm_cti_i (wb_dbg_cti_i), + .wbm_bte_i (wb_dbg_bte_i), + .wbm_dat_o (wb_dbg_dat_o), + .wbm_ack_o (wb_dbg_ack_o), + .wbm_err_o (wb_dbg_err_o), + .wbm_rty_o (wb_dbg_rty_o), + .wbs_adr_o ({wb_m2s_dbg_sdram_dbus_adr, wb_m2s_dbg_uart0_adr, wb_m2s_dbg_gpio0_adr}), + .wbs_dat_o ({wb_m2s_dbg_sdram_dbus_dat, wb_m2s_dbg_uart0_dat, wb_m2s_dbg_gpio0_dat}), + .wbs_sel_o ({wb_m2s_dbg_sdram_dbus_sel, wb_m2s_dbg_uart0_sel, wb_m2s_dbg_gpio0_sel}), + .wbs_we_o ({wb_m2s_dbg_sdram_dbus_we, wb_m2s_dbg_uart0_we, wb_m2s_dbg_gpio0_we}), + .wbs_cyc_o ({wb_m2s_dbg_sdram_dbus_cyc, wb_m2s_dbg_uart0_cyc, wb_m2s_dbg_gpio0_cyc}), + .wbs_stb_o ({wb_m2s_dbg_sdram_dbus_stb, wb_m2s_dbg_uart0_stb, wb_m2s_dbg_gpio0_stb}), + .wbs_cti_o ({wb_m2s_dbg_sdram_dbus_cti, wb_m2s_dbg_uart0_cti, wb_m2s_dbg_gpio0_cti}), + .wbs_bte_o ({wb_m2s_dbg_sdram_dbus_bte, wb_m2s_dbg_uart0_bte, wb_m2s_dbg_gpio0_bte}), + .wbs_dat_i ({wb_s2m_dbg_sdram_dbus_dat, wb_s2m_dbg_uart0_dat, wb_s2m_dbg_gpio0_dat}), + .wbs_ack_i ({wb_s2m_dbg_sdram_dbus_ack, wb_s2m_dbg_uart0_ack, wb_s2m_dbg_gpio0_ack}), + .wbs_err_i ({wb_s2m_dbg_sdram_dbus_err, wb_s2m_dbg_uart0_err, wb_s2m_dbg_gpio0_err}), + .wbs_rty_i ({wb_s2m_dbg_sdram_dbus_rty, wb_s2m_dbg_uart0_rty, wb_s2m_dbg_gpio0_rty})); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_uart0 + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_uart0_adr, wb_m2s_dbg_uart0_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_uart0_dat, wb_m2s_dbg_uart0_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_uart0_sel, wb_m2s_dbg_uart0_sel}), + .wbm_we_i ({wb_m2s_or1k_d_uart0_we, wb_m2s_dbg_uart0_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_uart0_cyc, wb_m2s_dbg_uart0_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_uart0_stb, wb_m2s_dbg_uart0_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_uart0_cti, wb_m2s_dbg_uart0_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_uart0_bte, wb_m2s_dbg_uart0_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_uart0_dat, wb_s2m_dbg_uart0_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_uart0_ack, wb_s2m_dbg_uart0_ack}), + .wbm_err_o ({wb_s2m_or1k_d_uart0_err, wb_s2m_dbg_uart0_err}), + .wbm_rty_o ({wb_s2m_or1k_d_uart0_rty, wb_s2m_dbg_uart0_rty}), + .wbs_adr_o (wb_m2s_resize_uart0_adr), + .wbs_dat_o (wb_m2s_resize_uart0_dat), + .wbs_sel_o (wb_m2s_resize_uart0_sel), + .wbs_we_o (wb_m2s_resize_uart0_we), + .wbs_cyc_o (wb_m2s_resize_uart0_cyc), + .wbs_stb_o (wb_m2s_resize_uart0_stb), + .wbs_cti_o (wb_m2s_resize_uart0_cti), + .wbs_bte_o (wb_m2s_resize_uart0_bte), + .wbs_dat_i (wb_s2m_resize_uart0_dat), + .wbs_ack_i (wb_s2m_resize_uart0_ack), + .wbs_err_i (wb_s2m_resize_uart0_err), + .wbs_rty_i (wb_s2m_resize_uart0_rty)); + +wb_data_resize + #(.aw (32), + .mdw (32), + .sdw (8)) + wb_data_resize_uart0 + (.wbm_adr_i (wb_m2s_resize_uart0_adr), + .wbm_dat_i (wb_m2s_resize_uart0_dat), + .wbm_sel_i (wb_m2s_resize_uart0_sel), + .wbm_we_i (wb_m2s_resize_uart0_we), + .wbm_cyc_i (wb_m2s_resize_uart0_cyc), + .wbm_stb_i (wb_m2s_resize_uart0_stb), + .wbm_cti_i (wb_m2s_resize_uart0_cti), + .wbm_bte_i (wb_m2s_resize_uart0_bte), + .wbm_dat_o (wb_s2m_resize_uart0_dat), + .wbm_ack_o (wb_s2m_resize_uart0_ack), + .wbm_err_o (wb_s2m_resize_uart0_err), + .wbm_rty_o (wb_s2m_resize_uart0_rty), + .wbs_adr_o (wb_uart0_adr_o), + .wbs_dat_o (wb_uart0_dat_o), + .wbs_we_o (wb_uart0_we_o), + .wbs_cyc_o (wb_uart0_cyc_o), + .wbs_stb_o (wb_uart0_stb_o), + .wbs_cti_o (wb_uart0_cti_o), + .wbs_bte_o (wb_uart0_bte_o), + .wbs_dat_i (wb_uart0_dat_i), + .wbs_ack_i (wb_uart0_ack_i), + .wbs_err_i (wb_uart0_err_i), + .wbs_rty_i (wb_uart0_rty_i)); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_gpio0 + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_gpio0_adr, wb_m2s_dbg_gpio0_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_gpio0_dat, wb_m2s_dbg_gpio0_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_gpio0_sel, wb_m2s_dbg_gpio0_sel}), + .wbm_we_i ({wb_m2s_or1k_d_gpio0_we, wb_m2s_dbg_gpio0_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_gpio0_cyc, wb_m2s_dbg_gpio0_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_gpio0_stb, wb_m2s_dbg_gpio0_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_gpio0_cti, wb_m2s_dbg_gpio0_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_gpio0_bte, wb_m2s_dbg_gpio0_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_gpio0_dat, wb_s2m_dbg_gpio0_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_gpio0_ack, wb_s2m_dbg_gpio0_ack}), + .wbm_err_o ({wb_s2m_or1k_d_gpio0_err, wb_s2m_dbg_gpio0_err}), + .wbm_rty_o ({wb_s2m_or1k_d_gpio0_rty, wb_s2m_dbg_gpio0_rty}), + .wbs_adr_o (wb_m2s_resize_gpio0_adr), + .wbs_dat_o (wb_m2s_resize_gpio0_dat), + .wbs_sel_o (wb_m2s_resize_gpio0_sel), + .wbs_we_o (wb_m2s_resize_gpio0_we), + .wbs_cyc_o (wb_m2s_resize_gpio0_cyc), + .wbs_stb_o (wb_m2s_resize_gpio0_stb), + .wbs_cti_o (wb_m2s_resize_gpio0_cti), + .wbs_bte_o (wb_m2s_resize_gpio0_bte), + .wbs_dat_i (wb_s2m_resize_gpio0_dat), + .wbs_ack_i (wb_s2m_resize_gpio0_ack), + .wbs_err_i (wb_s2m_resize_gpio0_err), + .wbs_rty_i (wb_s2m_resize_gpio0_rty)); + +wb_data_resize + #(.aw (32), + .mdw (32), + .sdw (8)) + wb_data_resize_gpio0 + (.wbm_adr_i (wb_m2s_resize_gpio0_adr), + .wbm_dat_i (wb_m2s_resize_gpio0_dat), + .wbm_sel_i (wb_m2s_resize_gpio0_sel), + .wbm_we_i (wb_m2s_resize_gpio0_we), + .wbm_cyc_i (wb_m2s_resize_gpio0_cyc), + .wbm_stb_i (wb_m2s_resize_gpio0_stb), + .wbm_cti_i (wb_m2s_resize_gpio0_cti), + .wbm_bte_i (wb_m2s_resize_gpio0_bte), + .wbm_dat_o (wb_s2m_resize_gpio0_dat), + .wbm_ack_o (wb_s2m_resize_gpio0_ack), + .wbm_err_o (wb_s2m_resize_gpio0_err), + .wbm_rty_o (wb_s2m_resize_gpio0_rty), + .wbs_adr_o (wb_gpio0_adr_o), + .wbs_dat_o (wb_gpio0_dat_o), + .wbs_we_o (wb_gpio0_we_o), + .wbs_cyc_o (wb_gpio0_cyc_o), + .wbs_stb_o (wb_gpio0_stb_o), + .wbs_cti_o (wb_gpio0_cti_o), + .wbs_bte_o (wb_gpio0_bte_o), + .wbs_dat_i (wb_gpio0_dat_i), + .wbs_ack_i (wb_gpio0_ack_i), + .wbs_err_i (wb_gpio0_err_i), + .wbs_rty_i (wb_gpio0_rty_i)); + +wb_arbiter + #(.num_masters (2)) + wb_arbiter_sdram_dbus + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i ({wb_m2s_or1k_d_sdram_dbus_adr, wb_m2s_dbg_sdram_dbus_adr}), + .wbm_dat_i ({wb_m2s_or1k_d_sdram_dbus_dat, wb_m2s_dbg_sdram_dbus_dat}), + .wbm_sel_i ({wb_m2s_or1k_d_sdram_dbus_sel, wb_m2s_dbg_sdram_dbus_sel}), + .wbm_we_i ({wb_m2s_or1k_d_sdram_dbus_we, wb_m2s_dbg_sdram_dbus_we}), + .wbm_cyc_i ({wb_m2s_or1k_d_sdram_dbus_cyc, wb_m2s_dbg_sdram_dbus_cyc}), + .wbm_stb_i ({wb_m2s_or1k_d_sdram_dbus_stb, wb_m2s_dbg_sdram_dbus_stb}), + .wbm_cti_i ({wb_m2s_or1k_d_sdram_dbus_cti, wb_m2s_dbg_sdram_dbus_cti}), + .wbm_bte_i ({wb_m2s_or1k_d_sdram_dbus_bte, wb_m2s_dbg_sdram_dbus_bte}), + .wbm_dat_o ({wb_s2m_or1k_d_sdram_dbus_dat, wb_s2m_dbg_sdram_dbus_dat}), + .wbm_ack_o ({wb_s2m_or1k_d_sdram_dbus_ack, wb_s2m_dbg_sdram_dbus_ack}), + .wbm_err_o ({wb_s2m_or1k_d_sdram_dbus_err, wb_s2m_dbg_sdram_dbus_err}), + .wbm_rty_o ({wb_s2m_or1k_d_sdram_dbus_rty, wb_s2m_dbg_sdram_dbus_rty}), + .wbs_adr_o (wb_sdram_dbus_adr_o), + .wbs_dat_o (wb_sdram_dbus_dat_o), + .wbs_sel_o (wb_sdram_dbus_sel_o), + .wbs_we_o (wb_sdram_dbus_we_o), + .wbs_cyc_o (wb_sdram_dbus_cyc_o), + .wbs_stb_o (wb_sdram_dbus_stb_o), + .wbs_cti_o (wb_sdram_dbus_cti_o), + .wbs_bte_o (wb_sdram_dbus_bte_o), + .wbs_dat_i (wb_sdram_dbus_dat_i), + .wbs_ack_i (wb_sdram_dbus_ack_i), + .wbs_err_i (wb_sdram_dbus_err_i), + .wbs_rty_i (wb_sdram_dbus_rty_i)); + +endmodule diff --git a/systems/de2/rtl/verilog/wb_intercon.vh b/systems/de2/rtl/verilog/wb_intercon.vh new file mode 100644 index 00000000..cc8a6714 --- /dev/null +++ b/systems/de2/rtl/verilog/wb_intercon.vh @@ -0,0 +1,197 @@ +wire [31:0] wb_m2s_or1k_i_adr; +wire [31:0] wb_m2s_or1k_i_dat; +wire [3:0] wb_m2s_or1k_i_sel; +wire wb_m2s_or1k_i_we; +wire wb_m2s_or1k_i_cyc; +wire wb_m2s_or1k_i_stb; +wire [2:0] wb_m2s_or1k_i_cti; +wire [1:0] wb_m2s_or1k_i_bte; +wire [31:0] wb_s2m_or1k_i_dat; +wire wb_s2m_or1k_i_ack; +wire wb_s2m_or1k_i_err; +wire wb_s2m_or1k_i_rty; +wire [31:0] wb_m2s_or1k_d_adr; +wire [31:0] wb_m2s_or1k_d_dat; +wire [3:0] wb_m2s_or1k_d_sel; +wire wb_m2s_or1k_d_we; +wire wb_m2s_or1k_d_cyc; +wire wb_m2s_or1k_d_stb; +wire [2:0] wb_m2s_or1k_d_cti; +wire [1:0] wb_m2s_or1k_d_bte; +wire [31:0] wb_s2m_or1k_d_dat; +wire wb_s2m_or1k_d_ack; +wire wb_s2m_or1k_d_err; +wire wb_s2m_or1k_d_rty; +wire [31:0] wb_m2s_dbg_adr; +wire [31:0] wb_m2s_dbg_dat; +wire [3:0] wb_m2s_dbg_sel; +wire wb_m2s_dbg_we; +wire wb_m2s_dbg_cyc; +wire wb_m2s_dbg_stb; +wire [2:0] wb_m2s_dbg_cti; +wire [1:0] wb_m2s_dbg_bte; +wire [31:0] wb_s2m_dbg_dat; +wire wb_s2m_dbg_ack; +wire wb_s2m_dbg_err; +wire wb_s2m_dbg_rty; +wire [31:0] wb_m2s_uart0_adr; +wire [31:0] wb_m2s_uart0_dat; +wire [3:0] wb_m2s_uart0_sel; +wire wb_m2s_uart0_we; +wire wb_m2s_uart0_cyc; +wire wb_m2s_uart0_stb; +wire [2:0] wb_m2s_uart0_cti; +wire [1:0] wb_m2s_uart0_bte; +wire [31:0] wb_s2m_uart0_dat; +wire wb_s2m_uart0_ack; +wire wb_s2m_uart0_err; +wire wb_s2m_uart0_rty; +wire [31:0] wb_m2s_gpio0_adr; +wire [31:0] wb_m2s_gpio0_dat; +wire [3:0] wb_m2s_gpio0_sel; +wire wb_m2s_gpio0_we; +wire wb_m2s_gpio0_cyc; +wire wb_m2s_gpio0_stb; +wire [2:0] wb_m2s_gpio0_cti; +wire [1:0] wb_m2s_gpio0_bte; +wire [31:0] wb_s2m_gpio0_dat; +wire wb_s2m_gpio0_ack; +wire wb_s2m_gpio0_err; +wire wb_s2m_gpio0_rty; +wire [31:0] wb_m2s_sdram_dbus_adr; +wire [31:0] wb_m2s_sdram_dbus_dat; +wire [3:0] wb_m2s_sdram_dbus_sel; +wire wb_m2s_sdram_dbus_we; +wire wb_m2s_sdram_dbus_cyc; +wire wb_m2s_sdram_dbus_stb; +wire [2:0] wb_m2s_sdram_dbus_cti; +wire [1:0] wb_m2s_sdram_dbus_bte; +wire [31:0] wb_s2m_sdram_dbus_dat; +wire wb_s2m_sdram_dbus_ack; +wire wb_s2m_sdram_dbus_err; +wire wb_s2m_sdram_dbus_rty; +wire [31:0] wb_m2s_rom0_adr; +wire [31:0] wb_m2s_rom0_dat; +wire [3:0] wb_m2s_rom0_sel; +wire wb_m2s_rom0_we; +wire wb_m2s_rom0_cyc; +wire wb_m2s_rom0_stb; +wire [2:0] wb_m2s_rom0_cti; +wire [1:0] wb_m2s_rom0_bte; +wire [31:0] wb_s2m_rom0_dat; +wire wb_s2m_rom0_ack; +wire wb_s2m_rom0_err; +wire wb_s2m_rom0_rty; +wire [31:0] wb_m2s_sdram_ibus_adr; +wire [31:0] wb_m2s_sdram_ibus_dat; +wire [3:0] wb_m2s_sdram_ibus_sel; +wire wb_m2s_sdram_ibus_we; +wire wb_m2s_sdram_ibus_cyc; +wire wb_m2s_sdram_ibus_stb; +wire [2:0] wb_m2s_sdram_ibus_cti; +wire [1:0] wb_m2s_sdram_ibus_bte; +wire [31:0] wb_s2m_sdram_ibus_dat; +wire wb_s2m_sdram_ibus_ack; +wire wb_s2m_sdram_ibus_err; +wire wb_s2m_sdram_ibus_rty; + +wb_intercon wb_intercon0 + (.wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_or1k_i_adr_i (wb_m2s_or1k_i_adr), + .wb_or1k_i_dat_i (wb_m2s_or1k_i_dat), + .wb_or1k_i_sel_i (wb_m2s_or1k_i_sel), + .wb_or1k_i_we_i (wb_m2s_or1k_i_we), + .wb_or1k_i_cyc_i (wb_m2s_or1k_i_cyc), + .wb_or1k_i_stb_i (wb_m2s_or1k_i_stb), + .wb_or1k_i_cti_i (wb_m2s_or1k_i_cti), + .wb_or1k_i_bte_i (wb_m2s_or1k_i_bte), + .wb_or1k_i_dat_o (wb_s2m_or1k_i_dat), + .wb_or1k_i_ack_o (wb_s2m_or1k_i_ack), + .wb_or1k_i_err_o (wb_s2m_or1k_i_err), + .wb_or1k_i_rty_o (wb_s2m_or1k_i_rty), + .wb_or1k_d_adr_i (wb_m2s_or1k_d_adr), + .wb_or1k_d_dat_i (wb_m2s_or1k_d_dat), + .wb_or1k_d_sel_i (wb_m2s_or1k_d_sel), + .wb_or1k_d_we_i (wb_m2s_or1k_d_we), + .wb_or1k_d_cyc_i (wb_m2s_or1k_d_cyc), + .wb_or1k_d_stb_i (wb_m2s_or1k_d_stb), + .wb_or1k_d_cti_i (wb_m2s_or1k_d_cti), + .wb_or1k_d_bte_i (wb_m2s_or1k_d_bte), + .wb_or1k_d_dat_o (wb_s2m_or1k_d_dat), + .wb_or1k_d_ack_o (wb_s2m_or1k_d_ack), + .wb_or1k_d_err_o (wb_s2m_or1k_d_err), + .wb_or1k_d_rty_o (wb_s2m_or1k_d_rty), + .wb_dbg_adr_i (wb_m2s_dbg_adr), + .wb_dbg_dat_i (wb_m2s_dbg_dat), + .wb_dbg_sel_i (wb_m2s_dbg_sel), + .wb_dbg_we_i (wb_m2s_dbg_we), + .wb_dbg_cyc_i (wb_m2s_dbg_cyc), + .wb_dbg_stb_i (wb_m2s_dbg_stb), + .wb_dbg_cti_i (wb_m2s_dbg_cti), + .wb_dbg_bte_i (wb_m2s_dbg_bte), + .wb_dbg_dat_o (wb_s2m_dbg_dat), + .wb_dbg_ack_o (wb_s2m_dbg_ack), + .wb_dbg_err_o (wb_s2m_dbg_err), + .wb_dbg_rty_o (wb_s2m_dbg_rty), + .wb_uart0_adr_o (wb_m2s_uart0_adr), + .wb_uart0_dat_o (wb_m2s_uart0_dat), + .wb_uart0_sel_o (wb_m2s_uart0_sel), + .wb_uart0_we_o (wb_m2s_uart0_we), + .wb_uart0_cyc_o (wb_m2s_uart0_cyc), + .wb_uart0_stb_o (wb_m2s_uart0_stb), + .wb_uart0_cti_o (wb_m2s_uart0_cti), + .wb_uart0_bte_o (wb_m2s_uart0_bte), + .wb_uart0_dat_i (wb_s2m_uart0_dat), + .wb_uart0_ack_i (wb_s2m_uart0_ack), + .wb_uart0_err_i (wb_s2m_uart0_err), + .wb_uart0_rty_i (wb_s2m_uart0_rty), + .wb_gpio0_adr_o (wb_m2s_gpio0_adr), + .wb_gpio0_dat_o (wb_m2s_gpio0_dat), + .wb_gpio0_sel_o (wb_m2s_gpio0_sel), + .wb_gpio0_we_o (wb_m2s_gpio0_we), + .wb_gpio0_cyc_o (wb_m2s_gpio0_cyc), + .wb_gpio0_stb_o (wb_m2s_gpio0_stb), + .wb_gpio0_cti_o (wb_m2s_gpio0_cti), + .wb_gpio0_bte_o (wb_m2s_gpio0_bte), + .wb_gpio0_dat_i (wb_s2m_gpio0_dat), + .wb_gpio0_ack_i (wb_s2m_gpio0_ack), + .wb_gpio0_err_i (wb_s2m_gpio0_err), + .wb_gpio0_rty_i (wb_s2m_gpio0_rty), + .wb_sdram_dbus_adr_o (wb_m2s_sdram_dbus_adr), + .wb_sdram_dbus_dat_o (wb_m2s_sdram_dbus_dat), + .wb_sdram_dbus_sel_o (wb_m2s_sdram_dbus_sel), + .wb_sdram_dbus_we_o (wb_m2s_sdram_dbus_we), + .wb_sdram_dbus_cyc_o (wb_m2s_sdram_dbus_cyc), + .wb_sdram_dbus_stb_o (wb_m2s_sdram_dbus_stb), + .wb_sdram_dbus_cti_o (wb_m2s_sdram_dbus_cti), + .wb_sdram_dbus_bte_o (wb_m2s_sdram_dbus_bte), + .wb_sdram_dbus_dat_i (wb_s2m_sdram_dbus_dat), + .wb_sdram_dbus_ack_i (wb_s2m_sdram_dbus_ack), + .wb_sdram_dbus_err_i (wb_s2m_sdram_dbus_err), + .wb_sdram_dbus_rty_i (wb_s2m_sdram_dbus_rty), + .wb_rom0_adr_o (wb_m2s_rom0_adr), + .wb_rom0_dat_o (wb_m2s_rom0_dat), + .wb_rom0_sel_o (wb_m2s_rom0_sel), + .wb_rom0_we_o (wb_m2s_rom0_we), + .wb_rom0_cyc_o (wb_m2s_rom0_cyc), + .wb_rom0_stb_o (wb_m2s_rom0_stb), + .wb_rom0_cti_o (wb_m2s_rom0_cti), + .wb_rom0_bte_o (wb_m2s_rom0_bte), + .wb_rom0_dat_i (wb_s2m_rom0_dat), + .wb_rom0_ack_i (wb_s2m_rom0_ack), + .wb_rom0_err_i (wb_s2m_rom0_err), + .wb_rom0_rty_i (wb_s2m_rom0_rty), + .wb_sdram_ibus_adr_o (wb_m2s_sdram_ibus_adr), + .wb_sdram_ibus_dat_o (wb_m2s_sdram_ibus_dat), + .wb_sdram_ibus_sel_o (wb_m2s_sdram_ibus_sel), + .wb_sdram_ibus_we_o (wb_m2s_sdram_ibus_we), + .wb_sdram_ibus_cyc_o (wb_m2s_sdram_ibus_cyc), + .wb_sdram_ibus_stb_o (wb_m2s_sdram_ibus_stb), + .wb_sdram_ibus_cti_o (wb_m2s_sdram_ibus_cti), + .wb_sdram_ibus_bte_o (wb_m2s_sdram_ibus_bte), + .wb_sdram_ibus_dat_i (wb_s2m_sdram_ibus_dat), + .wb_sdram_ibus_ack_i (wb_s2m_sdram_ibus_ack), + .wb_sdram_ibus_err_i (wb_s2m_sdram_ibus_err), + .wb_sdram_ibus_rty_i (wb_s2m_sdram_ibus_rty)); + diff --git a/systems/de2/scripts/build_summary b/systems/de2/scripts/build_summary new file mode 100755 index 00000000..a9422658 --- /dev/null +++ b/systems/de2/scripts/build_summary @@ -0,0 +1,21 @@ +#!/bin/bash + +FITTER_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Summary" | gawk '{print $1}' FS=":") +FITTER_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.fit.rpt | grep -nhr "; Fitter Settings" | gawk '{print $1}' FS=":") + +FITTER_REPORT_START=$(($FITTER_REPORT_START - 1)) +FITTER_REPORT_END=$(($FITTER_REPORT_END - 4)) + +echo -e "\033[31m" +sed -n ${FITTER_REPORT_START},${FITTER_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.fit.rpt + + +FMAX_REPORT_START=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "; Slow Model Fmax Summary" | gawk '{print $1}' FS=":") +FMAX_REPORT_END=$(cat ${BUILD_ROOT}/bld-quartus/de2.sta.rpt | grep -nhr "This panel reports FMAX" | gawk '{print $1}' FS=":") + +FMAX_REPORT_START=$(($FMAX_REPORT_START - 1)) +FMAX_REPORT_END=$(($FMAX_REPORT_END - 1)) + +echo +sed -n ${FMAX_REPORT_START},${FMAX_REPORT_END}p ${BUILD_ROOT}/bld-quartus/de2.sta.rpt +echo -e "\033[0m" diff --git a/systems/generic/bench/orpsoc_tb.v b/systems/generic/bench/orpsoc_tb.v deleted file mode 100644 index fae0c270..00000000 --- a/systems/generic/bench/orpsoc_tb.v +++ /dev/null @@ -1,66 +0,0 @@ -`include "timescale.v" - -module orpsoc_tb; - - reg clk = 0; - reg rst_n = 1; - - always - #5 clk <= ~clk; - - initial begin - #100 rst_n <= 0; - #200 rst_n <= 1; - end - - vlog_tb_utils vlog_tb_utils0(); - - integer mem_words; - integer i; - reg [31:0] mem_word; - reg [1023:0] elf_file; - - initial begin - if($value$plusargs("elf_load=%s", elf_file)) begin - $elf_load_file(elf_file); - - mem_words = $elf_get_size/4; - for(i=0; i < mem_words; i = i+1) - orpsoc_tb.dut.ram_wb0.ram_wb_b3_0.mem[i] = $elf_read_32(i*4); - end else - $display("No ELF file specified"); - end - - reg enable_jtag_vpi; - initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi"); - - jtag_vpi jtag_vpi0 - (.tms (tms), - .tck (tck), - .tdi (tdi), - .tdo (tdo), - .enable (enable_jtag_vpi), - .init_done (orpsoc_tb.dut.wb_rst)); - - orpsoc_top dut - (.clk_pad_i (clk), - .rst_n_pad_i (rst_n), - //JTAG interface - .tms_pad_i(tms), - .tck_pad_i(tck), - .tdi_pad_i(tdi), - .tdo_pad_o(tdo), - //UART interface - .uart0_srx_pad_i(uart), - .uart0_stx_pad_o(uart)); - - or1200_monitor i_monitor(); - - //FIXME: Get correct baud rate from parameter - uart_decoder - #(.uart_baudrate_period_ns(8680/2)) - uart_decoder0 - (.clk(clk), - .uart_tx(uart)); - -endmodule diff --git a/systems/generic/bench/uart_decoder.v b/systems/generic/bench/uart_decoder.v deleted file mode 100644 index 8046c3db..00000000 --- a/systems/generic/bench/uart_decoder.v +++ /dev/null @@ -1,93 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// ORPSoC Testbench UART Decoder //// -//// //// -//// Description //// -//// ORPSoC Testbench UART output decoder //// -//// //// -//// To Do: //// -//// //// -//// //// -//// Author(s): //// -//// - jb, jb@orsoc.se //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2009 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals. -`timescale 1ns/1ns -module uart_decoder(clk, uart_tx); - - input clk; - input uart_tx; - - // Default baud of 115200, period (ns) - parameter uart_baudrate_period_ns = 8680; - - // Something to trigger the task - always @(posedge clk) - uart_decoder; - - task uart_decoder; - reg [7:0] tx_byte; - begin - while (uart_tx !== 1'b1) - @(uart_tx); - // Wait for start bit - while (uart_tx !== 1'b0) - @(uart_tx); - #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2)); - tx_byte[0] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[1] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[2] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[3] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[4] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[5] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[6] = uart_tx; - #uart_baudrate_period_ns; - tx_byte[7] = uart_tx; - #uart_baudrate_period_ns; - //Check for stop bit - if (uart_tx !== 1'b1) - begin - // Wait for return to idle - while (uart_tx !== 1'b1) - @(uart_tx); - end - // display the char - $write("%c", tx_byte); - end - endtask // user_uart_read_byte - -endmodule // uart_decoder diff --git a/systems/generic/generic.system b/systems/generic/generic.system deleted file mode 100644 index 1e024e79..00000000 --- a/systems/generic/generic.system +++ /dev/null @@ -1,3 +0,0 @@ -SAPI=1 -[main] -description = "Generic technology independent OpenRISC system diff --git a/systems/generic/rtl/verilog/include/orpsoc-params.v b/systems/generic/rtl/verilog/include/orpsoc-params.v deleted file mode 100644 index daf74eab..00000000 --- a/systems/generic/rtl/verilog/include/orpsoc-params.v +++ /dev/null @@ -1,95 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// orpsoc-params //// -//// //// -//// Top level ORPSoC parameters file //// -//// //// -//// Included in toplevel and testbench //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -/////////////////////////// -// // -// Peripheral parameters // -// // -/////////////////////////// - -// UART 0 params -parameter uart0_wb_adr = 8'h90; -parameter uart0_aw = 3; - -// Interrupt generator (intgen) params -parameter intgen_wb_adr = 8'he1; -parameter intgen_addr_width = 1; - -// ROM -parameter rom0_dw = 32; -parameter rom0_aw = 6; - -////////////////////////////////////////////////////// -// // -// Wishbone bus parameters // -// // -////////////////////////////////////////////////////// - -//////////////////////// -// // -// Arbiter parameters // -// // -//////////////////////// - -parameter wb_dw = 32; // Default Wishbone full word width -parameter wb_aw = 32; // Default Wishbone full address width - -/////////////////////////// -// // -// Instruction bus // -// // -/////////////////////////// - -parameter ibus_slaves = 2; -parameter rom0_slave_nr = 0; -parameter mc0_ibus_slave_nr = 1; - -/////////////////////////// -// // -// Data bus // -// // -/////////////////////////// -parameter dbus_slaves = 2; -parameter mc0_dbus_slave_nr = 0; -parameter bbus_slave_nr = 1; - -/////////////////////////////// -// // -// Byte-wide peripheral bus // -// // -/////////////////////////////// -parameter bbus_slaves = 2; -parameter uart_slave_nr = 0; -parameter intgen_slave_nr = 1; diff --git a/systems/generic/rtl/verilog/include/timescale.v b/systems/generic/rtl/verilog/include/timescale.v deleted file mode 100644 index ff200d44..00000000 --- a/systems/generic/rtl/verilog/include/timescale.v +++ /dev/null @@ -1 +0,0 @@ -`timescale 1ns/10ps diff --git a/systems/generic/rtl/verilog/intgen.v b/systems/generic/rtl/verilog/intgen.v deleted file mode 100644 index 3caf8a26..00000000 --- a/systems/generic/rtl/verilog/intgen.v +++ /dev/null @@ -1,70 +0,0 @@ -/* - * - * Interrupt generation module - * - * A counter is loaded with a value over the Wishbone bus interface, which then - * counts down and issues an interrupt when the value is 1 - * - * - * Register 0 - write only - counter value - * - * Register 1 - read/write - interrupt status/clear - * - */ - -module intgen( - clk_i, - rst_i, - wb_adr_i, - wb_cyc_i, - wb_stb_i, - wb_dat_i, - wb_we_i, - wb_ack_o, - wb_dat_o, - - irq_o - ); - - - input clk_i; - input rst_i; - - input wb_adr_i; - input wb_cyc_i; - input wb_stb_i; - input [7:0] wb_dat_i; - input wb_we_i; - output wb_ack_o; - output [7:0] wb_dat_o; - - output reg irq_o; - - reg [7:0] counter; - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - counter <= 0; - else if (wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i) - // Write to adress 0 loads counter - counter <= wb_dat_i; - else if (|counter) - counter <= counter - 1; - - always @(posedge clk_i or posedge rst_i) - if (rst_i) - irq_o <= 0; - else if (wb_stb_i & wb_cyc_i & wb_we_i & wb_adr_i) - // Clear on write to reg 1 - irq_o <= 0; - else if (counter==8'd1) - irq_o <= 1; - - assign wb_ack_o = wb_stb_i & wb_cyc_i; - assign wb_dat_o = (wb_adr_i) ? {7'd0,irq_o} : counter; - -endmodule // intgen - - - - \ No newline at end of file diff --git a/systems/generic/rtl/verilog/orpsoc_top.v b/systems/generic/rtl/verilog/orpsoc_top.v deleted file mode 100644 index db9b2017..00000000 --- a/systems/generic/rtl/verilog/orpsoc_top.v +++ /dev/null @@ -1,780 +0,0 @@ -////////////////////////////////////////////////////////////////////// -/// //// -/// ORPSoC top level //// -/// //// -/// Define I/O ports, instantiate modules //// -/// //// -/// Julius Baxter, julius@opencores.org //// -/// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`include "orpsoc-defines.v" - -module orpsoc_top - ( - input clk_pad_i, - input rst_n_pad_i, - //JTAG Interface - output tdo_pad_o, - input tms_pad_i, - input tck_pad_i, - input tdi_pad_i, - //UART Interface - input uart0_srx_pad_i, - output uart0_stx_pad_o - ); - -`include "orpsoc-params.v" - - parameter IDCODE_VALUE=32'h14951185; - //////////////////////////////////////////////////////////////////////// - // - // Clock and reset generation module - // - //////////////////////////////////////////////////////////////////////// - - wire async_rst; - wire wb_clk, wb_rst; - wire dbg_tck; - - clkgen clkgen0 - ( - .clk_pad_i (clk_pad_i), - .rst_n_pad_i (rst_n_pad_i), - .async_rst_o (async_rst), - //Wishbone clocks - .wb_clk_o (wb_clk), - .wb_rst_o (wb_rst), - //JTAG clocks - .tck_pad_i (tck_pad_i), - .dbg_tck_o (dbg_tck)); - - // OR1200 instruction bus wires - wire [wb_aw-1:0] wb_or1200_i_adr; - wire [wb_dw-1:0] wb_or1200_i_dat; - wire [3:0] wb_or1200_i_sel; - wire wb_or1200_i_we; - wire wb_or1200_i_cyc; - wire wb_or1200_i_stb; - wire [2:0] wb_or1200_i_cti; - wire [1:0] wb_or1200_i_bte; - - wire [wb_dw-1:0] wb_or1200_i_sdt; - wire wb_or1200_i_ack; - wire wb_or1200_i_err; - wire wb_or1200_i_rty; - - // OR1200 data bus wires - wire [wb_aw-1:0] wb_or1200_d_adr; - wire [wb_dw-1:0] wb_or1200_d_dat; - wire [3:0] wb_or1200_d_sel; - wire wb_or1200_d_we; - wire wb_or1200_d_cyc; - wire wb_or1200_d_stb; - wire [2:0] wb_or1200_d_cti; - wire [1:0] wb_or1200_d_bte; - - wire [wb_dw-1:0] wb_or1200_d_sdt; - wire wb_or1200_d_ack; - wire wb_or1200_d_err; - wire wb_or1200_d_rty; - - // Debug interface bus wires - wire [wb_aw-1:0] wb_dbg_adr; - wire [wb_dw-1:0] wb_dbg_dat; - wire [3:0] wb_dbg_sel; - wire wb_dbg_we; - wire wb_dbg_cyc; - wire wb_dbg_stb; - wire [2:0] wb_dbg_cti; - wire [1:0] wb_dbg_bte; - - wire [wb_dw-1:0] wb_dbg_sdt; - wire wb_dbg_ack; - wire wb_dbg_err; - wire wb_dbg_rty; - - wire [wb_aw-1:0] wbm_dbus_adr; - wire [wb_dw-1:0] wbm_dbus_dat; - wire [3:0] wbm_dbus_sel; - wire wbm_dbus_we; - wire wbm_dbus_cyc; - wire wbm_dbus_stb; - wire [2:0] wbm_dbus_cti; - wire [1:0] wbm_dbus_bte; - - wire [wb_dw-1:0] wbm_dbus_sdt; - wire wbm_dbus_ack; - wire wbm_dbus_err; - wire wbm_dbus_rty; - - // Byte bus bridge master signals - wire [wb_dw-1:0] wb_bbus_sdt; - wire wb_bbus_ack; - wire wb_bbus_err; - wire wb_bbus_rty; - - // Instruction bus slave wires // - - // rom0 instruction bus wires - wire [31:0] wb_rom0_sdt; - wire wb_rom0_ack; - wire wb_rom0_err; - wire wb_rom0_rty; - // mc0 instruction bus wires - wire [31:0] wb_mc0_ibus_sdt; - wire wb_mc0_ibus_ack; - wire wb_mc0_ibus_err; - wire wb_mc0_ibus_rty; - // mc0 data bus wires - wire [31:0] wb_mc0_dbus_sdt; - wire wb_mc0_dbus_ack; - wire wb_mc0_dbus_err; - wire wb_mc0_dbus_rty; - - // Data bus slave wires // - - // uart0 wires - wire [7:0] wb_uart_sdt; - wire wb_uart_ack; - wire wb_uart_err; - wire wb_uart_rty; - // intgen wires - wire [7:0] wb_intgen_sdt; - wire wb_intgen_ack; - wire wb_intgen_err; - wire wb_intgen_rty; - - wire [ibus_slaves-1:0] ibus_slave_sel = - {wb_or1200_i_adr[31:28] != 4'hf, - wb_or1200_i_adr[31:28] == 4'hf}; - - - wire [31:0] wb_ibus_adr; - wire [31:0] wb_ibus_dat; - wire [3:0] wb_ibus_sel; - wire wb_ibus_we; - wire [ibus_slaves-1:0] wb_ibus_cyc; - wire [ibus_slaves-1:0] wb_ibus_stb; - wire [2:0] wb_ibus_cti; - wire [1:0] wb_ibus_bte; - - - // - // Wishbone instruction bus arbiter - // - wb_mux wb_mux_ibus - (.wb_clk (wb_clk), - .wb_rst (wb_rst), - .slave_sel_i (ibus_slave_sel), - // Master Interface - .wbm_adr_i (wb_or1200_i_adr), - .wbm_dat_i (wb_or1200_i_dat), - .wbm_sel_i (wb_or1200_i_sel), - .wbm_we_i (wb_or1200_i_we), - .wbm_cyc_i (wb_or1200_i_cyc), - .wbm_stb_i (wb_or1200_i_stb), - .wbm_cti_i (wb_or1200_i_cti), - .wbm_bte_i (wb_or1200_i_bte), - .wbm_sdt_o (wb_or1200_i_sdt), - .wbm_ack_o (wb_or1200_i_ack), - .wbm_err_o (wb_or1200_i_err), - .wbm_rty_o (wb_or1200_i_rty), - //Slave interface - .wbs_adr_o (wb_ibus_adr), - .wbs_dat_o (wb_ibus_dat), - .wbs_sel_o (wb_ibus_sel), - .wbs_we_o (wb_ibus_we), - .wbs_cyc_o (wb_ibus_cyc), - .wbs_stb_o (wb_ibus_stb), - .wbs_cti_o (wb_ibus_cti), - .wbs_bte_o (wb_ibus_bte), - .wbs_sdt_i ({wb_mc0_ibus_sdt, wb_rom0_sdt}), - .wbs_ack_i ({wb_mc0_ibus_ack, wb_rom0_ack}), - .wbs_err_i ({wb_mc0_ibus_err, wb_rom0_err}), - .wbs_rty_i ({wb_mc0_ibus_rty, wb_rom0_rty})); - - - wb_arbiter wb_arbiter_dbus - (.wb_clk (wb_clk), - .wb_rst (wb_rst), - // Master Interface - .wbm_adr_i ({wb_dbg_adr, wb_or1200_d_adr}), - .wbm_dat_i ({wb_dbg_dat, wb_or1200_d_dat}), - .wbm_sel_i ({wb_dbg_sel, wb_or1200_d_sel}), - .wbm_we_i ({wb_dbg_we , wb_or1200_d_we }), - .wbm_cyc_i ({wb_dbg_cyc, wb_or1200_d_cyc}), - .wbm_stb_i ({wb_dbg_stb, wb_or1200_d_stb}), - .wbm_cti_i ({wb_dbg_cti, wb_or1200_d_cti}), - .wbm_bte_i ({wb_dbg_bte, wb_or1200_d_bte}), - .wbm_sdt_o ({wb_dbg_sdt, wb_or1200_d_sdt}), - .wbm_ack_o ({wb_dbg_ack, wb_or1200_d_ack}), - .wbm_err_o ({wb_dbg_err, wb_or1200_d_err}), - .wbm_rty_o ({wb_dbg_rty, wb_or1200_d_rty}), - //Slave interface - .wbs_adr_o (wbm_dbus_adr), - .wbs_dat_o (wbm_dbus_dat), - .wbs_sel_o (wbm_dbus_sel), - .wbs_we_o (wbm_dbus_we), - .wbs_cyc_o (wbm_dbus_cyc), - .wbs_stb_o (wbm_dbus_stb), - .wbs_cti_o (wbm_dbus_cti), - .wbs_bte_o (wbm_dbus_bte), - .wbs_sdt_i (wbm_dbus_sdt), - .wbs_ack_i (wbm_dbus_ack), - .wbs_err_i (wbm_dbus_err), - .wbs_rty_i (wbm_dbus_rty)); - - wire [dbus_slaves-1:0] dbus_slave_sel = - {wbm_dbus_adr[31:28] != 4'h0, - wbm_dbus_adr[31:28] == 4'h0}; - - wire [31:0] wb_dbus_adr; - wire [31:0] wb_dbus_dat; - wire [3:0] wb_dbus_sel; - wire wb_dbus_we; - wire [ibus_slaves-1:0] wb_dbus_cyc; - wire [ibus_slaves-1:0] wb_dbus_stb; - wire [2:0] wb_dbus_cti; - wire [1:0] wb_dbus_bte; - - // - // Wishbone data bus multiplexer - // - wb_mux wb_mux_dbus - (.wb_clk (wb_clk), - .wb_rst (wb_rst), - .slave_sel_i (dbus_slave_sel), - // Master Interface - .wbm_adr_i (wbm_dbus_adr), - .wbm_dat_i (wbm_dbus_dat), - .wbm_sel_i (wbm_dbus_sel), - .wbm_we_i (wbm_dbus_we), - .wbm_cyc_i (wbm_dbus_cyc), - .wbm_stb_i (wbm_dbus_stb), - .wbm_cti_i (wbm_dbus_cti), - .wbm_bte_i (wbm_dbus_bte), - .wbm_sdt_o (wbm_dbus_sdt), - .wbm_ack_o (wbm_dbus_ack), - .wbm_err_o (wbm_dbus_err), - .wbm_rty_o (wbm_dbus_rty), - //Slave interface - .wbs_adr_o (wb_dbus_adr), - .wbs_dat_o (wb_dbus_dat), - .wbs_sel_o (wb_dbus_sel), - .wbs_we_o (wb_dbus_we), - .wbs_cyc_o (wb_dbus_cyc), - .wbs_stb_o (wb_dbus_stb), - .wbs_cti_o (wb_dbus_cti), - .wbs_bte_o (wb_dbus_bte), - .wbs_sdt_i ({wb_bbus_sdt, wb_mc0_dbus_sdt}), - .wbs_ack_i ({wb_bbus_ack, wb_mc0_dbus_ack}), - .wbs_err_i ({wb_bbus_err, wb_mc0_dbus_err}), - .wbs_rty_i ({wb_bbus_rty, wb_mc0_dbus_rty})); - - - wire [bbus_slaves-1:0] bbus_slave_sel = - {wb_or1200_d_adr[31:24] == 8'he1, - wb_or1200_d_adr[31:24] == 8'h90}; - - wire [31:0] wb_bbus_adr; - wire [7:0] wb_bbus_dat; - wire [3:0] wb_bbus_sel; - wire wb_bbus_we; - wire [bbus_slaves-1:0] wb_bbus_cyc; - wire [bbus_slaves-1:0] wb_bbus_stb; - wire [2:0] wb_bbus_cti; - wire [1:0] wb_bbus_bte; - - // - // Wishbone byte-wide bus arbiter - // - wb_mux - #(.sdw(8)) - wb_mux_bbus - (.wb_clk (wb_clk), - .wb_rst (wb_rst), - .slave_sel_i (bbus_slave_sel), - //Master interface - .wbm_adr_i (wb_dbus_adr), - .wbm_dat_i (wb_dbus_dat), - .wbm_sel_i (wb_dbus_sel), - .wbm_we_i (wb_dbus_we ), - .wbm_cyc_i (wb_dbus_cyc[bbus_slave_nr]), - .wbm_stb_i (wb_dbus_stb[bbus_slave_nr]), - .wbm_cti_i (wb_dbus_cti), - .wbm_bte_i (wb_dbus_bte), - .wbm_sdt_o (wb_bbus_sdt), - .wbm_ack_o (wb_bbus_ack), - .wbm_err_o (wb_bbus_err), - .wbm_rty_o (wb_bbus_rty), - //Slave interface - .wbs_adr_o (wb_bbus_adr), - .wbs_dat_o (wb_bbus_dat), - .wbs_sel_o ( ), - .wbs_we_o (wb_bbus_we ), - .wbs_cyc_o (wb_bbus_cyc), - .wbs_stb_o (wb_bbus_stb), - .wbs_cti_o (wb_bbus_cti), - .wbs_bte_o (wb_bbus_bte), - .wbs_sdt_i ({wb_intgen_sdt, wb_uart_sdt}), - .wbs_ack_i ({wb_intgen_ack, wb_uart_ack}), - .wbs_err_i ({wb_intgen_err, wb_uart_err}), - .wbs_rty_i ({wb_intgen_rty, wb_uart_rty})); - - //////////////////////////////////////////////////////////////////////// - // - // JTAG TAP - // - //////////////////////////////////////////////////////////////////////// - - wire dbg_if_select; - wire dbg_if_tdo; - wire jtag_tap_tdo; - wire jtag_tap_shift_dr, jtag_tap_pause_dr, - jtag_tap_update_dr, jtag_tap_capture_dr; - - tap_top #(.IDCODE_VALUE(IDCODE_VALUE)) jtag_tap0 - ( - // Ports to pads - .tdo_pad_o (tdo_pad_o), - .tms_pad_i (tms_pad_i), - .tck_pad_i (dbg_tck), - .trst_pad_i (async_rst), - .tdi_pad_i (tdi_pad_i), - - .tdo_padoe_o (), - - .tdo_o (jtag_tap_tdo), - - .shift_dr_o (jtag_tap_shift_dr), - .pause_dr_o (jtag_tap_pause_dr), - .update_dr_o (jtag_tap_update_dr), - .capture_dr_o (jtag_tap_capture_dr), - - .extest_select_o (), - .sample_preload_select_o (), - .mbist_select_o (), - .debug_select_o (dbg_if_select), - - - .bs_chain_tdi_i (1'b0), - .mbist_tdi_i (1'b0), - .debug_tdi_i (dbg_if_tdo) - - ); - - //////////////////////////////////////////////////////////////////////// - // - // or1200 - // - //////////////////////////////////////////////////////////////////////// - - wire [19:0] or1200_pic_ints; - - wire [31:0] or1200_dbg_dat_i; - wire [31:0] or1200_dbg_adr_i; - wire or1200_dbg_we_i; - wire or1200_dbg_stb_i; - wire or1200_dbg_ack_o; - wire [31:0] or1200_dbg_dat_o; - - wire or1200_dbg_stall_i; - wire or1200_dbg_ewt_i; - wire [3:0] or1200_dbg_lss_o; - wire [1:0] or1200_dbg_is_o; - wire [10:0] or1200_dbg_wp_o; - wire or1200_dbg_bp_o; - wire or1200_dbg_rst; - - wire sig_tick; - wire or1200_rst = wb_rst | or1200_dbg_rst; - - or1200_top #(.boot_adr(32'hf0000000)) or1200_top0 - ( - // Instruction bus, clocks, reset - .iwb_clk_i (wb_clk), - .iwb_rst_i (wb_rst), - .iwb_ack_i (wb_or1200_i_ack), - .iwb_err_i (wb_or1200_i_err), - .iwb_rty_i (wb_or1200_i_rty), - .iwb_dat_i (wb_or1200_i_sdt), - - .iwb_cyc_o (wb_or1200_i_cyc), - .iwb_adr_o (wb_or1200_i_adr), - .iwb_stb_o (wb_or1200_i_stb), - .iwb_we_o (wb_or1200_i_we), - .iwb_sel_o (wb_or1200_i_sel), - .iwb_dat_o (wb_or1200_i_dat), - .iwb_cti_o (wb_or1200_i_cti), - .iwb_bte_o (wb_or1200_i_bte), - - // Data bus, clocks, reset - .dwb_clk_i (wb_clk), - .dwb_rst_i (wb_rst), - .dwb_ack_i (wb_or1200_d_ack), - .dwb_err_i (wb_or1200_d_err), - .dwb_rty_i (wb_or1200_d_rty), - .dwb_dat_i (wb_or1200_d_sdt), - - .dwb_cyc_o (wb_or1200_d_cyc), - .dwb_adr_o (wb_or1200_d_adr), - .dwb_stb_o (wb_or1200_d_stb), - .dwb_we_o (wb_or1200_d_we), - .dwb_sel_o (wb_or1200_d_sel), - .dwb_dat_o (wb_or1200_d_dat), - .dwb_cti_o (wb_or1200_d_cti), - .dwb_bte_o (wb_or1200_d_bte), - - // Debug interface ports - .dbg_stall_i (or1200_dbg_stall_i), - //.dbg_ewt_i (or1200_dbg_ewt_i), - .dbg_ewt_i (1'b0), - .dbg_lss_o (or1200_dbg_lss_o), - .dbg_is_o (or1200_dbg_is_o), - .dbg_wp_o (or1200_dbg_wp_o), - .dbg_bp_o (or1200_dbg_bp_o), - - .dbg_adr_i (or1200_dbg_adr_i), - .dbg_we_i (or1200_dbg_we_i ), - .dbg_stb_i (or1200_dbg_stb_i), - .dbg_dat_i (or1200_dbg_dat_i), - .dbg_dat_o (or1200_dbg_dat_o), - .dbg_ack_o (or1200_dbg_ack_o), - - .pm_clksd_o (), - .pm_dc_gate_o (), - .pm_ic_gate_o (), - .pm_dmmu_gate_o (), - .pm_immu_gate_o (), - .pm_tt_gate_o (), - .pm_cpu_gate_o (), - .pm_wakeup_o (), - .pm_lvolt_o (), - - // Core clocks, resets - .clk_i (wb_clk), - .rst_i (or1200_rst), - - .clmode_i (2'b00), - // Interrupts - .pic_ints_i (or1200_pic_ints), - .sig_tick(sig_tick), - /* - .mbist_so_o (), - .mbist_si_i (0), - .mbist_ctrl_i (0), - */ - - .pm_cpustall_i (1'b0) - - ); - - //////////////////////////////////////////////////////////////////////// - - - //////////////////////////////////////////////////////////////////////// - // - // OR1200 Debug Interface - // - //////////////////////////////////////////////////////////////////////// -/* - dbg_top dbg_if0 - ( - // OR1200 interface - .cpu0_clk_i (wb_clk), - .cpu0_rst_o (or1200_dbg_rst), - .cpu0_addr_o (or1200_dbg_adr_i), - .cpu0_data_o (or1200_dbg_dat_i), - .cpu0_stb_o (or1200_dbg_stb_i), - .cpu0_we_o (or1200_dbg_we_i), - .cpu0_data_i (or1200_dbg_dat_o), - .cpu0_ack_i (or1200_dbg_ack_o), - - - .cpu0_stall_o (or1200_dbg_stall_i), - .cpu0_bp_i (or1200_dbg_bp_o), - - // TAP interface - .tck_i (dbg_tck), - .tdi_i (jtag_tap_tdo), - .tdo_o (dbg_if_tdo), - .rst_i (wb_rst), - .shift_dr_i (jtag_tap_shift_dr), - .pause_dr_i (jtag_tap_pause_dr), - .update_dr_i (jtag_tap_update_dr), - .debug_select_i (dbg_if_select), - - // Wishbone debug master - .wb_clk_i (wb_clk), - .wb_dat_i (wb_dbg_sdt), - .wb_ack_i (wb_dbg_ack), - .wb_err_i (wb_dbg_err), - .wb_adr_o (wb_dbg_adr), - .wb_dat_o (wb_dbg_dat), - .wb_cyc_o (wb_dbg_cyc), - .wb_stb_o (wb_dbg_stb), - .wb_sel_o (wb_dbg_sel), - .wb_we_o (wb_dbg_we ), - .wb_cti_o (wb_dbg_cti), - .wb_cab_o (), - .wb_bte_o (wb_dbg_bte) - ); -*/ - adbg_top dbg_if0 - ( - // OR1200 interface - .cpu0_clk_i (wb_clk), - .cpu0_rst_o (or1200_dbg_rst), - .cpu0_addr_o (or1200_dbg_adr_i), - .cpu0_data_o (or1200_dbg_dat_i), - .cpu0_stb_o (or1200_dbg_stb_i), - .cpu0_we_o (or1200_dbg_we_i), - .cpu0_data_i (or1200_dbg_dat_o), - .cpu0_ack_i (or1200_dbg_ack_o), - .cpu0_stall_o (or1200_dbg_stall_i), - .cpu0_bp_i (or1200_dbg_bp_o), - - // TAP interface - .tck_i (dbg_tck), - .tdi_i (jtag_tap_tdo), - .tdo_o (dbg_if_tdo), - .rst_i (wb_rst), - .capture_dr_i (jtag_tap_capture_dr), - .shift_dr_i (jtag_tap_shift_dr), - .pause_dr_i (jtag_tap_pause_dr), - .update_dr_i (jtag_tap_update_dr), - .debug_select_i (dbg_if_select), - - // Wishbone debug master - .wb_clk_i (wb_clk), - .wb_dat_i (wb_dbg_sdt), - .wb_ack_i (wb_dbg_ack), - .wb_err_i (wb_dbg_err), - - .wb_adr_o (wb_dbg_adr), - .wb_dat_o (wb_dbg_dat), - .wb_cyc_o (wb_dbg_cyc), - .wb_stb_o (wb_dbg_stb), - .wb_sel_o (wb_dbg_sel), - .wb_we_o (wb_dbg_we ), - .wb_cti_o (wb_dbg_cti), - .wb_bte_o (wb_dbg_bte) - ); - - //////////////////////////////////////////////////////////////////////// - // - // ROM - // - //////////////////////////////////////////////////////////////////////// -`ifdef BOOTROM - rom - #(.addr_width(rom0_aw)) - rom0 - ( - .wb_clk (wb_clk), - .wb_rst (wb_rst), - .wb_adr_i (wb_ibus_adr[(rom0_aw+2)-1:2]), - .wb_cyc_i (wb_ibus_cyc[rom0_slave_nr]), - .wb_stb_i (wb_ibus_stb[rom0_slave_nr]), - .wb_cti_i (wb_ibus_cti), - .wb_bte_i (wb_ibus_bte), - .wb_dat_o (wb_rom0_sdt), - .wb_ack_o (wb_rom0_ack)); -`else // !`ifdef BOOTROM - assign wb_rom0_dat_o = 0; - assign wb_rom0_ack_o = 0; -`endif // !`ifdef BOOTROM - assign wb_rom0_err = 1'b0; - assign wb_rom0_rty = 1'b0; - - //////////////////////////////////////////////////////////////////////// - - //////////////////////////////////////////////////////////////////////// - // - // Generic main RAM - // - //////////////////////////////////////////////////////////////////////// - - ram_wb #(.aw(wb_aw), - .dw(wb_dw), - .mem_size_bytes(8192*1024), // 8MB - .mem_adr_width(23)) // log2(8192*1024) - ram_wb0 - ( - // Wishbone slave interface 0 - .wbm0_dat_i (wb_ibus_dat), - .wbm0_adr_i (wb_ibus_adr), - .wbm0_sel_i (wb_ibus_sel), - .wbm0_cti_i (wb_ibus_cti), - .wbm0_bte_i (wb_ibus_bte), - .wbm0_we_i (wb_ibus_we ), - .wbm0_cyc_i (wb_ibus_cyc[mc0_ibus_slave_nr]), - .wbm0_stb_i (wb_ibus_stb[mc0_ibus_slave_nr]), - .wbm0_dat_o (wb_mc0_ibus_sdt), - .wbm0_ack_o (wb_mc0_ibus_ack), - .wbm0_err_o (wb_mc0_ibus_err), - .wbm0_rty_o (wb_mc0_ibus_rty), - // Wishbone slave interface 1 - .wbm1_dat_i (wb_dbus_dat), - .wbm1_adr_i (wb_dbus_adr), - .wbm1_sel_i (wb_dbus_sel), - .wbm1_cti_i (wb_dbus_cti), - .wbm1_bte_i (wb_dbus_bte), - .wbm1_we_i (wb_dbus_we), - .wbm1_cyc_i (wb_dbus_cyc[mc0_dbus_slave_nr]), - .wbm1_stb_i (wb_dbus_stb[mc0_dbus_slave_nr]), - .wbm1_dat_o (wb_mc0_dbus_sdt), - .wbm1_ack_o (wb_mc0_dbus_ack), - .wbm1_err_o (wb_mc0_dbus_err), - .wbm1_rty_o (wb_mc0_dbus_rty), - // Wishbone slave interface 2 - .wbm2_dat_i (32'd0), - .wbm2_adr_i (32'd0), - .wbm2_sel_i (4'd0), - .wbm2_cti_i (3'd0), - .wbm2_bte_i (2'd0), - .wbm2_we_i (1'd0), - .wbm2_cyc_i (1'd0), - .wbm2_stb_i (1'd0), - .wbm2_dat_o (), - .wbm2_ack_o (), - .wbm2_err_o (), - .wbm2_rty_o (), - // Clock, reset - .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst)); - - //////////////////////////////////////////////////////////////////////// - // - // UART0 - // - //////////////////////////////////////////////////////////////////////// - - wire uart0_irq; - - assign wb_uart_err = 0; - assign wb_uart_rty = 0; - - uart_top uart16550_0 - ( - // Wishbone slave interface - .wb_clk_i (wb_clk), - .wb_rst_i (wb_rst), - .wb_adr_i (wb_bbus_adr[uart0_aw-1:0]), - .wb_dat_i (wb_bbus_dat), - .wb_we_i (wb_bbus_we), - .wb_stb_i (wb_bbus_stb[uart_slave_nr]), - .wb_cyc_i (wb_bbus_cyc[uart_slave_nr]), - .wb_sel_i (), - .wb_dat_o (wb_uart_sdt), - .wb_ack_o (wb_uart_ack), - - .int_o (uart0_irq), - .stx_pad_o (uart0_stx_pad_o), - .rts_pad_o (), - .dtr_pad_o (), - // .baud_o (), - // Inputs - .srx_pad_i (uart0_srx_pad_i), - .cts_pad_i (1'b0), - .dsr_pad_i (1'b0), - .ri_pad_i (1'b0), - .dcd_pad_i (1'b0)); - -`ifdef INTGEN - - wire intgen_irq; - - intgen intgen0 - ( - .clk_i (wb_clk), - .rst_i (wb_rst), - .wb_adr_i (wb_bbus_adr[intgen_addr_width-1:0]), - .wb_dat_i (wb_bbus_dat), - .wb_we_i (wb_bbus_we ), - .wb_cyc_i (wb_bbus_cyc[intgen_slave_nr]), - .wb_stb_i (wb_bbus_stb[intgen_slave_nr]), - .wb_ack_o (wb_intgen_ack), - .wb_dat_o (wb_intgen_sdt), - - .irq_o (intgen_irq) - ); - -`endif // `ifdef INTGEN - assign wb_intgen_err = 0; - assign wb_intgen_rty = 0; - - - //////////////////////////////////////////////////////////////////////// - // - // OR1200 Interrupt assignment - // - //////////////////////////////////////////////////////////////////////// - - assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200 - assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200 -`ifdef UART0 - assign or1200_pic_ints[2] = uart0_irq; -`else - assign or1200_pic_ints[2] = 0; -`endif - assign or1200_pic_ints[3] = 0; - assign or1200_pic_ints[4] = 0; - assign or1200_pic_ints[5] = 0; -`ifdef SPI0 - assign or1200_pic_ints[6] = spi0_irq; -`else - assign or1200_pic_ints[6] = 0; -`endif - assign or1200_pic_ints[7] = 0; - assign or1200_pic_ints[8] = 0; - assign or1200_pic_ints[9] = 0; - assign or1200_pic_ints[10] = 0; - assign or1200_pic_ints[11] = 0; - assign or1200_pic_ints[12] = 0; - assign or1200_pic_ints[13] = 0; - assign or1200_pic_ints[14] = 0; - assign or1200_pic_ints[15] = 0; - assign or1200_pic_ints[16] = 0; - assign or1200_pic_ints[17] = 0; - assign or1200_pic_ints[18] = 0; -`ifdef INTGEN - assign or1200_pic_ints[19] = intgen_irq; -`else - assign or1200_pic_ints[19] = 0; -`endif - -endmodule // top - -// Local Variables: -// verilog-library-directories:("." "../arbiter" "../uart16550" "../or1200" "../dbg_if" "../jtag_tap" "../rom" "../simple_spi" ) -// verilog-library-files:() -// verilog-library-extensions:(".v" ".h") -// End: -