diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 50cc18a6ec5e..d2526a2f6b16 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -943,6 +943,13 @@ properties: - const: qcom,qcs615 - const: qcom,sm6150 + - items: + - enum: + - qcom,talos-lyra-evk + - const: qcom,talos-lyra-evk-som + - const: qcom,qcs615 + - const: qcom,sm6150 + - items: - enum: - qcom,sa8155p-adp diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f33c4e2f09c..23179d54ec6f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -409,6 +409,14 @@ dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb talos-evk-lvds-auo,g133han01-dtbs := \ talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-lyra-evk.dtb +talos-lyra-evk-camx-dtbs := talos-lyra-evk.dtb talos-lyra-evk-camx.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-lyra-evk-camx.dtb +talos-lyra-evk-dlc0697-dtbs := talos-lyra-evk.dtb talos-lyra-evk-dlc0697.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-lyra-evk-dlc0697.dtb +talos-lyra-evk-raspberrypi-dsi-7inch-dtbs := talos-lyra-evk.dtb talos-lyra-evk-raspberrypi-dsi-7inch.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-lyra-evk-raspberrypi-dsi-7inch.dtb + x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/talos-camera-lyra-evk.dtsi b/arch/arm64/boot/dts/qcom/talos-camera-lyra-evk.dtsi new file mode 100644 index 000000000000..d8c8ed9c46a2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-camera-lyra-evk.dtsi @@ -0,0 +1,123 @@ +&tlmm { + cam-sensor-active-rst0 { + /* RESET */ + mux { + pins = "gpio40"; + }; + + config { + pins = "gpio40"; + }; + }; + + cam-sensor-active-rst1 { + /* RESET */ + mux { + pins = "gpio54"; + }; + + config { + pins = "gpio54"; + }; + }; + + cam-sensor-active-rst2 { + /* RESET */ + mux { + pins = "gpio42"; + }; + + config { + pins = "gpio42"; + }; + }; + + cam-sensor-suspend-rst0 { + /* RESET */ + mux { + pins = "gpio40"; + }; + + config { + pins = "gpio40"; + }; + }; + + cam-sensor-suspend-rst1 { + /* RESET */ + mux { + pins = "gpio54"; + }; + + config { + pins = "gpio54"; + }; + }; + + cam-sensor-suspend-rst2 { + /* RESET */ + mux { + pins = "gpio42"; + }; + + config { + pins = "gpio42"; + }; + }; + + cam_sensor_mclk0_active: cam-sensor-mclk0-active { + /* MCLK */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam-sensor-mclk1-active { + /* MCLK */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam-sensor-mclk0-suspend { + /* MCLK */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam-sensor-mclk1-suspend { + /* MCLK */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-camera-sensor-lyra-evk.dtsi b/arch/arm64/boot/dts/qcom/talos-camera-sensor-lyra-evk.dtsi new file mode 100644 index 000000000000..40927ccb1bad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-camera-sensor-lyra-evk.dtsi @@ -0,0 +1,682 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +&cam_cci { + /*ACTUATOR0: OV13B10*/ + actuator_cam4: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM0: OV13B10*/ + eeprom_cam4: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&expander1 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK4", + "CAMIF_RESET4", + "CAM_CUSTOM4"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*CAM0: OV13B10*/ + tl_slot4: qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam4>; + actuator-src = <&actuator_cam4>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&expander1 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK4", + "CAMIF_RESET4", + "CAM_CUSTOM4"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*ACTUATOR1: OV13B10*/ + actuator_cam5: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM1: OV13B10*/ + eeprom_cam5: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 29 0>, + <&tlmm 54 0>, + <&expander1 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK5", + "CAMIF_RESET5", + "CAM_CUSTOM5"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*CAM1: OV13B10*/ + tl_slot5: qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam5>; + actuator-src = <&actuator_cam5>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 29 0>, + <&tlmm 54 0>, + <&expander1 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK5", + "CAMIF_RESET5", + "CAM_CUSTOM5"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*ACTUATOR2: OV13B10*/ + actuator_cam6: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM2: OV13B10*/ + eeprom_cam6: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 30 0>, + <&tlmm 42 0>, + <&expander1 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK6", + "CAMIF_RESET6", + "CAM_CUSTOM6"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*CAM2: OV13B10*/ + tl_slot6: qcom,cam-sensor6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam6>; + actuator-src = <&actuator_cam6>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 30 0>, + <&tlmm 42 0>, + <&expander1 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK6", + "CAMIF_RESET6", + "CAM_CUSTOM6"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*ACTUATOR3: IMX858*/ + actuator_cam7: qcom,actuator7 { + cell-index = <7>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM3: IMX858*/ + eeprom_cam7: qcom,eeprom7 { + cell-index = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&expander1 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK7", + "CAMIF_RESET7", + "CAM_CUSTOM7"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*CAM3: IMX858*/ + tl_slot7: qcom,cam-sensor7 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam7>; + actuator-src = <&actuator_cam7>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>, + <&expander1 0 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK7", + "CAMIF_RESET7", + "CAM_CUSTOM7"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*ACTUATOR4: IMX858*/ + actuator_cam8: qcom,actuator8 { + cell-index = <8>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM4: IMX858*/ + eeprom_cam8: qcom,eeprom8 { + cell-index = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 29 0>, + <&tlmm 54 0>, + <&expander1 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK8", + "CAMIF_RESET8", + "CAM_CUSTOM8"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*CAM4: IMX858*/ + tl_slot8: qcom,cam-sensor8 { + cell-index = <8>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam8>; + actuator-src = <&actuator_cam8>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 29 0>, + <&tlmm 54 0>, + <&expander1 1 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK8", + "CAMIF_RESET8", + "CAM_CUSTOM8"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*ACTUATOR5: IMX858*/ + actuator_cam9: qcom,actuator9 { + cell-index = <9>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + status = "okay"; + }; + + /*EEPROM5: IMX858*/ + eeprom_cam9: qcom,eeprom9 { + cell-index = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 30 0>, + <&tlmm 42 0>, + <&expander1 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK9", + "CAMIF_RESET9", + "CAM_CUSTOM9"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*CAM5: IMX858*/ + tl_slot9: qcom,cam-sensor9 { + cell-index = <9>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_cam9>; + actuator-src = <&actuator_cam9>; + cam_vio-supply = <&vreg_campin>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <4000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 30 0>, + <&tlmm 42 0>, + <&expander1 2 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAM_MCLK9", + "CAMIF_RESET9", + "CAM_CUSTOM9"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <19200000>; + status = "okay"; + }; + + /*CAM6: IMX577*/ + tl_slot10: qcom,cam-sensor10 { + cell-index = <10>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 28 0>, + <&tlmm 40 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK10", + "CAMIF_RESET10"; + cci-master = <0>; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*CAM7: IMX577*/ + tl_slot11: qcom,cam-sensor11 { + cell-index = <11>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 29 0>, + <&tlmm 54 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK11", + "CAMIF_RESET11"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; + + /*CAM8: IMX577*/ + tl_slot12: qcom,cam-sensor12 { + cell-index = <12>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&vreg_s4a>; + regulator-names = "cam_vio"; + power-domains = <&camcc TITAN_TOP_GDSC>; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 30 0>, + <&tlmm 42 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAM_MCLK12", + "CAMIF_RESET12"; + cci-master = <1>; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "okay"; + }; +}; + +&soc { + vreg_campin: regulator-dbb1 { + compatible = "regulator-fixed"; + regulator-name = "vreg_campin"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-camx.dtso b/arch/arm64/boot/dts/qcom/talos-lyra-evk-camx.dtso new file mode 100644 index 000000000000..98cd84ee831e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-camx.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "talos-camera.dtsi" +#include "talos-camera-lyra-evk.dtsi" +#include "talos-camera-sensor-lyra-evk.dtsi" diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-dlc0697.dtso b/arch/arm64/boot/dts/qcom/talos-lyra-evk-dlc0697.dtso new file mode 100644 index 000000000000..f278e53ca2d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-dlc0697.dtso @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include + +<9611uxd { + status = "disabled"; + /delete-node/ ports; +}; + +&hdmi_connector { + status = "disabled"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "dlc,dlc0697"; + reg = <0>; + + reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_s4a>; + bias-supply = <&vreg_disp_3p3>; + + pinctrl-0 = <&panel_rst_n &panel_te_pin &backlight_en>; + pinctrl-1 = <&panel_rst_n_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&tlmm { + backlight_en: backlight-en-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n: panel-rst-n-state { + pins = "gpio118"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins = "gpio118"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins = "gpio98"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-raspberrypi-dsi-7inch.dtso b/arch/arm64/boot/dts/qcom/talos-lyra-evk-raspberrypi-dsi-7inch.dtso new file mode 100644 index 000000000000..6c6e145b8ca2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-raspberrypi-dsi-7inch.dtso @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include + +&{/} { + display_bl: backlight { + compatible = "pwm-backlight"; + power-supply = <&vreg_disp_3p3>; + pwms = <®_backlight 0 255 0>; + }; +}; + +<9611uxd { + status = "disabled"; +}; + +&hdmi_connector { + status = "disabled"; +}; + +/* + * Override vreg_disp_3p3: switch GPIO from tlmm 3 (lt9611) to expander0 pin 1 + * (RPI panel/touch 3.3V supply). + */ +&vreg_disp_3p3 { + regulator-name = "rpi-dsi-touch"; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + regulator-boot-on; + regulator-always-on; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + reg_backlight: reg_backlight@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + vcc-supply = <&vreg_disp_3p3>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raspberrypi,dsi-7inch"; + reg = <0>; + + reset-gpios = <®_backlight 0 GPIO_ACTIVE_LOW>; + power-supply = <&vreg_disp_3p3>; + iovcc-supply = <&vreg_s4a>; + backlight = <&display_bl>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1>; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi new file mode 100644 index 000000000000..cc7a43f31865 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include +#include "talos.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s3a: smps3 { + regulator-name = "vreg_s3a"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a: smps6 { + regulator-name = "vreg_s6a"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1404000>; + regulator-initial-mode = ; + }; + + vreg_l1a: ldo1 { + regulator-name = "vreg_l1a"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10a: ldo10 { + regulator-name = "vreg_l10a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17a: ldo17 { + regulator-name = "vreg_l17a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; +}; + +ðernet { + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0x7>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&pcie { + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + iommu-map = <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>, + <0x208 &apps_smmu 0x402 0x1>, + <0x210 &apps_smmu 0x403 0x1>, + <0x218 &apps_smmu 0x404 0x1>, + <0x300 &apps_smmu 0x405 0x1>, + <0x400 &apps_smmu 0x406 0x1>, + <0x500 &apps_smmu 0x407 0x1>, + <0x501 &apps_smmu 0x408 0x1>; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&pcie_port0 { + tc9563: pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + #gpio-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c5 0x77>; + + resx-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_state>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + + ep-pwr-en-gpio = <&tc9563 2 GPIO_ACTIVE_HIGH>; + ep-reset-gpio = <&tc9563 5 GPIO_ACTIVE_HIGH>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + + ep-pwr-en-gpio = <&tc9563 4 GPIO_ACTIVE_HIGH>; + ep-reset-gpio = <&tc9563 3 GPIO_ACTIVE_HIGH>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs615/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs615/cdsp.mbn"; + + status = "okay"; +}; + +&rpmhcc { + clocks = <&xo_board_clk>; +}; + +&tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio105"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tc9563_resx_state: tc9563-resx-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts new file mode 100644 index 000000000000..b94e7fd81fdc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include "talos-lyra-evk-som.dtsi" + +/ { + model = "Qualcomm QCS615 Talos lyra EVK"; + compatible = "qcom,talos-lyra-evk", "qcom,talos-lyra-evk-som", "qcom,qcs615", + "qcom,sm6150"; + chassis-type = "embedded"; + + aliases { + i2c2 = &i2c2; + }; + + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + hpd-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + + hdmi_connector: hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + vreg_disp_3p3: regulator-disp-3p3 { + compatible = "regulator-fixed"; + regulator-name = "vreg_disp_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_bias_en>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,talos-lyra-sndcard"; + model = "qcs615-snd-card"; + + pinctrl-names = "default"; + pinctrl-0 = <&lpi_spkr_i2s_mclk_a>, <&lpi_i2s1_clk>, <&lpi_i2s1_data>, <&lpi_i2s1_ws>; + + sec-mi2s-playback-dai-link { + link-name = "Secondary MI2S Playback"; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>; + }; + + codec { + sound-dai = <&max98091>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + codec { + sound-dai = <&max98091>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + lt9611uxd: lt9611uxd@41 { + compatible = "lontium,lt9611uxd"; + reg = <0x41>; + interrupts-extended = <&tlmm 60 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_disp_3p3>; + vdd-supply = <&vreg_s4a>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + expander0: gpio@20 { + compatible = "kinetic,kts1622", "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@21 { + compatible = "kinetic,kts1622", "nxp,pca9555"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + + emac0_phy_en_hog: emac0-phy-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "emac0-phy-en"; + }; + }; + + expander2: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&i2c5 { + status = "okay"; + max98091: max98091@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + #sound-dai-cells = <0>; + clock-names = "mclk"; + clocks = <&q6prmcc LPASS_CLK_ID_SPEAKER_I2S_OSR LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + interrupt-parent = <&tlmm>; + interrupts = <119 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&int_codec>; + }; +}; + +&tlmm { + int_codec: gpio-irq-state { + pins = "gpio119"; + function = "gpio"; + }; +}; + +&lpass_tlmm { + lpi_spkr_i2s_mclk_a: lpi-spkr-i2s-mclk-a-state { + pins = "gpio19"; + function = "spkr_i2s_mclk_a"; + drive-strength = <16>; + bias-disable; + output-high; + }; + lpi_i2s1_clk: lpi-i2s1-clk-state { + pins = "gpio8"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + lpi_i2s1_clk_sleep: lpi-i2s1-clk-sleep-state { + pins = "gpio8"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + lpi_i2s1_data: lpi-i2s1-data-state { + pins = "gpio10", "gpio11"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + lpi_i2s1_data_sleep: lpi-i2s1-data-sleep-state { + pins = "gpio10", "gpio11"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + lpi_i2s1_ws: lpi-i2s1-ws-state { + pins = "gpio9"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + lpi_i2s1_ws_sleep: lpi-i2s1-ws-sleep-state { + pins = "gpio9"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; +}; + +&soc { + lpass_tlmm: pinctrl@62B40000 { + compatible = "qcom,qcs615-lpass-lpi-pinctrl"; + reg = <0x0 0x62B40000 0x0 0x20000>, + <0x0 0x62B00000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 32>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; + + status = "okay"; +}; + + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l11a>; + + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&spi6 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&tlmm { + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lcd_bias_en: lcd-bias-en-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index fb1bbc51bb8a..344c16b385e0 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -50,10 +50,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -75,10 +75,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_100: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -100,10 +100,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_200: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -125,10 +125,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_300: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -150,10 +150,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_400: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -175,10 +175,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_500: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -201,10 +201,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_600: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -226,10 +226,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_700: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -635,8 +635,8 @@ cluster_pd: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_0 - &cluster_sleep_1 - &cluster_sleep_2>; + &cluster_sleep_1 + &cluster_sleep_2>; }; }; @@ -686,6 +686,40 @@ #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", + "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>; @@ -693,8 +727,8 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; + "bi_tcxo_ao", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; @@ -721,14 +755,14 @@ sdhc_1: mmc@7c4000 { compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x007c4000 0x0 0x1000>, - <0x0 0x007c5000 0x0 0x1000>, - <0x0 0x007c8000 0x0 0x8000>; + <0x0 0x007c5000 0x0 0x1000>, + <0x0 0x007c8000 0x0 0x8000>; reg-names = "hc", - "cqhci", - "ice"; + "cqhci", + "ice"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -737,9 +771,9 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", - "core", - "xo", - "ice"; + "core", + "xo", + "ice"; resets = <&gcc GCC_SDCC1_BCR>; @@ -751,7 +785,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", - "cpu-sdhc"; + "cpu-sdhc"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; @@ -790,13 +824,13 @@ reg = <0x0 0x800000 0x0 0x60000>; #dma-cells = <3>; interrupts = , - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xd6 0x0>; @@ -810,7 +844,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", - "s-ahb"; + "s-ahb"; iommus = <&apps_smmu 0xc3 0x0>; #address-cells = <2>; #size-cells = <2>; @@ -829,7 +863,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -852,14 +886,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; + <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -880,14 +914,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; + <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -904,13 +938,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; + <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -923,14 +957,14 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, - <&qup_uart2_tx>, <&qup_uart2_rx>; + <&qup_uart2_tx>, <&qup_uart2_rx>; pinctrl-names = "default"; interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -953,14 +987,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; + <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; }; @@ -970,13 +1004,13 @@ reg = <0x0 0xa00000 0x0 0x60000>; #dma-cells = <3>; interrupts = , - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0x376 0x0>; @@ -990,7 +1024,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", - "s-ahb"; + "s-ahb"; iommus = <&apps_smmu 0x363 0x0>; #address-cells = <2>; #size-cells = <2>; @@ -1013,14 +1047,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; + <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1039,13 +1073,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; + <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1055,7 +1089,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, - <&qup_uart4_tx>, <&qup_uart4_rx>; + <&qup_uart4_tx>, <&qup_uart4_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1063,7 +1097,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1086,14 +1120,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; + <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1114,14 +1148,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; + <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1140,13 +1174,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; + <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1156,7 +1190,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, - <&qup_uart6_tx>, <&qup_uart6_rx>; + <&qup_uart6_tx>, <&qup_uart6_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1164,7 +1198,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1187,14 +1221,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; + <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1213,13 +1247,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; + <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1229,7 +1263,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, - <&qup_uart7_tx>, <&qup_uart7_rx>; + <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1237,7 +1271,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1280,17 +1314,17 @@ device_type = "pci"; compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; reg = <0x0 0x01c08000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf1d>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x1000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c0b000 0x0 0x1000>; + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; + "dbi", + "elbi", + "atu", + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, @@ -1303,14 +1337,14 @@ num-lanes = <1>; interrupts = , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1335,11 +1369,11 @@ <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -1350,7 +1384,7 @@ interconnect-names = "pcie-mem", "cpu-pcie"; iommu-map = <0x0 &apps_smmu 0x400 0x1>, - <0x100 &apps_smmu 0x401 0x1>; + <0x100 &apps_smmu 0x401 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1404,10 +1438,10 @@ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", - "cfg_ahb", - "ref", - "refgen", - "pipe"; + "cfg_ahb", + "ref", + "refgen", + "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1426,9 +1460,9 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>, - <0x0 0x01d90000 0x0 0x8000>; + <0x0 0x01d90000 0x0 0x8000>; reg-names = "std", - "ice"; + "ice"; interrupts = ; @@ -1441,13 +1475,13 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; clock-names = "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "ice_core_clk"; + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -1458,7 +1492,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "ufs-ddr", - "cpu-ufs"; + "cpu-ufs"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -1522,8 +1556,8 @@ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux", - "qref"; + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -1573,11 +1607,11 @@ tlmm: pinctrl@3100000 { compatible = "qcom,qcs615-tlmm"; reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03d00000 0x0 0x300000>; + <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03d00000 0x0 0x300000>; reg-names = "east", - "west", - "south"; + "west", + "south"; interrupts = ; gpio-ranges = <&tlmm 0 0 124>; gpio-controller; @@ -1952,11 +1986,11 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-612.0", "qcom,adreno"; reg = <0x0 0x05000000 0x0 0x40000>, - <0x0 0x0509e000 0x0 0x1000>, - <0x0 0x05061000 0x0 0x800>; + <0x0 0x0509e000 0x0 0x1000>, + <0x0 0x05061000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; + "cx_mem", + "cx_dbgc"; clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; clock-names = "core"; @@ -2027,18 +2061,18 @@ <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", - "cxo", - "axi", - "memnoc", - "smmu_vote"; + "cxo", + "axi", + "memnoc", + "smmu_vote"; power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; power-domain-names = "cx", - "gx"; + "gx"; interrupts = , - ; + ; interrupt-names = "oob", "gmu"; @@ -2069,25 +2103,25 @@ adreno_smmu: iommu@50a0000 { compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; + "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x050a0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + ; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "mem", - "hlos", - "iface"; + "hlos", + "iface"; power-domains = <&gpucc CX_GDSC>; dma-coherent; }; @@ -2095,9 +2129,9 @@ stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, - <0x0 0x16280000 0x0 0x180000>; + <0x0 0x16280000 0x0 0x180000>; reg-names = "stm-base", - "stm-stimulus-base"; + "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3749,10 +3783,10 @@ reg = <0x0 0x08300000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", @@ -3910,7 +3944,7 @@ reg-names = "hc"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -3918,8 +3952,8 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", - "core", - "xo"; + "core", + "xo"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; @@ -3930,7 +3964,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", - "cpu-sdhc"; + "cpu-sdhc"; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; @@ -3960,7 +3994,7 @@ qspi: spi@88df000 { compatible = "qcom,qcs615-qspi", - "qcom,qspi-v1"; + "qcom,qspi-v1"; reg = <0x0 0x088df000 0x0 0x1000>; interrupts = ; @@ -3968,14 +4002,14 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", - "core"; + "core"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qspi-config", - "qspi-memory"; + "qspi-memory"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qspi_opp_table>; @@ -4001,9 +4035,9 @@ llcc: system-cache-controller@9200000 { compatible = "qcom,qcs615-llcc"; reg = <0x0 0x09200000 0x0 0x50000>, - <0x0 0x09600000 0x0 0x50000>; + <0x0 0x09600000 0x0 0x50000>; reg-names = "llcc0_base", - "llcc_broadcast_base"; + "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { @@ -4024,17 +4058,17 @@ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; clock-names = "core", - "iface", - "bus", - "vcodec0_core", - "vcodec0_bus"; + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, <&rpmhpd RPMHPD_CX>; power-domain-names = "venus", - "vcodec0", - "cx"; + "vcodec0", + "cx"; operating-points-v2 = <&venus_opp_table>; @@ -4043,7 +4077,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "video-mem", - "cpu-cfg"; + "cpu-cfg"; iommus = <&apps_smmu 0xe60 0x20>; @@ -4108,8 +4142,8 @@ <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CCI_CLK>; clock-names = "camnoc_axi", - "cpas_ahb", - "cci"; + "cpas_ahb", + "cci"; pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; pinctrl-names = "default"; @@ -4137,45 +4171,45 @@ compatible = "qcom,sm6150-camss"; reg = <0x0 0x0acb3000 0x0 0x1000>, - <0x0 0x0acba000 0x0 0x1000>, - <0x0 0x0acc8000 0x0 0x1000>, - <0x0 0x0ac65000 0x0 0x1000>, - <0x0 0x0ac66000 0x0 0x1000>, - <0x0 0x0ac67000 0x0 0x1000>, - <0x0 0x0acaf000 0x0 0x4000>, - <0x0 0x0acb6000 0x0 0x4000>, - <0x0 0x0acc4000 0x0 0x4000>, - <0x0 0x0ac6f000 0x0 0x3000>, - <0x0 0x0ac42000 0x0 0x5000>, - <0x0 0x0ac48000 0x0 0x1000>, - <0x0 0x0ac40000 0x0 0x1000>, - <0x0 0x0ac18000 0x0 0x3000>, - <0x0 0x0ac00000 0x0 0x6000>, - <0x0 0x0ac10000 0x0 0x8000>, - <0x0 0x0ac87000 0x0 0x3000>, - <0x0 0x0ac52000 0x0 0x4000>, - <0x0 0x0ac4e000 0x0 0x4000>, - <0x0 0x0ac6b000 0x0 0x0a00>; + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac6f000 0x0 0x3000>, + <0x0 0x0ac42000 0x0 0x5000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac87000 0x0 0x3000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0x0a00>; reg-names = "csid0", - "csid1", - "csid_lite", - "csiphy0", - "csiphy1", - "csiphy2", - "vfe0", - "vfe1", - "vfe_lite", - "bps", - "camnoc", - "cpas_cdm", - "cpas_top", - "icp_csr", - "icp_qgic", - "icp_sierra", - "ipe0", - "jpeg_dma", - "jpeg_enc", - "lrme"; + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "bps", + "camnoc", + "cpas_cdm", + "cpas_top", + "icp_csr", + "icp_qgic", + "icp_sierra", + "ipe0", + "jpeg_dma", + "jpeg_enc", + "lrme"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, @@ -4211,38 +4245,38 @@ <&camcc CAM_CC_JPEG_CLK>, <&camcc CAM_CC_LRME_CLK>; clock-names = "gcc_ahb", - "gcc_axi_hf", - "camnoc_axi", - "cpas_ahb", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "soc_ahb", - "vfe0", - "vfe0_axi", - "vfe0_cphy_rx", - "vfe0_csid", - "vfe1", - "vfe1_axi", - "vfe1_cphy_rx", - "vfe1_csid", - "vfe_lite", - "vfe_lite_cphy_rx", - "vfe_lite_csid", - "bps", - "bps_ahb", - "bps_axi", - "bps_areg", - "icp", - "ipe0", - "ipe0_ahb", - "ipe0_areg", - "ipe0_axi", - "jpeg", - "lrme"; + "gcc_axi_hf", + "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_axi", + "bps_areg", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, @@ -4253,25 +4287,25 @@ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ahb", - "hf_0", - "hf_1", - "sf_mnoc"; + "hf_0", + "hf_1", + "sf_mnoc"; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "csid0", "csid1", "csid_lite", @@ -4308,10 +4342,10 @@ <&camcc BPS_GDSC>, <&camcc IPE_0_GDSC>; power-domain-names = "ife0", - "ife1", - "top", - "bps", - "ipe"; + "ife1", + "top", + "bps", + "ipe"; status = "disabled"; @@ -4354,7 +4388,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", - "cpu-cfg"; + "cpu-cfg"; power-domains = <&dispcc MDSS_CORE_GDSC>; @@ -4377,18 +4411,18 @@ mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm6150-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x2008>; reg-names = "mdp", - "vbif"; + "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", - "bus", - "core", - "vsync"; + "bus", + "core", + "vsync"; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd RPMHPD_CX>; @@ -4440,10 +4474,10 @@ compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; reg = <0x0 0x0ae90000 0x0 0x200>, - <0x0 0x0ae90200 0x0 0x200>, - <0x0 0x0ae90400 0x0 0x600>, - <0x0 0x0ae90a00 0x0 0x600>, - <0x0 0x0ae91000 0x0 0x600>; + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4455,11 +4489,11 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel"; + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, @@ -4533,11 +4567,11 @@ <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; + "byte_intf", + "pixel", + "core", + "iface", + "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; @@ -4587,11 +4621,11 @@ mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,sm6150-dsi-phy-14nm"; reg = <0x0 0x0ae94400 0x0 0x100>, - <0x0 0x0ae94500 0x0 0x300>, - <0x0 0x0ae94800 0x0 0x124>; + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; + "dsi_phy_lane", + "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; @@ -4599,7 +4633,7 @@ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", - "ref"; + "ref"; status = "disabled"; }; @@ -4625,7 +4659,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, - <0x0 0x17c000f0 0x0 0x64>; + <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; interrupt-parent = <&intc>; #interrupt-cells = <2>; @@ -4668,84 +4702,84 @@ dma-coherent; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x100000>, - <0x0 0x0e700000 0x0 0xa0000>, - <0x0 0x0c40a000 0x0 0x26000>; + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", - "chnls", - "obsrvr", - "intr", - "cnfg"; + "chnls", + "obsrvr", + "intr", + "cnfg"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; @@ -4759,7 +4793,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; #address-cells = <0>; #interrupt-cells = <4>; @@ -4780,7 +4814,7 @@ apss_shared: mailbox@17c00000 { compatible = "qcom,qcs615-apss-shared", - "qcom,sdm845-apss-shared"; + "qcom,sdm845-apss-shared"; reg = <0x0 0x17c00000 0x0 0x1000>; #mbox-cells = <1>; }; @@ -4801,10 +4835,10 @@ frame@17c21000 { reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; + <0x17c22000 0x1000>; frame-number = <0>; interrupts = , - ; + ; }; frame@17c23000 { @@ -4853,15 +4887,15 @@ apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", - "drv-1", - "drv-2"; + "drv-1", + "drv-2"; interrupts = , - , - ; + , + ; qcom,drv-id = <2>; qcom,tcs-offset = <0xd00>; @@ -4968,7 +5002,7 @@ clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "cfg_ahb", - "ref"; + "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; @@ -4986,9 +5020,9 @@ <&gcc GCC_AHB2PHY_WEST_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", - "ref", - "cfg_ahb", - "pipe"; + "ref", + "cfg_ahb", + "pipe"; resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; @@ -5013,14 +5047,14 @@ <&gcc GCC_AHB2PHY_WEST_CLK>, <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; clock-names = "aux", - "ref", - "cfg_ahb", - "pipe"; + "ref", + "cfg_ahb", + "pipe"; resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, <&gcc GCC_USB3_DP_PHY_SEC_BCR>; reset-names = "phy_phy", - "dp_phy"; + "dp_phy"; #clock-cells = <1>; #phy-cells = <1>; @@ -5041,22 +5075,22 @@ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>; clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>, - <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", @@ -5099,21 +5133,21 @@ <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB2_PRIM_CLKREF_CLK>; clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 11 IRQ_TYPE_EDGE_BOTH>, - <&pdc 10 IRQ_TYPE_EDGE_BOTH>; + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", @@ -5147,9 +5181,9 @@ tsens0: thermal-sensor@c263000 { compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c263000 0x0 0x1000>, - <0x0 0x0c222000 0x0 0x1000>; + <0x0 0x0c222000 0x0 0x1000>; interrupts = , - ; + ; interrupt-names = "uplow", "critical"; #qcom,sensors = <16>; #thermal-sensor-cells = <1>; @@ -5160,10 +5194,10 @@ reg = <0x0 0x62400000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", @@ -5285,9 +5319,9 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + , + , + ; }; thermal-zones { diff --git a/drivers/regulator/rpi-panel-v2-regulator.c b/drivers/regulator/rpi-panel-v2-regulator.c index 30b78aa75ee3..4e84f05f6811 100644 --- a/drivers/regulator/rpi-panel-v2-regulator.c +++ b/drivers/regulator/rpi-panel-v2-regulator.c @@ -11,6 +11,7 @@ #include #include #include +#include /* I2C registers of the microcontroller. */ #define REG_ID 0x01 @@ -66,10 +67,27 @@ static int rpi_panel_v2_i2c_probe(struct i2c_client *i2c) .parent = &i2c->dev, .reg_set_base = REG_POWERON, }; + struct regulator *vcc; struct regmap *regmap; struct pwm_chip *pc; int ret; + vcc = devm_regulator_get_optional(&i2c->dev, "vcc"); + if (IS_ERR(vcc)) { + ret = PTR_ERR(vcc); + if (ret == -EPROBE_DEFER) + return ret; + /* vcc-supply is optional, proceed without it */ + vcc = NULL; + } + + if (vcc) { + ret = regulator_enable(vcc); + if (ret) + return dev_err_probe(&i2c->dev, ret, + "Failed to enable vcc supply\n"); + } + pc = devm_pwmchip_alloc(&i2c->dev, 1, 0); if (IS_ERR(pc)) return PTR_ERR(pc);