From c30d92f0f19302c8bcf4ab940be605f28860b085 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Tue, 8 Sep 2026 01:53:19 +0530 Subject: [PATCH] FROMLIST: net: stmmac: qcom-ethqos: set initial RGMII link clock to lowest speed On probe the RGMII link clock is initialised at SPEED_1000, which translates to a 250 MHz source clock even when no PHY link is present, drawing unnecessary power. Initialise at SPEED_10 instead; fix_mac_speed updates the rate once a link is established. Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-7-bbe3389d0652@oss.qualcomm.com/ Reviewed-by: Maxime Chevallier Signed-off-by: Mohd Ayaan Anwar --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index ac7d6d3e205a..89912b1b8c35 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -759,7 +759,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) "Failed to get serdes phy\n"); ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, - SPEED_1000); + SPEED_10); qcom_ethqos_set_sgmii_loopback(ethqos, true); ethqos_set_func_clk_en(ethqos);