Enable ICE for UFS on Hamoa IoT EVK (#848)

Enable ICE for UFS on Hamoa IoT EVK

Author: sgaud-quic

Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml

@@ -23,6 +23,7 @@ properties:
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
           - qcom,sm8750-inline-crypto-engine
+          - qcom,x1e80100-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:
@@ -55,12 +56,12 @@ additionalProperties: false
 
 allOf:
   - if:
-    properties:
-      compatible:
-        contains:
-          enum:
-            - qcom,eliza-inline-crypto-engine
-            - qcom,milos-inline-crypto-engine
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-inline-crypto-engine
+              - qcom,milos-inline-crypto-engine
 
     then:
       required:

arch/arm64/boot/dts/qcom/hamoa.dtsi

@@ -3943,6 +3943,8 @@
 			phys = <&ufs_mem_phy>;
 			phy-names = "ufsphy";
 
+			qcom,ice = <&ice>;
+
 			#reset-cells = <1>;
 
 			status = "disabled";
@@ -3988,6 +3990,17 @@
 			};
 		};
 
+		ice: crypto@1d88000 {
+			compatible = "qcom,x1e80100-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0 0x01f40000 0 0x20000>;