From 38ec53589e27b84449702f4c35b383b9c73e223a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Wed, 4 Dec 2013 14:49:01 +0100
Subject: [PATCH 01/20] Add information on status of the EFLAGS register.

---
 docs/x86/optable.xml | 253 +++++++++++++++++++++++++++++++++++++++++++
 libudis86/decode.h   |   1 +
 libudis86/extern.h   |   2 +
 libudis86/types.h    |  29 +++++
 libudis86/udis86.c   |  15 +++
 scripts/ud_itab.py   |  13 ++-
 scripts/ud_opcode.py |  20 +++-
 7 files changed, 330 insertions(+), 3 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 1984088..66e7fc7 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -103,6 +103,7 @@
 
     <instruction>
         <mnemonic>aaa</mnemonic>
+        <eflags>UUUMUM_____</eflags>
         <def>
             <opc>37 /m=!64</opc>
         </def>
@@ -110,6 +111,7 @@
 
     <instruction>
         <mnemonic>aad</mnemonic>
+        <eflags>UMMUMU_____</eflags>
         <def>
             <opc>d5 /m=!64</opc>
             <opr>Ib</opr>
@@ -118,6 +120,7 @@
 
     <instruction>
         <mnemonic>aam</mnemonic>
+        <eflags>UMMUMU_____</eflags>
         <def>
             <opc>d4 /m=!64</opc>
             <opr>Ib</opr>
@@ -126,6 +129,7 @@
 
     <instruction>
         <mnemonic>aas</mnemonic>
+        <eflags>UUUMUM_____</eflags>
         <def>
             <opc>3f /m=!64</opc>
         </def>
@@ -133,6 +137,7 @@
 
     <instruction>
         <mnemonic>adc</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>10</opc>
@@ -187,6 +192,7 @@
 
     <instruction>
         <mnemonic>add</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>00</opc>
@@ -362,6 +368,7 @@
 
     <instruction>
         <mnemonic>and</mnemonic>
+        <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>20</opc>
@@ -456,6 +463,7 @@
 
     <instruction>
         <mnemonic>arpl</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso</pfx>
             <opc>63 /m=!64</opc>
@@ -474,6 +482,7 @@
 
     <instruction>
         <mnemonic>call</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>ff /reg=2 /m=!64</opc>
@@ -505,6 +514,7 @@
 
     <instruction>
         <mnemonic>cbw</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>98 /o=16</opc>
@@ -529,6 +539,7 @@
 
     <instruction>
         <mnemonic>clc</mnemonic>
+        <eflags>_____R_____</eflags>
         <def>
             <opc>f8</opc>
         </def>
@@ -536,6 +547,7 @@
 
     <instruction>
         <mnemonic>cld</mnemonic>
+        <eflags>________R__</eflags>
         <def>
             <opc>fc</opc>
         </def>
@@ -560,6 +572,7 @@
 
     <instruction>
         <mnemonic>cli</mnemonic>
+        <eflags>_______R___</eflags>
         <def>
             <opc>fa</opc>
         </def>
@@ -567,6 +580,7 @@
 
     <instruction>
         <mnemonic>clts</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 06</opc>
         </def>
@@ -574,6 +588,7 @@
 
     <instruction>
         <mnemonic>cmc</mnemonic>
+        <eflags>_____M_____</eflags>
         <def>
             <opc>f5</opc>
         </def>
@@ -581,6 +596,7 @@
 
     <instruction>
         <mnemonic>cmovo</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 40</opc>
@@ -590,6 +606,7 @@
 
     <instruction>
         <mnemonic>cmovno</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 41</opc>
@@ -599,6 +616,7 @@
 
     <instruction>
         <mnemonic>cmovb</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 42</opc>
@@ -608,6 +626,7 @@
 
     <instruction>
         <mnemonic>cmovae</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 43</opc>
@@ -617,6 +636,7 @@
 
     <instruction>
         <mnemonic>cmovz</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 44</opc>
@@ -626,6 +646,7 @@
 
     <instruction>
         <mnemonic>cmovnz</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 45</opc>
@@ -635,6 +656,7 @@
 
     <instruction>
         <mnemonic>cmovbe</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 46</opc>
@@ -644,6 +666,7 @@
 
     <instruction>
         <mnemonic>cmova</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 47</opc>
@@ -653,6 +676,7 @@
 
     <instruction>
         <mnemonic>cmovs</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 48</opc>
@@ -662,6 +686,7 @@
 
     <instruction>
         <mnemonic>cmovns</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 49</opc>
@@ -671,6 +696,7 @@
 
     <instruction>
         <mnemonic>cmovp</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4a</opc>
@@ -680,6 +706,7 @@
 
     <instruction>
         <mnemonic>cmovnp</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4b</opc>
@@ -689,6 +716,7 @@
 
     <instruction>
         <mnemonic>cmovl</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4c</opc>
@@ -698,6 +726,7 @@
 
     <instruction>
         <mnemonic>cmovge</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4d</opc>
@@ -707,6 +736,7 @@
 
     <instruction>
         <mnemonic>cmovle</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4e</opc>
@@ -716,6 +746,7 @@
 
     <instruction>
         <mnemonic>cmovg</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 4f</opc>
@@ -725,6 +756,7 @@
 
     <instruction>
         <mnemonic>cmp</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>38</opc>
@@ -779,6 +811,7 @@
 
     <instruction>
         <mnemonic>cmppd</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f c2</opc>
@@ -789,6 +822,7 @@
 
     <instruction>
         <mnemonic>cmpps</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f c2</opc>
@@ -799,6 +833,7 @@
 
     <instruction>
         <mnemonic>cmpsb</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz seg</pfx>
             <opc>a6</opc>
@@ -807,6 +842,7 @@
 
     <instruction>
         <mnemonic>cmpsw</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw seg</pfx>
             <opc>a7 /o=16</opc>
@@ -815,6 +851,7 @@
 
     <instruction>
         <mnemonic>cmpsd</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw seg</pfx>
             <opc>a7 /o=32</opc>
@@ -829,6 +866,7 @@
 
     <instruction>
         <mnemonic>cmpsq</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw seg</pfx>
             <opc>a7 /o=64</opc>
@@ -837,6 +875,7 @@
 
     <instruction>
         <mnemonic>cmpss</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f c2</opc>
@@ -847,6 +886,7 @@
 
     <instruction>
         <mnemonic>cmpxchg</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f b0</opc>
@@ -861,6 +901,7 @@
 
     <instruction>
         <mnemonic>cmpxchg8b</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f c7 /mod=!11 /reg=1 /o=16</opc>
@@ -875,6 +916,7 @@
 
     <instruction>
         <mnemonic>cmpxchg16b</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f c7 /mod=!11 /reg=1 /o=64</opc>
@@ -884,6 +926,7 @@
 
     <instruction>
         <mnemonic>comisd</mnemonic>
+        <eflags>RRMRMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 2f</opc>
@@ -894,6 +937,7 @@
 
     <instruction>
         <mnemonic>comiss</mnemonic>
+        <eflags>RRMRMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 2f</opc>
@@ -904,6 +948,7 @@
 
     <instruction>
         <mnemonic>cpuid</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f a2</opc>
         </def>
@@ -1125,6 +1170,7 @@
 
     <instruction>
         <mnemonic>cwd</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>99 /o=16</opc>
@@ -1149,6 +1195,7 @@
 
     <instruction>
         <mnemonic>daa</mnemonic>
+        <eflags>UMMMMM_____</eflags>
         <def>
             <opc>27 /m=!64</opc>
             <mode>inv64</mode>
@@ -1157,6 +1204,7 @@
 
     <instruction>
         <mnemonic>das</mnemonic>
+        <eflags>UMMMMM_____</eflags>
         <def>
             <opc>2f /m=!64</opc>
             <mode>inv64</mode>
@@ -1165,6 +1213,7 @@
 
     <instruction>
         <mnemonic>dec</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>48</opc>
@@ -1219,6 +1268,7 @@
 
     <instruction>
         <mnemonic>div</mnemonic>
+        <eflags>UUUUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=6</opc>
@@ -1300,6 +1350,7 @@
 
     <instruction>
         <mnemonic>enter</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>c8</opc>
             <opr>Iw Ib</opr>
@@ -1487,6 +1538,7 @@
 
     <instruction>
         <mnemonic>fcmovb</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=00</opc>
@@ -1524,6 +1576,7 @@
 
     <instruction>
         <mnemonic>fcmove</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=08</opc>
@@ -1561,6 +1614,7 @@
 
     <instruction>
         <mnemonic>fcmovbe</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=10</opc>
@@ -1598,6 +1652,7 @@
 
     <instruction>
         <mnemonic>fcmovu</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=18</opc>
@@ -1635,6 +1690,7 @@
 
     <instruction>
         <mnemonic>fcmovnb</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=00</opc>
@@ -1672,6 +1728,7 @@
 
     <instruction>
         <mnemonic>fcmovne</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=08</opc>
@@ -1709,6 +1766,7 @@
 
     <instruction>
         <mnemonic>fcmovnbe</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=10</opc>
@@ -1746,6 +1804,7 @@
 
     <instruction>
         <mnemonic>fcmovnu</mnemonic>
+        <eflags>__T_TT_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=18</opc>
@@ -1783,6 +1842,7 @@
 
     <instruction>
         <mnemonic>fucomi</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=28</opc>
@@ -1820,6 +1880,7 @@
 
     <instruction>
         <mnemonic>fcom</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -1867,6 +1928,7 @@
 
     <instruction>
         <mnemonic>fcom2</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87 UNDOC</cpuid>
         <def>
             <opc>dc /mod=11 /x87=10</opc>
@@ -1904,6 +1966,7 @@
 
     <instruction>
         <mnemonic>fcomp3</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87 UNDOC</cpuid>
         <def>
             <opc>dc /mod=11 /x87=18</opc>
@@ -1941,6 +2004,7 @@
 
     <instruction>
         <mnemonic>fcomi</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=30</opc>
@@ -1978,6 +2042,7 @@
 
     <instruction>
         <mnemonic>fucomip</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>df /mod=11 /x87=28</opc>
@@ -2015,6 +2080,7 @@
 
     <instruction>
         <mnemonic>fcomip</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>df /mod=11 /x87=30</opc>
@@ -2052,6 +2118,7 @@
 
     <instruction>
         <mnemonic>fcomp</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -2099,6 +2166,7 @@
 
     <instruction>
         <mnemonic>fcomp5</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87 UNDOC</cpuid>
         <def>
             <opc>de /mod=11 /x87=10</opc>
@@ -2136,6 +2204,7 @@
 
     <instruction>
         <mnemonic>fcompp</mnemonic>
+        <eflags>__M_MM_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>de /mod=11 /x87=19</opc>
@@ -3752,6 +3821,7 @@
 
      <instruction>
         <mnemonic>hlt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>f4</opc>
         </def>
@@ -3759,6 +3829,7 @@
 
     <instruction>
         <mnemonic>idiv</mnemonic>
+        <eflags>UUUUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=7</opc>
@@ -3773,6 +3844,7 @@
 
     <instruction>
         <mnemonic>in</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>e4</opc>
             <opr>AL Ib</opr>
@@ -3795,6 +3867,7 @@
 
     <instruction>
         <mnemonic>imul</mnemonic>
+        <eflags>MUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f af</opc>
@@ -3824,6 +3897,7 @@
 
     <instruction>
         <mnemonic>inc</mnemonic>
+        <eflags>MMMMM______</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>40</opc>
@@ -3878,6 +3952,7 @@
 
     <instruction>
         <mnemonic>insb</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
             <opc>6c</opc>
@@ -3886,6 +3961,7 @@
 
     <instruction>
         <mnemonic>insw</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
             <opc>6d /o=16</opc>
@@ -3894,6 +3970,7 @@
 
     <instruction>
         <mnemonic>insd</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
             <opc>6d /o=32</opc>
@@ -3902,6 +3979,7 @@
 
     <instruction>
         <mnemonic>int1</mnemonic>
+        <eflags>______R__R_</eflags>
         <def>
             <opc>f1</opc>
         </def>
@@ -3909,6 +3987,7 @@
 
     <instruction>
         <mnemonic>int3</mnemonic>
+        <eflags>______R__R_</eflags>
         <def>
             <opc>cc</opc>
         </def>
@@ -3916,6 +3995,7 @@
 
     <instruction>
         <mnemonic>int</mnemonic>
+        <eflags>______R__R_</eflags>
         <def>
             <opc>cd</opc>
             <opr>Ib</opr>
@@ -3924,6 +4004,7 @@
 
     <instruction>
         <mnemonic>into</mnemonic>
+        <eflags>T_____R__R_</eflags>
         <def>
             <opc>ce /m=!64</opc>
             <mode>inv64</mode>
@@ -3932,6 +4013,7 @@
 
     <instruction>
         <mnemonic>invd</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 08</opc>
         </def>
@@ -3952,6 +4034,7 @@
 
     <instruction>
         <mnemonic>invlpg</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=7 /mod=!11</opc>
@@ -3982,6 +4065,7 @@
 
     <instruction>
         <mnemonic>iretw</mnemonic>
+        <eflags>PPPPPPPPPT_</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>cf /o=16</opc>
@@ -3990,6 +4074,7 @@
 
     <instruction>
         <mnemonic>iretd</mnemonic>
+        <eflags>PPPPPPPPPT_</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>cf /o=32</opc>
@@ -3998,6 +4083,7 @@
 
     <instruction>
         <mnemonic>iretq</mnemonic>
+        <eflags>PPPPPPPPPT_</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>cf /o=64</opc>
@@ -4006,6 +4092,7 @@
 
     <instruction>
         <mnemonic>jo</mnemonic>
+        <eflags>T__________</eflags>
         <def>
             <opc>70</opc>
             <opr>Jb</opr>
@@ -4020,6 +4107,7 @@
 
     <instruction>
         <mnemonic>jno</mnemonic>
+        <eflags>T__________</eflags>
         <def>
             <opc>71</opc>
             <opr>Jb</opr>
@@ -4034,6 +4122,7 @@
 
     <instruction>
         <mnemonic>jb</mnemonic>
+        <eflags>_____T_____</eflags>
         <def>
             <opc>72</opc>
             <opr>Jb</opr>
@@ -4048,6 +4137,7 @@
 
     <instruction>
         <mnemonic>jae</mnemonic>
+        <eflags>_____T_____</eflags>
         <def>
             <opc>73</opc>
             <opr>Jb</opr>
@@ -4062,6 +4152,7 @@
 
     <instruction>
         <mnemonic>jz</mnemonic>
+        <eflags>__T________</eflags>
         <def>
             <opc>74</opc>
             <opr>Jb</opr>
@@ -4076,6 +4167,7 @@
 
     <instruction>
         <mnemonic>jnz</mnemonic>
+        <eflags>__T________</eflags>
         <def>
             <opc>75</opc>
             <opr>Jb</opr>
@@ -4090,6 +4182,7 @@
 
     <instruction>
         <mnemonic>jbe</mnemonic>
+        <eflags>__T__T_____</eflags>
         <def>
             <opc>76</opc>
             <opr>Jb</opr>
@@ -4104,6 +4197,7 @@
 
     <instruction>
         <mnemonic>ja</mnemonic>
+        <eflags>__T__T_____</eflags>
         <def>
             <opc>77</opc>
             <opr>Jb</opr>
@@ -4118,6 +4212,7 @@
 
     <instruction>
         <mnemonic>js</mnemonic>
+        <eflags>_T_________</eflags>
         <def>
             <opc>78</opc>
             <opr>Jb</opr>
@@ -4132,6 +4227,7 @@
 
     <instruction>
         <mnemonic>jns</mnemonic>
+        <eflags>_T_________</eflags>
         <def>
             <opc>79</opc>
             <opr>Jb</opr>
@@ -4146,6 +4242,7 @@
 
     <instruction>
         <mnemonic>jp</mnemonic>
+        <eflags>____T______</eflags>
         <def>
             <opc>7a</opc>
             <opr>Jb</opr>
@@ -4160,6 +4257,7 @@
 
     <instruction>
         <mnemonic>jnp</mnemonic>
+        <eflags>____T______</eflags>
         <def>
             <opc>7b</opc>
             <opr>Jb</opr>
@@ -4174,6 +4272,7 @@
 
     <instruction>
         <mnemonic>jl</mnemonic>
+        <eflags>TT_________</eflags>
         <def>
             <opc>7c</opc>
             <opr>Jb</opr>
@@ -4188,6 +4287,7 @@
 
     <instruction>
         <mnemonic>jge</mnemonic>
+        <eflags>TT_________</eflags>
         <def>
             <opc>7d</opc>
             <opr>Jb</opr>
@@ -4202,6 +4302,7 @@
 
     <instruction>
         <mnemonic>jle</mnemonic>
+        <eflags>TTT________</eflags>
         <def>
             <opc>7e</opc>
             <opr>Jb</opr>
@@ -4216,6 +4317,7 @@
 
     <instruction>
         <mnemonic>jg</mnemonic>
+        <eflags>TTT________</eflags>
         <def>
             <opc>7f</opc>
             <opr>Jb</opr>
@@ -4230,6 +4332,7 @@
 
     <instruction>
         <mnemonic>jcxz</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
             <opc>e3 /a=16</opc>
@@ -4239,6 +4342,7 @@
 
     <instruction>
         <mnemonic>jecxz</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
             <opc>e3 /a=32</opc>
@@ -4248,6 +4352,7 @@
 
     <instruction>
         <mnemonic>jrcxz</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
             <opc>e3 /a=64</opc>
@@ -4257,6 +4362,7 @@
 
     <instruction>
         <mnemonic>jmp</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>ff /reg=4</opc>
@@ -4288,6 +4394,7 @@
 
     <instruction>
         <mnemonic>lahf</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>9f</opc>
         </def>
@@ -4295,6 +4402,7 @@
 
     <instruction>
         <mnemonic>lar</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 02</opc>
@@ -4313,6 +4421,7 @@
 
     <instruction>
         <mnemonic>lds</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso</pfx>
             <opc>c5 /vex=none /m=!64</opc>
@@ -4322,6 +4431,7 @@
 
     <instruction>
         <mnemonic>lea</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>8d</opc>
@@ -4331,6 +4441,7 @@
 
     <instruction>
         <mnemonic>les</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso</pfx>
             <opc>c4 /m=!64</opc>
@@ -4340,6 +4451,7 @@
 
     <instruction>
         <mnemonic>lfs</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f b4</opc>
@@ -4349,6 +4461,7 @@
 
     <instruction>
         <mnemonic>lgs</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f b5</opc>
@@ -4358,6 +4471,7 @@
 
     <instruction>
         <mnemonic>lidt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=3 /mod=!11</opc>
@@ -4376,6 +4490,7 @@
 
     <instruction>
         <mnemonic>leave</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>c9</opc>
         </def>
@@ -4411,6 +4526,7 @@
 
     <instruction>
         <mnemonic>lgdt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=2 /mod=!11</opc>
@@ -4420,6 +4536,7 @@
 
     <instruction>
         <mnemonic>lldt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 00 /reg=2</opc>
@@ -4429,6 +4546,7 @@
 
     <instruction>
         <mnemonic>lmsw</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=6 /mod=!11</opc>
@@ -4443,6 +4561,7 @@
 
     <instruction>
         <mnemonic>lock</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>f0</opc>
         </def>
@@ -4450,6 +4569,7 @@
 
     <instruction>
         <mnemonic>lodsb</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
             <opc>ac</opc>
@@ -4458,6 +4578,7 @@
 
     <instruction>
         <mnemonic>lodsw</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ad /o=16</opc>
@@ -4466,6 +4587,7 @@
 
     <instruction>
         <mnemonic>lodsd</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ad /o=32</opc>
@@ -4474,6 +4596,7 @@
 
     <instruction>
         <mnemonic>lodsq</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ad /o=64</opc>
@@ -4482,6 +4605,7 @@
 
     <instruction>
         <mnemonic>loopne</mnemonic>
+        <eflags>__T________</eflags>
         <def>
             <opc>e0</opc>
             <opr>Jb</opr>
@@ -4490,6 +4614,7 @@
 
     <instruction>
         <mnemonic>loope</mnemonic>
+        <eflags>__T________</eflags>
         <def>
             <opc>e1</opc>
             <opr>Jb</opr>
@@ -4498,6 +4623,7 @@
 
     <instruction>
         <mnemonic>loop</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>e2</opc>
             <opr>Jb</opr>
@@ -4506,6 +4632,7 @@
 
     <instruction>
         <mnemonic>lsl</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f 03</opc>
@@ -4515,6 +4642,7 @@
 
     <instruction>
         <mnemonic>ltr</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 00 /reg=3</opc>
@@ -4641,6 +4769,7 @@
 
     <instruction>
         <mnemonic>monitor</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 01 /reg=1 /mod=11 /rm=0</opc>
         </def>
@@ -4655,6 +4784,7 @@
 
     <instruction>
         <mnemonic>mov</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>c6 /reg=0</opc>
@@ -4794,21 +4924,25 @@
             <opr>R7v Iv</opr>
         </def>
         <def>
+            <eflags>UUUUUU_____</eflags>
             <pfx>rexr rexw rexb</pfx>
             <opc>0f 20</opc>
             <opr>R C</opr>
         </def>
         <def>
+            <eflags>UUUUUU_____</eflags>
             <pfx>rexr rexw rexb</pfx>
             <opc>0f 21</opc>
             <opr>R D</opr>
         </def>
         <def>
+            <eflags>UUUUUU_____</eflags>
             <pfx>rexr rexw rexb</pfx>
             <opc>0f 22</opc>
             <opr>C R</opr>
         </def>
         <def>
+            <eflags>UUUUUU_____</eflags>
             <pfx>rexr rexw rexb</pfx>
             <opc>0f 23</opc>
             <opr>D R</opr>
@@ -5104,6 +5238,7 @@
 
     <instruction>
         <mnemonic>movsb</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
             <opc>a4</opc>
@@ -5112,6 +5247,7 @@
 
     <instruction>
         <mnemonic>movsw</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>a5 /o=16</opc>
@@ -5120,6 +5256,7 @@
 
     <instruction>
         <mnemonic>movsd</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>a5 /o=32</opc>
@@ -5140,6 +5277,7 @@
 
     <instruction>
         <mnemonic>movsq</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>a5 /o=64</opc>
@@ -5148,6 +5286,7 @@
 
     <instruction>
         <mnemonic>movss</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 10</opc>
@@ -5164,6 +5303,7 @@
 
     <instruction>
         <mnemonic>movsx</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f be</opc>
@@ -5210,6 +5350,7 @@
 
     <instruction>
         <mnemonic>movzx</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f b6</opc>
@@ -5224,6 +5365,7 @@
 
     <instruction>
         <mnemonic>mul</mnemonic>
+        <eflags>MUUUUM_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=4</opc>
@@ -5278,6 +5420,7 @@
 
     <instruction>
         <mnemonic>mwait</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 01 /reg=1 /mod=11 /rm=1</opc>
         </def>
@@ -5285,6 +5428,7 @@
 
     <instruction>
         <mnemonic>neg</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=3</opc>
@@ -5299,6 +5443,7 @@
 
     <instruction>
         <mnemonic>nop</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 19</opc>
@@ -5338,6 +5483,7 @@
 
     <instruction>
         <mnemonic>not</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=2</opc>
@@ -5352,6 +5498,7 @@
 
     <instruction>
         <mnemonic>or</mnemonic>
+        <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>08</opc>
@@ -5425,6 +5572,7 @@
 
     <instruction>
         <mnemonic>out</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>e6</opc>
             <opr>Ib AL</opr>
@@ -5447,6 +5595,7 @@
 
     <instruction>
         <mnemonic>outsb</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
             <opc>6e</opc>
@@ -5455,6 +5604,7 @@
 
     <instruction>
         <mnemonic>outsw</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
             <opc>6f /o=16</opc>
@@ -5463,6 +5613,7 @@
 
     <instruction>
         <mnemonic>outsd</mnemonic>
+        <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
             <opc>6f /o=32</opc>
@@ -6064,6 +6215,7 @@
 
     <instruction>
         <mnemonic>pop</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>07 /m=!64</opc>
             <opr>ES</opr>
@@ -6145,6 +6297,7 @@
 
     <instruction>
         <mnemonic>popa</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>61 /o=16 /m=!64</opc>
@@ -6154,6 +6307,7 @@
 
     <instruction>
         <mnemonic>popad</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>61 /o=32 /m=!64</opc>
@@ -6163,6 +6317,7 @@
 
     <instruction>
         <mnemonic>popfw</mnemonic>
+        <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>9d /m=!64 /o=16</opc>
@@ -6171,6 +6326,7 @@
 
     <instruction>
         <mnemonic>popfd</mnemonic>
+        <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>9d /m=!64 /o=32</opc>
@@ -6179,6 +6335,7 @@
 
     <instruction>
         <mnemonic>popfq</mnemonic>
+        <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>9d /m=64 /o=32</opc>
@@ -6923,6 +7080,7 @@
 
     <instruction>
         <mnemonic>push</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>06 /m=!64</opc>
             <opr>ES</opr>
@@ -7021,6 +7179,7 @@
 
     <instruction>
         <mnemonic>pusha</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>60 /o=16 /m=!64</opc>
@@ -7030,6 +7189,7 @@
 
     <instruction>
         <mnemonic>pushad</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>60 /o=32 /m=!64</opc>
@@ -7039,6 +7199,7 @@
 
     <instruction>
         <mnemonic>pushfw</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>9c /m=!64 /o=16</opc>
@@ -7052,6 +7213,7 @@
 
     <instruction>
         <mnemonic>pushfd</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
             <opc>9c /m=!64 /o=32</opc>
@@ -7060,6 +7222,7 @@
 
     <instruction>
         <mnemonic>pushfq</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
             <opc>9c /m=64 /o=32</opc>
@@ -7089,6 +7252,7 @@
 
     <instruction>
         <mnemonic>rcl</mnemonic>
+        <eflags>U____M_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>c0 /reg=2</opc>
@@ -7100,6 +7264,7 @@
             <opr>Ev Ib</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=2</opc>
             <opr>Eb I1</opr>
@@ -7115,6 +7280,7 @@
             <opr>Ev CL</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=2</opc>
             <opr>Ev I1</opr>
@@ -7123,7 +7289,9 @@
 
     <instruction>
         <mnemonic>rcr</mnemonic>
+        <eflags>U____M_____</eflags>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=3</opc>
             <opr>Eb I1</opr>
@@ -7139,6 +7307,7 @@
             <opr>Eb Ib</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=3</opc>
             <opr>Ev I1</opr>
@@ -7157,17 +7326,20 @@
 
     <instruction>
         <mnemonic>rol</mnemonic>
+        <eflags>U____M_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>c0 /reg=0</opc>
             <opr>Eb Ib</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=0</opc>
             <opr>Eb I1</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=0</opc>
             <opr>Ev I1</opr>
@@ -7191,7 +7363,9 @@
 
     <instruction>
         <mnemonic>ror</mnemonic>
+        <eflags>U____M_____</eflags>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=1</opc>
             <opr>Eb I1</opr>
@@ -7207,6 +7381,7 @@
             <opr>Ev Ib</opr>
         </def>
         <def>
+            <eflags>M____M_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=1</opc>
             <opr>Ev I1</opr>
@@ -7245,6 +7420,7 @@
 
     <instruction>
         <mnemonic>rdmsr</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 32</opc>
         </def>
@@ -7252,6 +7428,7 @@
 
     <instruction>
         <mnemonic>rdpmc</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 33</opc>
         </def>
@@ -7259,6 +7436,7 @@
 
     <instruction>
         <mnemonic>rdtsc</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 31</opc>
         </def>
@@ -7274,6 +7452,7 @@
 
     <instruction>
         <mnemonic>repne</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>f2</opc>
         </def>
@@ -7281,6 +7460,7 @@
 
     <instruction>
         <mnemonic>rep</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>f3</opc>
         </def>
@@ -7288,6 +7468,7 @@
 
     <instruction>
         <mnemonic>ret</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>c2</opc>
             <opr>Iw</opr>
@@ -7310,6 +7491,7 @@
 
     <instruction>
         <mnemonic>rsm</mnemonic>
+        <eflags>MMMMMMMMMMM</eflags>
         <def>
             <opc>0f aa</opc>
         </def>
@@ -7337,6 +7519,7 @@
 
     <instruction>
         <mnemonic>sahf</mnemonic>
+        <eflags>_PPPPP_____</eflags>
         <def>
             <opc>9e</opc>
         </def>
@@ -7344,6 +7527,7 @@
 
     <instruction>
         <mnemonic>sal</mnemonic>
+        <eflags>MMM_MM_____</eflags>
     </instruction>
 
     <instruction>
@@ -7356,7 +7540,9 @@
 
     <instruction>
         <mnemonic>sar</mnemonic>
+        <eflags>_MM_MM_____</eflags>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=7</opc>
             <opr>Ev I1</opr>
@@ -7367,6 +7553,7 @@
             <opr>Eb Ib</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=7</opc>
             <opr>Eb I1</opr>
@@ -7390,6 +7577,7 @@
 
     <instruction>
         <mnemonic>shl</mnemonic>
+        <eflags>_MM_MM_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>c0 /reg=6</opc>
@@ -7401,6 +7589,7 @@
             <opr>Ev Ib</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=6</opc>
             <opr>Eb I1</opr>
@@ -7426,11 +7615,13 @@
             <opr>Eb CL</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=4</opc>
             <opr>Ev I1</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=4</opc>
             <opr>Eb I1</opr>
@@ -7446,6 +7637,7 @@
             <opr>Ev CL</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=6</opc>
             <opr>Ev I1</opr>
@@ -7454,6 +7646,7 @@
 
     <instruction>
         <mnemonic>shr</mnemonic>
+        <eflags>_MM_MM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>c1 /reg=5</opc>
@@ -7465,11 +7658,13 @@
             <opr>Eb CL</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>d1 /reg=5</opc>
             <opr>Ev I1</opr>
         </def>
         <def>
+            <eflags>MMM_MM_____</eflags>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>d0 /reg=5</opc>
             <opr>Eb I1</opr>
@@ -7488,6 +7683,7 @@
 
     <instruction>
         <mnemonic>sbb</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>18</opc>
@@ -7542,6 +7738,7 @@
 
     <instruction>
         <mnemonic>scasb</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz</pfx>
             <opc>ae</opc>
@@ -7550,6 +7747,7 @@
 
     <instruction>
         <mnemonic>scasw</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
             <opc>af /o=16</opc>
@@ -7558,6 +7756,7 @@
 
     <instruction>
         <mnemonic>scasd</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
             <opc>af /o=32</opc>
@@ -7566,6 +7765,7 @@
 
     <instruction>
         <mnemonic>scasq</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
             <opc>af /o=64</opc>
@@ -7574,6 +7774,7 @@
 
     <instruction>
         <mnemonic>seto</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 90</opc>
@@ -7583,6 +7784,7 @@
 
     <instruction>
         <mnemonic>setno</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 91</opc>
@@ -7592,6 +7794,7 @@
 
     <instruction>
         <mnemonic>setb</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 92</opc>
@@ -7601,6 +7804,7 @@
 
     <instruction>
         <mnemonic>setae</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 93</opc>
@@ -7610,6 +7814,7 @@
 
     <instruction>
         <mnemonic>setz</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 94</opc>
@@ -7619,6 +7824,7 @@
 
     <instruction>
         <mnemonic>setnz</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 95</opc>
@@ -7628,6 +7834,7 @@
 
     <instruction>
         <mnemonic>setbe</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 96</opc>
@@ -7637,6 +7844,7 @@
 
     <instruction>
         <mnemonic>seta</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 97</opc>
@@ -7646,6 +7854,7 @@
 
     <instruction>
         <mnemonic>sets</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 98</opc>
@@ -7655,6 +7864,7 @@
 
     <instruction>
         <mnemonic>setns</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 99</opc>
@@ -7664,6 +7874,7 @@
 
     <instruction>
         <mnemonic>setp</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9a</opc>
@@ -7673,6 +7884,7 @@
 
     <instruction>
         <mnemonic>setnp</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9b</opc>
@@ -7682,6 +7894,7 @@
 
     <instruction>
         <mnemonic>setl</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9c</opc>
@@ -7691,6 +7904,7 @@
 
     <instruction>
         <mnemonic>setge</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9d</opc>
@@ -7700,6 +7914,7 @@
 
     <instruction>
         <mnemonic>setle</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9e</opc>
@@ -7709,6 +7924,7 @@
 
     <instruction>
         <mnemonic>setg</mnemonic>
+        <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9f</opc>
@@ -7746,6 +7962,7 @@
 
     <instruction>
         <mnemonic>sgdt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=0 /mod=!11</opc>
@@ -7755,6 +7972,7 @@
 
     <instruction>
         <mnemonic>shld</mnemonic>
+        <eflags>UMMUMM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f a4</opc>
@@ -7769,6 +7987,7 @@
 
     <instruction>
         <mnemonic>shrd</mnemonic>
+        <eflags>UMMUMM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f ac</opc>
@@ -7803,6 +8022,7 @@
 
     <instruction>
         <mnemonic>sidt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 01 /reg=1 /mod=!11</opc>
@@ -7812,6 +8032,7 @@
 
     <instruction>
         <mnemonic>sldt</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>0f 00 /reg=0</opc>
@@ -7821,6 +8042,7 @@
 
     <instruction>
         <mnemonic>smsw</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>0f 01 /reg=4 /mod=!11</opc>
@@ -7875,6 +8097,7 @@
 
     <instruction>
         <mnemonic>stc</mnemonic>
+        <eflags>_____S_____</eflags>
         <def>
             <opc>f9</opc>
         </def>
@@ -7882,6 +8105,7 @@
 
     <instruction>
         <mnemonic>std</mnemonic>
+        <eflags>________S__</eflags>
         <def>
             <opc>fd</opc>
         </def>
@@ -7897,6 +8121,7 @@
 
     <instruction>
         <mnemonic>sti</mnemonic>
+        <eflags>_______S___</eflags>
         <def>
             <opc>fb</opc>
         </def>
@@ -7922,6 +8147,7 @@
 
     <instruction>
         <mnemonic>stosb</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>rep seg</pfx>
             <opc>aa</opc>
@@ -7930,6 +8156,7 @@
 
     <instruction>
         <mnemonic>stosw</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ab /o=16</opc>
@@ -7938,6 +8165,7 @@
 
     <instruction>
         <mnemonic>stosd</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ab /o=32</opc>
@@ -7946,6 +8174,7 @@
 
     <instruction>
         <mnemonic>stosq</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
             <opc>ab /o=64</opc>
@@ -7954,6 +8183,7 @@
 
     <instruction>
         <mnemonic>str</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>0f 00 /reg=1</opc>
@@ -7963,6 +8193,7 @@
 
     <instruction>
         <mnemonic>sub</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>28</opc>
@@ -8100,6 +8331,7 @@
 
     <instruction>
         <mnemonic>test</mnemonic>
+        <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=0</opc>
@@ -8143,6 +8375,7 @@
 
     <instruction>
         <mnemonic>ucomisd</mnemonic>
+        <eflags>RRMRMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 2e</opc>
@@ -8153,6 +8386,7 @@
 
     <instruction>
         <mnemonic>ucomiss</mnemonic>
+        <eflags>RRMRMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 2e</opc>
@@ -8163,6 +8397,7 @@
 
     <instruction>
         <mnemonic>ud2</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 0b</opc>
         </def>
@@ -8210,6 +8445,7 @@
 
     <instruction>
         <mnemonic>verr</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 00 /reg=4</opc>
@@ -8219,6 +8455,7 @@
 
     <instruction>
         <mnemonic>verw</mnemonic>
+        <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 00 /reg=5</opc>
@@ -8364,6 +8601,7 @@
 
     <instruction>
         <mnemonic>wait</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>9b</opc>
         </def>
@@ -8371,6 +8609,7 @@
 
     <instruction>
         <mnemonic>wbinvd</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 09</opc>
         </def>
@@ -8378,6 +8617,7 @@
 
     <instruction>
         <mnemonic>wrmsr</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <opc>0f 30</opc>
         </def>
@@ -8385,6 +8625,7 @@
 
     <instruction>
         <mnemonic>xadd</mnemonic>
+        <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso oso rexr rexx rexb</pfx>
             <opc>0f c0</opc>
@@ -8399,6 +8640,7 @@
 
     <instruction>
         <mnemonic>xchg</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>86</opc>
@@ -8460,6 +8702,7 @@
 
     <instruction>
         <mnemonic>xlatb</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>rexw seg</pfx>
             <opc>d7</opc>
@@ -8468,6 +8711,7 @@
 
     <instruction>
         <mnemonic>xor</mnemonic>
+        <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>30</opc>
@@ -9379,6 +9623,7 @@
 
     <instruction>
         <mnemonic>bound</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>aso oso</pfx>
             <opc>62 /m=!64</opc>
@@ -9388,6 +9633,7 @@
 
     <instruction>
         <mnemonic>bsf</mnemonic>
+        <eflags>UUMUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f bc</opc>
@@ -9397,6 +9643,7 @@
 
     <instruction>
         <mnemonic>bsr</mnemonic>
+        <eflags>UUMUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f bd</opc>
@@ -9406,6 +9653,7 @@
 
     <instruction>
         <mnemonic>bswap</mnemonic>
+        <eflags>___________</eflags>
         <def>
             <pfx>oso rexw rexb</pfx>
             <opc>0f c8</opc>
@@ -9450,6 +9698,7 @@
 
     <instruction>
         <mnemonic>bt</mnemonic>
+        <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f ba /reg=4</opc>
@@ -9464,6 +9713,7 @@
 
     <instruction>
         <mnemonic>btc</mnemonic>
+        <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f bb</opc>
@@ -9478,6 +9728,7 @@
 
     <instruction>
         <mnemonic>btr</mnemonic>
+        <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f b3</opc>
@@ -9492,6 +9743,7 @@
 
     <instruction>
         <mnemonic>bts</mnemonic>
+        <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f ab</opc>
@@ -9676,6 +9928,7 @@
 
      <instruction>
         <mnemonic>popcnt</mnemonic>
+        <eflags>RRMRRR_____</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>/sse=f3 0f b8</opc>
diff --git a/libudis86/decode.h b/libudis86/decode.h
index 3949c4e..0d4a36e 100644
--- a/libudis86/decode.h
+++ b/libudis86/decode.h
@@ -177,6 +177,7 @@ struct ud_itab_entry
   struct ud_itab_entry_operand  operand3;
   struct ud_itab_entry_operand  operand4;
   uint32_t                      prefix;
+  struct ud_eflags   eflags;
 };
 
 struct ud_lookup_table_list_entry {
diff --git a/libudis86/extern.h b/libudis86/extern.h
index 71a01fd..69bad12 100644
--- a/libudis86/extern.h
+++ b/libudis86/extern.h
@@ -94,6 +94,8 @@ extern LIBUDIS86_DLLEXTERN enum ud_mnemonic_code ud_insn_mnemonic(const struct u
 
 extern LIBUDIS86_DLLEXTERN const char* ud_lookup_mnemonic(enum ud_mnemonic_code c);
 
+extern LIBUDIS86_DLLEXTERN const struct ud_eflags* ud_lookup_eflags(struct ud *u);
+
 extern LIBUDIS86_DLLEXTERN void ud_set_user_opaque_data(struct ud*, void*);
 
 extern LIBUDIS86_DLLEXTERN void* ud_get_user_opaque_data(const struct ud*);
diff --git a/libudis86/types.h b/libudis86/types.h
index d79dae9..e73bdf8 100644
--- a/libudis86/types.h
+++ b/libudis86/types.h
@@ -128,6 +128,35 @@ enum ud_type
   UD_OP_JIMM, UD_OP_CONST
 };
 
+enum ud_eflag_state
+{
+  UD_FLAG_UNCHANGED,
+  UD_FLAG_TESTED,
+  UD_FLAG_MODIFIED,
+  UD_FLAG_RESET,
+  UD_FLAG_SET,
+  UD_FLAG_UNDEFINED,
+  UD_FLAG_PRIOR
+};
+
+/* This structure describes the state of the EFLAGS register
+ * once an instruction has been executed.
+ */
+struct ud_eflags
+{
+    enum ud_eflag_state of_state;
+    enum ud_eflag_state sf_state;
+    enum ud_eflag_state zf_state;
+    enum ud_eflag_state af_state;
+    enum ud_eflag_state pf_state;
+    enum ud_eflag_state cf_state;
+    enum ud_eflag_state tf_state;
+    enum ud_eflag_state if_state;
+    enum ud_eflag_state df_state;
+    enum ud_eflag_state nt_state;
+    enum ud_eflag_state rf_state;
+};
+
 #include "itab.h"
 
 union ud_lval {
diff --git a/libudis86/udis86.c b/libudis86/udis86.c
index e039c4e..489ed3b 100644
--- a/libudis86/udis86.c
+++ b/libudis86/udis86.c
@@ -340,6 +340,21 @@ ud_lookup_mnemonic(enum ud_mnemonic_code c)
   }
 }
 
+/* =============================================================================
+ * ud_lookup_eflags
+ *    Looks up eflags information structure
+ *    Returns NULL if invalid.
+ * =============================================================================
+ */
+const struct ud_eflags*
+ud_lookup_eflags(struct ud *u)
+{
+  if (u == NULL || u->itab_entry == NULL) {
+    return NULL;
+  } else {
+    return &u->itab_entry->eflags;
+  }
+}
 
 /* 
  * ud_inp_init
diff --git a/scripts/ud_itab.py b/scripts/ud_itab.py
index 841233d..2bee4ca 100644
--- a/scripts/ud_itab.py
+++ b/scripts/ud_itab.py
@@ -280,8 +280,17 @@ def genInsnTable( self ):
                 pfx_c.append( "P_none" )
             pfx = "|".join( pfx_c )
 
-            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s },\n" \
-                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, pfx ) )
+            flag_map = {'_': 'UD_FLAG_UNCHANGED',
+                        'T': 'UD_FLAG_TESTED',
+                        'M': 'UD_FLAG_MODIFIED',
+                        'R': 'UD_FLAG_RESET',
+                        'S': 'UD_FLAG_SET',
+                        'U': 'UD_FLAG_UNDEFINED',
+                        'P': 'UD_FLAG_PRIOR'}
+            eflags = ", ".join(map(lambda f: flag_map[f], [flag for flag in insn.eflags]))
+
+            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s, {%s} },\n" \
+                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, pfx, eflags ) )
         self.ItabC.write( "};\n" )
 
    
diff --git a/scripts/ud_opcode.py b/scripts/ud_opcode.py
index c43a320..7bdbc90 100644
--- a/scripts/ud_opcode.py
+++ b/scripts/ud_opcode.py
@@ -30,6 +30,7 @@ class UdInsnDef:
     """
     def __init__(self, **insnDef):
         self.mnemonic  = insnDef['mnemonic']
+        self.eflags    = insnDef['eflags']
         self.prefixes  = insnDef['prefixes']
         self.opcodes   = insnDef['opcodes']
         self.operands  = insnDef['operands']
@@ -310,7 +311,7 @@ def __init__(self, xml):
 
         # add an invalid instruction entry without any mapping
         # in the opcode tables.
-        self.invalidInsn = UdInsnDef(mnemonic="invalid", opcodes=[], cpuid=[],
+        self.invalidInsn = UdInsnDef(mnemonic="invalid", eflags="___________", opcodes=[], cpuid=[],
                                      operands=[], prefixes=[])
         self._insns.append(self.invalidInsn)
 
@@ -370,6 +371,10 @@ def addInsn(self, **insnDef):
         # Canonicalize opcode list
         opcexts = insnDef['opcexts']
         opcodes = list(insnDef['opcodes'])
+        eflags = insnDef['eflags'] if 'eflags' in insnDef else "___________"
+
+        # TODO: REMOVE!
+        # print opcodes, eflags, insnDef['mnemonic']
 
         # Re-order vex
         if '/vex' in opcexts:
@@ -386,6 +391,7 @@ def addInsn(self, **insnDef):
                 opcodes.append(ext + '=' + opcexts[ext])
 
         insn = UdInsnDef(mnemonic = insnDef['mnemonic'],
+                         eflags   = insnDef['eflags'],
                          prefixes = insnDef['prefixes'],
                          operands = insnDef['operands'],
                          opcodes  = opcodes,
@@ -458,6 +464,7 @@ def addInsnDef(self, insnDef):
             fn = self.addSSE2AVXInsn
 
         fn(mnemonic = insnDef['mnemonic'],
+           eflags   = insnDef['eflags'],
            prefixes = insnDef['prefixes'],
            opcodes  = opcodes,
            opcexts  = opcexts,
@@ -474,6 +481,7 @@ def addSSE2AVXInsn(self, **insnDef):
 
         # SSE
         ssemnemonic = insnDef['mnemonic']
+        sseeflags   = insnDef['eflags']
         sseopcodes  = insnDef['opcodes']
         # remove vex opcode extensions
         sseopcexts  = dict([(e, v) for e, v in insnDef['opcexts'].iteritems()
@@ -490,6 +498,7 @@ def addSSE2AVXInsn(self, **insnDef):
                         if not flag.startswith('avx')]
 
         self.addInsn(mnemonic = ssemnemonic,
+                     eflags   = sseeflags,
                      prefixes = sseprefixes,
                      opcodes  = sseopcodes,
                      opcexts  = sseopcexts,
@@ -498,6 +507,7 @@ def addSSE2AVXInsn(self, **insnDef):
 
         # AVX
         vexmnemonic = 'v' + insnDef['mnemonic']
+        vexeflags   = insnDef['eflags']
         vexprefixes = insnDef['prefixes']
         vexopcodes  = ['c4']
         vexopcexts  = dict([(e, insnDef['opcexts'][e])
@@ -518,6 +528,7 @@ def addSSE2AVXInsn(self, **insnDef):
                         if not flag.startswith('sse')]
 
         self.addInsn(mnemonic = vexmnemonic,
+                     eflags   = vexeflags,
                      prefixes = vexprefixes,
                      opcodes  = vexopcodes,
                      opcexts  = vexopcexts,
@@ -589,25 +600,32 @@ def parseOptableXML(xml):
                 raise Exception("warning: invalid insn node - %s" % insnNode.localName)
             mnemonic = insnNode.getElementsByTagName('mnemonic')[0].firstChild.data
             vendor, cpuid = '', []
+            global_eflags = "___________"
 
             for node in insnNode.childNodes:
                 if node.localName == 'vendor':
                     vendor = node.firstChild.data.split()
                 elif node.localName == 'cpuid':
                     cpuid = node.firstChild.data.split()
+                elif node.localName == 'eflags':
+                    global_eflags = node.firstChild.data
 
             for node in insnNode.childNodes:
                 if node.localName == 'def':
+                    eflags = global_eflags
                     insnDef = { 'pfx' : [] }
                     for node in node.childNodes:
                         if not node.localName:
                             continue
                         if node.localName in ('pfx', 'opc', 'opr', 'vendor', 'cpuid'):
                             insnDef[node.localName] = node.firstChild.data.split()
+                        elif node.localName == 'eflags':
+                            eflags = node.firstChild.data
                         elif node.localName == 'mode':
                             insnDef['pfx'].extend(node.firstChild.data.split())
                     insns.append({'prefixes' : insnDef.get('pfx', []),
                                   'mnemonic' : mnemonic,
+                                  'eflags'   : eflags,
                                   'opcodes'  : insnDef.get('opc', []),
                                   'operands' : insnDef.get('opr', []),
                                   'vendor'   : insnDef.get('vendor', vendor),

From 5fa744fb53f7c99a5e47d9fea09ce20eccc610ac Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Thu, 5 Dec 2013 09:25:54 +0100
Subject: [PATCH 02/20] Add an option to udcli to display EFLAGS information of
 disassembled instructions.

---
 udcli/udcli.c | 78 ++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 62 insertions(+), 16 deletions(-)

diff --git a/udcli/udcli.c b/udcli/udcli.c
index 9b044ca..2b3d9e7 100644
--- a/udcli/udcli.c
+++ b/udcli/udcli.c
@@ -73,6 +73,7 @@ static char help[] =
   "               hexadecimal representation. Example: 0f 01 ae 00\n"
   "    -noff    : Do not display the offset of instructions.\n"
   "    -nohex   : Do not display the hexadecimal code of instructions.\n"
+  "    -eflags  : Display information on EFLAGS register.\n"
   "    -h       : Display this help message.\n"
   "    --version: Show version.\n"
   "\n"
@@ -87,11 +88,40 @@ unsigned char o_do_count= 0;
 unsigned char o_do_off = 1;
 unsigned char o_do_hex = 1;
 unsigned char o_do_x = 0;
+unsigned char o_do_eflags = 0;
 unsigned o_vendor = UD_VENDOR_AMD;
 
 int input_hook_x(ud_t* u);
 int input_hook_file(ud_t* u);
 
+void print_flag(enum ud_eflag_state flag)
+{
+  switch(flag) {
+    case UD_FLAG_UNCHANGED: printf("_"); break;
+    case UD_FLAG_TESTED:    printf("T"); break;
+    case UD_FLAG_MODIFIED:  printf("M"); break;
+    case UD_FLAG_RESET:     printf("R"); break;
+    case UD_FLAG_SET:       printf("S"); break;
+    case UD_FLAG_UNDEFINED: printf("U"); break;
+    case UD_FLAG_PRIOR:     printf("P"); break;
+  }
+}
+
+void print_eflags(const struct ud_eflags *state)
+{
+  printf("of:"); print_flag(state->of_state); printf(" ");
+  printf("sf:"); print_flag(state->sf_state); printf(" ");
+  printf("zf:"); print_flag(state->zf_state); printf(" ");
+  printf("af:"); print_flag(state->af_state); printf(" ");
+  printf("pf:"); print_flag(state->pf_state); printf(" ");
+  printf("cf:"); print_flag(state->cf_state); printf(" ");
+  printf("tf:"); print_flag(state->tf_state); printf(" ");
+  printf("if:"); print_flag(state->if_state); printf(" ");
+  printf("df:"); print_flag(state->df_state); printf(" ");
+  printf("nt:"); print_flag(state->nt_state); printf(" ");
+  printf("rf:"); print_flag(state->rf_state);
+}
+
 int main(int argc, char **argv)
 {
   char *prog_path = *argv;
@@ -133,6 +163,8 @@ int main(int argc, char **argv)
 		o_do_off = 0;
 	else if (strcmp(*argv,"-nohex") == 0)
 		o_do_hex = 0;
+	else if (strcmp(*argv,"-eflags") == 0)
+		o_do_eflags = 1;
 	else if (strcmp(*argv,"-x") == 0)
 		o_do_x = 1;
 	else if (strcmp(*argv,"-s") == 0)
@@ -209,25 +241,39 @@ int main(int argc, char **argv)
 	ud_input_skip(&ud_obj, o_skip);
   }
 
+  // Note: I use another variable, because I plan to add
+  // other options in the future. Hence, o_do_meta holds
+  // the information about if we have to display any
+  // metadata.
+  unsigned char o_do_meta = o_do_eflags;
+
   /* disassembly loop */
   while (ud_disassemble(&ud_obj)) {
-	if (o_do_off)
-		printf("%016" FMT64 "x ", ud_insn_off(&ud_obj));
-	if (o_do_hex) {
-		const char* hex1, *hex2;
-		hex1 = ud_insn_hex(&ud_obj);
-		hex2 = hex1 + 16;
-		printf("%-16.16s %-24s", hex1, ud_insn_asm(&ud_obj));
-		if (strlen(hex1) > 16) {
-			printf("\n");
-			if (o_do_off)
-				printf("%15s -", "");
-			printf("%-16s", hex2);
-		}
-	} 
-	else printf(" %-24s", ud_insn_asm(&ud_obj));
+    if (o_do_off)
+      printf("%016" FMT64 "x ", ud_insn_off(&ud_obj));
+    if (o_do_hex) {
+      const char* hex1, *hex2;
+      hex1 = ud_insn_hex(&ud_obj);
+      hex2 = hex1 + 16;
+      printf("%-16.16s %-24s", hex1, ud_insn_asm(&ud_obj));
+      if (strlen(hex1) > 16) {
+        printf("\n");
+        if (o_do_off)
+          printf("%15s -", "");
+        printf("%-16s", hex2);
+      }
+    }
+    else printf(" %-24s", ud_insn_asm(&ud_obj));
+      
+    if (o_do_meta) {
+      printf(" ; ");
+      if (o_do_eflags) {
+        const struct ud_eflags* eflags = ud_lookup_eflags(&ud_obj);
+        print_eflags(eflags);
+      }
+    }
 
-	printf("\n");
+    printf("\n");
   }
   
   exit(EXIT_SUCCESS);

From 632344f62f368a9ff82ba66cfa6602cd211bab22 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Thu, 5 Dec 2013 11:42:54 +0100
Subject: [PATCH 03/20] Add a field in the operand structure, to know if it has
 a signed immediate or not.

---
 libudis86/decode.c | 28 +++++++++++++++++++++-------
 libudis86/types.h  |  1 +
 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/libudis86/decode.c b/libudis86/decode.c
index 83e8e18..ecf4d19 100644
--- a/libudis86/decode.c
+++ b/libudis86/decode.c
@@ -1244,13 +1244,27 @@ ud_decode(struct ud *u)
     u->mnemonic = u->itab_entry->mnemonic;
   } 
 
-    /* maybe this stray segment override byte
-     * should be spewed out?
-     */
-    if ( !P_SEG( u->itab_entry->prefix ) && 
-            u->operand[0].type != UD_OP_MEM &&
-            u->operand[1].type != UD_OP_MEM )
-        u->pfx_seg = 0;
+  /* maybe this stray segment override byte
+   * should be spewed out?
+   */
+  if ( !P_SEG( u->itab_entry->prefix ) && 
+          u->operand[0].type != UD_OP_MEM &&
+          u->operand[1].type != UD_OP_MEM )
+      u->pfx_seg = 0;
+
+  /* Retrieve some information about operands. */
+  for (int i=0; i<4; i++) {
+    struct ud_operand *op = &u->operand[i];
+    switch (op->type) {
+      case UD_OP_REG:   op->signed_lval = 0; break;
+      case UD_OP_MEM:   op->signed_lval = 0; break;
+      case UD_OP_IMM:   op->signed_lval = (op->_oprcode == OP_sI ? 1 : 0); break;
+      case UD_OP_JIMM:  op->signed_lval = 1; break;
+      case UD_OP_PTR:   op->signed_lval = 0; break;
+      case UD_OP_CONST: op->signed_lval = 0; break;
+      default: break;
+    }
+  }
 
   u->insn_offset = u->pc; /* set offset of instruction */
   u->asm_buf_fill = 0;   /* set translation buffer index to 0 */
diff --git a/libudis86/types.h b/libudis86/types.h
index e73bdf8..45163ee 100644
--- a/libudis86/types.h
+++ b/libudis86/types.h
@@ -186,6 +186,7 @@ struct ud_operand {
   uint8_t         scale;  
   uint8_t         offset;
   union ud_lval   lval;
+  uint8_t         signed_lval;
   /*
    * internal use only
    */

From 5d45db83a0df04b9ef9ee002c96a2e91aa94935c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Mon, 9 Dec 2013 14:19:25 +0100
Subject: [PATCH 04/20] Update EFLAGS values for FPU instructions.

---
 docs/x86/optable.xml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 66e7fc7..5c4f518 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -1538,7 +1538,7 @@
 
     <instruction>
         <mnemonic>fcmovb</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>_____T_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=00</opc>
@@ -1576,7 +1576,7 @@
 
     <instruction>
         <mnemonic>fcmove</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>__T________</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=08</opc>
@@ -1614,7 +1614,7 @@
 
     <instruction>
         <mnemonic>fcmovbe</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>__T__T_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=10</opc>
@@ -1652,7 +1652,7 @@
 
     <instruction>
         <mnemonic>fcmovu</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>____T______</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>da /mod=11 /x87=18</opc>
@@ -1690,7 +1690,7 @@
 
     <instruction>
         <mnemonic>fcmovnb</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>_____T_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=00</opc>
@@ -1728,7 +1728,7 @@
 
     <instruction>
         <mnemonic>fcmovne</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>__T________</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=08</opc>
@@ -1766,7 +1766,7 @@
 
     <instruction>
         <mnemonic>fcmovnbe</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>__T__T_____</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=10</opc>
@@ -1804,7 +1804,7 @@
 
     <instruction>
         <mnemonic>fcmovnu</mnemonic>
-        <eflags>__T_TT_____</eflags>
+        <eflags>____T______</eflags>
         <cpuid>X87</cpuid>
         <def>
             <opc>db /mod=11 /x87=18</opc>

From 234fa3624b87aae9378eeb7962ffc90b712f35ed Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Mon, 9 Dec 2013 14:32:31 +0100
Subject: [PATCH 05/20] Some information about the <eflags> field.

---
 docs/x86/optable.xml | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 5c4f518..ca9639b 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -99,6 +99,24 @@
 
      If the above transformations do not generate the required
      definitions, the instructions will need to be defined separately.
+    
+    EFLAGS
+      The <eflags> field describe the status of the EFLAGS register
+    once the instruction has been executed. This is an array of eleven
+    values, for each bit of the EFLAGS register.
+    
+      The order of the flags is OF, SF, ZF, AF, PF, CF, TF, IF, DF, NT, RF.
+      Each flag can have one of these values:
+          _ : the flag is not used
+          T : flag is tested
+          M : flag is modified according to the result of the operation
+          R : flag is reset (its value is 0)
+          S : flag is set (its value is 1)
+          U : flag is undefined
+          P : flag is set to its prior value (like push / pop)
+
+      By default, we assume that the mask value is "___________".
+
   -->
 
     <instruction>

From 7abe41dcabc5dde9d44fdbae24d8afa0d215318c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Mon, 9 Dec 2013 17:53:25 +0100
Subject: [PATCH 06/20] Add meta-information about operand access mode
 (read/write or both) and implicite register used or defined.

---
 docs/x86/avx.xml     | 359 ++++++++++++++++++++
 docs/x86/optable.xml | 785 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 1131 insertions(+), 13 deletions(-)

diff --git a/docs/x86/avx.xml b/docs/x86/avx.xml
index 9b7b12c..e74ab7a 100644
--- a/docs/x86/avx.xml
+++ b/docs/x86/avx.xml
@@ -1,5 +1,6 @@
   <instruction>
     <mnemonic>vaddpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 58</opc>
     <opr>V H W</opr>
@@ -8,6 +9,7 @@
 
   <instruction>
     <mnemonic>vaddps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 58</opc>
     <opr>V H W</opr>
@@ -16,6 +18,7 @@
 
   <instruction>
     <mnemonic>vaddsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 58</opc>
     <opr>V H W</opr>
@@ -24,6 +27,7 @@
 
   <instruction>
     <mnemonic>vaddss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 58</opc>
     <opr>V H W</opr>
@@ -32,6 +36,7 @@
 
   <instruction>
     <mnemonic>vandpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 54</opc>
     <opr>V H W</opr>
@@ -40,6 +45,7 @@
 
   <instruction>
     <mnemonic>vandps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 54</opc>
     <opr>V H W</opr>
@@ -48,6 +54,7 @@
 
   <instruction>
     <mnemonic>vandnpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 55</opc>
     <opr>V H W</opr>
@@ -56,6 +63,7 @@
 
   <instruction>
     <mnemonic>vandnps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 55</opc>
     <opr>V H W</opr>
@@ -64,6 +72,7 @@
 
   <instruction>
     <mnemonic>vcmppd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f c2</opc>
     <opr>V W Ib</opr>
@@ -72,6 +81,7 @@
 
   <instruction>
     <mnemonic>vcmpps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f c2</opc>
     <opr>V W Ib</opr>
@@ -80,6 +90,7 @@
 
   <instruction>
     <mnemonic>vcmpsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f c2</opc>
     <opr>V W Ib</opr>
@@ -88,6 +99,7 @@
 
   <instruction>
     <mnemonic>vcmpss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f c2</opc>
     <opr>V W Ib</opr>
@@ -112,6 +124,7 @@
 
   <instruction>
     <mnemonic>vcvtdq2pd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f e6</opc>
     <opr>V H W</opr>
@@ -120,6 +133,7 @@
 
   <instruction>
     <mnemonic>vcvtdq2ps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 5b</opc>
     <opr>V H W</opr>
@@ -128,6 +142,7 @@
 
   <instruction>
     <mnemonic>vcvtpd2dq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f e6</opc>
     <opr>V H W</opr>
@@ -136,6 +151,7 @@
 
   <instruction>
     <mnemonic>vcvtpd2pi</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 2d</opc>
     <opr>P W</opr>
@@ -144,6 +160,7 @@
 
   <instruction>
     <mnemonic>vcvtpd2ps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5a</opc>
     <opr>V H W</opr>
@@ -152,6 +169,7 @@
 
   <instruction>
     <mnemonic>vcvtpi2ps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 2a</opc>
     <opr>V Q</opr>
@@ -160,6 +178,7 @@
 
   <instruction>
     <mnemonic>vcvtpi2pd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 2a</opc>
     <opr>V Q</opr>
@@ -168,6 +187,7 @@
 
   <instruction>
     <mnemonic>vcvtps2dq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5b</opc>
     <opr>V H W</opr>
@@ -176,6 +196,7 @@
 
   <instruction>
     <mnemonic>vcvtps2pi</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 2d</opc>
     <opr>P W</opr>
@@ -184,6 +205,8 @@
 
   <instruction>
     <mnemonic>vcvtps2pd</mnemonic>
+    <first_operand_access>W</first_operand_access>
+    
     <pfx>vex.L</pfx>
     <opc>vex.0f 5a</opc>
     <opr>V H W</opr>
@@ -192,6 +215,7 @@
 
   <instruction>
     <mnemonic>vcvtsd2si</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.f20f 2d</opc>
     <opr>Gy W</opr>
@@ -200,6 +224,7 @@
 
   <instruction>
     <mnemonic>vcvtsd2ss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 5a</opc>
     <opr>V H W</opr>
@@ -208,6 +233,7 @@
 
   <instruction>
     <mnemonic>vcvtsi2ss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso</pfx>
     <opc>vex.f30f 2a</opc>
     <opr>V Ey</opr>
@@ -216,6 +242,7 @@
 
   <instruction>
     <mnemonic>vcvtss2si</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.f30f 2d</opc>
     <opr>Gy W</opr>
@@ -224,6 +251,7 @@
 
   <instruction>
     <mnemonic>vcvtss2sd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 5a</opc>
     <opr>V H W</opr>
@@ -232,6 +260,7 @@
 
   <instruction>
     <mnemonic>vcvttpd2pi</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 2c</opc>
     <opr>P W</opr>
@@ -240,6 +269,7 @@
 
   <instruction>
     <mnemonic>vcvttpd2dq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e6</opc>
     <opr>V H W</opr>
@@ -248,6 +278,7 @@
 
   <instruction>
     <mnemonic>vcvttps2dq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 5b</opc>
     <opr>V H W</opr>
@@ -256,6 +287,7 @@
 
   <instruction>
     <mnemonic>vcvttps2pi</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 2c</opc>
     <opr>P W</opr>
@@ -264,6 +296,7 @@
 
   <instruction>
     <mnemonic>vcvttsd2si</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.f20f 2c</opc>
     <opr>Gy W</opr>
@@ -272,6 +305,7 @@
 
   <instruction>
     <mnemonic>vcvtsi2sd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso</pfx>
     <opc>vex.f20f 2a</opc>
     <opr>V Ey</opr>
@@ -280,6 +314,7 @@
 
   <instruction>
     <mnemonic>vcvttss2si</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.f30f 2c</opc>
     <opr>Gy W</opr>
@@ -288,6 +323,7 @@
 
   <instruction>
     <mnemonic>vdivpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5e</opc>
     <opr>V H W</opr>
@@ -296,6 +332,7 @@
 
   <instruction>
     <mnemonic>vdivps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 5e</opc>
     <opr>V H W</opr>
@@ -304,6 +341,7 @@
 
   <instruction>
     <mnemonic>vdivsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 5e</opc>
     <opr>V H W</opr>
@@ -312,6 +350,7 @@
 
   <instruction>
     <mnemonic>vdivss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 5e</opc>
     <opr>V H W</opr>
@@ -328,6 +367,7 @@
 
   <instruction>
     <mnemonic>vmaxpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5f</opc>
     <opr>V H W</opr>
@@ -336,6 +376,7 @@
 
   <instruction>
     <mnemonic>vmaxps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 5f</opc>
     <opr>V H W</opr>
@@ -344,6 +385,7 @@
 
   <instruction>
     <mnemonic>vmaxsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 5f</opc>
     <opr>V H W</opr>
@@ -352,6 +394,7 @@
 
   <instruction>
     <mnemonic>vmaxss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 5f</opc>
     <opr>V H W</opr>
@@ -360,6 +403,7 @@
 
   <instruction>
     <mnemonic>vminpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5d</opc>
     <opr>V H W</opr>
@@ -368,6 +412,7 @@
 
   <instruction>
     <mnemonic>vminps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 5d</opc>
     <opr>V H W</opr>
@@ -376,6 +421,7 @@
 
   <instruction>
     <mnemonic>vminsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 5d</opc>
     <opr>V H W</opr>
@@ -384,6 +430,7 @@
 
   <instruction>
     <mnemonic>vminss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 5d</opc>
     <opr>V H W</opr>
@@ -392,6 +439,7 @@
 
   <instruction>
     <mnemonic>vmovapd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 28</opc>
     <opr>V H W</opr>
@@ -400,6 +448,7 @@
 
   <instruction>
     <mnemonic>vmovapd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 29</opc>
     <opr>W H V</opr>
@@ -408,6 +457,7 @@
 
   <instruction>
     <mnemonic>vmovaps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 28</opc>
     <opr>V H W</opr>
@@ -416,6 +466,7 @@
 
   <instruction>
     <mnemonic>vmovaps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 29</opc>
     <opr>W H V</opr>
@@ -424,6 +475,7 @@
 
   <instruction>
     <mnemonic>vmovd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 6e</opc>
     <opr>V Ey</opr>
@@ -432,6 +484,7 @@
 
   <instruction>
     <mnemonic>vmovd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 6e</opc>
     <opr>P Ey</opr>
@@ -440,6 +493,7 @@
 
   <instruction>
     <mnemonic>vmovd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 7e</opc>
     <opr>Ey V</opr>
@@ -448,6 +502,7 @@
 
   <instruction>
     <mnemonic>vmovd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 7e</opc>
     <opr>Ey P</opr>
@@ -456,6 +511,7 @@
 
   <instruction>
     <mnemonic>vmovhpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 16 /mod=!11</opc>
     <opr>V M</opr>
@@ -464,6 +520,7 @@
 
   <instruction>
     <mnemonic>vmovhpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 17</opc>
     <opr>M V</opr>
@@ -472,6 +529,7 @@
 
   <instruction>
     <mnemonic>vmovhps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 16 /mod=!11</opc>
     <opr>V M</opr>
@@ -480,6 +538,7 @@
 
   <instruction>
     <mnemonic>vmovhps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 17</opc>
     <opr>M V</opr>
@@ -488,6 +547,7 @@
 
   <instruction>
     <mnemonic>vmovlhps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 16 /mod=11</opc>
     <opr>V U</opr>
@@ -496,6 +556,7 @@
 
   <instruction>
     <mnemonic>vmovlpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 12 /mod=!11</opc>
     <opr>V M</opr>
@@ -504,6 +565,7 @@
 
   <instruction>
     <mnemonic>vmovlpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 13</opc>
     <opr>M V</opr>
@@ -512,6 +574,7 @@
 
   <instruction>
     <mnemonic>vmovlps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 12 /mod=!11</opc>
     <opr>V M</opr>
@@ -520,6 +583,7 @@
 
   <instruction>
     <mnemonic>vmovlps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 13</opc>
     <opr>M V</opr>
@@ -528,6 +592,7 @@
 
   <instruction>
     <mnemonic>vmovhlps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 12 /mod=11</opc>
     <opr>V U</opr>
@@ -536,6 +601,7 @@
 
   <instruction>
     <mnemonic>vmovmskpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.660f 50</opc>
     <opr>Gd U</opr>
@@ -544,6 +610,7 @@
 
   <instruction>
     <mnemonic>vmovmskps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.0f 50</opc>
     <opr>Gd U</opr>
@@ -552,6 +619,7 @@
 
   <instruction>
     <mnemonic>vmovntdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f e7</opc>
     <opr>M V</opr>
@@ -560,6 +628,7 @@
 
   <instruction>
     <mnemonic>vmovnti</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f c3</opc>
     <opr>M Gy</opr>
@@ -568,6 +637,7 @@
 
   <instruction>
     <mnemonic>vmovntpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f 2b</opc>
     <opr>M V</opr>
@@ -576,6 +646,7 @@
 
   <instruction>
     <mnemonic>vmovntps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f 2b</opc>
     <opr>M V</opr>
@@ -584,6 +655,7 @@
 
   <instruction>
     <mnemonic>vmovntq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.0f e7</opc>
     <opr>M V</opr>
@@ -592,6 +664,7 @@
 
   <instruction>
     <mnemonic>vmovq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 6f</opc>
     <opr>V W</opr>
@@ -600,6 +673,7 @@
 
   <instruction>
     <mnemonic>vmovq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d6</opc>
     <opr>W H V</opr>
@@ -608,6 +682,7 @@
 
   <instruction>
     <mnemonic>vmovq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 7e</opc>
     <opr>V H W</opr>
@@ -616,6 +691,7 @@
 
   <instruction>
     <mnemonic>vmovq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 7f</opc>
     <opr>W V</opr>
@@ -624,6 +700,7 @@
 
   <instruction>
     <mnemonic>vmovsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 10</opc>
     <opr>V H W</opr>
@@ -632,6 +709,7 @@
 
   <instruction>
     <mnemonic>vmovsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 11</opc>
     <opr>W H V</opr>
@@ -640,6 +718,7 @@
 
   <instruction>
     <mnemonic>vmovss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 10</opc>
     <opr>V H W</opr>
@@ -648,6 +727,7 @@
 
   <instruction>
     <mnemonic>vmovss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 11</opc>
     <opr>W H V</opr>
@@ -656,6 +736,7 @@
 
   <instruction>
     <mnemonic>vmovsx</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f be</opc>
     <opr>Gv Eb</opr>
@@ -664,6 +745,7 @@
 
   <instruction>
     <mnemonic>vmovsx</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f bf</opc>
     <opr>Gy Ew</opr>
@@ -672,6 +754,7 @@
 
   <instruction>
     <mnemonic>vmovupd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 10</opc>
     <opr>V H W</opr>
@@ -680,6 +763,7 @@
 
   <instruction>
     <mnemonic>vmovupd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 11</opc>
     <opr>W H V</opr>
@@ -688,6 +772,7 @@
 
   <instruction>
     <mnemonic>vmovups</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 10</opc>
     <opr>V H W</opr>
@@ -696,6 +781,7 @@
 
   <instruction>
     <mnemonic>vmovups</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 11</opc>
     <opr>W H V</opr>
@@ -704,6 +790,7 @@
 
   <instruction>
     <mnemonic>vmovzx</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f b6</opc>
     <opr>Gv Eb</opr>
@@ -712,6 +799,7 @@
 
   <instruction>
     <mnemonic>vmovzx</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f b7</opc>
     <opr>Gy Ew</opr>
@@ -720,6 +808,7 @@
 
   <instruction>
     <mnemonic>vmulpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 59</opc>
     <opr>V H W</opr>
@@ -728,6 +817,7 @@
 
   <instruction>
     <mnemonic>vmulps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 59</opc>
     <opr>V H W</opr>
@@ -736,6 +826,7 @@
 
   <instruction>
     <mnemonic>vmulsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 59</opc>
     <opr>V H W</opr>
@@ -744,6 +835,7 @@
 
   <instruction>
     <mnemonic>vmulss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 59</opc>
     <opr>V H W</opr>
@@ -752,6 +844,7 @@
 
   <instruction>
     <mnemonic>vorps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 56</opc>
     <opr>V H W</opr>
@@ -760,6 +853,7 @@
 
   <instruction>
     <mnemonic>vpacksswb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 63</opc>
     <opr>V H W</opr>
@@ -768,6 +862,7 @@
 
   <instruction>
     <mnemonic>vpacksswb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 63</opc>
     <opr>V W</opr>
@@ -776,6 +871,7 @@
 
   <instruction>
     <mnemonic>vpackssdw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 6b</opc>
     <opr>V H W</opr>
@@ -784,6 +880,7 @@
 
   <instruction>
     <mnemonic>vpackssdw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 6b</opc>
     <opr>V W</opr>
@@ -792,6 +889,7 @@
 
   <instruction>
     <mnemonic>vpackuswb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 67</opc>
     <opr>V H W</opr>
@@ -800,6 +898,7 @@
 
   <instruction>
     <mnemonic>vpackuswb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 67</opc>
     <opr>V W</opr>
@@ -808,6 +907,7 @@
 
   <instruction>
     <mnemonic>vpaddb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f fc</opc>
     <opr>V H W</opr>
@@ -816,6 +916,7 @@
 
   <instruction>
     <mnemonic>vpaddb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f fc</opc>
     <opr>V W</opr>
@@ -824,6 +925,7 @@
 
   <instruction>
     <mnemonic>vpaddw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f fd</opc>
     <opr>V W</opr>
@@ -832,6 +934,7 @@
 
   <instruction>
     <mnemonic>vpaddw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f fd</opc>
     <opr>V H W</opr>
@@ -840,6 +943,7 @@
 
   <instruction>
     <mnemonic>vpaddd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f fe</opc>
     <opr>V W</opr>
@@ -848,6 +952,7 @@
 
   <instruction>
     <mnemonic>vpaddd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f fe</opc>
     <opr>V H W</opr>
@@ -856,6 +961,7 @@
 
   <instruction>
     <mnemonic>vpaddsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f ec</opc>
     <opr>V W</opr>
@@ -864,6 +970,7 @@
 
   <instruction>
     <mnemonic>vpaddsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f ec</opc>
     <opr>V H W</opr>
@@ -872,6 +979,7 @@
 
   <instruction>
     <mnemonic>vpaddsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f ed</opc>
     <opr>V W</opr>
@@ -880,6 +988,7 @@
 
   <instruction>
     <mnemonic>vpaddsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f ed</opc>
     <opr>V H W</opr>
@@ -888,6 +997,7 @@
 
   <instruction>
     <mnemonic>vpaddusb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f dc</opc>
     <opr>V W</opr>
@@ -896,6 +1006,7 @@
 
   <instruction>
     <mnemonic>vpaddusb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f dc</opc>
     <opr>V H W</opr>
@@ -904,6 +1015,7 @@
 
   <instruction>
     <mnemonic>vpaddusw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f dd</opc>
     <opr>V W</opr>
@@ -912,6 +1024,7 @@
 
   <instruction>
     <mnemonic>vpaddusw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f dd</opc>
     <opr>V H W</opr>
@@ -920,6 +1033,7 @@
 
   <instruction>
     <mnemonic>vpand</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f db</opc>
     <opr>V H W</opr>
@@ -928,6 +1042,7 @@
 
   <instruction>
     <mnemonic>vpand</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f db</opc>
     <opr>V W</opr>
@@ -936,6 +1051,7 @@
 
   <instruction>
     <mnemonic>vpandn</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f df</opc>
     <opr>V H W</opr>
@@ -944,6 +1060,7 @@
 
   <instruction>
     <mnemonic>vpandn</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f df</opc>
     <opr>V W</opr>
@@ -952,6 +1069,7 @@
 
   <instruction>
     <mnemonic>vpavgb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e0</opc>
     <opr>V H W</opr>
@@ -960,6 +1078,7 @@
 
   <instruction>
     <mnemonic>vpavgb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e0</opc>
     <opr>V W</opr>
@@ -968,6 +1087,7 @@
 
   <instruction>
     <mnemonic>vpavgw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e3</opc>
     <opr>V H W</opr>
@@ -976,6 +1096,7 @@
 
   <instruction>
     <mnemonic>vpavgw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e3</opc>
     <opr>V W</opr>
@@ -984,6 +1105,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 74</opc>
     <opr>V W</opr>
@@ -992,6 +1114,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 74</opc>
     <opr>V H W</opr>
@@ -1000,6 +1123,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 75</opc>
     <opr>V W</opr>
@@ -1008,6 +1132,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 75</opc>
     <opr>V H W</opr>
@@ -1016,6 +1141,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 76</opc>
     <opr>V W</opr>
@@ -1024,6 +1150,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 76</opc>
     <opr>V H W</opr>
@@ -1032,6 +1159,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 64</opc>
     <opr>V H W</opr>
@@ -1040,6 +1168,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 64</opc>
     <opr>V W</opr>
@@ -1048,6 +1177,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 65</opc>
     <opr>V H W</opr>
@@ -1056,6 +1186,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 65</opc>
     <opr>V W</opr>
@@ -1064,6 +1195,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 66</opc>
     <opr>V H W</opr>
@@ -1072,6 +1204,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 66</opc>
     <opr>V W</opr>
@@ -1080,6 +1213,7 @@
 
   <instruction>
     <mnemonic>vpextrb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.660f3a 14</opc>
     <opr>MbRv V Ib</opr>
@@ -1088,6 +1222,7 @@
 
   <instruction>
     <mnemonic>vpextrd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 16 /o=16</opc>
     <opr>Ed V Ib</opr>
@@ -1096,6 +1231,7 @@
 
   <instruction>
     <mnemonic>vpextrd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 16 /o=32</opc>
     <opr>Ed V Ib</opr>
@@ -1104,6 +1240,7 @@
 
   <instruction>
     <mnemonic>vpextrq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 16 /o=64</opc>
     <opr>Eq V Ib</opr>
@@ -1112,6 +1249,7 @@
 
   <instruction>
     <mnemonic>vpextrw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.660f c5</opc>
     <opr>Gd U Ib</opr>
@@ -1120,6 +1258,7 @@
 
   <instruction>
     <mnemonic>vpextrw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.0f c5</opc>
     <opr>Gd N Ib</opr>
@@ -1128,6 +1267,7 @@
 
   <instruction>
     <mnemonic>vpinsrb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.660f3a 20</opc>
     <opr>V MbRd Ib</opr>
@@ -1136,6 +1276,7 @@
 
   <instruction>
     <mnemonic>vpinsrw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.0f c4</opc>
     <opr>P MwRy Ib</opr>
@@ -1144,6 +1285,7 @@
 
   <instruction>
     <mnemonic>vpinsrw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.660f c4</opc>
     <opr>V MwRy Ib</opr>
@@ -1152,6 +1294,7 @@
 
   <instruction>
     <mnemonic>vpinsrd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 22 /o=16</opc>
     <opr>V Ed Ib</opr>
@@ -1160,6 +1303,7 @@
 
   <instruction>
     <mnemonic>vpinsrd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 22 /o=32</opc>
     <opr>V Ed Ib</opr>
@@ -1168,6 +1312,7 @@
 
   <instruction>
     <mnemonic>vpinsrq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 22 /o=64</opc>
     <opr>V Eq Ib</opr>
@@ -1176,6 +1321,7 @@
 
   <instruction>
     <mnemonic>vpmaddwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f5</opc>
     <opr>V W</opr>
@@ -1184,6 +1330,7 @@
 
   <instruction>
     <mnemonic>vpmaddwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f5</opc>
     <opr>V H W</opr>
@@ -1192,6 +1339,7 @@
 
   <instruction>
     <mnemonic>vpmaxsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f ee</opc>
     <opr>V H W</opr>
@@ -1200,6 +1348,7 @@
 
   <instruction>
     <mnemonic>vpmaxsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f ee</opc>
     <opr>V W</opr>
@@ -1208,6 +1357,7 @@
 
   <instruction>
     <mnemonic>vpmaxub</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f de</opc>
     <opr>V W</opr>
@@ -1216,6 +1366,7 @@
 
   <instruction>
     <mnemonic>vpmaxub</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f de</opc>
     <opr>V H W</opr>
@@ -1224,6 +1375,7 @@
 
   <instruction>
     <mnemonic>vpminsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f ea</opc>
     <opr>V H W</opr>
@@ -1232,6 +1384,7 @@
 
   <instruction>
     <mnemonic>vpminsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f ea</opc>
     <opr>V W</opr>
@@ -1240,6 +1393,7 @@
 
   <instruction>
     <mnemonic>vpminub</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f da</opc>
     <opr>V H W</opr>
@@ -1248,6 +1402,7 @@
 
   <instruction>
     <mnemonic>vpminub</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f da</opc>
     <opr>V W</opr>
@@ -1256,6 +1411,7 @@
 
   <instruction>
     <mnemonic>vpmovmskb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.660f d7</opc>
     <opr>Gd U</opr>
@@ -1264,6 +1420,7 @@
 
   <instruction>
     <mnemonic>vpmovmskb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.0f d7</opc>
     <opr>Gd N</opr>
@@ -1272,6 +1429,7 @@
 
   <instruction>
     <mnemonic>vpmulhuw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e4</opc>
     <opr>V W</opr>
@@ -1280,6 +1438,7 @@
 
   <instruction>
     <mnemonic>vpmulhuw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e4</opc>
     <opr>V H W</opr>
@@ -1288,6 +1447,7 @@
 
   <instruction>
     <mnemonic>vpmulhw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e5</opc>
     <opr>V H W</opr>
@@ -1296,6 +1456,7 @@
 
   <instruction>
     <mnemonic>vpmulhw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e5</opc>
     <opr>V W</opr>
@@ -1304,6 +1465,7 @@
 
   <instruction>
     <mnemonic>vpmullw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d5</opc>
     <opr>V W</opr>
@@ -1312,6 +1474,7 @@
 
   <instruction>
     <mnemonic>vpmullw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d5</opc>
     <opr>V H W</opr>
@@ -1320,6 +1483,7 @@
 
   <instruction>
     <mnemonic>vpop</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.W vex.L</pfx>
     <opc>vex.0f a9</opc>
     <opr>GS</opr>
@@ -1328,6 +1492,7 @@
 
   <instruction>
     <mnemonic>vpop</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f a1</opc>
     <opr>FS</opr>
@@ -1336,6 +1501,7 @@
 
   <instruction>
     <mnemonic>vpor</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f eb</opc>
     <opr>V H W</opr>
@@ -1344,6 +1510,7 @@
 
   <instruction>
     <mnemonic>vpor</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f eb</opc>
     <opr>V W</opr>
@@ -1448,6 +1615,7 @@
 
   <instruction>
     <mnemonic>vpsadbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f6</opc>
     <opr>V H W</opr>
@@ -1456,6 +1624,7 @@
 
   <instruction>
     <mnemonic>vpsadbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f6</opc>
     <opr>V W</opr>
@@ -1464,6 +1633,7 @@
 
   <instruction>
     <mnemonic>vpshufw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 70</opc>
     <opr>P Q Ib</opr>
@@ -1472,6 +1642,7 @@
 
   <instruction>
     <mnemonic>vpsllw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f1</opc>
     <opr>V H W</opr>
@@ -1480,6 +1651,7 @@
 
   <instruction>
     <mnemonic>vpsllw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f1</opc>
     <opr>V W</opr>
@@ -1488,6 +1660,7 @@
 
   <instruction>
     <mnemonic>vpsllw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 71 /reg=6</opc>
     <opr>U Ib</opr>
@@ -1496,6 +1669,7 @@
 
   <instruction>
     <mnemonic>vpsllw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 71 /reg=6</opc>
     <opr>N Ib</opr>
@@ -1504,6 +1678,7 @@
 
   <instruction>
     <mnemonic>vpslld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f2</opc>
     <opr>V H W</opr>
@@ -1512,6 +1687,7 @@
 
   <instruction>
     <mnemonic>vpslld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f2</opc>
     <opr>V W</opr>
@@ -1520,6 +1696,7 @@
 
   <instruction>
     <mnemonic>vpslld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 72 /reg=6</opc>
     <opr>U Ib</opr>
@@ -1528,6 +1705,7 @@
 
   <instruction>
     <mnemonic>vpslld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 72 /reg=6</opc>
     <opr>N Ib</opr>
@@ -1536,6 +1714,7 @@
 
   <instruction>
     <mnemonic>vpsllq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f3</opc>
     <opr>V H W</opr>
@@ -1544,6 +1723,7 @@
 
   <instruction>
     <mnemonic>vpsllq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f3</opc>
     <opr>V W</opr>
@@ -1552,6 +1732,7 @@
 
   <instruction>
     <mnemonic>vpsllq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 73 /reg=6</opc>
     <opr>U Ib</opr>
@@ -1560,6 +1741,7 @@
 
   <instruction>
     <mnemonic>vpsllq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 73 /reg=6</opc>
     <opr>N Ib</opr>
@@ -1568,6 +1750,7 @@
 
   <instruction>
     <mnemonic>vpsraw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e1</opc>
     <opr>V W</opr>
@@ -1576,6 +1759,7 @@
 
   <instruction>
     <mnemonic>vpsraw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e1</opc>
     <opr>V H W</opr>
@@ -1584,6 +1768,7 @@
 
   <instruction>
     <mnemonic>vpsraw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 71 /reg=4</opc>
     <opr>U Ib</opr>
@@ -1592,6 +1777,7 @@
 
   <instruction>
     <mnemonic>vpsraw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 71 /reg=4</opc>
     <opr>N Ib</opr>
@@ -1600,6 +1786,7 @@
 
   <instruction>
     <mnemonic>vpsrad</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 72 /reg=4</opc>
     <opr>N Ib</opr>
@@ -1608,6 +1795,7 @@
 
   <instruction>
     <mnemonic>vpsrad</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e2</opc>
     <opr>V H W</opr>
@@ -1616,6 +1804,7 @@
 
   <instruction>
     <mnemonic>vpsrad</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e2</opc>
     <opr>V W</opr>
@@ -1624,6 +1813,7 @@
 
   <instruction>
     <mnemonic>vpsrad</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 72 /reg=4</opc>
     <opr>U Ib</opr>
@@ -1632,6 +1822,7 @@
 
   <instruction>
     <mnemonic>vpsrlw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 71 /reg=2</opc>
     <opr>N Ib</opr>
@@ -1640,6 +1831,7 @@
 
   <instruction>
     <mnemonic>vpsrlw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d1</opc>
     <opr>V W</opr>
@@ -1648,6 +1840,7 @@
 
   <instruction>
     <mnemonic>vpsrlw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d1</opc>
     <opr>V H W</opr>
@@ -1656,6 +1849,7 @@
 
   <instruction>
     <mnemonic>vpsrlw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 71 /reg=2</opc>
     <opr>U Ib</opr>
@@ -1664,6 +1858,7 @@
 
   <instruction>
     <mnemonic>vpsrld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 72 /reg=2</opc>
     <opr>N Ib</opr>
@@ -1672,6 +1867,7 @@
 
   <instruction>
     <mnemonic>vpsrld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d2</opc>
     <opr>V W</opr>
@@ -1680,6 +1876,7 @@
 
   <instruction>
     <mnemonic>vpsrld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d2</opc>
     <opr>V H W</opr>
@@ -1688,6 +1885,7 @@
 
   <instruction>
     <mnemonic>vpsrld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 72 /reg=2</opc>
     <opr>U Ib</opr>
@@ -1696,6 +1894,7 @@
 
   <instruction>
     <mnemonic>vpsrlq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 73 /reg=2</opc>
     <opr>N Ib</opr>
@@ -1704,6 +1903,7 @@
 
   <instruction>
     <mnemonic>vpsrlq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d3</opc>
     <opr>V W</opr>
@@ -1712,6 +1912,7 @@
 
   <instruction>
     <mnemonic>vpsrlq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d3</opc>
     <opr>V H W</opr>
@@ -1720,6 +1921,7 @@
 
   <instruction>
     <mnemonic>vpsrlq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 73 /reg=2</opc>
     <opr>U Ib</opr>
@@ -1728,6 +1930,7 @@
 
   <instruction>
     <mnemonic>vpsubb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f8</opc>
     <opr>V H W</opr>
@@ -1736,6 +1939,7 @@
 
   <instruction>
     <mnemonic>vpsubb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f8</opc>
     <opr>V W</opr>
@@ -1744,6 +1948,7 @@
 
   <instruction>
     <mnemonic>vpsubw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f9</opc>
     <opr>V H W</opr>
@@ -1752,6 +1957,7 @@
 
   <instruction>
     <mnemonic>vpsubw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f9</opc>
     <opr>V W</opr>
@@ -1760,6 +1966,7 @@
 
   <instruction>
     <mnemonic>vpsubd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f fa</opc>
     <opr>V W</opr>
@@ -1768,6 +1975,7 @@
 
   <instruction>
     <mnemonic>vpsubd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f fa</opc>
     <opr>V H W</opr>
@@ -1776,6 +1984,7 @@
 
   <instruction>
     <mnemonic>vpsubsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e8</opc>
     <opr>V W</opr>
@@ -1784,6 +1993,7 @@
 
   <instruction>
     <mnemonic>vpsubsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e8</opc>
     <opr>V H W</opr>
@@ -1792,6 +2002,7 @@
 
   <instruction>
     <mnemonic>vpsubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f e9</opc>
     <opr>V W</opr>
@@ -1800,6 +2011,7 @@
 
   <instruction>
     <mnemonic>vpsubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f e9</opc>
     <opr>V H W</opr>
@@ -1808,6 +2020,7 @@
 
   <instruction>
     <mnemonic>vpsubusb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d8</opc>
     <opr>V W</opr>
@@ -1816,6 +2029,7 @@
 
   <instruction>
     <mnemonic>vpsubusb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d8</opc>
     <opr>V H W</opr>
@@ -1824,6 +2038,7 @@
 
   <instruction>
     <mnemonic>vpsubusw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d9</opc>
     <opr>V W</opr>
@@ -1832,6 +2047,7 @@
 
   <instruction>
     <mnemonic>vpsubusw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d9</opc>
     <opr>V H W</opr>
@@ -1840,6 +2056,7 @@
 
   <instruction>
     <mnemonic>vpunpckhbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 68</opc>
     <opr>V H W</opr>
@@ -1848,6 +2065,7 @@
 
   <instruction>
     <mnemonic>vpunpckhbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 68</opc>
     <opr>V W</opr>
@@ -1856,6 +2074,7 @@
 
   <instruction>
     <mnemonic>vpunpckhwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 69</opc>
     <opr>V H W</opr>
@@ -1864,6 +2083,7 @@
 
   <instruction>
     <mnemonic>vpunpckhwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 69</opc>
     <opr>V W</opr>
@@ -1872,6 +2092,7 @@
 
   <instruction>
     <mnemonic>vpunpckhdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 6a</opc>
     <opr>V H W</opr>
@@ -1880,6 +2101,7 @@
 
   <instruction>
     <mnemonic>vpunpckhdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 6a</opc>
     <opr>V W</opr>
@@ -1888,6 +2110,7 @@
 
   <instruction>
     <mnemonic>vpunpcklbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 60</opc>
     <opr>V H W</opr>
@@ -1896,6 +2119,7 @@
 
   <instruction>
     <mnemonic>vpunpcklbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 60</opc>
     <opr>V W</opr>
@@ -1904,6 +2128,7 @@
 
   <instruction>
     <mnemonic>vpunpcklwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 61</opc>
     <opr>V H W</opr>
@@ -1912,6 +2137,7 @@
 
   <instruction>
     <mnemonic>vpunpcklwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 61</opc>
     <opr>V W</opr>
@@ -1920,6 +2146,7 @@
 
   <instruction>
     <mnemonic>vpunpckldq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 62</opc>
     <opr>V H W</opr>
@@ -1928,6 +2155,7 @@
 
   <instruction>
     <mnemonic>vpunpckldq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 62</opc>
     <opr>V W</opr>
@@ -1952,6 +2180,7 @@
 
   <instruction>
     <mnemonic>vpxor</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f ef</opc>
     <opr>V H W</opr>
@@ -1960,6 +2189,7 @@
 
   <instruction>
     <mnemonic>vpxor</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f ef</opc>
     <opr>V W</opr>
@@ -1968,6 +2198,7 @@
 
   <instruction>
     <mnemonic>vrcpps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 53</opc>
     <opr>V H W</opr>
@@ -1976,6 +2207,7 @@
 
   <instruction>
     <mnemonic>vrcpss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 53</opc>
     <opr>V H W</opr>
@@ -1984,6 +2216,7 @@
 
   <instruction>
     <mnemonic>vrsqrtps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 52</opc>
     <opr>V H W</opr>
@@ -1992,6 +2225,7 @@
 
   <instruction>
     <mnemonic>vrsqrtss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 52</opc>
     <opr>V H W</opr>
@@ -2000,6 +2234,7 @@
 
   <instruction>
     <mnemonic>vshufpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f c6</opc>
     <opr>V W Ib</opr>
@@ -2008,6 +2243,7 @@
 
   <instruction>
     <mnemonic>vshufps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f c6</opc>
     <opr>V W Ib</opr>
@@ -2016,6 +2252,7 @@
 
   <instruction>
     <mnemonic>vsqrtps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 51</opc>
     <opr>V H W</opr>
@@ -2024,6 +2261,7 @@
 
   <instruction>
     <mnemonic>vsqrtpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 51</opc>
     <opr>V H W</opr>
@@ -2032,6 +2270,7 @@
 
   <instruction>
     <mnemonic>vsqrtsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 51</opc>
     <opr>V H W</opr>
@@ -2040,6 +2279,7 @@
 
   <instruction>
     <mnemonic>vsqrtss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 51</opc>
     <opr>V H W</opr>
@@ -2048,6 +2288,7 @@
 
   <instruction>
     <mnemonic>vsubpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 5c</opc>
     <opr>V H W</opr>
@@ -2056,6 +2297,7 @@
 
   <instruction>
     <mnemonic>vsubps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 5c</opc>
     <opr>V H W</opr>
@@ -2064,6 +2306,7 @@
 
   <instruction>
     <mnemonic>vsubsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f20f 5c</opc>
     <opr>V H W</opr>
@@ -2072,6 +2315,7 @@
 
   <instruction>
     <mnemonic>vsubss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.f30f 5c</opc>
     <opr>V H W</opr>
@@ -2096,6 +2340,7 @@
 
   <instruction>
     <mnemonic>vunpckhpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 15</opc>
     <opr>V H W</opr>
@@ -2104,6 +2349,7 @@
 
   <instruction>
     <mnemonic>vunpckhps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 15</opc>
     <opr>V H W</opr>
@@ -2112,6 +2358,7 @@
 
   <instruction>
     <mnemonic>vunpcklps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 14</opc>
     <opr>V H W</opr>
@@ -2120,6 +2367,7 @@
 
   <instruction>
     <mnemonic>vunpcklpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 14</opc>
     <opr>V H W</opr>
@@ -2128,6 +2376,7 @@
 
   <instruction>
     <mnemonic>vxorpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 57</opc>
     <opr>V H W</opr>
@@ -2136,6 +2385,7 @@
 
   <instruction>
     <mnemonic>vxorps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f 57</opc>
     <opr>V H W</opr>
@@ -2144,6 +2394,7 @@
 
   <instruction>
     <mnemonic>vmovdqa</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 7f</opc>
     <opr>W H V</opr>
@@ -2152,6 +2403,7 @@
 
   <instruction>
     <mnemonic>vmovdqa</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 6f</opc>
     <opr>V H W</opr>
@@ -2160,6 +2412,7 @@
 
   <instruction>
     <mnemonic>vmovdq2q</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f d6</opc>
     <opr>P U</opr>
@@ -2168,6 +2421,7 @@
 
   <instruction>
     <mnemonic>vmovdqu</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 6f</opc>
     <opr>V H W</opr>
@@ -2176,6 +2430,7 @@
 
   <instruction>
     <mnemonic>vmovdqu</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 7f</opc>
     <opr>W H V</opr>
@@ -2184,6 +2439,7 @@
 
   <instruction>
     <mnemonic>vmovq2dq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f d6</opc>
     <opr>V N</opr>
@@ -2192,6 +2448,7 @@
 
   <instruction>
     <mnemonic>vpaddq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f d4</opc>
     <opr>V W</opr>
@@ -2200,6 +2457,7 @@
 
   <instruction>
     <mnemonic>vpaddq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d4</opc>
     <opr>V H W</opr>
@@ -2208,6 +2466,7 @@
 
   <instruction>
     <mnemonic>vpsubq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f fb</opc>
     <opr>V H W</opr>
@@ -2216,6 +2475,7 @@
 
   <instruction>
     <mnemonic>vpsubq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f fb</opc>
     <opr>V W</opr>
@@ -2224,6 +2484,7 @@
 
   <instruction>
     <mnemonic>vpmuludq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f f4</opc>
     <opr>V W</opr>
@@ -2232,6 +2493,7 @@
 
   <instruction>
     <mnemonic>vpmuludq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f f4</opc>
     <opr>V H W</opr>
@@ -2240,6 +2502,7 @@
 
   <instruction>
     <mnemonic>vpshufhw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 70</opc>
     <opr>V W Ib</opr>
@@ -2248,6 +2511,7 @@
 
   <instruction>
     <mnemonic>vpshuflw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f 70</opc>
     <opr>V W Ib</opr>
@@ -2256,6 +2520,7 @@
 
   <instruction>
     <mnemonic>vpshufd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 70</opc>
     <opr>V W Ib</opr>
@@ -2264,6 +2529,7 @@
 
   <instruction>
     <mnemonic>vpslldq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 73 /reg=7</opc>
     <opr>U Ib</opr>
@@ -2272,6 +2538,7 @@
 
   <instruction>
     <mnemonic>vpsrldq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 73 /reg=3</opc>
     <opr>U Ib</opr>
@@ -2280,6 +2547,7 @@
 
   <instruction>
     <mnemonic>vpunpckhqdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 6d</opc>
     <opr>V H W</opr>
@@ -2288,6 +2556,7 @@
 
   <instruction>
     <mnemonic>vpunpcklqdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 6c</opc>
     <opr>V H W</opr>
@@ -2296,6 +2565,7 @@
 
   <instruction>
     <mnemonic>vaddsubpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f d0</opc>
     <opr>V H W</opr>
@@ -2304,6 +2574,7 @@
 
   <instruction>
     <mnemonic>vaddsubps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f d0</opc>
     <opr>V H W</opr>
@@ -2312,6 +2583,7 @@
 
   <instruction>
     <mnemonic>vhaddpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 7c</opc>
     <opr>V H W</opr>
@@ -2320,6 +2592,7 @@
 
   <instruction>
     <mnemonic>vhaddps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f 7c</opc>
     <opr>V H W</opr>
@@ -2328,6 +2601,7 @@
 
   <instruction>
     <mnemonic>vhsubpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f 7d</opc>
     <opr>V H W</opr>
@@ -2336,6 +2610,7 @@
 
   <instruction>
     <mnemonic>vhsubps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f 7d</opc>
     <opr>V H W</opr>
@@ -2344,6 +2619,7 @@
 
   <instruction>
     <mnemonic>vmovddup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f 12 /mod=11</opc>
     <opr>V H W</opr>
@@ -2352,6 +2628,7 @@
 
   <instruction>
     <mnemonic>vmovddup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f20f 12 /mod=!11</opc>
     <opr>V H W</opr>
@@ -2360,6 +2637,7 @@
 
   <instruction>
     <mnemonic>vmovshdup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 16 /mod=11</opc>
     <opr>V H W</opr>
@@ -2368,6 +2646,7 @@
 
   <instruction>
     <mnemonic>vmovshdup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 16 /mod=!11</opc>
     <opr>V H W</opr>
@@ -2376,6 +2655,7 @@
 
   <instruction>
     <mnemonic>vmovsldup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 12 /mod=11</opc>
     <opr>V H W</opr>
@@ -2384,6 +2664,7 @@
 
   <instruction>
     <mnemonic>vmovsldup</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.f30f 12 /mod=!11</opc>
     <opr>V H W</opr>
@@ -2392,6 +2673,7 @@
 
   <instruction>
     <mnemonic>vpabsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 1c</opc>
     <opr>V W</opr>
@@ -2400,6 +2682,7 @@
 
   <instruction>
     <mnemonic>vpabsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 1c</opc>
     <opr>V H W</opr>
@@ -2408,6 +2691,7 @@
 
   <instruction>
     <mnemonic>vpabsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 1d</opc>
     <opr>V W</opr>
@@ -2416,6 +2700,7 @@
 
   <instruction>
     <mnemonic>vpabsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 1d</opc>
     <opr>V H W</opr>
@@ -2424,6 +2709,7 @@
 
   <instruction>
     <mnemonic>vpabsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.0f38 1e</opc>
     <opr>V W</opr>
@@ -2432,6 +2718,7 @@
 
   <instruction>
     <mnemonic>vpabsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.660f38 1e</opc>
     <opr>V H W</opr>
@@ -2440,6 +2727,7 @@
 
   <instruction>
     <mnemonic>vpsignb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 00</opc>
     <opr>V W</opr>
@@ -2448,6 +2736,7 @@
 
   <instruction>
     <mnemonic>vpsignb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 00</opc>
     <opr>V H W</opr>
@@ -2456,6 +2745,7 @@
 
   <instruction>
     <mnemonic>vphaddw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 01</opc>
     <opr>V W</opr>
@@ -2464,6 +2754,7 @@
 
   <instruction>
     <mnemonic>vphaddw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 01</opc>
     <opr>V H W</opr>
@@ -2472,6 +2763,7 @@
 
   <instruction>
     <mnemonic>vphaddd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 02</opc>
     <opr>V W</opr>
@@ -2480,6 +2772,7 @@
 
   <instruction>
     <mnemonic>vphaddd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 02</opc>
     <opr>V H W</opr>
@@ -2488,6 +2781,7 @@
 
   <instruction>
     <mnemonic>vphaddsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 03</opc>
     <opr>V W</opr>
@@ -2496,6 +2790,7 @@
 
   <instruction>
     <mnemonic>vphaddsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 03</opc>
     <opr>V H W</opr>
@@ -2504,6 +2799,7 @@
 
   <instruction>
     <mnemonic>vpmaddubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 04</opc>
     <opr>V W</opr>
@@ -2512,6 +2808,7 @@
 
   <instruction>
     <mnemonic>vpmaddubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 04</opc>
     <opr>V H W</opr>
@@ -2520,6 +2817,7 @@
 
   <instruction>
     <mnemonic>vphsubw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 05</opc>
     <opr>V W</opr>
@@ -2528,6 +2826,7 @@
 
   <instruction>
     <mnemonic>vphsubw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 05</opc>
     <opr>V H W</opr>
@@ -2536,6 +2835,7 @@
 
   <instruction>
     <mnemonic>vphsubd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 06</opc>
     <opr>V W</opr>
@@ -2544,6 +2844,7 @@
 
   <instruction>
     <mnemonic>vphsubd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 06</opc>
     <opr>V H W</opr>
@@ -2552,6 +2853,7 @@
 
   <instruction>
     <mnemonic>vphsubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 07</opc>
     <opr>V W</opr>
@@ -2560,6 +2862,7 @@
 
   <instruction>
     <mnemonic>vphsubsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 07</opc>
     <opr>V H W</opr>
@@ -2568,6 +2871,7 @@
 
   <instruction>
     <mnemonic>vpsignb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 08</opc>
     <opr>V W</opr>
@@ -2576,6 +2880,7 @@
 
   <instruction>
     <mnemonic>vpsignb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 08</opc>
     <opr>V H W</opr>
@@ -2584,6 +2889,7 @@
 
   <instruction>
     <mnemonic>vpsignd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 0a</opc>
     <opr>V W</opr>
@@ -2592,6 +2898,7 @@
 
   <instruction>
     <mnemonic>vpsignd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 0a</opc>
     <opr>V H W</opr>
@@ -2600,6 +2907,7 @@
 
   <instruction>
     <mnemonic>vpsignw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 09</opc>
     <opr>V W</opr>
@@ -2608,6 +2916,7 @@
 
   <instruction>
     <mnemonic>vpsignw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 09</opc>
     <opr>V H W</opr>
@@ -2616,6 +2925,7 @@
 
   <instruction>
     <mnemonic>vpmulhrsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f38 0b</opc>
     <opr>V W</opr>
@@ -2624,6 +2934,7 @@
 
   <instruction>
     <mnemonic>vpmulhrsw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 0b</opc>
     <opr>V H W</opr>
@@ -2632,6 +2943,7 @@
 
   <instruction>
     <mnemonic>vpalignr</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.0f3a 0f</opc>
     <opr>P Q Ib</opr>
@@ -2640,6 +2952,7 @@
 
   <instruction>
     <mnemonic>vpalignr</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 0f</opc>
     <opr>V W Ib</opr>
@@ -2648,6 +2961,7 @@
 
   <instruction>
     <mnemonic>vpblendvb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 10</opc>
     <opr>V H W</opr>
@@ -2656,6 +2970,7 @@
 
   <instruction>
     <mnemonic>vpmuldq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 28</opc>
     <opr>V H W</opr>
@@ -2664,6 +2979,7 @@
 
   <instruction>
     <mnemonic>vpminsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 38</opc>
     <opr>V H W</opr>
@@ -2672,6 +2988,7 @@
 
   <instruction>
     <mnemonic>vpminsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.660f38 39</opc>
     <opr>V H W</opr>
@@ -2680,6 +2997,7 @@
 
   <instruction>
     <mnemonic>vpminuw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 3a</opc>
     <opr>V H W</opr>
@@ -2688,6 +3006,7 @@
 
   <instruction>
     <mnemonic>vpminud</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 3b</opc>
     <opr>V H W</opr>
@@ -2696,6 +3015,7 @@
 
   <instruction>
     <mnemonic>vpmaxsb</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 3c</opc>
     <opr>V H W</opr>
@@ -2704,6 +3024,7 @@
 
   <instruction>
     <mnemonic>vpmaxsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.660f38 3d</opc>
     <opr>V H W</opr>
@@ -2712,6 +3033,7 @@
 
   <instruction>
     <mnemonic>vpmaxud</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 3f</opc>
     <opr>V H W</opr>
@@ -2720,6 +3042,7 @@
 
   <instruction>
     <mnemonic>vpmaxuw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 3e</opc>
     <opr>V H W</opr>
@@ -2728,6 +3051,7 @@
 
   <instruction>
     <mnemonic>vpmulld</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 40</opc>
     <opr>V H W</opr>
@@ -2736,6 +3060,7 @@
 
   <instruction>
     <mnemonic>vphminposuw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 41</opc>
     <opr>V H W</opr>
@@ -2744,6 +3069,7 @@
 
   <instruction>
     <mnemonic>vroundps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 08</opc>
     <opr>V W Ib</opr>
@@ -2752,6 +3078,7 @@
 
   <instruction>
     <mnemonic>vroundpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 09</opc>
     <opr>V W Ib</opr>
@@ -2760,6 +3087,7 @@
 
   <instruction>
     <mnemonic>vroundss</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.660f3a 0a</opc>
     <opr>V W Ib</opr>
@@ -2768,6 +3096,7 @@
 
   <instruction>
     <mnemonic>vroundsd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx></pfx>
     <opc>vex.660f3a 0b</opc>
     <opr>V W Ib</opr>
@@ -2776,6 +3105,7 @@
 
   <instruction>
     <mnemonic>vblendpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 0d</opc>
     <opr>V W Ib</opr>
@@ -2784,6 +3114,7 @@
 
   <instruction>
     <mnemonic>vpblendw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 0e</opc>
     <opr>V W Ib</opr>
@@ -2792,6 +3123,7 @@
 
   <instruction>
     <mnemonic>vblendps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 0c</opc>
     <opr>V W Ib</opr>
@@ -2800,6 +3132,7 @@
 
   <instruction>
     <mnemonic>vblendvpd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 15</opc>
     <opr>V H W</opr>
@@ -2808,6 +3141,7 @@
 
   <instruction>
     <mnemonic>vblendvps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 14</opc>
     <opr>V H W</opr>
@@ -2816,6 +3150,7 @@
 
   <instruction>
     <mnemonic>vdpps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 40</opc>
     <opr>V W Ib</opr>
@@ -2824,6 +3159,7 @@
 
   <instruction>
     <mnemonic>vdppd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 41</opc>
     <opr>V W Ib</opr>
@@ -2832,6 +3168,7 @@
 
   <instruction>
     <mnemonic>vmpsadbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 42</opc>
     <opr>V W Ib</opr>
@@ -2840,6 +3177,7 @@
 
   <instruction>
     <mnemonic>vextractps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.W vex.L</pfx>
     <opc>vex.660f3a 17</opc>
     <opr>MdRy V Ib</opr>
@@ -2848,6 +3186,7 @@
 
   <instruction>
     <mnemonic>vinsertps</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f3a 21</opc>
     <opr>V Md Ib</opr>
@@ -2856,6 +3195,7 @@
 
   <instruction>
     <mnemonic>vmovntdqa</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 2a</opc>
     <opr>V Mo</opr>
@@ -2864,6 +3204,7 @@
 
   <instruction>
     <mnemonic>vpackusdw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 2b</opc>
     <opr>V H W</opr>
@@ -2872,6 +3213,7 @@
 
   <instruction>
     <mnemonic>vpmovsxbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 20</opc>
     <opr>V MqU</opr>
@@ -2880,6 +3222,7 @@
 
   <instruction>
     <mnemonic>vpmovsxbd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 21</opc>
     <opr>V MdU</opr>
@@ -2888,6 +3231,7 @@
 
   <instruction>
     <mnemonic>vpmovsxbq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 22</opc>
     <opr>V MwU</opr>
@@ -2896,6 +3240,7 @@
 
   <instruction>
     <mnemonic>vpmovsxwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 23</opc>
     <opr>V MqU</opr>
@@ -2904,6 +3249,7 @@
 
   <instruction>
     <mnemonic>vpmovsxwq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 24</opc>
     <opr>V MdU</opr>
@@ -2912,6 +3258,7 @@
 
   <instruction>
     <mnemonic>vpmovsxdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 25</opc>
     <opr>V MqU</opr>
@@ -2920,6 +3267,7 @@
 
   <instruction>
     <mnemonic>vpmovzxbw</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 30</opc>
     <opr>V MqU</opr>
@@ -2928,6 +3276,7 @@
 
   <instruction>
     <mnemonic>vpmovzxbd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 31</opc>
     <opr>V MdU</opr>
@@ -2936,6 +3285,7 @@
 
   <instruction>
     <mnemonic>vpmovzxbq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 32</opc>
     <opr>V MwU</opr>
@@ -2944,6 +3294,7 @@
 
   <instruction>
     <mnemonic>vpmovzxwd</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 33</opc>
     <opr>V MqU</opr>
@@ -2952,6 +3303,7 @@
 
   <instruction>
     <mnemonic>vpmovzxwq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 34</opc>
     <opr>V MdU</opr>
@@ -2960,6 +3312,7 @@
 
   <instruction>
     <mnemonic>vpmovzxdq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>aso vex.L</pfx>
     <opc>vex.660f38 35</opc>
     <opr>V MqU</opr>
@@ -2968,6 +3321,7 @@
 
   <instruction>
     <mnemonic>vpcmpeqq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 29</opc>
     <opr>V H W</opr>
@@ -2984,6 +3338,7 @@
 
   <instruction>
     <mnemonic>vpcmpestri</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 61</opc>
     <opr>V W Ib</opr>
@@ -2992,6 +3347,7 @@
 
   <instruction>
     <mnemonic>vpcmpestrm</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 60</opc>
     <opr>V W Ib</opr>
@@ -3000,6 +3356,7 @@
 
   <instruction>
     <mnemonic>vpcmpgtq</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f38 37</opc>
     <opr>V H W</opr>
@@ -3008,6 +3365,7 @@
 
   <instruction>
     <mnemonic>vpcmpistri</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 63</opc>
     <opr>V W Ib</opr>
@@ -3016,6 +3374,7 @@
 
   <instruction>
     <mnemonic>vpcmpistrm</mnemonic>
+    <first_operand_access>W</first_operand_access>
     <pfx>vex.L</pfx>
     <opc>vex.660f3a 62</opc>
     <opr>V W Ib</opr>
diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index ca9639b..1120753 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -122,6 +122,8 @@
     <instruction>
         <mnemonic>aaa</mnemonic>
         <eflags>UUUMUM_____</eflags>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
         <def>
             <opc>37 /m=!64</opc>
         </def>
@@ -129,6 +131,8 @@
 
     <instruction>
         <mnemonic>aad</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_def>ax</implicit_register_def>
         <eflags>UMMUMU_____</eflags>
         <def>
             <opc>d5 /m=!64</opc>
@@ -138,6 +142,8 @@
 
     <instruction>
         <mnemonic>aam</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_def>ax</implicit_register_def>
         <eflags>UMMUMU_____</eflags>
         <def>
             <opc>d4 /m=!64</opc>
@@ -147,6 +153,8 @@
 
     <instruction>
         <mnemonic>aas</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
         <eflags>UUUMUM_____</eflags>
         <def>
             <opc>3f /m=!64</opc>
@@ -155,6 +163,7 @@
 
     <instruction>
         <mnemonic>adc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -210,6 +219,7 @@
 
     <instruction>
         <mnemonic>add</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -265,6 +275,7 @@
 
     <instruction>
         <mnemonic>addpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 58</opc>
@@ -275,6 +286,7 @@
 
     <instruction>
         <mnemonic>addps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 58</opc>
@@ -285,6 +297,7 @@
 
     <instruction>
         <mnemonic>addsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 58</opc>
@@ -295,6 +308,7 @@
 
     <instruction>
         <mnemonic>addss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 58</opc>
@@ -305,6 +319,7 @@
 
     <instruction>
         <mnemonic>addsubpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f d0</opc>
@@ -315,6 +330,7 @@
 
     <instruction>
         <mnemonic>addsubps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f d0</opc>
@@ -325,6 +341,7 @@
 
     <instruction>
         <mnemonic>aesdec</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 de</opc>
@@ -335,6 +352,7 @@
 
     <instruction>
         <mnemonic>aesdeclast</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 df</opc>
@@ -345,6 +363,7 @@
 
     <instruction>
         <mnemonic>aesenc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <cpuid>aesni</cpuid>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -356,6 +375,7 @@
 
     <instruction>
         <mnemonic>aesenclast</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <cpuid>aesni avx</cpuid>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -366,6 +386,7 @@
 
     <instruction>
         <mnemonic>aesimc</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 db</opc>
@@ -376,6 +397,7 @@
 
     <instruction>
         <mnemonic>aeskeygenassist</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a df</opc>
@@ -386,6 +408,7 @@
 
     <instruction>
         <mnemonic>and</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -441,6 +464,7 @@
 
     <instruction>
         <mnemonic>andpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 54</opc>
@@ -451,6 +475,7 @@
 
     <instruction>
         <mnemonic>andps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 54</opc>
@@ -461,6 +486,7 @@
 
     <instruction>
         <mnemonic>andnpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 55</opc>
@@ -471,6 +497,7 @@
 
     <instruction>
         <mnemonic>andnps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 55</opc>
@@ -481,6 +508,7 @@
 
     <instruction>
         <mnemonic>arpl</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>__M________</eflags>
         <def>
             <pfx>aso</pfx>
@@ -491,6 +519,7 @@
 
     <instruction>
         <mnemonic>movsxd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso oso rexw rexx rexr rexb</pfx>
             <opc>63 /m=64</opc>
@@ -500,6 +529,9 @@
 
     <instruction>
         <mnemonic>call</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -532,6 +564,8 @@
 
     <instruction>
         <mnemonic>cbw</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_def>ax</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
@@ -541,6 +575,8 @@
 
     <instruction>
         <mnemonic>cwde</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
         <def>
             <pfx>oso rexw</pfx>
             <opc>98 /o=32</opc>
@@ -549,6 +585,8 @@
 
     <instruction>
         <mnemonic>cdqe</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
         <def>
             <pfx>oso rexw</pfx>
             <opc>98 /o=64</opc>
@@ -573,6 +611,7 @@
 
     <instruction>
         <mnemonic>clflush</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f ae /reg=7 /mod=!11</opc>
@@ -598,6 +637,8 @@
 
     <instruction>
         <mnemonic>clts</mnemonic>
+        <implicit_register_use>cr0</implicit_register_use>
+        <implicit_register_def>cr0</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>0f 06</opc>
@@ -614,6 +655,7 @@
 
     <instruction>
         <mnemonic>cmovo</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -624,6 +666,7 @@
 
     <instruction>
         <mnemonic>cmovno</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -634,6 +677,7 @@
 
     <instruction>
         <mnemonic>cmovb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -644,6 +688,7 @@
 
     <instruction>
         <mnemonic>cmovae</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -654,6 +699,7 @@
 
     <instruction>
         <mnemonic>cmovz</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -664,6 +710,7 @@
 
     <instruction>
         <mnemonic>cmovnz</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -674,6 +721,7 @@
 
     <instruction>
         <mnemonic>cmovbe</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -684,6 +732,7 @@
 
     <instruction>
         <mnemonic>cmova</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -694,6 +743,7 @@
 
     <instruction>
         <mnemonic>cmovs</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -704,6 +754,7 @@
 
     <instruction>
         <mnemonic>cmovns</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -714,6 +765,7 @@
 
     <instruction>
         <mnemonic>cmovp</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -724,6 +776,7 @@
 
     <instruction>
         <mnemonic>cmovnp</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -734,6 +787,7 @@
 
     <instruction>
         <mnemonic>cmovl</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -744,6 +798,7 @@
 
     <instruction>
         <mnemonic>cmovge</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -754,6 +809,7 @@
 
     <instruction>
         <mnemonic>cmovle</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -764,6 +820,7 @@
 
     <instruction>
         <mnemonic>cmovg</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -829,6 +886,7 @@
 
     <instruction>
         <mnemonic>cmppd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
@@ -840,6 +898,7 @@
 
     <instruction>
         <mnemonic>cmpps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
@@ -851,6 +910,10 @@
 
     <instruction>
         <mnemonic>cmpsb</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz seg</pfx>
@@ -860,6 +923,10 @@
 
     <instruction>
         <mnemonic>cmpsw</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw seg</pfx>
@@ -871,10 +938,15 @@
         <mnemonic>cmpsd</mnemonic>
         <eflags>MMMMMM_____</eflags>
         <def>
+            <implicit_register_use>rsi</implicit_register_use>
+            <implicit_register_use>rdi</implicit_register_use>
+            <implicit_register_def>rsi</implicit_register_def>
+            <implicit_register_def>rdi</implicit_register_def>
             <pfx>repz oso rexw seg</pfx>
             <opc>a7 /o=32</opc>
         </def>
         <def>
+            <first_operand_access>RW</first_operand_access>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f c2</opc>
             <opr>V H W Ib</opr>
@@ -884,6 +956,10 @@
 
     <instruction>
         <mnemonic>cmpsq</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw seg</pfx>
@@ -893,6 +969,7 @@
 
     <instruction>
         <mnemonic>cmpss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -904,6 +981,9 @@
 
     <instruction>
         <mnemonic>cmpxchg</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -919,6 +999,11 @@
 
     <instruction>
         <mnemonic>cmpxchg8b</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_use>rdx</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
+        <implicit_register_def>rdx</implicit_register_def>
+        <first_operand_access>RW</first_operand_access>
         <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -934,6 +1019,11 @@
 
     <instruction>
         <mnemonic>cmpxchg16b</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_use>rdx</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
+        <implicit_register_def>rdx</implicit_register_def>
+        <first_operand_access>RW</first_operand_access>
         <eflags>__M________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -966,6 +1056,11 @@
 
     <instruction>
         <mnemonic>cpuid</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>ebx</implicit_register_def>
+        <implicit_register_def>ecx</implicit_register_def>
+        <implicit_register_def>edx</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>0f a2</opc>
@@ -974,6 +1069,7 @@
 
     <instruction>
         <mnemonic>cvtdq2pd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f3 0f e6</opc>
@@ -984,6 +1080,7 @@
 
     <instruction>
         <mnemonic>cvtdq2ps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 5b</opc>
@@ -994,6 +1091,7 @@
 
     <instruction>
         <mnemonic>cvtpd2dq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f2 0f e6</opc>
@@ -1004,6 +1102,7 @@
 
     <instruction>
         <mnemonic>cvtpd2pi</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 2d</opc>
@@ -1013,6 +1112,7 @@
 
     <instruction>
         <mnemonic>cvtpd2ps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5a</opc>
@@ -1023,6 +1123,7 @@
 
     <instruction>
         <mnemonic>cvtpi2ps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 2a</opc>
@@ -1032,6 +1133,7 @@
 
     <instruction>
         <mnemonic>cvtpi2pd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 2a</opc>
@@ -1041,6 +1143,7 @@
 
     <instruction>
         <mnemonic>cvtps2dq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5b</opc>
@@ -1051,6 +1154,7 @@
 
     <instruction>
         <mnemonic>cvtps2pd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 5a</opc>
@@ -1061,6 +1165,7 @@
 
     <instruction>
         <mnemonic>cvtps2pi</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 2d</opc>
@@ -1070,6 +1175,7 @@
 
     <instruction>
         <mnemonic>cvtsd2si</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 2d</opc>
@@ -1080,6 +1186,7 @@
 
     <instruction>
         <mnemonic>cvtsd2ss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 5a</opc>
@@ -1090,6 +1197,7 @@
 
     <instruction>
         <mnemonic>cvtsi2sd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 2a</opc>
@@ -1100,6 +1208,7 @@
 
     <instruction>
         <mnemonic>cvtsi2ss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 2a</opc>
@@ -1110,6 +1219,7 @@
 
     <instruction>
         <mnemonic>cvtss2sd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 5a</opc>
@@ -1120,6 +1230,7 @@
 
     <instruction>
         <mnemonic>cvtss2si</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 2d</opc>
@@ -1130,6 +1241,7 @@
 
     <instruction>
         <mnemonic>cvttpd2dq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f e6</opc>
@@ -1140,6 +1252,7 @@
 
     <instruction>
         <mnemonic>cvttpd2pi</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 2c</opc>
@@ -1149,6 +1262,7 @@
 
     <instruction>
         <mnemonic>cvttps2dq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f3 0f 5b</opc>
@@ -1159,6 +1273,7 @@
 
     <instruction>
         <mnemonic>cvttps2pi</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 2c</opc>
@@ -1168,6 +1283,7 @@
 
     <instruction>
         <mnemonic>cvttsd2si</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 2c</opc>
@@ -1178,6 +1294,7 @@
 
     <instruction>
         <mnemonic>cvttss2si</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 2c</opc>
@@ -1188,6 +1305,9 @@
 
     <instruction>
         <mnemonic>cwd</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_def>ax</implicit_register_def>
+        <implicit_register_def>dx</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
@@ -1197,6 +1317,9 @@
 
     <instruction>
         <mnemonic>cdq</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>edx</implicit_register_def>
         <def>
             <pfx>oso rexw</pfx>
             <opc>99 /o=32</opc>
@@ -1205,6 +1328,9 @@
 
     <instruction>
         <mnemonic>cqo</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
+        <implicit_register_def>rdx</implicit_register_def>
         <def>
             <pfx>oso rexw</pfx>
             <opc>99 /o=64</opc>
@@ -1213,6 +1339,8 @@
 
     <instruction>
         <mnemonic>daa</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
         <eflags>UMMMMM_____</eflags>
         <def>
             <opc>27 /m=!64</opc>
@@ -1222,6 +1350,8 @@
 
     <instruction>
         <mnemonic>das</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
         <eflags>UMMMMM_____</eflags>
         <def>
             <opc>2f /m=!64</opc>
@@ -1231,6 +1361,7 @@
 
     <instruction>
         <mnemonic>dec</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>oso</pfx>
@@ -1286,13 +1417,20 @@
 
     <instruction>
         <mnemonic>div</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>UUUUUU_____</eflags>
         <def>
+            <implicit_register_use>ax</implicit_register_use>
+            <implicit_register_use>dx</implicit_register_use>
+            <implicit_register_def>ax</implicit_register_def>
+            <implicit_register_def>dx</implicit_register_def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=6</opc>
             <opr>Ev</opr>
         </def>
         <def>
+            <implicit_register_use>ax</implicit_register_use>
+            <implicit_register_def>ax</implicit_register_def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=6</opc>
             <opr>Eb</opr>
@@ -1301,6 +1439,7 @@
 
     <instruction>
         <mnemonic>divpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5e</opc>
@@ -1311,6 +1450,7 @@
 
     <instruction>
         <mnemonic>divps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 5e</opc>
@@ -1321,6 +1461,7 @@
 
     <instruction>
         <mnemonic>divsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 5e</opc>
@@ -1331,6 +1472,7 @@
 
     <instruction>
         <mnemonic>divss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 5e</opc>
@@ -1341,6 +1483,7 @@
 
     <instruction>
         <mnemonic>dppd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 41</opc>
@@ -1351,6 +1494,7 @@
 
     <instruction>
         <mnemonic>dpps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 3a 40</opc>
@@ -1378,6 +1522,7 @@
 
     <instruction>
         <mnemonic>extractps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 3a 17</opc>
@@ -1388,6 +1533,8 @@
 
     <instruction>
         <mnemonic>f2xm1</mnemonic>
+        <implicit_register_use>st0</implicit_register_use>
+        <implicit_register_def>st0</implicit_register_def>
         <cpuid>X87</cpuid>
         <def>
             <opc>d9 /mod=11 /x87=30</opc>
@@ -1396,6 +1543,8 @@
 
     <instruction>
         <mnemonic>fabs</mnemonic>
+        <implicit_register_use>st0</implicit_register_use>
+        <implicit_register_def>st0</implicit_register_def>
         <cpuid>X87</cpuid>
         <def>
             <opc>d9 /mod=11 /x87=21</opc>
@@ -3849,11 +3998,17 @@
         <mnemonic>idiv</mnemonic>
         <eflags>UUUUUU_____</eflags>
         <def>
+            <implicit_register_use>rax</implicit_register_use>
+            <implicit_register_use>rdx</implicit_register_use>
+            <implicit_register_def>rax</implicit_register_def>
+            <implicit_register_def>rdx</implicit_register_def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=7</opc>
             <opr>Ev</opr>
         </def>
         <def>
+            <implicit_register_use>rax</implicit_register_use>
+            <implicit_register_def>rax</implicit_register_def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=7</opc>
             <opr>Eb</opr>
@@ -3862,6 +4017,7 @@
 
     <instruction>
         <mnemonic>in</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <opc>e4</opc>
@@ -3885,6 +4041,7 @@
 
     <instruction>
         <mnemonic>imul</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -3892,11 +4049,16 @@
             <opr>Gv Ev</opr>
         </def>
         <def>
+            <implicit_register_use>al</implicit_register_use>
+            <implicit_register_def>ax</implicit_register_def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=5</opc>
             <opr>Eb</opr>
         </def>
         <def>
+            <implicit_register_use>rax</implicit_register_use>
+            <implicit_register_def>rax</implicit_register_def>
+            <implicit_register_def>rdx</implicit_register_def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=5</opc>
             <opr>Ev</opr>
@@ -3915,6 +4077,7 @@
 
     <instruction>
         <mnemonic>inc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMM______</eflags>
         <def>
             <pfx>oso</pfx>
@@ -3970,6 +4133,9 @@
 
     <instruction>
         <mnemonic>insb</mnemonic>
+        <implicit_register_use>dx</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -3979,6 +4145,9 @@
 
     <instruction>
         <mnemonic>insw</mnemonic>
+        <implicit_register_use>dx</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
@@ -3988,6 +4157,9 @@
 
     <instruction>
         <mnemonic>insd</mnemonic>
+        <implicit_register_use>dx</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
@@ -4110,6 +4282,7 @@
 
     <instruction>
         <mnemonic>jo</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>T__________</eflags>
         <def>
             <opc>70</opc>
@@ -4125,6 +4298,7 @@
 
     <instruction>
         <mnemonic>jno</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>T__________</eflags>
         <def>
             <opc>71</opc>
@@ -4140,6 +4314,7 @@
 
     <instruction>
         <mnemonic>jb</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>_____T_____</eflags>
         <def>
             <opc>72</opc>
@@ -4155,6 +4330,7 @@
 
     <instruction>
         <mnemonic>jae</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>_____T_____</eflags>
         <def>
             <opc>73</opc>
@@ -4170,6 +4346,7 @@
 
     <instruction>
         <mnemonic>jz</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>__T________</eflags>
         <def>
             <opc>74</opc>
@@ -4185,6 +4362,7 @@
 
     <instruction>
         <mnemonic>jnz</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>__T________</eflags>
         <def>
             <opc>75</opc>
@@ -4200,6 +4378,7 @@
 
     <instruction>
         <mnemonic>jbe</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>__T__T_____</eflags>
         <def>
             <opc>76</opc>
@@ -4215,6 +4394,7 @@
 
     <instruction>
         <mnemonic>ja</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>__T__T_____</eflags>
         <def>
             <opc>77</opc>
@@ -4230,6 +4410,7 @@
 
     <instruction>
         <mnemonic>js</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>_T_________</eflags>
         <def>
             <opc>78</opc>
@@ -4245,6 +4426,7 @@
 
     <instruction>
         <mnemonic>jns</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>_T_________</eflags>
         <def>
             <opc>79</opc>
@@ -4260,6 +4442,7 @@
 
     <instruction>
         <mnemonic>jp</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>____T______</eflags>
         <def>
             <opc>7a</opc>
@@ -4275,6 +4458,7 @@
 
     <instruction>
         <mnemonic>jnp</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>____T______</eflags>
         <def>
             <opc>7b</opc>
@@ -4290,6 +4474,7 @@
 
     <instruction>
         <mnemonic>jl</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>TT_________</eflags>
         <def>
             <opc>7c</opc>
@@ -4305,6 +4490,7 @@
 
     <instruction>
         <mnemonic>jge</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>TT_________</eflags>
         <def>
             <opc>7d</opc>
@@ -4320,6 +4506,7 @@
 
     <instruction>
         <mnemonic>jle</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>TTT________</eflags>
         <def>
             <opc>7e</opc>
@@ -4335,6 +4522,7 @@
 
     <instruction>
         <mnemonic>jg</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>TTT________</eflags>
         <def>
             <opc>7f</opc>
@@ -4350,6 +4538,7 @@
 
     <instruction>
         <mnemonic>jcxz</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
@@ -4360,6 +4549,7 @@
 
     <instruction>
         <mnemonic>jecxz</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
@@ -4370,6 +4560,7 @@
 
     <instruction>
         <mnemonic>jrcxz</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso</pfx>
@@ -4380,6 +4571,7 @@
 
     <instruction>
         <mnemonic>jmp</mnemonic>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4412,6 +4604,7 @@
 
     <instruction>
         <mnemonic>lahf</mnemonic>
+        <implicit_register_def>ah</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>9f</opc>
@@ -4420,6 +4613,7 @@
 
     <instruction>
         <mnemonic>lar</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>__M________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4439,6 +4633,7 @@
 
     <instruction>
         <mnemonic>lds</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso</pfx>
@@ -4449,6 +4644,7 @@
 
     <instruction>
         <mnemonic>lea</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4459,6 +4655,8 @@
 
     <instruction>
         <mnemonic>les</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>es</implicit_register_use>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso</pfx>
@@ -4469,6 +4667,8 @@
 
     <instruction>
         <mnemonic>lfs</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>fs</implicit_register_use>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4479,6 +4679,8 @@
 
     <instruction>
         <mnemonic>lgs</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>fs</implicit_register_use>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4499,6 +4701,8 @@
 
     <instruction>
         <mnemonic>lss</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>ss</implicit_register_use>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>0f b2</opc>
@@ -4508,6 +4712,9 @@
 
     <instruction>
         <mnemonic>leave</mnemonic>
+        <implicit_register_use>rbp</implicit_register_use>
+        <implicit_register_def>rbp</implicit_register_def>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>c9</opc>
@@ -4564,6 +4771,7 @@
 
     <instruction>
         <mnemonic>lmsw</mnemonic>
+        <implicit_register_def>cr0</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -4587,6 +4795,9 @@
 
     <instruction>
         <mnemonic>lodsb</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -4596,6 +4807,9 @@
 
     <instruction>
         <mnemonic>lodsw</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>ax</implicit_register_def>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -4605,6 +4819,9 @@
 
     <instruction>
         <mnemonic>lodsd</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -4614,6 +4831,9 @@
 
     <instruction>
         <mnemonic>lodsq</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rax</implicit_register_def>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -4650,6 +4870,7 @@
 
     <instruction>
         <mnemonic>lsl</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>__M________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -4670,6 +4891,7 @@
 
     <instruction>
         <mnemonic>maskmovq</mnemonic>
+        <implicit_register_use>rdi</implicit_register_use>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f f7 /mod=11</opc>
@@ -4679,6 +4901,7 @@
 
     <instruction>
         <mnemonic>maxpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5f</opc>
@@ -4689,6 +4912,7 @@
 
     <instruction>
         <mnemonic>maxps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 5f</opc>
@@ -4699,6 +4923,7 @@
 
     <instruction>
         <mnemonic>maxsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 5f</opc>
@@ -4709,6 +4934,7 @@
 
     <instruction>
         <mnemonic>maxss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 5f</opc>
@@ -4747,6 +4973,7 @@
 
     <instruction>
         <mnemonic>minpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5d</opc>
@@ -4757,6 +4984,7 @@
 
     <instruction>
         <mnemonic>minps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 5d</opc>
@@ -4767,6 +4995,7 @@
 
     <instruction>
         <mnemonic>minsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 5d</opc>
@@ -4777,6 +5006,7 @@
 
     <instruction>
         <mnemonic>minss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 5d</opc>
@@ -4787,6 +5017,8 @@
 
     <instruction>
         <mnemonic>monitor</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_use>rdx</implicit_register_use>
         <eflags>___________</eflags>
         <def>
             <opc>0f 01 /reg=1 /mod=11 /rm=0</opc>
@@ -4802,6 +5034,7 @@
 
     <instruction>
         <mnemonic>mov</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -4969,6 +5202,7 @@
 
     <instruction>
         <mnemonic>movapd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 28</opc>
@@ -4985,6 +5219,7 @@
 
     <instruction>
         <mnemonic>movaps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 28</opc>
@@ -5001,6 +5236,7 @@
 
     <instruction>
         <mnemonic>movd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f 6e /o=16</opc>
@@ -5054,6 +5290,7 @@
 
     <instruction>
         <mnemonic>movhpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 16 /mod=!11</opc>
@@ -5070,6 +5307,7 @@
 
     <instruction>
         <mnemonic>movhps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 16 /mod=!11</opc>
@@ -5086,6 +5324,7 @@
 
     <instruction>
         <mnemonic>movlhps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 16 /mod=11</opc>
@@ -5096,6 +5335,7 @@
 
     <instruction>
         <mnemonic>movlpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 12 /mod=!11</opc>
@@ -5111,6 +5351,7 @@
 
     <instruction>
         <mnemonic>movlps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 12 /mod=!11</opc>
@@ -5126,6 +5367,7 @@
 
     <instruction>
         <mnemonic>movhlps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 12 /mod=11</opc>
@@ -5136,6 +5378,7 @@
 
     <instruction>
         <mnemonic>movmskpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>oso rexr rexb vexl</pfx>
             <opc>/sse=66 0f 50</opc>
@@ -5146,6 +5389,7 @@
 
     <instruction>
         <mnemonic>movmskps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>oso rexr rexb</pfx>
             <opc>0f 50</opc>
@@ -5156,6 +5400,7 @@
 
     <instruction>
         <mnemonic>movntdq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f e7</opc>
@@ -5166,6 +5411,7 @@
 
     <instruction>
         <mnemonic>movnti</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f c3</opc>
@@ -5175,6 +5421,7 @@
 
     <instruction>
         <mnemonic>movntpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 2b</opc>
@@ -5185,6 +5432,7 @@
 
     <instruction>
         <mnemonic>movntps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 2b</opc>
@@ -5195,6 +5443,7 @@
 
     <instruction>
         <mnemonic>movntq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f e7</opc>
@@ -5204,6 +5453,7 @@
 
     <instruction>
         <mnemonic>movq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f 6e /o=64</opc>
@@ -5256,6 +5506,9 @@
 
     <instruction>
         <mnemonic>movsb</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -5265,6 +5518,9 @@
 
     <instruction>
         <mnemonic>movsw</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -5274,6 +5530,9 @@
 
     <instruction>
         <mnemonic>movsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -5295,6 +5554,9 @@
 
     <instruction>
         <mnemonic>movsq</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -5304,6 +5566,7 @@
 
     <instruction>
         <mnemonic>movss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>________T__</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -5321,6 +5584,7 @@
 
     <instruction>
         <mnemonic>movsx</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -5336,6 +5600,7 @@
 
     <instruction>
         <mnemonic>movupd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 10</opc>
@@ -5352,6 +5617,7 @@
 
     <instruction>
         <mnemonic>movups</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 10</opc>
@@ -5368,6 +5634,7 @@
 
     <instruction>
         <mnemonic>movzx</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -5385,11 +5652,16 @@
         <mnemonic>mul</mnemonic>
         <eflags>MUUUUM_____</eflags>
         <def>
+            <implicit_register_use>al</implicit_register_use>
+            <implicit_register_def>ax</implicit_register_def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>f6 /reg=4</opc>
             <opr>Eb</opr>
         </def>
         <def>
+            <implicit_register_use>rax</implicit_register_use>
+            <implicit_register_def>rax</implicit_register_def>
+            <implicit_register_def>rdx</implicit_register_def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>f7 /reg=4</opc>
             <opr>Ev</opr>
@@ -5398,6 +5670,7 @@
 
     <instruction>
         <mnemonic>mulpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 59</opc>
@@ -5408,6 +5681,7 @@
 
     <instruction>
         <mnemonic>mulps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 59</opc>
@@ -5418,6 +5692,7 @@
 
     <instruction>
         <mnemonic>mulsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 59</opc>
@@ -5428,6 +5703,7 @@
 
     <instruction>
         <mnemonic>mulss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 59</opc>
@@ -5446,6 +5722,7 @@
 
     <instruction>
         <mnemonic>neg</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -5501,6 +5778,7 @@
 
     <instruction>
         <mnemonic>not</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -5516,6 +5794,7 @@
 
     <instruction>
         <mnemonic>or</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -5570,6 +5849,7 @@
 
     <instruction>
         <mnemonic>orpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 56</opc>
@@ -5613,6 +5893,8 @@
 
     <instruction>
         <mnemonic>outsb</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -5622,6 +5904,8 @@
 
     <instruction>
         <mnemonic>outsw</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
@@ -5631,6 +5915,8 @@
 
     <instruction>
         <mnemonic>outsd</mnemonic>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep oso seg</pfx>
@@ -5640,6 +5926,7 @@
 
     <instruction>
         <mnemonic>packsswb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 63</opc>
@@ -5656,6 +5943,7 @@
 
     <instruction>
         <mnemonic>packssdw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 6b</opc>
@@ -5672,6 +5960,7 @@
 
     <instruction>
         <mnemonic>packuswb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 67</opc>
@@ -5688,6 +5977,7 @@
 
     <instruction>
         <mnemonic>paddb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f fc</opc>
@@ -5704,6 +5994,7 @@
 
     <instruction>
         <mnemonic>paddw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f fd</opc>
@@ -5720,6 +6011,7 @@
 
     <instruction>
         <mnemonic>paddd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f fe</opc>
@@ -5737,6 +6029,7 @@
 
     <instruction>
         <mnemonic>paddsb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f ec</opc>
@@ -5752,6 +6045,7 @@
 
     <instruction>
         <mnemonic>paddsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f ed</opc>
@@ -5767,6 +6061,7 @@
 
     <instruction>
         <mnemonic>paddusb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f dc</opc>
@@ -5782,6 +6077,7 @@
 
     <instruction>
         <mnemonic>paddusw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f dd</opc>
@@ -5797,6 +6093,7 @@
 
     <instruction>
         <mnemonic>pand</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f db</opc>
@@ -5812,6 +6109,7 @@
 
     <instruction>
         <mnemonic>pandn</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f df</opc>
@@ -5827,6 +6125,7 @@
 
     <instruction>
         <mnemonic>pavgb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f e0</opc>
@@ -5842,6 +6141,7 @@
 
     <instruction>
         <mnemonic>pavgw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f e3</opc>
@@ -5857,6 +6157,7 @@
 
     <instruction>
         <mnemonic>pcmpeqb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 74</opc>
@@ -5872,6 +6173,7 @@
 
     <instruction>
         <mnemonic>pcmpeqw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 75</opc>
@@ -5887,6 +6189,7 @@
 
     <instruction>
         <mnemonic>pcmpeqd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 76</opc>
@@ -5902,6 +6205,7 @@
 
     <instruction>
         <mnemonic>pcmpgtb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 64</opc>
@@ -5917,6 +6221,7 @@
 
     <instruction>
         <mnemonic>pcmpgtw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 65</opc>
@@ -5932,6 +6237,7 @@
 
     <instruction>
         <mnemonic>pcmpgtd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 66</opc>
@@ -5947,6 +6253,7 @@
 
     <instruction>
         <mnemonic>pextrb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexx rexr rexb</pfx>
             <opc>/sse=66 0f 3a 14 /vexw=0</opc>
@@ -5958,6 +6265,7 @@
 
     <instruction>
         <mnemonic>pextrd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexw rexb</pfx>
             <opc>/sse=66 0f 3a 16 /o=16 /vexw=0</opc>
@@ -5974,6 +6282,7 @@
 
     <instruction>
         <mnemonic>pextrq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexb</pfx>
             <opc>/sse=66 0f 3a 16 /o=64 /vexw=1</opc>
@@ -5985,6 +6294,7 @@
 
    <instruction>
         <mnemonic>pextrw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexb</pfx>
             <opc>/sse=66 0f c5</opc>
@@ -6006,6 +6316,7 @@
 
     <instruction>
         <mnemonic>pinsrb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 20</opc>
@@ -6016,6 +6327,7 @@
 
     <instruction>
         <mnemonic>pinsrw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f c4</opc>
@@ -6033,6 +6345,7 @@
 
     <instruction>
         <mnemonic>pinsrd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 22 /o=16</opc>
@@ -6050,6 +6363,7 @@
 
     <instruction>
         <mnemonic>pinsrq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 22 /o=64</opc>
@@ -6060,6 +6374,7 @@
 
     <instruction>
         <mnemonic>vpinsrb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>/vex=66_0f3a 20 /vexw=0 /vexl=0</opc>
@@ -6070,6 +6385,7 @@
 
     <instruction>
         <mnemonic>vpinsrd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>/vex=66_0f3a 22 /m=!64 /vexw=0 /vexl=0</opc>
@@ -6087,6 +6403,7 @@
 
     <instruction>
         <mnemonic>vpinsrq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
             <opc>/vex=66_0f3a 22 /m=64 /vexw=1 /vexl=0</opc>
@@ -6098,6 +6415,7 @@
 
     <instruction>
         <mnemonic>pmaddwd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f f5</opc>
@@ -6113,6 +6431,7 @@
 
     <instruction>
         <mnemonic>pmaxsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f ee</opc>
@@ -6128,6 +6447,7 @@
 
     <instruction>
         <mnemonic>pmaxub</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f de</opc>
@@ -6143,6 +6463,7 @@
 
     <instruction>
         <mnemonic>pminsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f ea</opc>
@@ -6158,6 +6479,7 @@
 
     <instruction>
         <mnemonic>pminub</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f da</opc>
@@ -6173,6 +6495,7 @@
 
     <instruction>
         <mnemonic>pmovmskb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>oso rexr rexw rexb</pfx>
             <opc>/sse=66 0f d7 /vexl=0</opc>
@@ -6188,6 +6511,7 @@
 
     <instruction>
         <mnemonic>pmulhuw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f e4</opc>
@@ -6203,6 +6527,7 @@
 
     <instruction>
         <mnemonic>pmulhw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f e5</opc>
@@ -6218,6 +6543,7 @@
 
     <instruction>
         <mnemonic>pmullw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f d5</opc>
@@ -6233,6 +6559,9 @@
 
     <instruction>
         <mnemonic>pop</mnemonic>
+        <first_operand_access>W</first_operand_access>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>07 /m=!64</opc>
@@ -6315,6 +6644,15 @@
 
     <instruction>
         <mnemonic>popa</mnemonic>
+        <implicit_register_use>di</implicit_register_use>
+        <implicit_register_use>si</implicit_register_use>
+        <implicit_register_use>bp</implicit_register_use>
+        <implicit_register_use>bx</implicit_register_use>
+        <implicit_register_use>dx</implicit_register_use>
+        <implicit_register_use>cx</implicit_register_use>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_use>rdp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -6325,6 +6663,15 @@
 
     <instruction>
         <mnemonic>popad</mnemonic>
+        <implicit_register_use>edi</implicit_register_use>
+        <implicit_register_use>esi</implicit_register_use>
+        <implicit_register_use>ebp</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ecx</implicit_register_use>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>rdp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -6335,6 +6682,8 @@
 
     <instruction>
         <mnemonic>popfw</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
@@ -6344,6 +6693,8 @@
 
     <instruction>
         <mnemonic>popfd</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
@@ -6353,6 +6704,8 @@
 
     <instruction>
         <mnemonic>popfq</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>PPPPPPPPPP_</eflags>
         <def>
             <pfx>oso</pfx>
@@ -6368,6 +6721,7 @@
 
     <instruction>
         <mnemonic>por</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f eb</opc>
@@ -6463,6 +6817,7 @@
 
     <instruction>
         <mnemonic>psadbw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f6</opc>
@@ -6478,6 +6833,7 @@
 
     <instruction>
         <mnemonic>pshufw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 70</opc>
@@ -6487,6 +6843,7 @@
 
      <instruction>
         <mnemonic>psllw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f1</opc>
@@ -6512,6 +6869,7 @@
 
     <instruction>
         <mnemonic>pslld</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f2</opc>
@@ -6537,6 +6895,7 @@
 
     <instruction>
         <mnemonic>psllq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f3</opc>
@@ -6562,6 +6921,7 @@
 
     <instruction>
         <mnemonic>psraw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f e1</opc>
@@ -6587,6 +6947,7 @@
 
     <instruction>
         <mnemonic>psrad</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <opc>0f 72 /reg=4</opc>
             <opr>N Ib</opr>
@@ -6612,6 +6973,7 @@
 
     <instruction>
         <mnemonic>psrlw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <opc>0f 71 /reg=2</opc>
             <opr>N Ib</opr>
@@ -6637,6 +6999,7 @@
 
     <instruction>
         <mnemonic>psrld</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <opc>0f 72 /reg=2</opc>
             <opr>N Ib</opr>
@@ -6662,6 +7025,7 @@
 
     <instruction>
         <mnemonic>psrlq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <opc>0f 73 /reg=2</opc>
             <opr>N Ib</opr>
@@ -6687,6 +7051,7 @@
 
     <instruction>
         <mnemonic>psubb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f8</opc>
@@ -6702,6 +7067,7 @@
 
     <instruction>
         <mnemonic>psubw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f9</opc>
@@ -6717,6 +7083,7 @@
 
     <instruction>
         <mnemonic>psubd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f fa</opc>
@@ -6732,6 +7099,7 @@
 
     <instruction>
         <mnemonic>psubsb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f e8</opc>
@@ -6747,6 +7115,7 @@
 
     <instruction>
         <mnemonic>psubsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f e9</opc>
@@ -6762,6 +7131,7 @@
 
     <instruction>
         <mnemonic>psubusb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f d8</opc>
@@ -6777,6 +7147,7 @@
 
     <instruction>
         <mnemonic>psubusw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f d9</opc>
@@ -6792,6 +7163,7 @@
 
     <instruction>
         <mnemonic>punpckhbw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 68</opc>
@@ -6807,6 +7179,7 @@
 
     <instruction>
         <mnemonic>punpckhwd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 69</opc>
@@ -6822,6 +7195,7 @@
 
     <instruction>
         <mnemonic>punpckhdq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 6a</opc>
@@ -6837,6 +7211,7 @@
 
     <instruction>
         <mnemonic>punpcklbw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 60</opc>
@@ -6852,6 +7227,7 @@
 
     <instruction>
         <mnemonic>punpcklwd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 61</opc>
@@ -6867,6 +7243,7 @@
 
     <instruction>
         <mnemonic>punpckldq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 62</opc>
@@ -6882,6 +7259,7 @@
 
     <instruction>
         <mnemonic>pi2fw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=0c</opc>
@@ -6891,6 +7269,7 @@
 
     <instruction>
         <mnemonic>pi2fd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=0d</opc>
@@ -6900,6 +7279,7 @@
 
     <instruction>
         <mnemonic>pf2iw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=1c</opc>
@@ -6909,6 +7289,7 @@
 
     <instruction>
         <mnemonic>pf2id</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=1d</opc>
@@ -6918,6 +7299,7 @@
 
     <instruction>
         <mnemonic>pfnacc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=8a</opc>
@@ -6927,6 +7309,7 @@
 
     <instruction>
         <mnemonic>pfpnacc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=8e</opc>
@@ -6936,6 +7319,7 @@
 
     <instruction>
         <mnemonic>pfcmpge</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=90</opc>
@@ -6945,6 +7329,7 @@
 
     <instruction>
         <mnemonic>pfmin</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=94</opc>
@@ -6954,6 +7339,7 @@
 
     <instruction>
         <mnemonic>pfrcp</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=96</opc>
@@ -6963,6 +7349,7 @@
 
     <instruction>
         <mnemonic>pfrsqrt</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=97</opc>
@@ -6972,6 +7359,7 @@
 
     <instruction>
         <mnemonic>pfsub</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=9a</opc>
@@ -6981,6 +7369,7 @@
 
     <instruction>
         <mnemonic>pfadd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=9e</opc>
@@ -6990,6 +7379,7 @@
 
     <instruction>
         <mnemonic>pfcmpgt</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=a0</opc>
@@ -6999,6 +7389,7 @@
 
     <instruction>
         <mnemonic>pfmax</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=a4</opc>
@@ -7008,6 +7399,7 @@
 
     <instruction>
         <mnemonic>pfrcpit1</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=a6</opc>
@@ -7017,6 +7409,7 @@
 
     <instruction>
         <mnemonic>pfrsqit1</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=a7</opc>
@@ -7026,6 +7419,7 @@
 
     <instruction>
         <mnemonic>pfsubr</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=aa</opc>
@@ -7035,6 +7429,7 @@
 
     <instruction>
         <mnemonic>pfacc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=ae</opc>
@@ -7044,6 +7439,7 @@
 
     <instruction>
         <mnemonic>pfcmpeq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=b0</opc>
@@ -7053,6 +7449,7 @@
 
     <instruction>
         <mnemonic>pfmul</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=b4</opc>
@@ -7062,6 +7459,7 @@
 
     <instruction>
         <mnemonic>pfrcpit2</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=b6</opc>
@@ -7071,6 +7469,7 @@
 
     <instruction>
         <mnemonic>pmulhrw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=b7</opc>
@@ -7080,6 +7479,7 @@
 
     <instruction>
         <mnemonic>pswapd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=bb</opc>
@@ -7089,6 +7489,7 @@
 
     <instruction>
         <mnemonic>pavgusb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 0f /3dnow=bf</opc>
@@ -7098,6 +7499,8 @@
 
     <instruction>
         <mnemonic>push</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>06 /m=!64</opc>
@@ -7197,6 +7600,15 @@
 
     <instruction>
         <mnemonic>pusha</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_use>cx</implicit_register_use>
+        <implicit_register_use>dx</implicit_register_use>
+        <implicit_register_use>bx</implicit_register_use>
+        <implicit_register_use>bp</implicit_register_use>
+        <implicit_register_use>si</implicit_register_use>
+        <implicit_register_use>di</implicit_register_use>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -7207,6 +7619,15 @@
 
     <instruction>
         <mnemonic>pushad</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>ecx</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>ebp</implicit_register_use>
+        <implicit_register_use>esi</implicit_register_use>
+        <implicit_register_use>edi</implicit_register_use>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -7217,6 +7638,8 @@
 
     <instruction>
         <mnemonic>pushfw</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -7231,6 +7654,8 @@
 
     <instruction>
         <mnemonic>pushfd</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso</pfx>
@@ -7240,6 +7665,8 @@
 
     <instruction>
         <mnemonic>pushfq</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>oso rexw</pfx>
@@ -7255,6 +7682,7 @@
 
     <instruction>
         <mnemonic>pxor</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f ef</opc>
@@ -7270,6 +7698,7 @@
 
     <instruction>
         <mnemonic>rcl</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>U____M_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -7307,6 +7736,7 @@
 
     <instruction>
         <mnemonic>rcr</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>U____M_____</eflags>
         <def>
             <eflags>M____M_____</eflags>
@@ -7344,6 +7774,7 @@
 
     <instruction>
         <mnemonic>rol</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>U____M_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -7381,6 +7812,7 @@
 
     <instruction>
         <mnemonic>ror</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>U____M_____</eflags>
         <def>
             <eflags>M____M_____</eflags>
@@ -7418,6 +7850,7 @@
 
     <instruction>
         <mnemonic>rcpps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 53</opc>
@@ -7428,6 +7861,7 @@
 
     <instruction>
         <mnemonic>rcpss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 53</opc>
@@ -7438,6 +7872,9 @@
 
     <instruction>
         <mnemonic>rdmsr</mnemonic>
+        <implicit_register_use>ecx</implicit_register_use>
+        <implicit_register_def>rdx</implicit_register_def>
+        <implicit_register_def>rax</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>0f 32</opc>
@@ -7446,6 +7883,9 @@
 
     <instruction>
         <mnemonic>rdpmc</mnemonic>
+        <implicit_register_use>ecx</implicit_register_use>
+        <implicit_register_def>rdx</implicit_register_def>
+        <implicit_register_def>rax</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>0f 33</opc>
@@ -7454,6 +7894,8 @@
 
     <instruction>
         <mnemonic>rdtsc</mnemonic>
+        <implicit_register_def>rdx</implicit_register_def>
+        <implicit_register_def>rax</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>0f 31</opc>
@@ -7462,6 +7904,9 @@
 
     <instruction>
         <mnemonic>rdtscp</mnemonic>
+        <implicit_register_def>ecx</implicit_register_def>
+        <implicit_register_def>edx</implicit_register_def>
+        <implicit_register_def>eax</implicit_register_def>
         <vendor>amd</vendor>
         <def>
             <opc>0f 01 /reg=7 /mod=11 /rm=1</opc>
@@ -7470,6 +7915,8 @@
 
     <instruction>
         <mnemonic>repne</mnemonic>
+        <implicit_register_use>rcx</implicit_register_use>
+        <implicit_register_def>rcx</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>f2</opc>
@@ -7478,6 +7925,8 @@
 
     <instruction>
         <mnemonic>rep</mnemonic>
+        <implicit_register_use>rcx</implicit_register_use>
+        <implicit_register_def>rcx</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>f3</opc>
@@ -7486,6 +7935,8 @@
 
     <instruction>
         <mnemonic>ret</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>c2</opc>
@@ -7498,6 +7949,8 @@
 
     <instruction>
         <mnemonic>retf</mnemonic>
+        <implicit_register_use>rsp</implicit_register_use>
+        <implicit_register_def>rsp</implicit_register_def>
         <def>
             <opc>ca</opc>
             <opr>Iw</opr>
@@ -7517,6 +7970,7 @@
 
     <instruction>
         <mnemonic>rsqrtps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 52</opc>
@@ -7527,6 +7981,7 @@
 
     <instruction>
         <mnemonic>rsqrtss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 52</opc>
@@ -7537,6 +7992,7 @@
 
     <instruction>
         <mnemonic>sahf</mnemonic>
+        <implicit_register_use>ah</implicit_register_use>
         <eflags>_PPPPP_____</eflags>
         <def>
             <opc>9e</opc>
@@ -7545,11 +8001,13 @@
 
     <instruction>
         <mnemonic>sal</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMM_MM_____</eflags>
     </instruction>
 
     <instruction>
         <mnemonic>salc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <opc>d6 /m=!64</opc>
             <mode>inv64</mode>
@@ -7558,6 +8016,7 @@
 
     <instruction>
         <mnemonic>sar</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>_MM_MM_____</eflags>
         <def>
             <eflags>MMM_MM_____</eflags>
@@ -7595,6 +8054,7 @@
 
     <instruction>
         <mnemonic>shl</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>_MM_MM_____</eflags>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
@@ -7664,6 +8124,7 @@
 
     <instruction>
         <mnemonic>shr</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>_MM_MM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -7701,6 +8162,7 @@
 
     <instruction>
         <mnemonic>sbb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7723,10 +8185,14 @@
             <opr>Gv Ev</opr>
         </def>
         <def>
+            <implicit_register_use>al</implicit_register_use>
+            <implicit_register_def>al</implicit_register_def>
             <opc>1c</opc>
             <opr>AL Ib</opr>
         </def>
         <def>
+            <implicit_register_use>eax</implicit_register_use>
+            <implicit_register_def>eax</implicit_register_def>
             <pfx>oso rexw</pfx>
             <opc>1d</opc>
             <opr>rAX sIz</opr>
@@ -7756,6 +8222,9 @@
 
     <instruction>
         <mnemonic>scasb</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz</pfx>
@@ -7765,6 +8234,9 @@
 
     <instruction>
         <mnemonic>scasw</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
@@ -7774,6 +8246,9 @@
 
     <instruction>
         <mnemonic>scasd</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
@@ -7783,6 +8258,9 @@
 
     <instruction>
         <mnemonic>scasq</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>repz oso rexw</pfx>
@@ -7792,6 +8270,7 @@
 
     <instruction>
         <mnemonic>seto</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7802,6 +8281,7 @@
 
     <instruction>
         <mnemonic>setno</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7812,6 +8292,7 @@
 
     <instruction>
         <mnemonic>setb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7822,6 +8303,7 @@
 
     <instruction>
         <mnemonic>setae</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7832,6 +8314,7 @@
 
     <instruction>
         <mnemonic>setz</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7842,6 +8325,7 @@
 
     <instruction>
         <mnemonic>setnz</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7852,6 +8336,7 @@
 
     <instruction>
         <mnemonic>setbe</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7862,6 +8347,7 @@
 
     <instruction>
         <mnemonic>seta</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7872,6 +8358,7 @@
 
     <instruction>
         <mnemonic>sets</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7882,6 +8369,7 @@
 
     <instruction>
         <mnemonic>setns</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7892,6 +8380,7 @@
 
     <instruction>
         <mnemonic>setp</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7902,6 +8391,7 @@
 
     <instruction>
         <mnemonic>setnp</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7912,6 +8402,7 @@
 
     <instruction>
         <mnemonic>setl</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7922,6 +8413,7 @@
 
     <instruction>
         <mnemonic>setge</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7932,6 +8424,7 @@
 
     <instruction>
         <mnemonic>setle</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7942,6 +8435,7 @@
 
     <instruction>
         <mnemonic>setg</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -7990,6 +8484,7 @@
 
     <instruction>
         <mnemonic>shld</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>UMMUMM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -8005,6 +8500,7 @@
 
     <instruction>
         <mnemonic>shrd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>UMMUMM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -8020,6 +8516,7 @@
 
     <instruction>
         <mnemonic>shufpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f c6</opc>
@@ -8030,6 +8527,7 @@
 
     <instruction>
         <mnemonic>shufps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f c6</opc>
@@ -8040,6 +8538,7 @@
 
     <instruction>
         <mnemonic>sidt</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -8050,6 +8549,7 @@
 
     <instruction>
         <mnemonic>sldt</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
@@ -8060,6 +8560,7 @@
 
     <instruction>
         <mnemonic>smsw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
@@ -8075,6 +8576,7 @@
 
     <instruction>
         <mnemonic>sqrtps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 51</opc>
@@ -8085,6 +8587,7 @@
 
     <instruction>
         <mnemonic>sqrtpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 51</opc>
@@ -8095,6 +8598,7 @@
 
     <instruction>
         <mnemonic>sqrtsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 51</opc>
@@ -8105,6 +8609,7 @@
 
     <instruction>
         <mnemonic>sqrtss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 51</opc>
@@ -8147,6 +8652,15 @@
 
     <instruction>
         <mnemonic>skinit</mnemonic>
+        <implicit_register_def>rax</implicit_register_def>
+        <implicit_register_def>rbx</implicit_register_def>
+        <implicit_register_def>rcx</implicit_register_def>
+        <implicit_register_def>rdx</implicit_register_def>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
+        <implicit_register_def>rbp</implicit_register_def>
+        <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>cr0</implicit_register_def>
         <vendor>amd</vendor>
         <def>
             <opc>0f 01 /reg=3 /mod=11 /rm=6</opc>
@@ -8155,6 +8669,7 @@
 
     <instruction>
         <mnemonic>stmxcsr</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexw rexr rexx rexb</pfx>
             <opc>0f ae /mod=!11 /reg=3</opc>
@@ -8165,6 +8680,9 @@
 
     <instruction>
         <mnemonic>stosb</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -8174,6 +8692,9 @@
 
     <instruction>
         <mnemonic>stosw</mnemonic>
+        <implicit_register_use>ax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -8183,6 +8704,9 @@
 
     <instruction>
         <mnemonic>stosd</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -8192,6 +8716,9 @@
 
     <instruction>
         <mnemonic>stosq</mnemonic>
+        <implicit_register_use>rax</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -8211,6 +8738,7 @@
 
     <instruction>
         <mnemonic>sub</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -8266,6 +8794,7 @@
 
     <instruction>
         <mnemonic>subpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 5c</opc>
@@ -8276,6 +8805,7 @@
 
     <instruction>
         <mnemonic>subps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>0f 5c</opc>
@@ -8286,6 +8816,7 @@
 
     <instruction>
         <mnemonic>subsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 5c</opc>
@@ -8296,6 +8827,7 @@
 
     <instruction>
         <mnemonic>subss</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 5c</opc>
@@ -8306,6 +8838,7 @@
 
     <instruction>
         <mnemonic>swapgs</mnemonic>
+        <implicit_register_def>gs</implicit_register_def>
         <def>
             <opc>0f 01 /reg=7 /mod=11 /rm=0</opc>
         </def>
@@ -8313,6 +8846,11 @@
 
     <instruction>
         <mnemonic>syscall</mnemonic>
+        <implicit_register_use>rip</implicit_register_use>
+        <implicit_register_def>rcx</implicit_register_def>
+        <implicit_register_def>r11</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
+        <eflags>MMMMMMMMMMM</eflags>
         <def>
             <opc>0f 05</opc>
         </def>
@@ -8320,6 +8858,9 @@
 
     <instruction>
         <mnemonic>sysenter</mnemonic>
+        <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
+        <eflags>MMMMMMMMMMM</eflags>
         <def>
             <opc>0f 34 /m=!64</opc>
         </def>
@@ -8331,6 +8872,9 @@
 
     <instruction>
         <mnemonic>sysexit</mnemonic>
+        <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
+        <eflags>MMMMMMMMMMM</eflags>
         <def>
             <opc>0f 35 /m=!64</opc>
         </def>
@@ -8342,6 +8886,9 @@
 
     <instruction>
         <mnemonic>sysret</mnemonic>
+        <implicit_register_use>rcx</implicit_register_use>
+        <implicit_register_def>rip</implicit_register_def>
+        <eflags>MMMMMMMMMMM</eflags>
         <def>
             <opc>0f 07</opc>
         </def>
@@ -8423,6 +8970,7 @@
 
     <instruction>
         <mnemonic>unpckhpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 15</opc>
@@ -8433,6 +8981,7 @@
 
     <instruction>
         <mnemonic>unpckhps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 15</opc>
@@ -8443,6 +8992,7 @@
 
     <instruction>
         <mnemonic>unpcklps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 14</opc>
@@ -8453,6 +9003,7 @@
 
     <instruction>
         <mnemonic>unpcklpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 14</opc>
@@ -8491,6 +9042,7 @@
 
     <instruction>
         <mnemonic>rdrand</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>oso rexr rexw rexx rexb</pfx>
             <opc>0f c7 /mod=11 /reg=6</opc>
@@ -8635,6 +9187,8 @@
 
     <instruction>
         <mnemonic>wrmsr</mnemonic>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>eax</implicit_register_use>
         <eflags>___________</eflags>
         <def>
             <opc>0f 30</opc>
@@ -8643,6 +9197,8 @@
 
     <instruction>
         <mnemonic>xadd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
+        <second_operand_access>W</second_operand_access>
         <eflags>MMMMMM_____</eflags>
         <def>
             <pfx>aso oso rexr rexx rexb</pfx>
@@ -8658,6 +9214,8 @@
 
     <instruction>
         <mnemonic>xchg</mnemonic>
+        <first_operand_access>RW</first_operand_access>
+        <second_operand_access>RW</second_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -8713,6 +9271,9 @@
 
     <instruction>
         <mnemonic>xgetbv</mnemonic>
+        <implicit_register_use>ecx</implicit_register_use>
+        <implicit_register_def>edx</implicit_register_def>
+        <implicit_register_def>eax</implicit_register_def>
     <def>
         <opc>0f 01 /mod=11 /reg=2 /rm=0</opc>
     </def>
@@ -8720,6 +9281,9 @@
 
     <instruction>
         <mnemonic>xlatb</mnemonic>
+        <implicit_register_use>al</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_def>al</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <pfx>rexw seg</pfx>
@@ -8729,6 +9293,7 @@
 
     <instruction>
         <mnemonic>xor</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>RMMUMR_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
@@ -8784,6 +9349,7 @@
 
     <instruction>
         <mnemonic>xorpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 57</opc>
@@ -8794,6 +9360,7 @@
 
     <instruction>
         <mnemonic>xorps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 57</opc>
@@ -8804,6 +9371,13 @@
 
     <instruction>
         <mnemonic>xcryptecb</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=1</opc>
         </def>
@@ -8811,6 +9385,13 @@
 
     <instruction>
         <mnemonic>xcryptcbc</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=2</opc>
         </def>
@@ -8818,6 +9399,13 @@
 
     <instruction>
         <mnemonic>xcryptctr</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=3</opc>
         </def>
@@ -8825,6 +9413,13 @@
 
     <instruction>
         <mnemonic>xcryptcfb</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=4</opc>
         </def>
@@ -8832,6 +9427,13 @@
 
     <instruction>
         <mnemonic>xcryptofb</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>ebx</implicit_register_use>
+        <implicit_register_use>rsi</implicit_register_use>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_def>rdi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=5</opc>
         </def>
@@ -8839,31 +9441,43 @@
 
     <instruction>
         <mnemonic>xrstor</mnemonic>
-    <def>
-        <pfx>aso rexw rexr rexx rexb</pfx>
-        <opc>0f ae /reg=5 /mod=!11</opc>
-        <opr>M</opr>
-    </def>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>eax</implicit_register_use>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /reg=5 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
     </instruction>
 
     <instruction>
         <mnemonic>xsave</mnemonic>
-    <def>
-        <pfx>aso rexw rexr rexx rexb</pfx>
-        <opc>0f ae /reg=4 /mod=!11</opc>
-        <opr>M</opr>
-    </def>
+        <implicit_register_def>edx</implicit_register_def>
+        <implicit_register_def>eax</implicit_register_def>
+        <def>
+            <pfx>aso rexw rexr rexx rexb</pfx>
+            <opc>0f ae /reg=4 /mod=!11</opc>
+            <opr>M</opr>
+        </def>
     </instruction>
 
     <instruction>
         <mnemonic>xsetbv</mnemonic>
-    <def>
-        <opc>0f 01 /mod=11 /reg=2 /rm=1</opc>
-    </def>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>eax</implicit_register_use>
+        <def>
+          <opc>0f 01 /mod=11 /reg=2 /rm=1</opc>
+        </def>
     </instruction>
 
     <instruction>
         <mnemonic>xsha1</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>esi</implicit_register_use>
+        <implicit_register_use>edi</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>esi</implicit_register_def>
+        <implicit_register_def>edi</implicit_register_def>
         <def>
             <opc>0f a6 /mod=11 /rm=0 /reg=1</opc>
         </def>
@@ -8871,6 +9485,12 @@
 
     <instruction>
         <mnemonic>xsha256</mnemonic>
+        <implicit_register_use>eax</implicit_register_use>
+        <implicit_register_use>esi</implicit_register_use>
+        <implicit_register_use>edi</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>esi</implicit_register_def>
+        <implicit_register_def>edi</implicit_register_def>
         <def>
             <opc>0f a6 /mod=11 /rm=0 /reg=2</opc>
         </def>
@@ -8878,6 +9498,10 @@
 
     <instruction>
         <mnemonic>xstore</mnemonic>
+        <implicit_register_use>edx</implicit_register_use>
+        <implicit_register_use>edi</implicit_register_use>
+        <implicit_register_def>eax</implicit_register_def>
+        <implicit_register_def>edi</implicit_register_def>
         <def>
             <opc>0f a7 /mod=11 /rm=0 /reg=0</opc>
         </def>
@@ -8885,6 +9509,7 @@
 
     <instruction>
         <mnemonic>pclmulqdq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 44</opc>
@@ -8911,6 +9536,7 @@
 
     <instruction>
         <mnemonic>movdqa</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 7f</opc>
@@ -8926,6 +9552,7 @@
 
     <instruction>
         <mnemonic>maskmovdqu</mnemonic>
+        <implicit_register_use>rdi</implicit_register_use>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f f7 /mod=11</opc>
@@ -8936,6 +9563,7 @@
 
     <instruction>
         <mnemonic>movdq2q</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexb</pfx>
             <opc>/sse=f2 0f d6</opc>
@@ -8945,6 +9573,7 @@
 
     <instruction>
         <mnemonic>movdqu</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f3 0f 6f</opc>
@@ -8960,6 +9589,7 @@
 
     <instruction>
         <mnemonic>movq2dq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr</pfx>
             <opc>/sse=f3 0f d6</opc>
@@ -8969,6 +9599,7 @@
 
     <instruction>
         <mnemonic>paddq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f d4</opc>
@@ -8984,6 +9615,7 @@
 
     <instruction>
         <mnemonic>psubq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f fb</opc>
@@ -8999,6 +9631,7 @@
 
     <instruction>
         <mnemonic>pmuludq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f f4</opc>
@@ -9013,6 +9646,7 @@
 
     <instruction>
         <mnemonic>pshufhw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f3 0f 70</opc>
@@ -9023,6 +9657,7 @@
 
     <instruction>
         <mnemonic>pshuflw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 70</opc>
@@ -9033,6 +9668,7 @@
 
     <instruction>
         <mnemonic>pshufd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 70</opc>
@@ -9043,6 +9679,7 @@
 
     <instruction>
         <mnemonic>pslldq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>rexb</pfx>
             <opc>/sse=66 0f 73 /reg=7</opc>
@@ -9053,6 +9690,7 @@
 
     <instruction>
         <mnemonic>psrldq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>rexb</pfx>
             <opc>/sse=66 0f 73 /reg=3</opc>
@@ -9063,6 +9701,7 @@
 
     <instruction>
         <mnemonic>punpckhqdq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 6d</opc>
@@ -9073,6 +9712,7 @@
 
     <instruction>
         <mnemonic>punpcklqdq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 6c</opc>
@@ -9083,6 +9723,7 @@
 
     <instruction>
         <mnemonic>haddpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 7c</opc>
@@ -9093,6 +9734,7 @@
 
     <instruction>
         <mnemonic>haddps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f2 0f 7c</opc>
@@ -9103,6 +9745,7 @@
 
     <instruction>
         <mnemonic>hsubpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 7d</opc>
@@ -9113,6 +9756,7 @@
 
     <instruction>
         <mnemonic>hsubps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f2 0f 7d</opc>
@@ -9123,6 +9767,7 @@
 
     <instruction>
         <mnemonic>insertps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 3a 21</opc>
@@ -9133,6 +9778,7 @@
 
     <instruction>
         <mnemonic>lddqu</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f2 0f f0</opc>
@@ -9143,6 +9789,7 @@
 
     <instruction>
         <mnemonic>movddup</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=f2 0f 12 /mod=11</opc>
@@ -9158,6 +9805,7 @@
 
     <instruction>
         <mnemonic>movshdup</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f3 0f 16 /mod=11</opc>
@@ -9174,6 +9822,7 @@
 
     <instruction>
         <mnemonic>movsldup</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=f3 0f 12 /mod=11</opc>
@@ -9194,6 +9843,7 @@
 
     <instruction>
         <mnemonic>pabsb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 1c</opc>
@@ -9210,6 +9860,7 @@
 
     <instruction>
         <mnemonic>pabsw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 1d</opc>
@@ -9226,6 +9877,7 @@
 
     <instruction>
         <mnemonic>pabsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 1e</opc>
@@ -9242,6 +9894,7 @@
 
     <instruction>
         <mnemonic>pshufb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 00</opc>
@@ -9257,6 +9910,7 @@
 
     <instruction>
         <mnemonic>phaddw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 01</opc>
@@ -9272,6 +9926,7 @@
 
     <instruction>
         <mnemonic>phaddd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 02</opc>
@@ -9287,6 +9942,7 @@
 
     <instruction>
         <mnemonic>phaddsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 03</opc>
@@ -9302,6 +9958,7 @@
 
     <instruction>
         <mnemonic>pmaddubsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 04</opc>
@@ -9317,6 +9974,7 @@
 
     <instruction>
         <mnemonic>phsubw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 05</opc>
@@ -9332,6 +9990,7 @@
 
     <instruction>
         <mnemonic>phsubd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 06</opc>
@@ -9347,6 +10006,7 @@
 
     <instruction>
         <mnemonic>phsubsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 07</opc>
@@ -9362,6 +10022,7 @@
 
     <instruction>
         <mnemonic>psignb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 08</opc>
@@ -9377,6 +10038,7 @@
 
     <instruction>
         <mnemonic>psignd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 0a</opc>
@@ -9392,6 +10054,7 @@
 
     <instruction>
         <mnemonic>psignw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 09</opc>
@@ -9407,6 +10070,7 @@
 
     <instruction>
         <mnemonic>pmulhrsw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 38 0b</opc>
@@ -9422,6 +10086,7 @@
 
     <instruction>
         <mnemonic>palignr</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 3a 0f</opc>
@@ -9441,6 +10106,7 @@
 
     <instruction>
         <mnemonic>pblendvb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 10</opc>
@@ -9451,6 +10117,7 @@
 
     <instruction>
         <mnemonic>pmuldq</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 28</opc>
@@ -9461,6 +10128,7 @@
 
     <instruction>
         <mnemonic>pminsb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 38</opc>
@@ -9471,6 +10139,7 @@
 
     <instruction>
         <mnemonic>pminsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 39</opc>
@@ -9481,6 +10150,7 @@
 
     <instruction>
         <mnemonic>pminuw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3a</opc>
@@ -9491,6 +10161,7 @@
 
     <instruction>
         <mnemonic>pminud</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3b</opc>
@@ -9501,6 +10172,7 @@
 
     <instruction>
         <mnemonic>pmaxsb</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3c</opc>
@@ -9511,6 +10183,7 @@
 
     <instruction>
         <mnemonic>pmaxsd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3d</opc>
@@ -9521,6 +10194,7 @@
 
     <instruction>
         <mnemonic>pmaxud</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3f</opc>
@@ -9531,6 +10205,7 @@
 
     <instruction>
         <mnemonic>pmaxuw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 3e</opc>
@@ -9541,6 +10216,7 @@
 
     <instruction>
         <mnemonic>pmulld</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 40</opc>
@@ -9551,6 +10227,7 @@
 
     <instruction>
         <mnemonic>phminposuw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 41</opc>
@@ -9561,6 +10238,7 @@
 
     <instruction>
         <mnemonic>roundps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 3a 08</opc>
@@ -9571,6 +10249,7 @@
 
     <instruction>
         <mnemonic>roundpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 3a 09</opc>
@@ -9581,6 +10260,7 @@
 
     <instruction>
         <mnemonic>roundss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 0a</opc>
@@ -9591,6 +10271,7 @@
 
     <instruction>
         <mnemonic>roundsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 0b</opc>
@@ -9601,6 +10282,7 @@
 
     <instruction>
         <mnemonic>blendpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 3a 0d</opc>
@@ -9611,6 +10293,7 @@
 
     <instruction>
         <mnemonic>blendps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 0c</opc>
@@ -9621,6 +10304,7 @@
 
     <instruction>
         <mnemonic>blendvpd</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 15</opc>
@@ -9631,6 +10315,7 @@
 
     <instruction>
         <mnemonic>blendvps</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 38 14</opc>
@@ -9651,6 +10336,7 @@
 
     <instruction>
         <mnemonic>bsf</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>UUMUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -9661,6 +10347,7 @@
 
     <instruction>
         <mnemonic>bsr</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>UUMUUU_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -9671,6 +10358,7 @@
 
     <instruction>
         <mnemonic>bswap</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>___________</eflags>
         <def>
             <pfx>oso rexw rexb</pfx>
@@ -9731,6 +10419,7 @@
 
     <instruction>
         <mnemonic>btc</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -9746,6 +10435,7 @@
 
     <instruction>
         <mnemonic>btr</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -9761,6 +10451,7 @@
 
     <instruction>
         <mnemonic>bts</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <eflags>UUUUUM_____</eflags>
         <def>
             <pfx>aso oso rexw rexr rexx rexb</pfx>
@@ -9776,6 +10467,7 @@
 
     <instruction>
         <mnemonic>pblendw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/sse=66 0f 3a 0e</opc>
@@ -9786,6 +10478,7 @@
 
     <instruction>
         <mnemonic>mpsadbw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/sse=66 0f 3a 42</opc>
@@ -9796,6 +10489,7 @@
 
     <instruction>
         <mnemonic>movntdqa</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb vexl</pfx>
             <opc>/sse=66 0f 38 2a</opc>
@@ -9806,6 +10500,7 @@
 
     <instruction>
         <mnemonic>packusdw</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb vexl</pfx>
             <opc>/sse=66 0f 38 2b</opc>
@@ -9816,6 +10511,7 @@
 
     <instruction>
         <mnemonic>pmovsxbw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 20</opc>
@@ -9826,6 +10522,7 @@
 
     <instruction>
         <mnemonic>pmovsxbd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 21</opc>
@@ -9836,6 +10533,7 @@
 
     <instruction>
         <mnemonic>pmovsxbq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 22</opc>
@@ -9846,6 +10544,7 @@
 
     <instruction>
         <mnemonic>pmovsxwd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 23</opc>
@@ -9856,6 +10555,7 @@
 
     <instruction>
         <mnemonic>pmovsxwq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 24</opc>
@@ -9866,6 +10566,7 @@
 
     <instruction>
         <mnemonic>pmovsxdq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 25</opc>
@@ -9876,6 +10577,7 @@
 
     <instruction>
         <mnemonic>pmovzxbw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 30</opc>
@@ -9886,6 +10588,7 @@
 
     <instruction>
         <mnemonic>pmovzxbd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 31</opc>
@@ -9896,6 +10599,7 @@
 
     <instruction>
         <mnemonic>pmovzxbq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 32</opc>
@@ -9906,6 +10610,7 @@
 
     <instruction>
         <mnemonic>pmovzxwd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 33</opc>
@@ -9916,6 +10621,7 @@
 
     <instruction>
         <mnemonic>pmovzxwq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 34</opc>
@@ -9926,6 +10632,7 @@
 
     <instruction>
         <mnemonic>pmovzxdq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexw rexx rexb</pfx>
             <opc>/sse=66 0f 38 35</opc>
@@ -9946,6 +10653,7 @@
 
      <instruction>
         <mnemonic>popcnt</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <eflags>RRMRRR_____</eflags>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
@@ -10017,6 +10725,7 @@
 
     <instruction>
         <mnemonic>movbe</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>0f 38 f0</opc>
@@ -10033,6 +10742,7 @@
 
     <instruction>
         <mnemonic>crc32</mnemonic>
+        <first_operand_access>RW</first_operand_access>
         <def>
             <pfx>aso oso rexr rexw rexx rexb</pfx>
             <opc>/sse=f2 0f 38 f0</opc>
@@ -10053,6 +10763,7 @@
 
     <instruction>
         <mnemonic>vbroadcastss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 18 /vexw=0</opc>
@@ -10063,6 +10774,7 @@
 
     <instruction>
         <mnemonic>vbroadcastsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 19 /vexw=0 /vexl=1</opc>
@@ -10073,6 +10785,7 @@
 
     <instruction>
         <mnemonic>vextractf128</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f3a 19 /vexw=0 /vexl=1</opc>
@@ -10083,6 +10796,7 @@
 
     <instruction>
         <mnemonic>vinsertf128</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f3a 18 /vexw=0 /vexl=1</opc>
@@ -10093,6 +10807,7 @@
 
     <instruction>
         <mnemonic>vmaskmovps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 2c /vexw=0</opc>
@@ -10109,6 +10824,7 @@
 
     <instruction>
         <mnemonic>vmaskmovpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 2d /vexw=0</opc>
@@ -10125,6 +10841,7 @@
 
     <instruction>
         <mnemonic>vpermilpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 0d /vexw=0</opc>
@@ -10141,6 +10858,7 @@
 
     <instruction>
         <mnemonic>vpermilps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f38 0c /vexw=0</opc>
@@ -10157,6 +10875,7 @@
 
     <instruction>
         <mnemonic>vperm2f128</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f3a 06 /vexw=0 /vexl=1</opc>
@@ -10187,6 +10906,22 @@
 
     <instruction>
         <mnemonic>vzeroupper</mnemonic>
+        <implicit_register_def>ymm0</implicit_register_def>
+        <implicit_register_def>ymm1</implicit_register_def>
+        <implicit_register_def>ymm2</implicit_register_def>
+        <implicit_register_def>ymm3</implicit_register_def>
+        <implicit_register_def>ymm4</implicit_register_def>
+        <implicit_register_def>ymm5</implicit_register_def>
+        <implicit_register_def>ymm6</implicit_register_def>
+        <implicit_register_def>ymm7</implicit_register_def>
+        <implicit_register_def>ymm8</implicit_register_def>
+        <implicit_register_def>ymm9</implicit_register_def>
+        <implicit_register_def>ymm10</implicit_register_def>
+        <implicit_register_def>ymm11</implicit_register_def>
+        <implicit_register_def>ymm12</implicit_register_def>
+        <implicit_register_def>ymm13</implicit_register_def>
+        <implicit_register_def>ymm14</implicit_register_def>
+        <implicit_register_def>ymm15</implicit_register_def>
         <def>
             <opc>/vex=0f 77 /vexl=0</opc>
             <cpuid>avx</cpuid>
@@ -10195,6 +10930,22 @@
 
     <instruction>
         <mnemonic>vzeroall</mnemonic>
+        <implicit_register_def>ymm0</implicit_register_def>
+        <implicit_register_def>ymm1</implicit_register_def>
+        <implicit_register_def>ymm2</implicit_register_def>
+        <implicit_register_def>ymm3</implicit_register_def>
+        <implicit_register_def>ymm4</implicit_register_def>
+        <implicit_register_def>ymm5</implicit_register_def>
+        <implicit_register_def>ymm6</implicit_register_def>
+        <implicit_register_def>ymm7</implicit_register_def>
+        <implicit_register_def>ymm8</implicit_register_def>
+        <implicit_register_def>ymm9</implicit_register_def>
+        <implicit_register_def>ymm10</implicit_register_def>
+        <implicit_register_def>ymm11</implicit_register_def>
+        <implicit_register_def>ymm12</implicit_register_def>
+        <implicit_register_def>ymm13</implicit_register_def>
+        <implicit_register_def>ymm14</implicit_register_def>
+        <implicit_register_def>ymm15</implicit_register_def>
         <def>
             <opc>/vex=0f 77 /vexl=1</opc>
             <cpuid>avx</cpuid>
@@ -10203,6 +10954,7 @@
 
     <instruction>
         <mnemonic>vblendvpd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f3a 4b /vexw=0</opc>
@@ -10213,6 +10965,7 @@
 
     <instruction>
         <mnemonic>vblendvps</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb vexl</pfx>
             <opc>/vex=66_0f3a 4a /vexw=0</opc>
@@ -10223,6 +10976,7 @@
 
     <instruction>
         <mnemonic>vmovsd</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=f2_0f 10 /mod=11</opc>
@@ -10251,6 +11005,7 @@
 
     <instruction>
         <mnemonic>vmovss</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=f3_0f 10 /mod=11</opc>
@@ -10279,6 +11034,7 @@
 
     <instruction>
         <mnemonic>vpblendvb</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=66_0f3a 4c /vexw=0</opc>
@@ -10289,6 +11045,7 @@
 
     <instruction>
         <mnemonic>vpsllw</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=66_0f f1 /vexl=0</opc>
@@ -10305,6 +11062,7 @@
 
      <instruction>
         <mnemonic>vpslld</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=66_0f f2 /vexl=0</opc>
@@ -10321,6 +11079,7 @@
 
       <instruction>
         <mnemonic>vpsllq</mnemonic>
+        <first_operand_access>W</first_operand_access>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>/vex=66_0f f3 /vexl=0</opc>

From c053e98b33494d448c0a567438198dd4c980c3c7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Mon, 9 Dec 2013 18:33:51 +0100
Subject: [PATCH 07/20] Export the Read / Write operand information.

---
 libudis86/decode.c   |   3 +
 libudis86/decode.h   |   6 +-
 libudis86/types.h    |   7 ++
 scripts/ud_itab.py   |  17 ++++-
 scripts/ud_opcode.py | 162 ++++++++++++++++++++++++++++++-------------
 5 files changed, 144 insertions(+), 51 deletions(-)

diff --git a/libudis86/decode.c b/libudis86/decode.c
index ecf4d19..ef86158 100644
--- a/libudis86/decode.c
+++ b/libudis86/decode.c
@@ -1266,6 +1266,9 @@ ud_decode(struct ud *u)
     }
   }
 
+  u->operand[0].access = u->itab_entry->operand1_access;
+  u->operand[1].access = u->itab_entry->operand2_access;
+
   u->insn_offset = u->pc; /* set offset of instruction */
   u->asm_buf_fill = 0;   /* set translation buffer index to 0 */
   u->pc += u->inp_ctr;    /* move program counter by bytes decoded */
diff --git a/libudis86/decode.h b/libudis86/decode.h
index 0d4a36e..1258049 100644
--- a/libudis86/decode.h
+++ b/libudis86/decode.h
@@ -162,7 +162,7 @@ Mx_reg_size(ud_operand_size_t size)
 struct ud_itab_entry_operand 
 {
   enum ud_operand_code type;
-  ud_operand_size_t size;
+  ud_operand_size_t    size;
 };
 
 
@@ -176,8 +176,10 @@ struct ud_itab_entry
   struct ud_itab_entry_operand  operand2;
   struct ud_itab_entry_operand  operand3;
   struct ud_itab_entry_operand  operand4;
+  uint8_t                       operand1_access;
+  uint8_t                       operand2_access;
   uint32_t                      prefix;
-  struct ud_eflags   eflags;
+  struct ud_eflags              eflags;
 };
 
 struct ud_lookup_table_list_entry {
diff --git a/libudis86/types.h b/libudis86/types.h
index 45163ee..9bb718b 100644
--- a/libudis86/types.h
+++ b/libudis86/types.h
@@ -139,6 +139,12 @@ enum ud_eflag_state
   UD_FLAG_PRIOR
 };
 
+enum ud_operand_access
+{
+  UD_OP_ACCESS_READ = 1,
+  UD_OP_ACCESS_WRITE = 2
+};
+
 /* This structure describes the state of the EFLAGS register
  * once an instruction has been executed.
  */
@@ -187,6 +193,7 @@ struct ud_operand {
   uint8_t         offset;
   union ud_lval   lval;
   uint8_t         signed_lval;
+  uint8_t         access;
   /*
    * internal use only
    */
diff --git a/scripts/ud_itab.py b/scripts/ud_itab.py
index 2bee4ca..4df9649 100644
--- a/scripts/ud_itab.py
+++ b/scripts/ud_itab.py
@@ -272,6 +272,19 @@ def genInsnTable( self ):
             opr = "%s %s %s %s" % (opr_c[0] + ",", opr_c[1] + ",",
                                    opr_c[2] + ",", opr_c[3])
 
+            op1_access = "UD_OP_ACCESS_READ";
+            op2_access = "UD_OP_ACCESS_READ";
+
+            if insn.firstOpAccess == "W":
+                op1_access = "UD_OP_ACCESS_WRITE"
+            elif insn.firstOpAccess == "RW":
+                op1_access = "UD_OP_ACCESS_READ | UD_OP_ACCESS_WRITE"
+
+            if insn.secondOpAccess == "W":
+                op2_access = "UD_OP_ACCESS_WRITE"
+            elif insn.secondOpAccess == "RW":
+                op2_access = "UD_OP_ACCESS_READ | UD_OP_ACCESS_WRITE"
+
             for p in insn.prefixes:
                 if not ( p in self.PrefixDict.keys() ):
                     print("error: invalid prefix specification: %s \n" % pfx)
@@ -289,8 +302,8 @@ def genInsnTable( self ):
                         'P': 'UD_FLAG_PRIOR'}
             eflags = ", ".join(map(lambda f: flag_map[f], [flag for flag in insn.eflags]))
 
-            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s, {%s} },\n" \
-                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, pfx, eflags ) )
+            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s, %s, %s, {%s} },\n" \
+                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, op1_access, op2_access, pfx, eflags ) )
         self.ItabC.write( "};\n" )
 
    
diff --git a/scripts/ud_opcode.py b/scripts/ud_opcode.py
index 7bdbc90..da93cfb 100644
--- a/scripts/ud_opcode.py
+++ b/scripts/ud_opcode.py
@@ -29,13 +29,17 @@ class UdInsnDef:
     """An x86 instruction definition
     """
     def __init__(self, **insnDef):
-        self.mnemonic  = insnDef['mnemonic']
-        self.eflags    = insnDef['eflags']
-        self.prefixes  = insnDef['prefixes']
-        self.opcodes   = insnDef['opcodes']
-        self.operands  = insnDef['operands']
-        self._cpuid    = insnDef['cpuid']
-        self._opcexts  = {}
+        self.mnemonic       = insnDef['mnemonic']
+        self.eflags         = insnDef['eflags']
+        self.firstOpAccess  = insnDef['firstOpAccess']
+        self.secondOpAccess = insnDef['secondOpAccess']
+        self.implicitRegUse = insnDef['implicitRegUse']
+        self.implicitRegDef = insnDef['implicitRegDef']
+        self.prefixes       = insnDef['prefixes']
+        self.opcodes        = insnDef['opcodes']
+        self.operands       = insnDef['operands']
+        self._cpuid         = insnDef['cpuid']
+        self._opcexts       = {}
 
         for opc in self.opcodes:
             if opc.startswith('/'):
@@ -311,8 +315,16 @@ def __init__(self, xml):
 
         # add an invalid instruction entry without any mapping
         # in the opcode tables.
-        self.invalidInsn = UdInsnDef(mnemonic="invalid", eflags="___________", opcodes=[], cpuid=[],
-                                     operands=[], prefixes=[])
+        self.invalidInsn = UdInsnDef(mnemonic="invalid",
+                                     eflags="___________",
+                                     firstOpAccess="",
+                                     secondOpAccess="",
+                                     implicitRegUse=[],
+                                     implicitRegDef=[],
+                                     opcodes=[],
+                                     cpuid=[],
+                                     operands=[],
+                                     prefixes=[])
         self._insns.append(self.invalidInsn)
 
         # Construct UdOpcodeTables object from the given
@@ -371,10 +383,14 @@ def addInsn(self, **insnDef):
         # Canonicalize opcode list
         opcexts = insnDef['opcexts']
         opcodes = list(insnDef['opcodes'])
-        eflags = insnDef['eflags'] if 'eflags' in insnDef else "___________"
+        eflags = insnDef['eflags']
+        firstOpAccess = insnDef['firstOpAccess']
+        secondOpAccess = insnDef['secondOpAccess']
+        implicitRegUse = insnDef['implicitRegUse']
+        implicitRegDef = insnDef['implicitRegDef']
 
         # TODO: REMOVE!
-        # print opcodes, eflags, insnDef['mnemonic']
+        # print opcodes, eflags, insnDef['mnemonic'], firstOpAccess, secondOpAccess, implicitRegUse, implicitRegDef
 
         # Re-order vex
         if '/vex' in opcexts:
@@ -392,6 +408,10 @@ def addInsn(self, **insnDef):
 
         insn = UdInsnDef(mnemonic = insnDef['mnemonic'],
                          eflags   = insnDef['eflags'],
+                         firstOpAccess = insnDef['firstOpAccess'],
+                         secondOpAccess = insnDef['secondOpAccess'],
+                         implicitRegUse = insnDef['implicitRegUse'],
+                         implicitRegDef = insnDef['implicitRegDef'],
                          prefixes = insnDef['prefixes'],
                          operands = insnDef['operands'],
                          opcodes  = opcodes,
@@ -463,13 +483,17 @@ def addInsnDef(self, insnDef):
         if 'avx' in insnDef['cpuid'] and '/sse' in opcexts:
             fn = self.addSSE2AVXInsn
 
-        fn(mnemonic = insnDef['mnemonic'],
-           eflags   = insnDef['eflags'],
-           prefixes = insnDef['prefixes'],
-           opcodes  = opcodes,
-           opcexts  = opcexts,
-           operands = insnDef['operands'],
-           cpuid    = insnDef['cpuid'])
+        fn(mnemonic       = insnDef['mnemonic'],
+           eflags         = insnDef['eflags'],
+           firstOpAccess  = insnDef['firstOpAccess'],
+           secondOpAccess = insnDef['secondOpAccess'],
+           implicitRegUse = insnDef['implicitRegUse'],
+           implicitRegDef = insnDef['implicitRegDef'],
+           prefixes       = insnDef['prefixes'],
+           opcodes        = opcodes,
+           opcexts        = opcexts,
+           operands       = insnDef['operands'],
+           cpuid          = insnDef['cpuid'])
 
 
     def addSSE2AVXInsn(self, **insnDef):
@@ -480,9 +504,13 @@ def addSSE2AVXInsn(self, **insnDef):
         """
 
         # SSE
-        ssemnemonic = insnDef['mnemonic']
-        sseeflags   = insnDef['eflags']
-        sseopcodes  = insnDef['opcodes']
+        ssemnemonic       = insnDef['mnemonic']
+        sseeflags         = insnDef['eflags']
+        ssefirstOpAccess  = insnDef['firstOpAccess']
+        ssesecondOpAccess = insnDef['secondOpAccess']
+        sseimplicitRegUse = insnDef['implicitRegUse']
+        sseimplicitRegDef = insnDef['implicitRegDef']
+        sseopcodes        = insnDef['opcodes']
         # remove vex opcode extensions
         sseopcexts  = dict([(e, v) for e, v in insnDef['opcexts'].iteritems()
                                   if not e.startswith('/vex')])
@@ -497,20 +525,28 @@ def addSSE2AVXInsn(self, **insnDef):
         ssecpuid    = [flag for flag in insnDef['cpuid']
                         if not flag.startswith('avx')]
 
-        self.addInsn(mnemonic = ssemnemonic,
-                     eflags   = sseeflags,
-                     prefixes = sseprefixes,
-                     opcodes  = sseopcodes,
-                     opcexts  = sseopcexts,
-                     operands = sseoperands,
-                     cpuid    = ssecpuid)
+        self.addInsn(mnemonic       = ssemnemonic,
+                     eflags         = sseeflags,
+                     firstOpAccess  = ssefirstOpAccess,
+                     secondOpAccess = ssesecondOpAccess,
+                     implicitRegUse = sseimplicitRegUse,
+                     implicitRegDef = sseimplicitRegDef,
+                     prefixes       = sseprefixes,
+                     opcodes        = sseopcodes,
+                     opcexts        = sseopcexts,
+                     operands       = sseoperands,
+                     cpuid          = ssecpuid)
 
         # AVX
-        vexmnemonic = 'v' + insnDef['mnemonic']
-        vexeflags   = insnDef['eflags']
-        vexprefixes = insnDef['prefixes']
-        vexopcodes  = ['c4']
-        vexopcexts  = dict([(e, insnDef['opcexts'][e])
+        vexmnemonic       = 'v' + insnDef['mnemonic']
+        vexeflags         = insnDef['eflags']
+        vexfirstOpAccess  = insnDef['firstOpAccess']
+        vexsecondOpAccess = insnDef['secondOpAccess']
+        veximplicitRegUse = insnDef['implicitRegUse']
+        veximplicitRegDef = insnDef['implicitRegDef']
+        vexprefixes       = insnDef['prefixes']
+        vexopcodes        = ['c4']
+        vexopcexts        = dict([(e, insnDef['opcexts'][e])
                               for e in insnDef['opcexts'] if e != '/sse'])
         vexopcexts['/vex'] = insnDef['opcexts']['/sse'] + '_' + '0f'
         if insnDef['opcodes'][1] == '38' or insnDef['opcodes'][1] == '3a':
@@ -527,13 +563,17 @@ def addSSE2AVXInsn(self, **insnDef):
         vexcpuid    = [flag for flag in insnDef['cpuid']
                         if not flag.startswith('sse')]
 
-        self.addInsn(mnemonic = vexmnemonic,
-                     eflags   = vexeflags,
-                     prefixes = vexprefixes,
-                     opcodes  = vexopcodes,
-                     opcexts  = vexopcexts,
-                     operands = vexoperands,
-                     cpuid    = vexcpuid)
+        self.addInsn(mnemonic       = vexmnemonic,
+                     eflags         = vexeflags,
+                     firstOpAccess  = vexfirstOpAccess,
+                     secondOpAccess = vexsecondOpAccess,
+                     implicitRegUse = veximplicitRegUse,
+                     implicitRegDef = veximplicitRegDef,
+                     prefixes       = vexprefixes,
+                     opcodes        = vexopcodes,
+                     opcexts        = vexopcexts,
+                     operands       = vexoperands,
+                     cpuid          = vexcpuid)
 
     def getInsnList(self):
         """Returns a list of all instructions in the collection"""
@@ -601,6 +641,10 @@ def parseOptableXML(xml):
             mnemonic = insnNode.getElementsByTagName('mnemonic')[0].firstChild.data
             vendor, cpuid = '', []
             global_eflags = "___________"
+            global_firstOpAccess = "R"
+            global_secondOpAccess = "R"
+            global_implicitRegUse = []
+            global_implicitRegDef = []
 
             for node in insnNode.childNodes:
                 if node.localName == 'vendor':
@@ -609,10 +653,22 @@ def parseOptableXML(xml):
                     cpuid = node.firstChild.data.split()
                 elif node.localName == 'eflags':
                     global_eflags = node.firstChild.data
+                elif node.localName == 'first_operand_access':
+                    global_firstOpAccess = node.firstChild.data
+                elif node.localName == 'second_operand_access':
+                    global_secondOpAccess = node.firstChild.data
+                elif node.localName == 'implicit_register_use':
+                    global_implicitRegUse.append(node.firstChild.data)
+                elif node.localName == 'implicit_register_def':
+                    global_implicitRegDef.append(node.firstChild.data)
 
             for node in insnNode.childNodes:
                 if node.localName == 'def':
                     eflags = global_eflags
+                    firstOpAccess = global_firstOpAccess
+                    secondOpAccess = global_secondOpAccess
+                    implicitRegUse = global_implicitRegUse
+                    implicitRegDef = global_implicitRegDef
                     insnDef = { 'pfx' : [] }
                     for node in node.childNodes:
                         if not node.localName:
@@ -621,13 +677,25 @@ def parseOptableXML(xml):
                             insnDef[node.localName] = node.firstChild.data.split()
                         elif node.localName == 'eflags':
                             eflags = node.firstChild.data
+                        elif node.localName == 'first_operand_access':
+                            firstOpAccess = node.firstChild.data
+                        elif node.localName == 'second_operand_access':
+                            secondOpAccess = node.firstChild.data
+                        elif node.localName == 'implicit_register_use':
+                            implicitRegUse.append(node.firstChild.data)
+                        elif node.localName == 'implicit_register_def':
+                            implicitRegDef.append(node.firstChild.data)
                         elif node.localName == 'mode':
                             insnDef['pfx'].extend(node.firstChild.data.split())
-                    insns.append({'prefixes' : insnDef.get('pfx', []),
-                                  'mnemonic' : mnemonic,
-                                  'eflags'   : eflags,
-                                  'opcodes'  : insnDef.get('opc', []),
-                                  'operands' : insnDef.get('opr', []),
-                                  'vendor'   : insnDef.get('vendor', vendor),
-                                  'cpuid'    : insnDef.get('cpuid', cpuid)})
+                    insns.append({'prefixes'       : insnDef.get('pfx', []),
+                                  'mnemonic'       : mnemonic,
+                                  'eflags'         : eflags,
+                                  'firstOpAccess'  : firstOpAccess,
+                                  'secondOpAccess' : secondOpAccess,
+                                  'implicitRegUse' : implicitRegUse,
+                                  'implicitRegDef' : implicitRegDef,
+                                  'opcodes'        : insnDef.get('opc', []),
+                                  'operands'       : insnDef.get('opr', []),
+                                  'vendor'         : insnDef.get('vendor', vendor),
+                                  'cpuid'          : insnDef.get('cpuid', cpuid)})
         return insns

From e0a269e295e1864f53c337bf4fa979e34b8f9a90 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 09:11:50 +0100
Subject: [PATCH 08/20] Fix access mode for operand 3 and 4.

---
 libudis86/decode.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libudis86/decode.c b/libudis86/decode.c
index ef86158..841924c 100644
--- a/libudis86/decode.c
+++ b/libudis86/decode.c
@@ -1268,6 +1268,8 @@ ud_decode(struct ud *u)
 
   u->operand[0].access = u->itab_entry->operand1_access;
   u->operand[1].access = u->itab_entry->operand2_access;
+  u->operand[2].access = UD_OP_ACCESS_READ;
+  u->operand[3].access = UD_OP_ACCESS_READ;
 
   u->insn_offset = u->pc; /* set offset of instruction */
   u->asm_buf_fill = 0;   /* set translation buffer index to 0 */

From 130ba9cd691ae5cebf112249eb0d876df9273217 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 09:33:43 +0100
Subject: [PATCH 09/20] Add information about implicit register changes for ret
 instructions.

---
 docs/x86/optable.xml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 1120753..dab79b3 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -7937,6 +7937,7 @@
         <mnemonic>ret</mnemonic>
         <implicit_register_use>rsp</implicit_register_use>
         <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
         <eflags>___________</eflags>
         <def>
             <opc>c2</opc>
@@ -7951,6 +7952,7 @@
         <mnemonic>retf</mnemonic>
         <implicit_register_use>rsp</implicit_register_use>
         <implicit_register_def>rsp</implicit_register_def>
+        <implicit_register_def>rip</implicit_register_def>
         <def>
             <opc>ca</opc>
             <opr>Iw</opr>

From 51d5a6a8adaaaef31f4372f4c9e18156d39d1809 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 09:40:03 +0100
Subject: [PATCH 10/20] Fix EFLAGS values of the SETcc instructions.

---
 docs/x86/optable.xml | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index dab79b3..20320ab 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -8273,7 +8273,7 @@
     <instruction>
         <mnemonic>seto</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>T__________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 90</opc>
@@ -8284,7 +8284,7 @@
     <instruction>
         <mnemonic>setno</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>T__________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 91</opc>
@@ -8295,7 +8295,7 @@
     <instruction>
         <mnemonic>setb</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>_____T_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 92</opc>
@@ -8306,7 +8306,7 @@
     <instruction>
         <mnemonic>setae</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>_____T_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 93</opc>
@@ -8317,7 +8317,7 @@
     <instruction>
         <mnemonic>setz</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>__T________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 94</opc>
@@ -8328,7 +8328,7 @@
     <instruction>
         <mnemonic>setnz</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>__T________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 95</opc>
@@ -8339,7 +8339,7 @@
     <instruction>
         <mnemonic>setbe</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>__T__T_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 96</opc>
@@ -8350,7 +8350,7 @@
     <instruction>
         <mnemonic>seta</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>__T__T_____</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 97</opc>
@@ -8361,7 +8361,7 @@
     <instruction>
         <mnemonic>sets</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>_T_________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 98</opc>
@@ -8372,7 +8372,7 @@
     <instruction>
         <mnemonic>setns</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>_T_________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 99</opc>
@@ -8383,7 +8383,7 @@
     <instruction>
         <mnemonic>setp</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>____T______</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9a</opc>
@@ -8394,7 +8394,7 @@
     <instruction>
         <mnemonic>setnp</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>____T______</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9b</opc>
@@ -8405,7 +8405,7 @@
     <instruction>
         <mnemonic>setl</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>TT_________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9c</opc>
@@ -8416,7 +8416,7 @@
     <instruction>
         <mnemonic>setge</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>TT_________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9d</opc>
@@ -8427,7 +8427,7 @@
     <instruction>
         <mnemonic>setle</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>TTT________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9e</opc>
@@ -8438,7 +8438,7 @@
     <instruction>
         <mnemonic>setg</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <eflags>TTT_TT_____</eflags>
+        <eflags>TTT________</eflags>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
             <opc>0f 9f</opc>

From e6b044f1683204e5550ac148c5c6a019645110aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 10:04:16 +0100
Subject: [PATCH 11/20] Export information about registers implicitly used or
 modified.

---
 docs/x86/optable.xml |  4 ++--
 libudis86/decode.h   |  2 ++
 libudis86/extern.h   |  4 ++++
 libudis86/udis86.c   | 32 ++++++++++++++++++++++++++++++++
 scripts/ud_itab.py   | 15 +++++++++++++--
 scripts/ud_opcode.py | 11 ++++++-----
 6 files changed, 59 insertions(+), 9 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 20320ab..4dc5ee9 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -6651,7 +6651,7 @@
         <implicit_register_use>dx</implicit_register_use>
         <implicit_register_use>cx</implicit_register_use>
         <implicit_register_use>ax</implicit_register_use>
-        <implicit_register_use>rdp</implicit_register_use>
+        <implicit_register_use>rbp</implicit_register_use>
         <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
@@ -6670,7 +6670,7 @@
         <implicit_register_use>edx</implicit_register_use>
         <implicit_register_use>ecx</implicit_register_use>
         <implicit_register_use>eax</implicit_register_use>
-        <implicit_register_use>rdp</implicit_register_use>
+        <implicit_register_use>rbp</implicit_register_use>
         <implicit_register_def>rsp</implicit_register_def>
         <eflags>___________</eflags>
         <def>
diff --git a/libudis86/decode.h b/libudis86/decode.h
index 1258049..82ca61a 100644
--- a/libudis86/decode.h
+++ b/libudis86/decode.h
@@ -180,6 +180,8 @@ struct ud_itab_entry
   uint8_t                       operand2_access;
   uint32_t                      prefix;
   struct ud_eflags              eflags;
+  enum ud_type                  implicit_register_uses[32];
+  enum ud_type                  implicit_register_defs[32];
 };
 
 struct ud_lookup_table_list_entry {
diff --git a/libudis86/extern.h b/libudis86/extern.h
index 69bad12..ba23cfd 100644
--- a/libudis86/extern.h
+++ b/libudis86/extern.h
@@ -96,6 +96,10 @@ extern LIBUDIS86_DLLEXTERN const char* ud_lookup_mnemonic(enum ud_mnemonic_code
 
 extern LIBUDIS86_DLLEXTERN const struct ud_eflags* ud_lookup_eflags(struct ud *u);
 
+extern LIBUDIS86_DLLEXTERN const enum ud_type* ud_lookup_implicit_reg_used_list(struct ud *u);
+
+extern LIBUDIS86_DLLEXTERN const enum ud_type* ud_lookup_implicit_reg_defined_list(struct ud *u);
+
 extern LIBUDIS86_DLLEXTERN void ud_set_user_opaque_data(struct ud*, void*);
 
 extern LIBUDIS86_DLLEXTERN void* ud_get_user_opaque_data(const struct ud*);
diff --git a/libudis86/udis86.c b/libudis86/udis86.c
index 489ed3b..20b914e 100644
--- a/libudis86/udis86.c
+++ b/libudis86/udis86.c
@@ -356,6 +356,38 @@ ud_lookup_eflags(struct ud *u)
   }
 }
 
+/* =============================================================================
+ * ud_lookup_implicit_reg_used_list
+ *    Returns the list of register implicitly used.
+ *    The list is terminated by UD_NONE.
+ *    Returns NULL if invalid.
+ * =============================================================================
+ */
+const enum ud_type*
+ud_lookup_implicit_reg_used_list(struct ud *u) {
+  if (u == NULL || u->itab_entry == NULL) {
+    return NULL;
+  } else {
+    return u->itab_entry->implicit_register_uses;
+  }
+}
+
+/* =============================================================================
+ * ud_lookup_implicit_reg_used_list
+ *    Returns the list of register implicitly modified.
+ *    The list is terminated by UD_NONE.
+ *    Returns NULL if invalid.
+ * =============================================================================
+ */
+const enum ud_type*
+ud_lookup_implicit_reg_defined_list(struct ud *u) {
+  if (u == NULL || u->itab_entry == NULL) {
+    return NULL;
+  } else {
+    return u->itab_entry->implicit_register_defs;
+  }
+}
+
 /* 
  * ud_inp_init
  *    Initializes the input system.
diff --git a/scripts/ud_itab.py b/scripts/ud_itab.py
index 4df9649..9c77516 100644
--- a/scripts/ud_itab.py
+++ b/scripts/ud_itab.py
@@ -301,9 +301,20 @@ def genInsnTable( self ):
                         'U': 'UD_FLAG_UNDEFINED',
                         'P': 'UD_FLAG_PRIOR'}
             eflags = ", ".join(map(lambda f: flag_map[f], [flag for flag in insn.eflags]))
+            
+            implicit_uses = ", ".join(map(lambda r: "UD_R_" + r.upper(), insn.implicitRegUse))
+            implicit_defs = ", ".join(map(lambda r: "UD_R_" + r.upper(), insn.implicitRegDef))
 
-            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s, %s, %s, {%s} },\n" \
-                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, op1_access, op2_access, pfx, eflags ) )
+            if len(implicit_uses) > 0:
+                implicit_uses += ", "
+            if len(implicit_defs) > 0:
+                implicit_defs += ", "
+
+            implicit_uses += "UD_NONE"
+            implicit_defs += "UD_NONE"
+
+            self.ItabC.write( "  /* %04d */ { UD_I%s %s, %s, %s, %s, {%s}, {%s}, {%s} },\n" \
+                        % ( self.getInsnIndex(insn), insn.mnemonic + ',', opr, op1_access, op2_access, pfx, eflags, implicit_uses, implicit_defs ) )
         self.ItabC.write( "};\n" )
 
    
diff --git a/scripts/ud_opcode.py b/scripts/ud_opcode.py
index da93cfb..466682e 100644
--- a/scripts/ud_opcode.py
+++ b/scripts/ud_opcode.py
@@ -24,6 +24,7 @@
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import os
+import copy
 
 class UdInsnDef:
     """An x86 instruction definition
@@ -664,11 +665,11 @@ def parseOptableXML(xml):
 
             for node in insnNode.childNodes:
                 if node.localName == 'def':
-                    eflags = global_eflags
-                    firstOpAccess = global_firstOpAccess
-                    secondOpAccess = global_secondOpAccess
-                    implicitRegUse = global_implicitRegUse
-                    implicitRegDef = global_implicitRegDef
+                    eflags         = copy.deepcopy(global_eflags)
+                    firstOpAccess  = copy.deepcopy(global_firstOpAccess)
+                    secondOpAccess = copy.deepcopy(global_secondOpAccess)
+                    implicitRegUse = copy.deepcopy(global_implicitRegUse)
+                    implicitRegDef = copy.deepcopy(global_implicitRegDef)
                     insnDef = { 'pfx' : [] }
                     for node in node.childNodes:
                         if not node.localName:

From 9bf277c4dbbd610ff803eb385277ff86b69f4f10 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 10:33:15 +0100
Subject: [PATCH 12/20] Update the "udcli" utility to display more meta
 information.

---
 udcli/udcli.c | 82 ++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 65 insertions(+), 17 deletions(-)

diff --git a/udcli/udcli.c b/udcli/udcli.c
index 2b3d9e7..a75879c 100644
--- a/udcli/udcli.c
+++ b/udcli/udcli.c
@@ -60,27 +60,31 @@ static char help[] =
 {
   "Usage: %s [-option[s]] file\n"
   "Options:\n"
-  "    -16      : Set the disassembly mode to 16 bits. \n"
-  "    -32      : Set the disassembly mode to 32 bits. (default)\n"
-  "    -64      : Set the disassembly mode to 64 bits.\n"
-  "    -intel   : Set the output to INTEL (NASM like) syntax. (default)\n"
-  "    -att     : Set the output to AT&T (GAS like) syntax.\n"
-  "    -v <v>   : Set vendor. <v> = {intel, amd}.\n"
-  "    -o <pc>  : Set the value of program counter to <pc>. (default = 0)\n"
-  "    -s <n>   : Set the number of bytes to skip before disassembly to <n>.\n"
-  "    -c <n>   : Set the number of bytes to disassemble to <n>.\n"
-  "    -x       : Set the input mode to whitespace separated 8-bit numbers in\n"
-  "               hexadecimal representation. Example: 0f 01 ae 00\n"
-  "    -noff    : Do not display the offset of instructions.\n"
-  "    -nohex   : Do not display the hexadecimal code of instructions.\n"
-  "    -eflags  : Display information on EFLAGS register.\n"
-  "    -h       : Display this help message.\n"
-  "    --version: Show version.\n"
+  "    -16       : Set the disassembly mode to 16 bits. \n"
+  "    -32       : Set the disassembly mode to 32 bits. (default)\n"
+  "    -64       : Set the disassembly mode to 64 bits.\n"
+  "    -intel    : Set the output to INTEL (NASM like) syntax. (default)\n"
+  "    -att      : Set the output to AT&T (GAS like) syntax.\n"
+  "    -v <v>    : Set vendor. <v> = {intel, amd}.\n"
+  "    -o <pc>   : Set the value of program counter to <pc>. (default = 0)\n"
+  "    -s <n>    : Set the number of bytes to skip before disassembly to <n>.\n"
+  "    -c <n>    : Set the number of bytes to disassemble to <n>.\n"
+  "    -x        : Set the input mode to whitespace separated 8-bit numbers in\n"
+  "                hexadecimal representation. Example: 0f 01 ae 00\n"
+  "    -noff     : Do not display the offset of instructions.\n"
+  "    -nohex    : Do not display the hexadecimal code of instructions.\n"
+  "    -eflags   : Display information on EFLAGS register.\n"
+  "    -access   : Display access information of operand.\n"
+  "    -implicit : Display implicit registers used or modified by the instruction.\n"
+  "    -h        : Display this help message.\n"
+  "    --version : Show version.\n"
   "\n"
   "Udcli is a front-end to the Udis86 Disassembler Library.\n" 
   "http://udis86.sourceforge.net/\n"
 };
 
+extern const char* ud_reg_tab[];
+
 FILE* fptr = NULL;
 uint64_t o_skip = 0;
 uint64_t o_count = 0;
@@ -89,6 +93,8 @@ unsigned char o_do_off = 1;
 unsigned char o_do_hex = 1;
 unsigned char o_do_x = 0;
 unsigned char o_do_eflags = 0;
+unsigned char o_do_access = 0;
+unsigned char o_do_implicit = 0;
 unsigned o_vendor = UD_VENDOR_AMD;
 
 int input_hook_x(ud_t* u);
@@ -127,6 +133,7 @@ int main(int argc, char **argv)
   char *prog_path = *argv;
   char *s;
   ud_t ud_obj;
+  int i;
 
   /* initialize */
   ud_init(&ud_obj);
@@ -165,6 +172,10 @@ int main(int argc, char **argv)
 		o_do_hex = 0;
 	else if (strcmp(*argv,"-eflags") == 0)
 		o_do_eflags = 1;
+	else if (strcmp(*argv,"-access") == 0)
+		o_do_access = 1;
+	else if (strcmp(*argv,"-implicit") == 0)
+		o_do_implicit = 1;
 	else if (strcmp(*argv,"-x") == 0)
 		o_do_x = 1;
 	else if (strcmp(*argv,"-s") == 0)
@@ -245,7 +256,7 @@ int main(int argc, char **argv)
   // other options in the future. Hence, o_do_meta holds
   // the information about if we have to display any
   // metadata.
-  unsigned char o_do_meta = o_do_eflags;
+  unsigned char o_do_meta = o_do_eflags | o_do_access | o_do_implicit;
 
   /* disassembly loop */
   while (ud_disassemble(&ud_obj)) {
@@ -271,6 +282,43 @@ int main(int argc, char **argv)
         const struct ud_eflags* eflags = ud_lookup_eflags(&ud_obj);
         print_eflags(eflags);
       }
+      if (o_do_access) {
+        o_do_access = 0;
+        for (i=0; i<4; i++) {
+          const struct ud_operand *op = ud_insn_opr(&ud_obj, i);
+          if (op != NULL) {
+            if (i == 0) {
+              if (o_do_eflags) printf(", ");
+              printf("access");
+              o_do_access = 1;
+            }
+            printf(" op%d=", i);
+            if (op->access == UD_OP_ACCESS_READ) printf("R");
+            else if (op->access == UD_OP_ACCESS_WRITE) printf("W");
+            else if (op->access == (UD_OP_ACCESS_READ|UD_OP_ACCESS_WRITE)) printf("RW");
+            else printf("-");
+          }
+        }
+      }
+      if (o_do_implicit) {
+        if (o_do_eflags | o_do_access) printf(", ");
+        const enum ud_type *imp_used = ud_lookup_implicit_reg_used_list(&ud_obj);
+        const enum ud_type *imp_modified = ud_lookup_implicit_reg_defined_list(&ud_obj);
+        printf("implicit reg used:");
+        if (imp_used == NULL || *imp_used == UD_NONE) {
+          printf(" none");
+        }
+        while (*imp_used != UD_NONE) {
+          printf(" %s", ud_reg_tab[*imp_used++ - 1]);
+        }
+        printf(", implicit reg modified:");
+        if (imp_modified == NULL || *imp_modified == UD_NONE) {
+          printf(" none");
+        }
+        while (*imp_modified != UD_NONE) {
+          printf(" %s", ud_reg_tab[*imp_modified++ - 1]);
+        }
+      }
     }
 
     printf("\n");

From 7a2bbb73cbac7231f7b3951c8182e104f7d09fd5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Tue, 10 Dec 2013 13:39:45 +0100
Subject: [PATCH 13/20] Replace some conditional instructions by their synonym.

---
 docs/x86/optable.xml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 4dc5ee9..89598c2 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -698,7 +698,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>cmovz</mnemonic>
+        <mnemonic>cmove</mnemonic>
         <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
@@ -709,7 +709,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>cmovnz</mnemonic>
+        <mnemonic>cmovne</mnemonic>
         <first_operand_access>W</first_operand_access>
         <eflags>TTT_TT_____</eflags>
         <def>
@@ -4345,7 +4345,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>jz</mnemonic>
+        <mnemonic>je</mnemonic>
         <implicit_register_def>rip</implicit_register_def>
         <eflags>__T________</eflags>
         <def>
@@ -4361,7 +4361,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>jnz</mnemonic>
+        <mnemonic>jne</mnemonic>
         <implicit_register_def>rip</implicit_register_def>
         <eflags>__T________</eflags>
         <def>
@@ -8315,7 +8315,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>setz</mnemonic>
+        <mnemonic>sete</mnemonic>
         <first_operand_access>W</first_operand_access>
         <eflags>__T________</eflags>
         <def>
@@ -8326,7 +8326,7 @@
     </instruction>
 
     <instruction>
-        <mnemonic>setnz</mnemonic>
+        <mnemonic>setne</mnemonic>
         <first_operand_access>W</first_operand_access>
         <eflags>__T________</eflags>
         <def>

From f4c68d55b30e4cedfca2a18016ac91b29444e106 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Thu, 19 Dec 2013 14:50:23 +0100
Subject: [PATCH 14/20] Add CMake file.

---
 CMakeLists.txt           |  6 +++
 libudis86/CMakeLists.txt | 18 ++++++++
 libudis86/udis86.c       | 91 ++++++++++++++++++++--------------------
 udcli/CMakeLists.txt     |  4 ++
 4 files changed, 74 insertions(+), 45 deletions(-)
 create mode 100644 CMakeLists.txt
 create mode 100644 libudis86/CMakeLists.txt
 create mode 100644 udcli/CMakeLists.txt

diff --git a/CMakeLists.txt b/CMakeLists.txt
new file mode 100644
index 0000000..b486548
--- /dev/null
+++ b/CMakeLists.txt
@@ -0,0 +1,6 @@
+project(udis86)
+cmake_minimum_required(VERSION 2.8)
+include_directories("${PROJECT_SOURCE_DIR}")
+add_subdirectory(libudis86)
+add_subdirectory(udcli)
+
diff --git a/libudis86/CMakeLists.txt b/libudis86/CMakeLists.txt
new file mode 100644
index 0000000..6257f9a
--- /dev/null
+++ b/libudis86/CMakeLists.txt
@@ -0,0 +1,18 @@
+project(libudis86)
+cmake_minimum_required(VERSION 2.8)
+
+set(FILES
+	decode.c
+	decode.h
+	extern.h
+	itab.c
+	itab.h
+	syn-att.c
+	syn-intel.c
+	syn.c
+	syn.h
+	types.h
+	udint.h
+	udis86.c)
+
+add_library(libudis86 STATIC ${FILES})
diff --git a/libudis86/udis86.c b/libudis86/udis86.c
index 20b914e..b52cdf0 100644
--- a/libudis86/udis86.c
+++ b/libudis86/udis86.c
@@ -2,31 +2,32 @@
  *
  * Copyright (c) 2002-2013 Vivek Thampi
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
- * 
- *     * Redistributions of source code must retain the above copyright notice, 
+ *
+ *     * Redistributions of source code must retain the above copyright notice,
  *       this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright notice, 
- *       this list of conditions and the following disclaimer in the documentation 
+ *     * Redistributions in binary form must reproduce the above copyright notice,
+ *       this list of conditions and the following disclaimer in the documentation
  *       and/or other materials provided with the distribution.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include "udint.h"
 #include "extern.h"
 #include "decode.h"
+#include <string.h>
 
 #if !defined(__UD_STANDALONE__)
 # if HAVE_STRING_H
@@ -41,7 +42,7 @@ static void ud_inp_init(struct ud *u);
  *    Initializes ud_t object.
  * =============================================================================
  */
-extern void 
+extern void
 ud_init(struct ud* u)
 {
   memset((void*)u, 0, sizeof(struct ud));
@@ -58,7 +59,7 @@ ud_init(struct ud* u)
 
 /* =============================================================================
  * ud_disassemble
- *    Disassembles one instruction and returns the number of 
+ *    Disassembles one instruction and returns the number of
  *    bytes disassembled. A zero means end of disassembly.
  * =============================================================================
  */
@@ -83,7 +84,7 @@ ud_disassemble(struct ud* u)
  * ud_set_mode() - Set Disassemly Mode.
  * =============================================================================
  */
-extern void 
+extern void
 ud_set_mode(struct ud* u, uint8_t m)
 {
   switch(m) {
@@ -98,7 +99,7 @@ ud_set_mode(struct ud* u, uint8_t m)
  * ud_set_vendor() - Set vendor.
  * =============================================================================
  */
-extern void 
+extern void
 ud_set_vendor(struct ud* u, unsigned v)
 {
   switch(v) {
@@ -114,10 +115,10 @@ ud_set_vendor(struct ud* u, unsigned v)
 }
 
 /* =============================================================================
- * ud_set_pc() - Sets code origin. 
+ * ud_set_pc() - Sets code origin.
  * =============================================================================
  */
-extern void 
+extern void
 ud_set_pc(struct ud* u, uint64_t o)
 {
   u->pc = o;
@@ -127,7 +128,7 @@ ud_set_pc(struct ud* u, uint64_t o)
  * ud_set_syntax() - Sets the output syntax.
  * =============================================================================
  */
-extern void 
+extern void
 ud_set_syntax(struct ud* u, void (*t)(struct ud*))
 {
   u->translator = t;
@@ -137,8 +138,8 @@ ud_set_syntax(struct ud* u, void (*t)(struct ud*))
  * ud_insn() - returns the disassembled instruction
  * =============================================================================
  */
-const char* 
-ud_insn_asm(const struct ud* u) 
+const char*
+ud_insn_asm(const struct ud* u)
 {
   return u->asm_buf;
 }
@@ -148,7 +149,7 @@ ud_insn_asm(const struct ud* u)
  * =============================================================================
  */
 uint64_t
-ud_insn_off(const struct ud* u) 
+ud_insn_off(const struct ud* u)
 {
   return u->insn_offset;
 }
@@ -158,8 +159,8 @@ ud_insn_off(const struct ud* u)
  * ud_insn_hex() - Returns hex form of disassembled instruction.
  * =============================================================================
  */
-const char* 
-ud_insn_hex(struct ud* u) 
+const char*
+ud_insn_hex(struct ud* u)
 {
   u->insn_hexcode[0] = 0;
   if (!u->error) {
@@ -184,10 +185,10 @@ ud_insn_hex(struct ud* u)
  *    disassembled.
  * =============================================================================
  */
-extern const uint8_t* 
-ud_insn_ptr(const struct ud* u) 
+extern const uint8_t*
+ud_insn_ptr(const struct ud* u)
 {
-  return (u->inp_buf == NULL) ? 
+  return (u->inp_buf == NULL) ?
             u->inp_sess : u->inp_buf + (u->inp_buf_index - u->inp_ctr);
 }
 
@@ -197,8 +198,8 @@ ud_insn_ptr(const struct ud* u)
  *    Returns the count of bytes disassembled.
  * =============================================================================
  */
-extern unsigned int 
-ud_insn_len(const struct ud* u) 
+extern unsigned int
+ud_insn_len(const struct ud* u)
 {
   return u->inp_ctr;
 }
@@ -215,7 +216,7 @@ const struct ud_operand*
 ud_insn_opr(const struct ud *u, unsigned int n)
 {
   if (n > 3 || u->operand[n].type == UD_NONE) {
-    return NULL; 
+    return NULL;
   } else {
     return &u->operand[n];
   }
@@ -230,7 +231,7 @@ ud_insn_opr(const struct ud *u, unsigned int n)
 int
 ud_opr_is_sreg(const struct ud_operand *opr)
 {
-  return opr->type == UD_OP_REG && 
+  return opr->type == UD_OP_REG &&
          opr->base >= UD_R_ES   &&
          opr->base <= UD_R_GS;
 }
@@ -245,7 +246,7 @@ ud_opr_is_sreg(const struct ud_operand *opr)
 int
 ud_opr_is_gpr(const struct ud_operand *opr)
 {
-  return opr->type == UD_OP_REG && 
+  return opr->type == UD_OP_REG &&
          opr->base >= UD_R_AL   &&
          opr->base <= UD_R_R15;
 }
@@ -304,7 +305,7 @@ ud_set_asm_buffer(struct ud *u, char *buf, size_t size)
  * =============================================================================
  */
 void
-ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*, 
+ud_set_sym_resolver(struct ud *u, const char* (*resolver)(struct ud*,
                                                           uint64_t addr,
                                                           int64_t *offset))
 {
@@ -388,7 +389,7 @@ ud_lookup_implicit_reg_defined_list(struct ud *u) {
   }
 }
 
-/* 
+/*
  * ud_inp_init
  *    Initializes the input system.
  */
@@ -412,7 +413,7 @@ ud_inp_init(struct ud *u)
  *    Sets input hook.
  * =============================================================================
  */
-void 
+void
 ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
 {
   ud_inp_init(u);
@@ -424,7 +425,7 @@ ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
  *    Set buffer as input.
  * =============================================================================
  */
-void 
+void
 ud_set_input_buffer(register struct ud* u, const uint8_t* buf, size_t len)
 {
   ud_inp_init(u);
@@ -440,13 +441,13 @@ ud_set_input_buffer(register struct ud* u, const uint8_t* buf, size_t len)
  *    Set FILE as input.
  * =============================================================================
  */
-static int 
+static int
 inp_file_hook(struct ud* u)
 {
   return fgetc(u->inp_file);
 }
 
-void 
+void
 ud_set_input_file(register struct ud* u, FILE* f)
 {
   ud_inp_init(u);
@@ -461,7 +462,7 @@ ud_set_input_file(register struct ud* u, FILE* f)
  *    Skip n input bytes.
  * ============================================================================
  */
-void 
+void
 ud_input_skip(struct ud* u, size_t n)
 {
   if (u->inp_end) {
@@ -478,10 +479,10 @@ ud_input_skip(struct ud* u, size_t n)
   } else {
     if (n > u->inp_buf_size ||
         u->inp_buf_index > u->inp_buf_size - n) {
-      u->inp_buf_index = u->inp_buf_size; 
+      u->inp_buf_index = u->inp_buf_size;
       goto eoi;
     }
-    u->inp_buf_index += n; 
+    u->inp_buf_index += n;
     return;
   }
 eoi:
diff --git a/udcli/CMakeLists.txt b/udcli/CMakeLists.txt
new file mode 100644
index 0000000..df5c3ec
--- /dev/null
+++ b/udcli/CMakeLists.txt
@@ -0,0 +1,4 @@
+project(udcli)
+cmake_minimum_required(VERSION 2.8)
+add_executable(udcli udcli.c)
+target_link_libraries(udcli libudis86)

From 42e246874a1643bdad16e1a065e460e26017ded7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20Be=CC=81nony?= <vincent.benony@me.com>
Date: Wed, 21 May 2014 17:21:49 +0200
Subject: [PATCH 15/20] Fix issues revealed by radare project.

---
 libudis86/syn.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/libudis86/syn.c b/libudis86/syn.c
index 1b9e1d4..8e64fc2 100644
--- a/libudis86/syn.c
+++ b/libudis86/syn.c
@@ -91,10 +91,16 @@ const char* ud_reg_tab[] =
 uint64_t
 ud_syn_rel_target(struct ud *u, struct ud_operand *opr)
 {
-  const uint64_t trunc_mask = 0xffffffffffffffffull >> (64 - u->opr_mode);
+  uint64_t trunc_mask = 0xffffffffffffffffull;
+  if (u->dis_mode != 64) trunc_mask >>= (64 - u->opr_mode);
   switch (opr->size) {
   case 8 : return (u->pc + opr->lval.sbyte)  & trunc_mask;
-  case 16: return (u->pc + opr->lval.sword)  & trunc_mask;
+  case 16: {
+      int delta = (opr->lval.sword & trunc_mask);
+      if ((u->pc + delta) > 0xffff)
+          return (u->pc & 0xf0000) + ((u->pc + delta) & 0xffff);
+      return (u->pc + delta);
+  }
   case 32: return (u->pc + opr->lval.sdword) & trunc_mask;
   default: UD_ASSERT(!"invalid relative offset size.");
     return 0ull;

From 85196b44650d4aed738a19e45314290a16420020 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20Be=CC=81nony?= <vincent.benony@me.com>
Date: Wed, 21 May 2014 17:22:57 +0200
Subject: [PATCH 16/20] Add an Xcode project.

---
 xcode/udcli/sample_input                      |   1 +
 xcode/udcli/udcli.xcodeproj/project.pbxproj   | 272 ++++++++++++++++
 xcode/udis.xcodeproj/project.pbxproj          | 307 ++++++++++++++++++
 .../udis.xcworkspace/contents.xcworkspacedata |  10 +
 4 files changed, 590 insertions(+)
 create mode 100644 xcode/udcli/sample_input
 create mode 100644 xcode/udcli/udcli.xcodeproj/project.pbxproj
 create mode 100644 xcode/udis.xcodeproj/project.pbxproj
 create mode 100644 xcode/udis.xcworkspace/contents.xcworkspacedata

diff --git a/xcode/udcli/sample_input b/xcode/udcli/sample_input
new file mode 100644
index 0000000..25b936d
--- /dev/null
+++ b/xcode/udcli/sample_input
@@ -0,0 +1 @@
+90 90 90
\ No newline at end of file
diff --git a/xcode/udcli/udcli.xcodeproj/project.pbxproj b/xcode/udcli/udcli.xcodeproj/project.pbxproj
new file mode 100644
index 0000000..b59effe
--- /dev/null
+++ b/xcode/udcli/udcli.xcodeproj/project.pbxproj
@@ -0,0 +1,272 @@
+// !$*UTF8*$!
+{
+	archiveVersion = 1;
+	classes = {
+	};
+	objectVersion = 46;
+	objects = {
+
+/* Begin PBXBuildFile section */
+		0750BF3A192CF9BB00F0FFA9 /* udcli.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF39192CF9BB00F0FFA9 /* udcli.c */; };
+		0750BF3C192CFA6100F0FFA9 /* libudis.a in Frameworks */ = {isa = PBXBuildFile; fileRef = 0750BF3B192CFA6100F0FFA9 /* libudis.a */; };
+/* End PBXBuildFile section */
+
+/* Begin PBXCopyFilesBuildPhase section */
+		0750BF2B192CF98400F0FFA9 /* CopyFiles */ = {
+			isa = PBXCopyFilesBuildPhase;
+			buildActionMask = 2147483647;
+			dstPath = /usr/share/man/man1/;
+			dstSubfolderSpec = 0;
+			files = (
+			);
+			runOnlyForDeploymentPostprocessing = 1;
+		};
+/* End PBXCopyFilesBuildPhase section */
+
+/* Begin PBXFileReference section */
+		0750BF2D192CF98400F0FFA9 /* udcli */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = udcli; sourceTree = BUILT_PRODUCTS_DIR; };
+		0750BF39192CF9BB00F0FFA9 /* udcli.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udcli.c; path = ../../../udcli/udcli.c; sourceTree = "<group>"; };
+		0750BF3B192CFA6100F0FFA9 /* libudis.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libudis.a; path = "../../../../Library/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug/libudis.a"; sourceTree = "<group>"; };
+		0750BF3E192CFB0300F0FFA9 /* sample_input */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = sample_input; sourceTree = "<group>"; };
+/* End PBXFileReference section */
+
+/* Begin PBXFrameworksBuildPhase section */
+		0750BF2A192CF98400F0FFA9 /* Frameworks */ = {
+			isa = PBXFrameworksBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				0750BF3C192CFA6100F0FFA9 /* libudis.a in Frameworks */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXFrameworksBuildPhase section */
+
+/* Begin PBXGroup section */
+		0750BF24192CF98400F0FFA9 = {
+			isa = PBXGroup;
+			children = (
+				0750BF3D192CFAEE00F0FFA9 /* sample */,
+				0750BF3B192CFA6100F0FFA9 /* libudis.a */,
+				0750BF2F192CF98400F0FFA9 /* udcli */,
+				0750BF2E192CF98400F0FFA9 /* Products */,
+			);
+			sourceTree = "<group>";
+		};
+		0750BF2E192CF98400F0FFA9 /* Products */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF2D192CF98400F0FFA9 /* udcli */,
+			);
+			name = Products;
+			sourceTree = "<group>";
+		};
+		0750BF2F192CF98400F0FFA9 /* udcli */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF39192CF9BB00F0FFA9 /* udcli.c */,
+			);
+			path = udcli;
+			sourceTree = "<group>";
+		};
+		0750BF3D192CFAEE00F0FFA9 /* sample */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF3E192CFB0300F0FFA9 /* sample_input */,
+			);
+			name = sample;
+			sourceTree = "<group>";
+		};
+/* End PBXGroup section */
+
+/* Begin PBXNativeTarget section */
+		0750BF2C192CF98400F0FFA9 /* udcli */ = {
+			isa = PBXNativeTarget;
+			buildConfigurationList = 0750BF36192CF98400F0FFA9 /* Build configuration list for PBXNativeTarget "udcli" */;
+			buildPhases = (
+				0750BF29192CF98400F0FFA9 /* Sources */,
+				0750BF2A192CF98400F0FFA9 /* Frameworks */,
+				0750BF2B192CF98400F0FFA9 /* CopyFiles */,
+			);
+			buildRules = (
+			);
+			dependencies = (
+			);
+			name = udcli;
+			productName = udcli;
+			productReference = 0750BF2D192CF98400F0FFA9 /* udcli */;
+			productType = "com.apple.product-type.tool";
+		};
+/* End PBXNativeTarget section */
+
+/* Begin PBXProject section */
+		0750BF25192CF98400F0FFA9 /* Project object */ = {
+			isa = PBXProject;
+			attributes = {
+				LastUpgradeCheck = 0510;
+				ORGANIZATIONNAME = "Cryptic Apps";
+			};
+			buildConfigurationList = 0750BF28192CF98400F0FFA9 /* Build configuration list for PBXProject "udcli" */;
+			compatibilityVersion = "Xcode 3.2";
+			developmentRegion = English;
+			hasScannedForEncodings = 0;
+			knownRegions = (
+				en,
+			);
+			mainGroup = 0750BF24192CF98400F0FFA9;
+			productRefGroup = 0750BF2E192CF98400F0FFA9 /* Products */;
+			projectDirPath = "";
+			projectRoot = "";
+			targets = (
+				0750BF2C192CF98400F0FFA9 /* udcli */,
+			);
+		};
+/* End PBXProject section */
+
+/* Begin PBXSourcesBuildPhase section */
+		0750BF29192CF98400F0FFA9 /* Sources */ = {
+			isa = PBXSourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				0750BF3A192CF9BB00F0FFA9 /* udcli.c in Sources */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXSourcesBuildPhase section */
+
+/* Begin XCBuildConfiguration section */
+		0750BF34192CF98400F0FFA9 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ALWAYS_SEARCH_USER_PATHS = NO;
+				CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x";
+				CLANG_CXX_LIBRARY = "libc++";
+				CLANG_ENABLE_MODULES = YES;
+				CLANG_ENABLE_OBJC_ARC = YES;
+				CLANG_WARN_BOOL_CONVERSION = YES;
+				CLANG_WARN_CONSTANT_CONVERSION = YES;
+				CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR;
+				CLANG_WARN_EMPTY_BODY = YES;
+				CLANG_WARN_ENUM_CONVERSION = YES;
+				CLANG_WARN_INT_CONVERSION = YES;
+				CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
+				CLANG_WARN__DUPLICATE_METHOD_MATCH = YES;
+				COPY_PHASE_STRIP = NO;
+				GCC_C_LANGUAGE_STANDARD = gnu99;
+				GCC_DYNAMIC_NO_PIC = NO;
+				GCC_ENABLE_OBJC_EXCEPTIONS = YES;
+				GCC_OPTIMIZATION_LEVEL = 0;
+				GCC_PREPROCESSOR_DEFINITIONS = (
+					"DEBUG=1",
+					"$(inherited)",
+				);
+				GCC_SYMBOLS_PRIVATE_EXTERN = NO;
+				GCC_WARN_64_TO_32_BIT_CONVERSION = YES;
+				GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR;
+				GCC_WARN_UNDECLARED_SELECTOR = YES;
+				GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE;
+				GCC_WARN_UNUSED_FUNCTION = YES;
+				GCC_WARN_UNUSED_VARIABLE = YES;
+				HEADER_SEARCH_PATHS = (
+					"$(inherited)",
+					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
+					$PROJECT_DIR/../libudis86,
+				);
+				MACOSX_DEPLOYMENT_TARGET = 10.9;
+				ONLY_ACTIVE_ARCH = YES;
+				SDKROOT = macosx;
+			};
+			name = Debug;
+		};
+		0750BF35192CF98400F0FFA9 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ALWAYS_SEARCH_USER_PATHS = NO;
+				CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x";
+				CLANG_CXX_LIBRARY = "libc++";
+				CLANG_ENABLE_MODULES = YES;
+				CLANG_ENABLE_OBJC_ARC = YES;
+				CLANG_WARN_BOOL_CONVERSION = YES;
+				CLANG_WARN_CONSTANT_CONVERSION = YES;
+				CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR;
+				CLANG_WARN_EMPTY_BODY = YES;
+				CLANG_WARN_ENUM_CONVERSION = YES;
+				CLANG_WARN_INT_CONVERSION = YES;
+				CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
+				CLANG_WARN__DUPLICATE_METHOD_MATCH = YES;
+				COPY_PHASE_STRIP = YES;
+				DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym";
+				ENABLE_NS_ASSERTIONS = NO;
+				GCC_C_LANGUAGE_STANDARD = gnu99;
+				GCC_ENABLE_OBJC_EXCEPTIONS = YES;
+				GCC_WARN_64_TO_32_BIT_CONVERSION = YES;
+				GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR;
+				GCC_WARN_UNDECLARED_SELECTOR = YES;
+				GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE;
+				GCC_WARN_UNUSED_FUNCTION = YES;
+				GCC_WARN_UNUSED_VARIABLE = YES;
+				HEADER_SEARCH_PATHS = (
+					"$(inherited)",
+					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
+					$PROJECT_DIR/../libudis86,
+				);
+				MACOSX_DEPLOYMENT_TARGET = 10.9;
+				SDKROOT = macosx;
+			};
+			name = Release;
+		};
+		0750BF37192CF98400F0FFA9 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				HEADER_SEARCH_PATHS = (
+					"$(inherited)",
+					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
+					$PROJECT_DIR/../..,
+				);
+				LIBRARY_SEARCH_PATHS = (
+					"$(inherited)",
+					"$(USER_LIBRARY_DIR)/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug",
+				);
+				PRODUCT_NAME = "$(TARGET_NAME)";
+			};
+			name = Debug;
+		};
+		0750BF38192CF98400F0FFA9 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				HEADER_SEARCH_PATHS = (
+					"$(inherited)",
+					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
+					$PROJECT_DIR/../..,
+				);
+				LIBRARY_SEARCH_PATHS = (
+					"$(inherited)",
+					"$(USER_LIBRARY_DIR)/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug",
+				);
+				PRODUCT_NAME = "$(TARGET_NAME)";
+			};
+			name = Release;
+		};
+/* End XCBuildConfiguration section */
+
+/* Begin XCConfigurationList section */
+		0750BF28192CF98400F0FFA9 /* Build configuration list for PBXProject "udcli" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				0750BF34192CF98400F0FFA9 /* Debug */,
+				0750BF35192CF98400F0FFA9 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
+		};
+		0750BF36192CF98400F0FFA9 /* Build configuration list for PBXNativeTarget "udcli" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				0750BF37192CF98400F0FFA9 /* Debug */,
+				0750BF38192CF98400F0FFA9 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+		};
+/* End XCConfigurationList section */
+	};
+	rootObject = 0750BF25192CF98400F0FFA9 /* Project object */;
+}
diff --git a/xcode/udis.xcodeproj/project.pbxproj b/xcode/udis.xcodeproj/project.pbxproj
new file mode 100644
index 0000000..172a70d
--- /dev/null
+++ b/xcode/udis.xcodeproj/project.pbxproj
@@ -0,0 +1,307 @@
+// !$*UTF8*$!
+{
+	archiveVersion = 1;
+	classes = {
+	};
+	objectVersion = 46;
+	objects = {
+
+/* Begin PBXBuildFile section */
+		0750BF11192CF72B00F0FFA9 /* decode.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF07192CF72B00F0FFA9 /* decode.c */; };
+		0750BF12192CF72B00F0FFA9 /* decode.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF08192CF72B00F0FFA9 /* decode.h */; };
+		0750BF13192CF72B00F0FFA9 /* extern.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF09192CF72B00F0FFA9 /* extern.h */; };
+		0750BF14192CF72B00F0FFA9 /* syn-att.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF0A192CF72B00F0FFA9 /* syn-att.c */; };
+		0750BF15192CF72B00F0FFA9 /* syn-intel.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF0B192CF72B00F0FFA9 /* syn-intel.c */; };
+		0750BF16192CF72B00F0FFA9 /* syn.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF0C192CF72B00F0FFA9 /* syn.c */; };
+		0750BF17192CF72B00F0FFA9 /* syn.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF0D192CF72B00F0FFA9 /* syn.h */; };
+		0750BF18192CF72B00F0FFA9 /* types.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF0E192CF72B00F0FFA9 /* types.h */; };
+		0750BF19192CF72B00F0FFA9 /* udint.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF0F192CF72B00F0FFA9 /* udint.h */; };
+		0750BF1A192CF72B00F0FFA9 /* udis86.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF10192CF72B00F0FFA9 /* udis86.c */; };
+		0750BF21192CF93B00F0FFA9 /* itab.c in Sources */ = {isa = PBXBuildFile; fileRef = 0750BF1F192CF93B00F0FFA9 /* itab.c */; };
+		0750BF22192CF93B00F0FFA9 /* itab.h in Headers */ = {isa = PBXBuildFile; fileRef = 0750BF20192CF93B00F0FFA9 /* itab.h */; };
+/* End PBXBuildFile section */
+
+/* Begin PBXFileReference section */
+		0750BF00192CF6B300F0FFA9 /* libudis.a */ = {isa = PBXFileReference; explicitFileType = archive.ar; includeInIndex = 0; path = libudis.a; sourceTree = BUILT_PRODUCTS_DIR; };
+		0750BF07192CF72B00F0FFA9 /* decode.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = decode.c; path = ../libudis86/decode.c; sourceTree = "<group>"; };
+		0750BF08192CF72B00F0FFA9 /* decode.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = decode.h; path = ../libudis86/decode.h; sourceTree = "<group>"; };
+		0750BF09192CF72B00F0FFA9 /* extern.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = extern.h; path = ../libudis86/extern.h; sourceTree = "<group>"; };
+		0750BF0A192CF72B00F0FFA9 /* syn-att.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "syn-att.c"; path = "../libudis86/syn-att.c"; sourceTree = "<group>"; };
+		0750BF0B192CF72B00F0FFA9 /* syn-intel.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "syn-intel.c"; path = "../libudis86/syn-intel.c"; sourceTree = "<group>"; };
+		0750BF0C192CF72B00F0FFA9 /* syn.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = syn.c; path = ../libudis86/syn.c; sourceTree = "<group>"; };
+		0750BF0D192CF72B00F0FFA9 /* syn.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = syn.h; path = ../libudis86/syn.h; sourceTree = "<group>"; };
+		0750BF0E192CF72B00F0FFA9 /* types.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = types.h; path = ../libudis86/types.h; sourceTree = "<group>"; };
+		0750BF0F192CF72B00F0FFA9 /* udint.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = udint.h; path = ../libudis86/udint.h; sourceTree = "<group>"; };
+		0750BF10192CF72B00F0FFA9 /* udis86.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udis86.c; path = ../libudis86/udis86.c; sourceTree = "<group>"; };
+		0750BF1C192CF75300F0FFA9 /* avx.xml */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xml; name = avx.xml; path = ../docs/x86/avx.xml; sourceTree = "<group>"; };
+		0750BF1D192CF75300F0FFA9 /* optable.xml */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.xml; name = optable.xml; path = ../docs/x86/optable.xml; sourceTree = "<group>"; };
+		0750BF1F192CF93B00F0FFA9 /* itab.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = itab.c; path = ../libudis86/itab.c; sourceTree = "<group>"; };
+		0750BF20192CF93B00F0FFA9 /* itab.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = itab.h; path = ../libudis86/itab.h; sourceTree = "<group>"; };
+/* End PBXFileReference section */
+
+/* Begin PBXFrameworksBuildPhase section */
+		0750BEFD192CF6B300F0FFA9 /* Frameworks */ = {
+			isa = PBXFrameworksBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXFrameworksBuildPhase section */
+
+/* Begin PBXGroup section */
+		0750BEF7192CF6B300F0FFA9 = {
+			isa = PBXGroup;
+			children = (
+				0750BF1B192CF73F00F0FFA9 /* xml */,
+				0750BF23192CF94100F0FFA9 /* generated */,
+				0750BF07192CF72B00F0FFA9 /* decode.c */,
+				0750BF08192CF72B00F0FFA9 /* decode.h */,
+				0750BF09192CF72B00F0FFA9 /* extern.h */,
+				0750BF0A192CF72B00F0FFA9 /* syn-att.c */,
+				0750BF0B192CF72B00F0FFA9 /* syn-intel.c */,
+				0750BF0C192CF72B00F0FFA9 /* syn.c */,
+				0750BF0D192CF72B00F0FFA9 /* syn.h */,
+				0750BF0E192CF72B00F0FFA9 /* types.h */,
+				0750BF0F192CF72B00F0FFA9 /* udint.h */,
+				0750BF10192CF72B00F0FFA9 /* udis86.c */,
+				0750BF01192CF6B300F0FFA9 /* Products */,
+			);
+			sourceTree = "<group>";
+		};
+		0750BF01192CF6B300F0FFA9 /* Products */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF00192CF6B300F0FFA9 /* libudis.a */,
+			);
+			name = Products;
+			sourceTree = "<group>";
+		};
+		0750BF1B192CF73F00F0FFA9 /* xml */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF1C192CF75300F0FFA9 /* avx.xml */,
+				0750BF1D192CF75300F0FFA9 /* optable.xml */,
+			);
+			name = xml;
+			sourceTree = "<group>";
+		};
+		0750BF23192CF94100F0FFA9 /* generated */ = {
+			isa = PBXGroup;
+			children = (
+				0750BF1F192CF93B00F0FFA9 /* itab.c */,
+				0750BF20192CF93B00F0FFA9 /* itab.h */,
+			);
+			name = generated;
+			sourceTree = "<group>";
+		};
+/* End PBXGroup section */
+
+/* Begin PBXHeadersBuildPhase section */
+		0750BEFE192CF6B300F0FFA9 /* Headers */ = {
+			isa = PBXHeadersBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				0750BF17192CF72B00F0FFA9 /* syn.h in Headers */,
+				0750BF13192CF72B00F0FFA9 /* extern.h in Headers */,
+				0750BF22192CF93B00F0FFA9 /* itab.h in Headers */,
+				0750BF19192CF72B00F0FFA9 /* udint.h in Headers */,
+				0750BF18192CF72B00F0FFA9 /* types.h in Headers */,
+				0750BF12192CF72B00F0FFA9 /* decode.h in Headers */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXHeadersBuildPhase section */
+
+/* Begin PBXNativeTarget section */
+		0750BEFF192CF6B300F0FFA9 /* udis */ = {
+			isa = PBXNativeTarget;
+			buildConfigurationList = 0750BF04192CF6B300F0FFA9 /* Build configuration list for PBXNativeTarget "udis" */;
+			buildPhases = (
+				0750BF1E192CF76100F0FFA9 /* ShellScript */,
+				0750BEFC192CF6B300F0FFA9 /* Sources */,
+				0750BEFD192CF6B300F0FFA9 /* Frameworks */,
+				0750BEFE192CF6B300F0FFA9 /* Headers */,
+			);
+			buildRules = (
+			);
+			dependencies = (
+			);
+			name = udis;
+			productName = udis;
+			productReference = 0750BF00192CF6B300F0FFA9 /* libudis.a */;
+			productType = "com.apple.product-type.library.static";
+		};
+/* End PBXNativeTarget section */
+
+/* Begin PBXProject section */
+		0750BEF8192CF6B300F0FFA9 /* Project object */ = {
+			isa = PBXProject;
+			attributes = {
+				LastUpgradeCheck = 0510;
+				ORGANIZATIONNAME = "Cryptic Apps";
+			};
+			buildConfigurationList = 0750BEFB192CF6B300F0FFA9 /* Build configuration list for PBXProject "udis" */;
+			compatibilityVersion = "Xcode 3.2";
+			developmentRegion = English;
+			hasScannedForEncodings = 0;
+			knownRegions = (
+				en,
+			);
+			mainGroup = 0750BEF7192CF6B300F0FFA9;
+			productRefGroup = 0750BF01192CF6B300F0FFA9 /* Products */;
+			projectDirPath = "";
+			projectRoot = "";
+			targets = (
+				0750BEFF192CF6B300F0FFA9 /* udis */,
+			);
+		};
+/* End PBXProject section */
+
+/* Begin PBXShellScriptBuildPhase section */
+		0750BF1E192CF76100F0FFA9 /* ShellScript */ = {
+			isa = PBXShellScriptBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+			);
+			inputPaths = (
+				$PROJECT_DIR/../docs/x86/optable.xml,
+				$PROJECT_DIR/../docs/x86/avx.xml,
+			);
+			outputPaths = (
+				$PROJECT_DIR/../itab.c,
+				$PROJECT_DIR/../itab.h,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+			shellPath = /bin/sh;
+			shellScript = "python \"${PROJECT_DIR}/../scripts\"/ud_itab.py \"${PROJECT_DIR}/../docs/x86/optable.xml\" \"${PROJECT_DIR}/../libudis86\"\npython \"${PROJECT_DIR}/../scripts\"/ud_opcode.py\n";
+		};
+/* End PBXShellScriptBuildPhase section */
+
+/* Begin PBXSourcesBuildPhase section */
+		0750BEFC192CF6B300F0FFA9 /* Sources */ = {
+			isa = PBXSourcesBuildPhase;
+			buildActionMask = 2147483647;
+			files = (
+				0750BF16192CF72B00F0FFA9 /* syn.c in Sources */,
+				0750BF21192CF93B00F0FFA9 /* itab.c in Sources */,
+				0750BF14192CF72B00F0FFA9 /* syn-att.c in Sources */,
+				0750BF15192CF72B00F0FFA9 /* syn-intel.c in Sources */,
+				0750BF1A192CF72B00F0FFA9 /* udis86.c in Sources */,
+				0750BF11192CF72B00F0FFA9 /* decode.c in Sources */,
+			);
+			runOnlyForDeploymentPostprocessing = 0;
+		};
+/* End PBXSourcesBuildPhase section */
+
+/* Begin XCBuildConfiguration section */
+		0750BF02192CF6B300F0FFA9 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ALWAYS_SEARCH_USER_PATHS = NO;
+				CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x";
+				CLANG_CXX_LIBRARY = "libc++";
+				CLANG_ENABLE_MODULES = YES;
+				CLANG_ENABLE_OBJC_ARC = YES;
+				CLANG_WARN_BOOL_CONVERSION = YES;
+				CLANG_WARN_CONSTANT_CONVERSION = YES;
+				CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR;
+				CLANG_WARN_EMPTY_BODY = YES;
+				CLANG_WARN_ENUM_CONVERSION = YES;
+				CLANG_WARN_INT_CONVERSION = YES;
+				CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
+				CLANG_WARN__DUPLICATE_METHOD_MATCH = YES;
+				COPY_PHASE_STRIP = NO;
+				GCC_C_LANGUAGE_STANDARD = gnu99;
+				GCC_DYNAMIC_NO_PIC = NO;
+				GCC_ENABLE_OBJC_EXCEPTIONS = YES;
+				GCC_OPTIMIZATION_LEVEL = 0;
+				GCC_PREPROCESSOR_DEFINITIONS = (
+					"DEBUG=1",
+					"$(inherited)",
+				);
+				GCC_SYMBOLS_PRIVATE_EXTERN = NO;
+				GCC_WARN_64_TO_32_BIT_CONVERSION = YES;
+				GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR;
+				GCC_WARN_UNDECLARED_SELECTOR = YES;
+				GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE;
+				GCC_WARN_UNUSED_FUNCTION = YES;
+				GCC_WARN_UNUSED_VARIABLE = YES;
+				MACOSX_DEPLOYMENT_TARGET = 10.9;
+				ONLY_ACTIVE_ARCH = YES;
+				SDKROOT = macosx;
+			};
+			name = Debug;
+		};
+		0750BF03192CF6B300F0FFA9 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				ALWAYS_SEARCH_USER_PATHS = NO;
+				CLANG_CXX_LANGUAGE_STANDARD = "gnu++0x";
+				CLANG_CXX_LIBRARY = "libc++";
+				CLANG_ENABLE_MODULES = YES;
+				CLANG_ENABLE_OBJC_ARC = YES;
+				CLANG_WARN_BOOL_CONVERSION = YES;
+				CLANG_WARN_CONSTANT_CONVERSION = YES;
+				CLANG_WARN_DIRECT_OBJC_ISA_USAGE = YES_ERROR;
+				CLANG_WARN_EMPTY_BODY = YES;
+				CLANG_WARN_ENUM_CONVERSION = YES;
+				CLANG_WARN_INT_CONVERSION = YES;
+				CLANG_WARN_OBJC_ROOT_CLASS = YES_ERROR;
+				CLANG_WARN__DUPLICATE_METHOD_MATCH = YES;
+				COPY_PHASE_STRIP = YES;
+				DEBUG_INFORMATION_FORMAT = "dwarf-with-dsym";
+				ENABLE_NS_ASSERTIONS = NO;
+				GCC_C_LANGUAGE_STANDARD = gnu99;
+				GCC_ENABLE_OBJC_EXCEPTIONS = YES;
+				GCC_WARN_64_TO_32_BIT_CONVERSION = YES;
+				GCC_WARN_ABOUT_RETURN_TYPE = YES_ERROR;
+				GCC_WARN_UNDECLARED_SELECTOR = YES;
+				GCC_WARN_UNINITIALIZED_AUTOS = YES_AGGRESSIVE;
+				GCC_WARN_UNUSED_FUNCTION = YES;
+				GCC_WARN_UNUSED_VARIABLE = YES;
+				MACOSX_DEPLOYMENT_TARGET = 10.9;
+				SDKROOT = macosx;
+			};
+			name = Release;
+		};
+		0750BF05192CF6B300F0FFA9 /* Debug */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				EXECUTABLE_PREFIX = lib;
+				PRODUCT_NAME = "$(TARGET_NAME)";
+			};
+			name = Debug;
+		};
+		0750BF06192CF6B300F0FFA9 /* Release */ = {
+			isa = XCBuildConfiguration;
+			buildSettings = {
+				EXECUTABLE_PREFIX = lib;
+				PRODUCT_NAME = "$(TARGET_NAME)";
+			};
+			name = Release;
+		};
+/* End XCBuildConfiguration section */
+
+/* Begin XCConfigurationList section */
+		0750BEFB192CF6B300F0FFA9 /* Build configuration list for PBXProject "udis" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				0750BF02192CF6B300F0FFA9 /* Debug */,
+				0750BF03192CF6B300F0FFA9 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
+		};
+		0750BF04192CF6B300F0FFA9 /* Build configuration list for PBXNativeTarget "udis" */ = {
+			isa = XCConfigurationList;
+			buildConfigurations = (
+				0750BF05192CF6B300F0FFA9 /* Debug */,
+				0750BF06192CF6B300F0FFA9 /* Release */,
+			);
+			defaultConfigurationIsVisible = 0;
+		};
+/* End XCConfigurationList section */
+	};
+	rootObject = 0750BEF8192CF6B300F0FFA9 /* Project object */;
+}
diff --git a/xcode/udis.xcworkspace/contents.xcworkspacedata b/xcode/udis.xcworkspace/contents.xcworkspacedata
new file mode 100644
index 0000000..94f744d
--- /dev/null
+++ b/xcode/udis.xcworkspace/contents.xcworkspacedata
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Workspace
+   version = "1.0">
+   <FileRef
+      location = "group:udcli/udcli.xcodeproj">
+   </FileRef>
+   <FileRef
+      location = "group:udis.xcodeproj">
+   </FileRef>
+</Workspace>

From 07271f87d30317054ce1dff129302b4e7de08cbb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20Be=CC=81nony?= <vincent.benony@me.com>
Date: Wed, 21 May 2014 17:25:36 +0200
Subject: [PATCH 17/20] Fix the udcli.c file path.

---
 xcode/udcli/udcli.xcodeproj/project.pbxproj | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xcode/udcli/udcli.xcodeproj/project.pbxproj b/xcode/udcli/udcli.xcodeproj/project.pbxproj
index b59effe..330e821 100644
--- a/xcode/udcli/udcli.xcodeproj/project.pbxproj
+++ b/xcode/udcli/udcli.xcodeproj/project.pbxproj
@@ -25,7 +25,7 @@
 
 /* Begin PBXFileReference section */
 		0750BF2D192CF98400F0FFA9 /* udcli */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = udcli; sourceTree = BUILT_PRODUCTS_DIR; };
-		0750BF39192CF9BB00F0FFA9 /* udcli.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udcli.c; path = ../../../udcli/udcli.c; sourceTree = "<group>"; };
+		0750BF39192CF9BB00F0FFA9 /* udcli.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = udcli.c; path = ../../udcli/udcli.c; sourceTree = SOURCE_ROOT; };
 		0750BF3B192CFA6100F0FFA9 /* libudis.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; name = libudis.a; path = "../../../../Library/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug/libudis.a"; sourceTree = "<group>"; };
 		0750BF3E192CFB0300F0FFA9 /* sample_input */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = sample_input; sourceTree = "<group>"; };
 /* End PBXFileReference section */
@@ -265,6 +265,7 @@
 				0750BF38192CF98400F0FFA9 /* Release */,
 			);
 			defaultConfigurationIsVisible = 0;
+			defaultConfigurationName = Release;
 		};
 /* End XCConfigurationList section */
 	};

From 1c8dd143807a4bccacc4d9328da20e13dbdf64df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20Be=CC=81nony?= <vincent.benony@me.com>
Date: Wed, 21 May 2014 18:33:03 +0200
Subject: [PATCH 18/20] Change sample file with an AVX2 instruction.

---
 xcode/udcli/sample_input | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xcode/udcli/sample_input b/xcode/udcli/sample_input
index 25b936d..f204a83 100644
--- a/xcode/udcli/sample_input
+++ b/xcode/udcli/sample_input
@@ -1 +1 @@
-90 90 90
\ No newline at end of file
+C4 E2 7D 18 C0
\ No newline at end of file

From 6dae47f7884ca4ef1f9a9cfcd62057c1fd6dee56 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Thu, 2 Apr 2015 10:47:18 +0200
Subject: [PATCH 19/20] Fix an error on SSE movsd implicit register list.

---
 docs/x86/optable.xml | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 89598c2..71bf407 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -5509,6 +5509,8 @@
         <first_operand_access>W</first_operand_access>
         <implicit_register_use>rsi</implicit_register_use>
         <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg</pfx>
@@ -5521,6 +5523,8 @@
         <first_operand_access>W</first_operand_access>
         <implicit_register_use>rsi</implicit_register_use>
         <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>
@@ -5531,10 +5535,12 @@
     <instruction>
         <mnemonic>movsd</mnemonic>
         <first_operand_access>W</first_operand_access>
-        <implicit_register_use>rsi</implicit_register_use>
-        <implicit_register_def>rsi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
+            <implicit_register_use>rsi</implicit_register_use>
+            <implicit_register_def>rsi</implicit_register_def>
+            <implicit_register_use>rdi</implicit_register_use>
+            <implicit_register_def>rdi</implicit_register_def>
             <pfx>rep seg oso rexw</pfx>
             <opc>a5 /o=32</opc>
         </def>
@@ -5557,6 +5563,8 @@
         <first_operand_access>W</first_operand_access>
         <implicit_register_use>rsi</implicit_register_use>
         <implicit_register_def>rsi</implicit_register_def>
+        <implicit_register_use>rdi</implicit_register_use>
+        <implicit_register_def>rdi</implicit_register_def>
         <eflags>________T__</eflags>
         <def>
             <pfx>rep seg oso rexw</pfx>

From a9efff534e0c327a244f4172e5e3e4fc10f8bcaa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vincent=20B=C3=A9nony?= <vbenony@nordnet.fr>
Date: Thu, 2 Apr 2015 10:47:46 +0200
Subject: [PATCH 20/20] Misc fixes

---
 libudis86/decode.c                            |  4 +-
 libudis86/syn.c                               |  2 +-
 libudis86/udis86.c                            |  2 +-
 xcode/udcli/udcli.xcodeproj/project.pbxproj   | 10 +----
 .../xcshareddata/udis.xccheckout              | 41 +++++++++++++++++++
 5 files changed, 47 insertions(+), 12 deletions(-)
 create mode 100644 xcode/udis.xcworkspace/xcshareddata/udis.xccheckout

diff --git a/libudis86/decode.c b/libudis86/decode.c
index 841924c..0929cca 100644
--- a/libudis86/decode.c
+++ b/libudis86/decode.c
@@ -668,7 +668,7 @@ decode_modrm_rm(struct ud         *u,
   }
 
   if (offset) {
-    decode_mem_disp(u, offset, op);
+    decode_mem_disp(u, (unsigned int) offset, op);
   } else {
     op->offset = 0;
   }
@@ -1276,7 +1276,7 @@ ud_decode(struct ud *u)
   u->pc += u->inp_ctr;    /* move program counter by bytes decoded */
 
   /* return number of bytes disassembled. */
-  return u->inp_ctr;
+  return (unsigned int) u->inp_ctr;
 }
 
 /*
diff --git a/libudis86/syn.c b/libudis86/syn.c
index 8e64fc2..b32e32b 100644
--- a/libudis86/syn.c
+++ b/libudis86/syn.c
@@ -122,7 +122,7 @@ ud_asmprintf(struct ud *u, const char *fmt, ...)
   int avail;
   va_list ap;
   va_start(ap, fmt);
-  avail = u->asm_buf_size - u->asm_buf_fill - 1 /* nullchar */;
+  avail = (int) (u->asm_buf_size - u->asm_buf_fill - 1 /* nullchar */);
   ret = vsnprintf((char*) u->asm_buf + u->asm_buf_fill, avail, fmt, ap);
   if (ret < 0 || ret > avail) {
       u->asm_buf_fill = u->asm_buf_size - 1;
diff --git a/libudis86/udis86.c b/libudis86/udis86.c
index b52cdf0..0b92570 100644
--- a/libudis86/udis86.c
+++ b/libudis86/udis86.c
@@ -201,7 +201,7 @@ ud_insn_ptr(const struct ud* u)
 extern unsigned int
 ud_insn_len(const struct ud* u)
 {
-  return u->inp_ctr;
+  return (unsigned int) u->inp_ctr;
 }
 
 
diff --git a/xcode/udcli/udcli.xcodeproj/project.pbxproj b/xcode/udcli/udcli.xcodeproj/project.pbxproj
index 330e821..e528d0a 100644
--- a/xcode/udcli/udcli.xcodeproj/project.pbxproj
+++ b/xcode/udcli/udcli.xcodeproj/project.pbxproj
@@ -222,10 +222,7 @@
 					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
 					$PROJECT_DIR/../..,
 				);
-				LIBRARY_SEARCH_PATHS = (
-					"$(inherited)",
-					"$(USER_LIBRARY_DIR)/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug",
-				);
+				LIBRARY_SEARCH_PATHS = "$(inherited)";
 				PRODUCT_NAME = "$(TARGET_NAME)";
 			};
 			name = Debug;
@@ -238,10 +235,7 @@
 					/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include,
 					$PROJECT_DIR/../..,
 				);
-				LIBRARY_SEARCH_PATHS = (
-					"$(inherited)",
-					"$(USER_LIBRARY_DIR)/Developer/Xcode/DerivedData/udis-cxhtywlfqipmbpakmbnrzkfnbegd/Build/Products/Debug",
-				);
+				LIBRARY_SEARCH_PATHS = "$(inherited)";
 				PRODUCT_NAME = "$(TARGET_NAME)";
 			};
 			name = Release;
diff --git a/xcode/udis.xcworkspace/xcshareddata/udis.xccheckout b/xcode/udis.xcworkspace/xcshareddata/udis.xccheckout
new file mode 100644
index 0000000..d3f87e1
--- /dev/null
+++ b/xcode/udis.xcworkspace/xcshareddata/udis.xccheckout
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+	<key>IDESourceControlProjectFavoriteDictionaryKey</key>
+	<false/>
+	<key>IDESourceControlProjectIdentifier</key>
+	<string>980919F3-84FE-4C51-AF58-3EA27FDB10DC</string>
+	<key>IDESourceControlProjectName</key>
+	<string>udis</string>
+	<key>IDESourceControlProjectOriginsDictionary</key>
+	<dict>
+		<key>47C64E3B-8DF9-411A-AF46-BDA10C0F0122</key>
+		<string>file:///Users/bsr/Dropbox/GIT/repos/udis86.git/</string>
+	</dict>
+	<key>IDESourceControlProjectPath</key>
+	<string>xcode/udis.xcworkspace</string>
+	<key>IDESourceControlProjectRelativeInstallPathDictionary</key>
+	<dict>
+		<key>47C64E3B-8DF9-411A-AF46-BDA10C0F0122</key>
+		<string>../..</string>
+	</dict>
+	<key>IDESourceControlProjectURL</key>
+	<string>file:///Users/bsr/Dropbox/GIT/repos/udis86.git/</string>
+	<key>IDESourceControlProjectVersion</key>
+	<integer>110</integer>
+	<key>IDESourceControlProjectWCCIdentifier</key>
+	<string>47C64E3B-8DF9-411A-AF46-BDA10C0F0122</string>
+	<key>IDESourceControlProjectWCConfigurations</key>
+	<array>
+		<dict>
+			<key>IDESourceControlRepositoryExtensionIdentifierKey</key>
+			<string>public.vcs.git</string>
+			<key>IDESourceControlWCCIdentifierKey</key>
+			<string>47C64E3B-8DF9-411A-AF46-BDA10C0F0122</string>
+			<key>IDESourceControlWCCName</key>
+			<string>udis86</string>
+		</dict>
+	</array>
+</dict>
+</plist>