ThreadStore: guard AMDGCN inline asm with __HIP_PLATFORM_SPIRV__#1
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ThreadStore: guard AMDGCN inline asm with __HIP_PLATFORM_SPIRV__#1
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The AMDGCN inline-asm specializations (flat_store_*, s_waitcnt) in HIPCUB_ASM_THREAD_STORE are meaningless on non-AMD targets. On SPIR-V targets (chipStar) they survive into the IR and crash SPIRV-LLVM-Translator at SPVWriter.cpp:5598 with a null-deref on InlineAsm call sites when SPV_INTEL_inline_assembly is not in the translator's extension allow-list. Gate the asm block on !defined(__HIP_PLATFORM_SPIRV__) so SPIR-V targets fall back to the existing __builtin_memcpy implementation of AsmThreadStore. AMD behavior is unchanged. Unblocks test_hipcub_thread under chipStar (all 100 gtest cases now pass on Arc A770 / Level Zero).
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Summary
AMDGCN inline-asm specializations in
HIPCUB_ASM_THREAD_STORE(flat_store_*,s_waitcnt) are meaningless on non-AMD targets. On SPIR-V targets (chipStar) they survive into the IR and crash SPIRV-LLVM-Translator atSPVWriter.cpp:5598with a null-deref onInlineAsmcall sites whenSPV_INTEL_inline_assemblyis not in the translator's extension allow-list.One-line fix: gate the existing
#if HIPCUB_THREAD_STORE_USE_CACHE_MODIFIERS == 1block on!defined(__HIP_PLATFORM_SPIRV__)so SPIR-V falls back to the already-present__builtin_memcpy-basedAsmThreadStore.Behavior
AsmThreadStoreresolves to the generic__builtin_memcpyfallback instead of emittingflat_store_dword ... glcContext
This is the library-side fix that complements chipStar PR CHIP-SPV/chipStar#1236, which strips AMDGCN inline asm in a chipStar LLVM pass as a defense-in-depth backstop. This PR is the right long-term fix for hipCUB specifically.
Test plan
test_hipcub_threadbuilds and all 100 gtest cases PASS on Arc A770 / Level Zero (chipStar)