[BugFix][Quant] Guard scale tails and FP32 absmax#4
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The full H100/CuTeDSL correctness run covers token and hidden sizes that do not land exactly on the kernel tile, scaling-factor block, or E5M6 packing granularity. Those edge tiles exposed two independent quantization issues. First, cast-back and lossless/per-token cast kernels could load or store scaling factors for padded token/channel blocks. The same edge condition also applied to packed E5M6 output rows and columns, where the final tile may not contain a full logical token row or hidden group. Second, per-token scale generation used in_config.dtype as the absmax fragment dtype. That dtype describes the input tensor storage, not the reduction accumulator. For BF16 and narrow quantization paths, keeping absmax in the input dtype can round or overflow the scale path before the final output cast, producing byte mismatches against the PyTorch reference. Guard scale loads/stores and packed E5M6 stores with the real token/channel extents, keep invalid scale lanes zero-initialized, and use FP32 fragments for per-token absmax reductions before computing the reciprocal scale. Co-authored-by: dingsg <shengge.ding@enflame-tech.com>
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Duplicate fork-local PR. The complete Quant fix is now tracked upstream by updating deepseek-ai#15; deepseek-ai#16 was closed as superseded. |
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Context
The full H100/CuTeDSL correctness run covers quantization shapes where token counts, hidden sizes, scale blocks, and packed E5M6 groups do not always land exactly on a kernel tile boundary.
That exposed two TileKernels-side issues:
in_config.dtypeas the absmax fragment dtype, even though that dtype describes input storage rather than the reduction accumulator.For BF16 and narrow quantization paths, using the input storage dtype as the absmax accumulator can round or overflow the scale path before the final cast, producing byte mismatches against the PyTorch reference.
Fix
T.float32fragments for per-token absmax reductions before computing reciprocal scales.Why this is a TileKernels fix
These are kernel-level bounds and accumulator-dtype issues. The implementation schedules aligned tile work for performance, but memory accesses and reduction precision must still follow the logical tensor/scaling-factor layout. The fix is not tied to one CuTeDSL package version.
Validation
Validated as part of the H100 PCIe CuTeDSL full correctness and benchmark run after the matching TileLang CuTeDSL fixes were applied.
Local sanity checks for this split branch:
git diff --check origin/main..82fbd40ruff checkon the changed TileKernels Python files