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[pull] master from vosen:master#8
pull[bot] wants to merge 398 commits into
banerRana:masterfrom
vosen:master

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@pull pull Bot commented Apr 29, 2024

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@pull pull Bot added ⤵️ pull merge-conflict Resolve conflicts manually labels Aug 9, 2024
vosen and others added 12 commits September 4, 2024 15:47
Replaces traditional LALRPOP-based parser with winnow-based parser to handle out-of-order instruction modifer. Generate instruction type and instruction visitor from a macro instead of writing by hand. Add separate compilation path using the new parser that only works in tests for now
This is very incomplete. Just enough code to emit LLVM bitcode and continue further development
The overarching goal is to refactor all passes so they are module-scoped and not function-scoped. Additionally, make improvements to the most egregiously buggy/unfit passes (so the code is ready for the next major features: linking, ftz handling) and continue adding more code to the LLVM backend
Additionally remove unused compilation paths
It's weird that it fails without `-mno-link-builtin-bitcode-postopt`. I've tested it only on ROCm 6.2, might be broken on older or newer ROCm
zluda-violet and others added 30 commits January 15, 2026 13:28
* Refactor emit_intrinsic to allow struct return type

* Implement extended precision integer addition

Uses `llvm.*add.with.overflow.*`. That intrinsic does not take a carry argument, so handling carry in requires multiple additions and combining the carry out, but the AMDGPU target is able to translate that pattern into a single instruction.

These four PTX instructions:

```
    add.cc.u32      r0, a0, b0;
    addc.cc.u32     r1, a1, b1;
    addc.cc.u32     r2, a2, b2;
    addc.u32        r3, a3, b3;
```

are translated into four RDNA3 instructions:

```
    v_add_co_u32 v0, vcc_lo, v0, v4
    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v6, vcc_lo
    v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo
```

* cargo fmt

* Rename to match convention

* cargo fmt
Adds `sub.cc`, `subc`, `subc.cc`, `mad.cc`, `madc`, and `madc.cc` on top of the work done in #607
Support cuMemAllocPitch_v2 and cuMemcpy2D_v2 and some other memory-related functions
Same cleanup as #610 did for emit_clz: replaces the hand-rolled
LLVMGetNamedFunction/LLVMAddFunction/LLVMBuildCall2 sequence with a
call to the existing emit_intrinsic helper. Output IR is unchanged,
the brev_llvm test fixture already expects the standard
@llvm.bitreverse.iN intrinsic call form that emit_intrinsic produces.
Rename the parameter to match the function name and align with the
sibling functions emit_vector_write and emit_vector_repack which name
their parameters after their argument types/intent. No behavior change.
The `?` operator already converts the error type via the `From` trait,
and `CompilerError` has `#[from]` impls (or explicit From impls) for
`io::Error`, `Utf8Error`, `Vec<PtxError<'_>>`, `TranslateError`, and
trivially for `CompilerError` itself. The explicit map_err calls are
no-ops. No behavior change.
This does not add full 32 bit support, just support in the compiler for a special 32bit on 64 bit mode. I expected the changes to be much smaller, but since they are so wide-reaching I prefer to get this piece out as soon as possible
Add cuCtxCreate_v4 and exit and a broken printf implementation
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