Added support for symbol relocation for RISC-V architecture#613
Added support for symbol relocation for RISC-V architecture#613adjordjevic-TT wants to merge 16 commits intoeliben:mainfrom
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@eliben Can you take a look at this? |
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@sevaa any concerns? |
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Looks in line with how relocation is handled for other architectures. Is there any way to test this? |
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Would it be enough to just provide arbitrary elf that uses RISCV relocations and just to add it to testfiles or those elfs have some specific content? @sevaa |
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An erroneously written piece of relocation logic most likely will not crash; it will produce wrong bits in the loaded section. How does one test that? |
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Ideally, we can create elf that uses RISCV relocations with some functions/variables and if we are able to find those symbols relocations are working properly, but I don't think it is practical to test every sing one relocation type. Everything that is implemented is taken from here: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#reloc-table |
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If @eliben says it's OK not to test this exhaustively, I will be OK with that :) |
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@adjordjevic-TT can you say what you're using these RISC-V relocations for? (in other words, why this PR?) @sevaa several of the readelf comparison tests rely on correct implementation of relocations. Wouldn't a file compiled for RISC-V with relocations inside therefore exercise this logic? |
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We are using it for finding variable's address or value and for implementing backtracing (callstack) for kernels that are running on our hardware that is based on RISCV arch. |
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@adjordjevic-TT could you add a simple unit test? Look at the other unit tests in the |
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The only sections that are parsed, dumped, and compared by the readelf test are the DWARF ones and notes; in executable/SO binaries, relocations against those are rare (none in the corpus, last time I checked). Were we to dump and compare the disassembly, though, or the initialized global data section, that would be the test. |
Let's continue this discussion in #601 |
Tests the RISC-V-specific calc functions (SET6/SUB6) with known inputs/outputs, and verifies the relocation recipe table has correct bytesizes and calc functions assigned for all supported types. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Adds riscv_reloc.o (a minimal hand-crafted RISC-V 64-bit relocatable ELF) and riscv_reloc_gen.py (the generator script with build instructions). The new TestRISCVRelocationEndToEnd test applies R_RISCV_32, R_RISCV_64, R_RISCV_SET6, and R_RISCV_SUB6 relocations via RelocationHandler and verifies the resulting bytes are correct. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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What are we testing exactly by that? I thought the idea was to test the parser of binaries against third party generators thereof, that is - publicly available compilers and linkers. Hand composing a binary defeats that purpose. |
Replace the hand-crafted riscv_reloc_gen.py with riscv_reloc_source.s,
a GNU assembly source that uses explicit .reloc directives to produce
the same four relocation types (R_RISCV_32, R_RISCV_64, R_RISCV_SET6,
R_RISCV_SUB6). The .o file is now compiled with:
riscv64-linux-gnu-gcc -c riscv_reloc_source.s -o riscv_reloc.o
Tested with riscv64-linux-gnu-gcc 11.4.0 / GNU Binutils 2.38.
Note: the assembler folds absolute symbol values into the RELA addend
(sym_idx=0), which is equivalent to the prior named-symbol approach.
All 18 tests continue to pass.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sevaa Is this what you've had in mind? If it is I will add tests for rest of relocation types. |
Extend riscv_reloc_source.s with 11 new .reloc entries covering SET8/16/32, ADD8/16/32/64, and SUB8/16/32/64. Recompile riscv_reloc.o. Add three new test methods to TestRISCVRelocationEndToEnd: - test_riscv_set8_set16_set32 - test_riscv_add8_add16_add32_add64 - test_riscv_sub8_sub16_sub32_sub64 Tests look up byte offsets dynamically from the RELA section rather than hardcoding them, so they are robust to future assembly changes. All 21 tests pass. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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It's still handcrafted, just in a different language. Don't you have a GCC for RISC-V? Build a Hello world in C, see if there are any relocs in it. |
3 participants
Added support for symbol relocation for RISC-V architecture.
Added ENUM_RELOC_TYPE_RISCV to enums.py
Added _RELOCATION_RECIPES_RISCV, two more relocation functions (_reloc_calc_value_plus_sym_6 and _reloc_calc_value_minus_sym_addend_6) and case when e-machine is RISC-V to relocation.py.