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[MCXA] WIP: Update with regenerated MCXA256 PAC #5561

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3 changes: 2 additions & 1 deletion embassy-mcxa/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ embedded-io = "0.7"
embedded-io-async = { version = "0.7.0" }
heapless = "0.9"
maitake-sync = { version = "0.2.2", default-features = false, features = ["critical-section", "no-cache-pad"] }
nxp-pac = { git = "https://github.com/embassy-rs/nxp-pac.git", rev = "718f9c0e9783321119e8c56f74f0d8d630ca4d9e", features = ["rt"] }
nxp-pac = { git = "https://github.com/embassy-rs/nxp-pac.git", rev = "9c52adff355603becd939b032a9368e20883d93e", features = ["rt"] }
nb = "1.1.0"
paste = "1.0.15"

Expand Down Expand Up @@ -129,3 +129,4 @@ custom-executor = []
#
mcxa2xx = ["nxp-pac/mcxa256"]
mcxa5xx = ["nxp-pac/mcxa577"]

120 changes: 60 additions & 60 deletions embassy-mcxa/src/adc.rs
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Expand Up @@ -886,7 +886,7 @@ macro_rules! impl_instance {
};
}

impl_instance!(0, 1, 2, 3);
impl_instance!(0, 1);

/// Trait implemented by any possible ADC pin
pub trait AdcPin<T: Instance>: sealed::SealedAdcPin<T> + GpioPin + PeripheralType {
Expand Down Expand Up @@ -1033,62 +1033,62 @@ impl_pin!(P3_31, ADC1, 20);
impl_pin!(P3_30, ADC1, 21);
impl_pin!(P3_29, ADC1, 22);

impl_pin!(P2_4, ADC2, 0);
impl_pin!(P2_10, ADC2, 1);
impl_pin!(P4_4, ADC2, 2);
// impl_pin!(P2_24, ADC2, 255); ???
impl_pin!(P2_16, ADC2, 4);
impl_pin!(P2_12, ADC2, 5);
impl_pin!(P2_20, ADC2, 6);
impl_pin!(P2_7, ADC2, 7);
#[cfg(feature = "swd-swo-as-gpio")]
impl_pin!(P0_2, ADC2, 8);
// ???
// impl_pin!(P0_4, ADC2, 255);
// impl_pin!(P0_5, ADC2, 255);
// impl_pin!(P0_6, ADC2, 255);
// impl_pin!(P0_7, ADC2, 255);
// impl_pin!(P0_12, ADC2, 255);
// impl_pin!(P0_13, ADC2, 255);
// ???
impl_pin!(P0_14, ADC2, 14);
impl_pin!(P0_15, ADC2, 15);
// ???
// impl_pin!(P4_0, ADC2, 255);
// impl_pin!(P4_1, ADC2, 255);
// ???
impl_pin!(P4_2, ADC2, 18);
impl_pin!(P4_3, ADC2, 19);
//impl_pin!(P4_4, ADC2, 20); // Conflit with ADC2_A3 and ADC2_A20 using the same pin
impl_pin!(P4_5, ADC2, 21);
impl_pin!(P4_6, ADC2, 22);
impl_pin!(P4_7, ADC2, 23);

impl_pin!(P2_5, ADC3, 0);
impl_pin!(P2_11, ADC3, 1);
impl_pin!(P2_23, ADC3, 2);
// impl_pin!(P2_25, ADC3, 255); // ???
impl_pin!(P2_17, ADC3, 4);
impl_pin!(P2_13, ADC3, 5);
impl_pin!(P2_21, ADC3, 6);
impl_pin!(P2_7, ADC3, 7);
// ???
// impl_pin!(P3_2, ADC3, 255);
// impl_pin!(P3_3, ADC3, 255);
// impl_pin!(P3_4, ADC3, 255);
// impl_pin!(P3_5, ADC3, 255);
// ???
impl_pin!(P3_6, ADC3, 12);
impl_pin!(P3_7, ADC3, 13);
impl_pin!(P3_12, ADC3, 14);
impl_pin!(P3_13, ADC3, 15);
impl_pin!(P3_14, ADC3, 16);
impl_pin!(P3_15, ADC3, 17);
impl_pin!(P3_20, ADC3, 18);
impl_pin!(P3_21, ADC3, 19);
impl_pin!(P3_22, ADC3, 20);
// ???
// impl_pin!(P3_23, ADC3, 255);
// impl_pin!(P3_24, ADC3, 255);
// impl_pin!(P3_25, ADC3, 255);
// ???
// impl_pin!(P2_4, ADC2, 0);
// impl_pin!(P2_10, ADC2, 1);
// impl_pin!(P4_4, ADC2, 2);
// // impl_pin!(P2_24, ADC2, 255); ???
// impl_pin!(P2_16, ADC2, 4);
// impl_pin!(P2_12, ADC2, 5);
// impl_pin!(P2_20, ADC2, 6);
// impl_pin!(P2_7, ADC2, 7);
// #[cfg(feature = "swd-swo-as-gpio")]
// impl_pin!(P0_2, ADC2, 8);
// // ???
// // impl_pin!(P0_4, ADC2, 255);
// // impl_pin!(P0_5, ADC2, 255);
// // impl_pin!(P0_6, ADC2, 255);
// // impl_pin!(P0_7, ADC2, 255);
// // impl_pin!(P0_12, ADC2, 255);
// // impl_pin!(P0_13, ADC2, 255);
// // ???
// impl_pin!(P0_14, ADC2, 14);
// impl_pin!(P0_15, ADC2, 15);
// // ???
// // impl_pin!(P4_0, ADC2, 255);
// // impl_pin!(P4_1, ADC2, 255);
// // ???
// impl_pin!(P4_2, ADC2, 18);
// impl_pin!(P4_3, ADC2, 19);
// //impl_pin!(P4_4, ADC2, 20); // Conflit with ADC2_A3 and ADC2_A20 using the same pin
// impl_pin!(P4_5, ADC2, 21);
// impl_pin!(P4_6, ADC2, 22);
// impl_pin!(P4_7, ADC2, 23);

// impl_pin!(P2_5, ADC3, 0);
// impl_pin!(P2_11, ADC3, 1);
// impl_pin!(P2_23, ADC3, 2);
// // impl_pin!(P2_25, ADC3, 255); // ???
// impl_pin!(P2_17, ADC3, 4);
// impl_pin!(P2_13, ADC3, 5);
// impl_pin!(P2_21, ADC3, 6);
// impl_pin!(P2_7, ADC3, 7);
// // ???
// // impl_pin!(P3_2, ADC3, 255);
// // impl_pin!(P3_3, ADC3, 255);
// // impl_pin!(P3_4, ADC3, 255);
// // impl_pin!(P3_5, ADC3, 255);
// // ???
// impl_pin!(P3_6, ADC3, 12);
// impl_pin!(P3_7, ADC3, 13);
// impl_pin!(P3_12, ADC3, 14);
// impl_pin!(P3_13, ADC3, 15);
// impl_pin!(P3_14, ADC3, 16);
// impl_pin!(P3_15, ADC3, 17);
// impl_pin!(P3_20, ADC3, 18);
// impl_pin!(P3_21, ADC3, 19);
// impl_pin!(P3_22, ADC3, 20);
// // ???
// // impl_pin!(P3_23, ADC3, 255);
// // impl_pin!(P3_24, ADC3, 255);
// // impl_pin!(P3_25, ADC3, 255);
// // ???
17 changes: 4 additions & 13 deletions embassy-mcxa/src/chips/mcxa2xx.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,11 @@ mod inner_periph {
embassy_hal_internal::peripherals!(
ADC0,
ADC1,
ADC2,
ADC3,

AOI0,
AOI1,

CAN0,
CAN1,

CDOG0,
CDOG1,
Expand Down Expand Up @@ -115,7 +112,6 @@ mod inner_periph {
LPUART2,
LPUART3,
LPUART4,
LPUART5,

MAU0,
MBC0,
Expand Down Expand Up @@ -369,16 +365,16 @@ mod inner_interrupt {
embassy_hal_internal::interrupt_mod!(
ADC0,
ADC1,
ADC2,
ADC3,
// ADC2,
// ADC3,
CAN0,
CAN1,
// CAN1,
CDOG0,
CDOG1,
CMC,
CMP0,
CMP1,
CMP2,
// CMP2,
CTIMER0,
CTIMER1,
CTIMER2,
Expand Down Expand Up @@ -437,7 +433,6 @@ mod inner_interrupt {
LPUART2,
LPUART3,
LPUART4,
LPUART5,
MAU,
MBC0,
OS_EVENT,
Expand All @@ -446,7 +441,6 @@ mod inner_interrupt {
RTC_1HZ,
SCG0,
SGI,
SLCD,
SMARTDMA,
SPC0,
TDET,
Expand Down Expand Up @@ -747,8 +741,6 @@ pub(crate) mod peripheral_gating {
// clocks do not match their needs.
impl_cc_gate!(ADC0, mrcc_glb_cc1, mrcc_glb_rst1, adc0, AdcConfig);
impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig);
impl_cc_gate!(ADC2, mrcc_glb_cc1, mrcc_glb_rst1, adc2, AdcConfig);
impl_cc_gate!(ADC3, mrcc_glb_cc1, mrcc_glb_rst1, adc3, AdcConfig);

impl_cc_gate!(I3C0, mrcc_glb_cc0, mrcc_glb_rst0, i3c0, I3cConfig);
impl_cc_gate!(CTIMER0, mrcc_glb_cc0, mrcc_glb_rst0, ctimer0, CTimerConfig);
Expand All @@ -767,7 +759,6 @@ pub(crate) mod peripheral_gating {
impl_cc_gate!(LPUART2, mrcc_glb_acc0, mrcc_glb_rst0, lpuart2, LpuartConfig);
impl_cc_gate!(LPUART3, mrcc_glb_acc0, mrcc_glb_rst0, lpuart3, LpuartConfig);
impl_cc_gate!(LPUART4, mrcc_glb_acc0, mrcc_glb_rst0, lpuart4, LpuartConfig);
impl_cc_gate!(LPUART5, mrcc_glb_acc1, mrcc_glb_rst1, lpuart5, LpuartConfig);

// DMA0 peripheral - uses NoConfig since it has no selectable clock source
impl_cc_gate!(DMA0, mrcc_glb_acc0, mrcc_glb_rst0, dma0, NoConfig);
Expand Down
6 changes: 3 additions & 3 deletions embassy-mcxa/src/clocks/periph_helpers/mcxa2xx.rs
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Expand Up @@ -362,8 +362,8 @@ pub enum LpuartInstance {
Lpuart3,
/// Instance 4
Lpuart4,
/// Instance 5
Lpuart5,
// /// Instance 5
// Lpuart5,
}

/// Top level configuration for `Lpuart` instances.
Expand All @@ -390,7 +390,7 @@ impl SPConfHelper for LpuartConfig {
LpuartInstance::Lpuart2 => (mrcc0.mrcc_lpuart2_clkdiv(), mrcc0.mrcc_lpuart2_clksel()),
LpuartInstance::Lpuart3 => (mrcc0.mrcc_lpuart3_clkdiv(), mrcc0.mrcc_lpuart3_clksel()),
LpuartInstance::Lpuart4 => (mrcc0.mrcc_lpuart4_clkdiv(), mrcc0.mrcc_lpuart4_clksel()),
LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()),
// LpuartInstance::Lpuart5 => (mrcc0.mrcc_lpuart5_clkdiv(), mrcc0.mrcc_lpuart5_clksel()),
};

let (freq, variant) = match self.source {
Expand Down
7 changes: 0 additions & 7 deletions embassy-mcxa/src/gpio.rs
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Expand Up @@ -43,11 +43,7 @@ static PORT_WAIT_MAPS: [WaitMap<usize, ()>; PORT_COUNT] = [
];

fn irq_handler(port_index: usize, gpio: crate::pac::gpio::Gpio, perf_wake: fn()) {
#[cfg(feature = "mcxa2xx")]
let isfr = gpio.isfr0();
#[cfg(feature = "mcxa5xx")]
let isfr = gpio.isfr(0);

for pin in BitIter(isfr.read().0) {
// Clear all pending interrupts
isfr.write(|w| w.0 = 1 << pin);
Expand Down Expand Up @@ -594,9 +590,6 @@ impl<'d> Flex<'d> {
//
// Clear any existing pending interrupt on this pin
// TODO: Fix PAC naming
#[cfg(feature = "mcxa2xx")]
self.pin.gpio().isfr0().write(|w| w.0 = 1 << self.pin.pin());
#[cfg(feature = "mcxa5xx")]
self.pin.gpio().isfr(0).write(|w| w.0 = 1 << self.pin.pin());
self.pin
.gpio()
Expand Down
2 changes: 1 addition & 1 deletion embassy-mcxa/src/lib.rs
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Expand Up @@ -29,7 +29,7 @@ mod mcxa2xx_exclusive {
pub mod reset_reason;
pub mod rtc;
pub mod spi;
pub mod trng;
// pub mod trng;
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@jamesmunns jamesmunns Mar 2, 2026

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@felipebalbi I'll probably need help with this

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@felipebalbi felipebalbi Mar 2, 2026

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sure thing, do you want me to push trng update directly to your branch or send a PR?

pub mod wwdt;

pub use crate::chips::mcxa2xx::{Peripherals, init, interrupt, peripherals};
Expand Down
2 changes: 1 addition & 1 deletion embassy-mcxa/src/lpuart/bbq.rs
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Expand Up @@ -1329,7 +1329,7 @@ macro_rules! impl_instance {
};
}

impl_instance!(0; 1; 2; 3; 4; 5);
impl_instance!(0; 1; 2; 3; 4);

// Basically the on_interrupt handler, but as a free function so it doesn't get
// monomorphized.
Expand Down
18 changes: 9 additions & 9 deletions embassy-mcxa/src/lpuart/mod.rs
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Expand Up @@ -177,7 +177,7 @@ macro_rules! impl_instance {
// LPUART3: RX=27, TX=28 -> Lpuart3RxRequest, Lpuart3TxRequest
// LPUART4: RX=29, TX=30 -> Lpuart4RxRequest, Lpuart4TxRequest
// LPUART5: RX=31, TX=32 -> Lpuart5RxRequest, Lpuart5TxRequest
impl_instance!(0; 1; 2; 3; 4; 5);
impl_instance!(0; 1; 2; 3; 4);

/// Perform software reset on the LPUART peripheral
fn perform_software_reset(info: &'static Info) {
Expand Down Expand Up @@ -599,17 +599,17 @@ impl_rts_pin!(LPUART4, P3_16, MUX2);
impl_rts_pin!(LPUART4, P3_30, MUX3);

// LPUART 5
impl_tx_pin!(LPUART5, P1_10, MUX8);
impl_tx_pin!(LPUART5, P1_17, MUX8);
// impl_tx_pin!(LPUART5, P1_10, MUX8);
// impl_tx_pin!(LPUART5, P1_17, MUX8);

impl_rx_pin!(LPUART5, P1_11, MUX8);
impl_rx_pin!(LPUART5, P1_16, MUX8);
// impl_rx_pin!(LPUART5, P1_11, MUX8);
// impl_rx_pin!(LPUART5, P1_16, MUX8);

impl_cts_pin!(LPUART5, P1_12, MUX8);
impl_cts_pin!(LPUART5, P1_19, MUX8);
// impl_cts_pin!(LPUART5, P1_12, MUX8);
// impl_cts_pin!(LPUART5, P1_19, MUX8);

impl_rts_pin!(LPUART5, P1_13, MUX8);
impl_rts_pin!(LPUART5, P1_18, MUX8);
// impl_rts_pin!(LPUART5, P1_13, MUX8);
// impl_rts_pin!(LPUART5, P1_18, MUX8);

/// LPUART error types
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
Expand Down