embassy-sync: add ThreadModeRawMutex support for riscv32#5822
embassy-sync: add ThreadModeRawMutex support for riscv32#5822cong-or wants to merge 1 commit intoembassy-rs:mainfrom
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| #[cfg(riscv32)] | ||
| // No interrupt executor on RISC-V yet, so always in thread mode. | ||
| return true; |
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That's false, esp-hal/esp-rtos provides an interrupt executor for risc-v chips.
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@bugadani Would an AtomicBool that the interrupt executor sets on entry/exit work? Or does esp-hal already have a mechanism for tracking interrupt context that this should hook into?
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There is no standard interrupt controller on RISC-V chips, and embassy-sync shouldn't rely on anything ESP32-specific. I'm not aware of an implementation-independent way to check if code is running in a thread context
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Wouldn't an AtomicBool set/cleared by the executor itself be implementation-independent? It doesn't need to know anything about the interrupt controller — just that the executor entered/exited interrupt context.
Fix ThreadModeRawMutex behavior on RISC-V (#5133)
ThreadModeRawMutexonly works oncortex_mright now, so it can’t be used onriscv32targets.The RISC-V executor is thread-only for now, so
in_thread_mode()just returnstrue.If we add an interrupt executor for RISC-V in the future, this will need proper tracking—but that’s a separate PR.
Testing
riscv32imac-unknown-none-elf