[PAL/vm-common] Use per-CPU L1d,L1i,L2 caches and one shared L3#32
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Previously, synthesized VM CPU/NUMA/caches topology had a bug: each CPU was pointing to the same L1d cache, same L1i cache, same L2 cache. This was interpreted by the LibOS layer as e.g. a single L1d cache on the platform shared by all CPUs. This bogus CPUs-caches topology confused some programs, in particular the GEMM Rust crate: the crate calculates the number of CPUs sharing a particular cache, then uses this number to calculate the "effective" number of bytes in the cache reserved for a single CPU, and then uses this number to optimize matrix multiplication: - https://github.com/sarah-ek/gemm/blob/8cdc1de4/gemm-common/src/cache.rs#L118 - https://github.com/sarah-ek/gemm/blob/8cdc1de4/gemm-common/src/cache.rs#L214 - https://github.com/sarah-ek/gemm/blob/8cdc1de4/gemm-common/src/gemm.rs#L356 This commit creates a correct CPUs-caches topology: each CPU has a dedicated L1d cache, L1i cache and L2 cache. L3 cache is shared by all CPUs (same as it was done previously). This satisfies the GEMM Rust crate and allows to run e.g. Candle ML framework. Signed-off-by: Dmitrii Kuvaiskii <dmitrii.kuvaiskii@intel.com>
dimakuv
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Jul 12, 2024
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a discussion (no related file):
FYI: We increase the data segment in the PAL binary, because instead of 4 statically allocated cache-infos, we now have MAX_NUM_CPUS * MAX_CACHES = 1024 statically allocated cache-infos.
I checked the final binary sizes before and after this PR: no change at all.
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Description of the changes
Previously, synthesized VM CPU/NUMA/caches topology had a bug: each CPU was pointing to the same L1d cache, same L1i cache, same L2 cache. This was interpreted by the LibOS layer as e.g. a single L1d cache on the platform shared by all CPUs. This bogus CPUs-caches topology confused some programs, in particular the GEMM Rust crate: the crate calculates the number of CPUs sharing a particular cache, then uses this number to calculate the "effective" number of bytes in the cache reserved for a single CPU, and then uses this number to optimize matrix multiplication:
This PR creates a correct CPUs-caches topology: each CPU has a dedicated L1d cache, L1i cache and L2 cache. L3 cache is shared by all CPUs (same as it was done previously). This satisfies the GEMM Rust crate and allows to run e.g. Candle ML framework.
How to test this PR?
Run #31.
This change is