Module: Priority Encoder

Overview

The priority_encoder module finds the most significant (leftmost) and least significant (rightmost) 1 in an input number and outputs two results:

• The input number with only the leftmost 1 bit retained.
• The input number with only the rightmost 1 bit retained.

If the input number contains no 1 bits, the output will be zero.

Functionality

Input/Output Behavior:

Input Number	Leftmost 1 Output	Rightmost 1 Output
5'b00110	5'b00100	5'b00010
5'b11111	5'b10000	5'b00001
5'b10000	5'b10000	5'b10000
5'b00000	5'b00000	5'b00000
5'b01000	5'b01000	5'b01000

The module works by analyzing the input data to detect the highest and lowest priority bits that are set to 1, and outputs only these bits.

Module Interface

Parameters:

Parameter Name	Type	Description
WIDTH	int	Bit-width of the input data.

I/O Ports:

Signal Name	Direction	Bit Width	Description
clk_i	input	1	Clock signal.
srst_i	input	1	Synchronous reset signal.
data_i	input	WIDTH	Input data containing WIDTH bits.
data_val_i	input	1	Input validity signal. When high, data on data_i is valid and should be processed.
data_left_o	output	WIDTH	Output data with only the leftmost 1 bit retained.
data_right_o	output	WIDTH	Output data with only the rightmost 1 bit retained.
data_val_o	output	1	Output validity signal. High when data_left_o and data_right_o contain valid data.