[PW_SID:1094688] clk/reset: anlogic: add support for DR1V90 SoC#1932
[PW_SID:1094688] clk/reset: anlogic: add support for DR1V90 SoC#1932linux-riscv-bot wants to merge 6 commits into
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The macro clk_div_mask() currently wraps to zero when width is 32 due to 1 << 32 being undefined behavior. This leads to incorrect mask generation and prevents correct retrieval of register field values for 32-bit-wide dividers. Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely on a 32-bit val entry in their div_table to match a div, so providing a full 32-bit mask is necessary. Fix this by using the standard GENMASK() macro. This safely resolves the undefined behavior on both 32-bit and 64-bit architectures, while also benefiting from the built-in compile-time type and bounds checking provided by the GENMASK() macro. Cc: Troy Mitchell <troy.mitchell@linux.spacemit.com> Cc: Brian Masney <bmasney@redhat.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add the Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, which is responsible for clock and reset management. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
The Clock and Reset Unit (CRU) in the Anlogic DR1V90 SoC provides management for the clock and reset. The clock driver includes support for: - Generic clocks: fixed-factor, divider, mux and gate. - PLL: "nm" type (parent * n / m) and "c" type (parent / c). These PLLs are set up by the FSBL and mared as "don't touch" in the datasheet, so only the recal_rate() op is provided. - Divider with gate: support both division and gating (by setting value to 0); some of them require a minimum divider value to avoid timing issues. This also prepares the structure for the reset controller support, registering an auxiliary device for resets. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add reset controller support for the Anlogic DR1V90 SoC, which is an auxiliary device associated with the Clock and Reset Unit (CRU). All resets are active-low. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add clocks and introduce the CRU (Clock and Reset) unit node for Anlogic DR1V90 SoC, providing both clock and reset support. The DR1V90 SoC uses three external clocks: - A crystal oscillator as the main system clock. - Two optional external clocks (via IO) for the CAN and WDT modules. The main crystal oscillator frequency is board-dependent. For the dr1v90-mlkpai-fs01 board, a 33.33 MHz oscillator is used and defined accordingly. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
Add a MAINTAINERS entry for the Anlogic DR1V90 Clock and Reset Unit (CRU) drivers. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 1: "[v5,1/6] clk: correct clk_div_mask() return value for width == 32" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 2: "[v5,2/6] dt-bindings: clock: add Anlogic DR1V90 CRU" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 4: "[v5,4/6] reset: anlogic: add support for Anlogic DR1V90 resets" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 5: "[v5,5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
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Patch 6: "[v5,6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry" |
PR for series 1094688 applied to workflow__riscv__fixes
Name: clk/reset: anlogic: add support for DR1V90 SoC
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1094688
Version: 5