[sram] Writes accompanied by defined read data#475
Draft
marnovandermaas wants to merge 1 commit intolowRISC:mainfrom
Draft
[sram] Writes accompanied by defined read data#475marnovandermaas wants to merge 1 commit intolowRISC:mainfrom
marnovandermaas wants to merge 1 commit intolowRISC:mainfrom
Conversation
The axi_to_detailed_mem module requires a valid read request to be accompanied by every write. This is problematic since at the start of time the content of SRAM is understandably undefined. Instead of feeding don't cares through the module alongside an rvalid signal. Now this feeds a recognisable hex sequence through the module so that it still works but it is also somewhat detectable if this read propagates to the output.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
The axi_to_detailed_mem module requires a valid read request to be accompanied by every write. This is problematic since at the start of time the content of SRAM is understandably undefined. Instead of feeding don't cares through the module alongside an rvalid signal. Now this feeds a recognisable hex sequence through the module so that it still works but it is also somewhat detectable if this read propagates to the output.
This change is mainly to unblock: #447