ad9912: mention lower f_ref, loop filter phase noise performance

[Spaqin]

ARTIQ Pull Request

Description of Changes

As discussed in #2489, documenting the consequences of using low f_ref and needing to make hardware changes to the loop filter for better performance.

Type of Changes

	Type
✓	📜 Docs

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[sbourdeauducq]

Is it "for better phase noise performance" or "for staying within specs at all"?

[sbourdeauducq]

Is it the case for all frequencies lower than the default? What is the tolerance?

[Spaqin]

And now that's something I couldn't get a straightforward answer to after much deliberation with @MorganTL, thus slightly vague wording.

The loop filter parameters on the 9912 Urukul board were chosen for a multiplier of 10, so 100MHz sysclk. Technically, for any different frequency it should be considered; and technically then it's not really designed for 125MHz we provide to the DDS either, but we consider it okay. From what I learned, using different sysclk than designed changes the phase margin and bandwidth. While phase margin is defined that it must be bigger than 45-50 degrees to keep the PLL stable (and for that extreme example of 10MHz mentioned earlier it is), but and there seems to be no exact guidelines on determining bandwidth, which determines output noise. Whole system performance depends on the quality of the provided clock, and whether adjusting the loop filter is necessary also depends on the use cases.

In such case maybe it would be better to just refer the user to the datasheet of AD9912.

[architeuthidae]

This is basically the same thing as solving the merge conflict, but for the record, I was putting f_ref and clk_div into double backticks.