feat: add nac3_{malloc, free}

[HTGAzureX1212]

Same as adding dynamic memory allocation support to ARTIQ/Zynq.

[sbourdeauducq]

Not sure if this works. RISC-V devices don't have cache coherency and I suspect this code assumes it.

[HTGAzureX1212]

Not sure if this works. RISC-V devices don't have cache coherency and I suspect this code assumes it.

Hmm, maybe I need to use atomic types then

[sbourdeauducq]

That's not going to help. Please read up on cache coherency models.

[HTGAzureX1212]

Would fence instructions help? (perhaps we could do what is already done on Zynq - having two separate heaps...)

[sbourdeauducq]

No, the cache issue is on MiSoC side and instructions like fence are not implemented. See how the caches are explicitly invalidated by the existing code when passing data between the CPU cores.
Two separate heaps would work.