feat(brillig): Phase 1 — linear-scan register allocator - #13313

Draft

aakoshh wants to merge 15 commits into

af/greedy-alloc-refactorfrom

Commits on Jul 9, 2026

chore(brillig): un-gate LiveIntervals for the linear-scan allocator

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38c4e27
feat(brillig): add pluggable allocator selection seam (greedy vs linear-scan)

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8787937
feat(brillig): linear-scan register assignment pass (fixed-home Plan)

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dce6573
feat(brillig): interval-set liveness with holes (LiveRanges)

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bb09072
feat(brillig): linear-scan register assignment over hole-aware ranges (no pressure)

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4b4439d
feat(brillig): wire the no-pressure linear-scan allocator end-to-end

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79028bb
feat(brillig): validate no-pressure linear-scan corpus-wide; fix split + frame-size bugs

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dc56ed2
chore(brillig): fix rustdoc links for the linear-scan module

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d8cdc26
feat(brillig): linear-scan pressure spilling in the assignment

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762bd25

Commits on Jul 10, 2026

fix(brillig): pin constant live-interval defs to their materialization point

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6129c93
feat(brillig): serve single-register plans with the linear-scan allocator

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06c482b
test(nargo_cli): exercise the linear-scan allocator under a small stack

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08c4775
feat(brillig): serve register-changing linear-scan plans via block-entry snapshots

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f308d08
feat(brillig): slot-canonical merge resolution for the linear-scan allocator

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7cb85d0
feat(brillig): serve register-to-register divergence via a fresh slot

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2696e5b