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d9b8420
Added dummy debug transport module for now.
JacobPease Jul 30, 2025
05d7512
Added tap controller based on Dr. Harris' implementation.
JacobPease Aug 1, 2025
d47fcf1
Merge branch 'main' of github.com:openhwgroup/cvw into debug
JacobPease Aug 1, 2025
45ff8f0
Added a Boundary Scan Register and Instruction Register initial imple…
JacobPease Aug 1, 2025
3dc149c
Lots of clarifying changes. Getting closer to a testable implementati…
JacobPease Aug 4, 2025
ca1ebf7
Fixed syntax errors.
JacobPease Aug 5, 2025
77396ef
update debug header for tap_controller.sv + some comments
stineje Aug 6, 2025
05318c8
Merge pull request #1 from stineje/debug
JacobPease Aug 6, 2025
44c3d9f
change indentation
stineje Aug 6, 2025
024bcab
add state definition for State
stineje Aug 6, 2025
01058ce
formatting
stineje Aug 6, 2025
7c54688
clarify comment
stineje Aug 6, 2025
4324dce
indentation issues on tap_controller
stineje Aug 6, 2025
79a15ce
Cleaned up syntax errors.
JacobPease Aug 7, 2025
cfcb70e
Resolved merge.
JacobPease Aug 7, 2025
02b6420
Fixed illegal unsized constant errors.
JacobPease Aug 7, 2025
33807ef
Bug fixes. Problems with sensitivity lists and resets.
JacobPease Aug 8, 2025
d6e7bf6
Fixed DTMCS reset bug. Need to reset other fields of important regist…
JacobPease Aug 8, 2025
62cc276
Might need to look at this op logic later in the DMI. For now, needs …
JacobPease Aug 8, 2025
3f7d6cd
possible data_reg_new.sv without packed
stineje Aug 11, 2025
9d7ad71
add another change to remove packed
stineje Aug 11, 2025
2f3ea35
clean up blunder on pcked def
stineje Aug 11, 2025
c2a2c33
update dtm
stineje Aug 11, 2025
d8ddb79
update tap_controller
stineje Aug 11, 2025
f7181c4
Added early debug module. Trying to figure out reading and writing th…
JacobPease Aug 13, 2025
be1ec74
small changes to format
stineje Aug 15, 2025
ea07012
Added state machine for halting and resuming the hart.
JacobPease Aug 16, 2025
d3ec8cf
Added ResumeReq masking when HaltReq is set in the debug module.
JacobPease Aug 16, 2025
944d8be
minor tweaks in comments
stineje Aug 17, 2025
eef6c71
Removed data fields.
JacobPease Aug 18, 2025
d146e8b
Fixed merged conflicts.
JacobPease Aug 18, 2025
f588941
update dm comment
stineje Aug 19, 2025
715fcb3
spacing in dm and a comment
stineje Aug 19, 2025
30234a7
Added the feature to read and write registers with the Abstract Acces…
JacobPease Aug 20, 2025
732f4e6
Resolved merge conflict.
JacobPease Aug 20, 2025
c57ae03
Fixed bug where reading a register was putting the wrong value in Data0.
JacobPease Aug 20, 2025
1902e1e
remove old HDL that is probably not needed
stineje Aug 21, 2025
5d796fd
minor tweak on spacing
stineje Aug 21, 2025
5e41892
Vivado linting revealed an issue with the tap_controller's reset sign…
JacobPease Aug 22, 2025
87e8d40
Fixed merge conflict. Merged.
JacobPease Aug 22, 2025
a79fcea
Removed synchronizers, added synchronizer to UpdateDR, and added Debu…
JacobPease Aug 22, 2025
e73cfa1
minor stylistic comment changes
stineje Aug 24, 2025
ca6514a
leave some comments
stineje Aug 24, 2025
0957ff7
add header to inst_reg.sv
stineje Aug 24, 2025
2a772cf
remove blank line bsr.sv
stineje Aug 24, 2025
86ee32f
Temporarily tied bypass to idcode as this fixes OpenOCD's interaction…
JacobPease Aug 26, 2025
429a6ad
Fixed merged conflict.
JacobPease Aug 26, 2025
f5a63ce
Fixed always_comb for cmderr. Now it works on fpga.
JacobPease Aug 26, 2025
fc252b3
Added some untested functionality to the debug module. This should be…
JacobPease Aug 27, 2025
7fefb89
Added the ability to read CSRs with Abstract Register read commands. …
JacobPease Sep 2, 2025
ef2fa06
Fixed bug where response valid wouldn't go high if command wasn't sup…
JacobPease Sep 2, 2025
82e7273
Added better cmderr handling to the Debug Module.
JacobPease Sep 3, 2025
e4e5683
Fixed GPR access, cmderr setting, and NextValid handling.
JacobPease Sep 4, 2025
d19fa5f
Fixed an if condition bug. Need to rebuild on FPGA.
JacobPease Sep 4, 2025
5dd3d0b
This commit is important. This particular commit fixes most issues wi…
JacobPease Sep 5, 2025
4f8d364
Fixed issues with synthesis, but synthesis was not the issue. Missing…
JacobPease Sep 5, 2025
ce67ed8
add ranges for registers per page 19 of the specification. I did not…
stineje Sep 7, 2025
785c3af
Change the way the registers were clocked so that everything is clock…
JacobPease Sep 8, 2025
03eb93b
remove comments in bsr.sv as they are self evident
stineje Sep 9, 2025
086a338
clean up dtm comments
stineje Sep 9, 2025
0e67ba9
remove unneeded signal
stineje Sep 9, 2025
54f51c4
remove unneeded comments
stineje Sep 9, 2025
2169fb7
silly comment clean up
stineje Sep 9, 2025
9f38240
comment cleanup
stineje Sep 9, 2025
87d4282
more comment cleanup on dtm
stineje Sep 9, 2025
630effe
fix spacing of data_reg.sv
stineje Sep 9, 2025
bd8ee8a
add comment on dtm.sv
stineje Sep 9, 2025
9986344
Merge branch 'main' of github.com:openhwgroup/cvw into debug
JacobPease Sep 13, 2025
1ceca47
Adds debug modules to wally
JacobPease Sep 18, 2025
c15788c
Added debugger submodule to primary testbench.
JacobPease Sep 18, 2025
6d5e422
add JEDEC information and hard code logic variable
stineje Sep 19, 2025
3ae4f59
Fixed testbench tdo assignment and fixed naming conflict in data_reg.sv
JacobPease Sep 19, 2025
717ceb3
Removed last traces of old structs.
JacobPease Sep 19, 2025
cb7e2bd
Initial debug csr module. It's a work in progress.
JacobPease Sep 19, 2025
eabc2be
Added Abstract Register Read and Write to CVW.
JacobPease Sep 22, 2025
023a428
get rid of comments - let's move forward :)
stineje Sep 23, 2025
016d12f
refine comments on config-shared
stineje Sep 23, 2025
0ab5f5d
Added DebugMode signal to Hazard Unit.
JacobPease Sep 23, 2025
a2aee1c
Merge branch 'debug' of github.com:JacobPease/cvw into debug
JacobPease Sep 23, 2025
60a73f5
Set up debug tests and fix many bugs.
JacobPease Sep 23, 2025
28e110d
fix(debug): fixed abstract GPR read enable pin
JacobPease Sep 24, 2025
c6d24e1
update debuggers.sv + description
stineje Sep 25, 2025
3220175
remove commented lines out
stineje Sep 25, 2025
459a083
update MD for Wally debug specification
stineje Oct 7, 2025
2179190
feat: Added debug test building
JacobPease Oct 10, 2025
2f31171
Merge branch 'debug' of github.com:JacobPease/cvw into debug
JacobPease Oct 10, 2025
6814085
feat: Initial skeleton of debug test creation python script.
JacobPease Oct 14, 2025
ed53a29
feat: debug test building able to build multiple tests
JacobPease Oct 15, 2025
e35f374
feat: Improved Debug Spec test building
JacobPease Oct 15, 2025
6ba0e21
fix: Multiple files now building for debug
JacobPease Oct 15, 2025
ba1af5b
cleanup of old signals not needed - moving onward and upward
stineje Oct 16, 2025
704abb3
update DFPR item in dm.sv - still need to update in FP regfile and FSM
stineje Oct 16, 2025
8c3e85e
added FPRDDebugEnable to make sure synthesis friendly - still need to…
stineje Oct 16, 2025
f3413ac
fix: objdumps now all build
JacobPease Oct 16, 2025
3ae7642
fix: All make rules now working.
JacobPease Oct 16, 2025
6768627
feat: testbench loads testvectors for debugger simultaneously
JacobPease Oct 16, 2025
36e5098
update Makefile w/header plus info on WALLY which will give error oth…
stineje Oct 17, 2025
079797c
feat: DPC sets PCF and Flushes on Resume
JacobPease Oct 17, 2025
3259dc7
chore: removed useless comment
JacobPease Oct 17, 2025
6eb6971
fix: Implemented correct resumeack and havereset bits
JacobPease Oct 23, 2025
7b0c2be
feat: Debug Module now works on FPGA
JacobPease Oct 28, 2025
ccf9ac1
feat(debug): Halting on reset
JacobPease Nov 6, 2025
669381d
feat(debug): Testbench runs multiple debug tests
JacobPease Nov 7, 2025
d1eddf1
feat(debug): Debugger now tracks testvector state
JacobPease Nov 24, 2025
14c3ae1
fix(debug): Fixed resuming from current PC
JacobPease Nov 25, 2025
a8b613d
feat(debug): Debugger now only prints on failure
JacobPease Nov 26, 2025
02a874a
Merged main into debug.
JacobPease Dec 9, 2025
3f06646
chore(debug): Removed tabs and trailing whitespaces
JacobPease Dec 9, 2025
38e7c0c
Merge branch 'main' of github.com:openhwgroup/cvw into debug
JacobPease Dec 9, 2025
d2dd1e7
fix(debug): SV fork works in Verilator now
JacobPease Dec 9, 2025
b074928
feat(debug): FPU register reading.
JacobPease Dec 13, 2025
bfbc84e
feat(debug): Added debug fpu test.
JacobPease Dec 13, 2025
45bfd17
fix(debug): fixed the debug fpu test signature
JacobPease Dec 16, 2025
f99c486
spacing in tap_controller
stineje Dec 18, 2025
f7c064f
add rv32 program even though not setup for it yet
stineje Dec 22, 2025
8e0ca30
chore: added comments to hazard.sv describing DebugResume
JacobPease Jan 28, 2026
90bce60
update feature list for Wally Debug - more on the way
stineje Jan 29, 2026
81623ff
update install for OpenOCD and wally-packages for OpenOCD
stineje Jan 31, 2026
8522499
delete unnecessary README for Debug OpenOCD
stineje Jan 31, 2026
9767f24
fix typo in wallydebug.md
stineje Feb 3, 2026
1427c94
update README to remove trailing whitespace
stineje Feb 3, 2026
ed997c9
remove modified from openocd-install.sh
stineje Feb 3, 2026
260faa4
remove whitespace after boostrap
stineje Feb 3, 2026
62e0b85
update headers for openocd bin install
stineje Feb 3, 2026
0864751
fix whitespace
stineje Feb 3, 2026
de1faa1
fix PEP8 debugtestgen.py line
stineje Feb 3, 2026
4e25781
add another test example for debug
stineje Feb 5, 2026
4125683
fix missing test for debug that I forgot to push
stineje Feb 5, 2026
6a447e9
fix whitespace tests.vh
stineje Feb 5, 2026
9b9dd6b
update WALLY-ex for debug
stineje Feb 5, 2026
7991a48
chore: added ebreak debug test for rv64
JacobPease Feb 18, 2026
5416d1e
fix: OpenOCD state on ebreak is updated now.
JacobPease Feb 19, 2026
bdc4fbb
update README.md with issue and better clarification for the README r…
stineje Feb 23, 2026
0ca64c6
fix typo in md for README on debug
stineje Feb 23, 2026
a31fecb
fix typos/grammatical issues in README
stineje Feb 23, 2026
5d64259
update README for program issue L122
stineje Feb 24, 2026
3e0ee15
update gcd example
stineje Feb 24, 2026
4bf7bff
add Python for users to see real result
stineje Feb 24, 2026
faeef07
change output of fpu.py to be better represented
stineje Feb 24, 2026
0508bb2
update WALLY-debug-02 test
stineje Feb 25, 2026
6e2c541
update WALLY-debug-01 immutability test
stineje Feb 25, 2026
7c3e003
add README to Python dir
stineje Feb 25, 2026
0067917
feat: Added ebreak to wally. Many fixes to halting and resuming.
JacobPease Feb 26, 2026
2f16b77
Merge branch 'debug' of github.com:JacobPease/cvw into debug
JacobPease Feb 26, 2026
199fcb9
fix: Added state machines for ResumeReq and HaltReq.
JacobPease Feb 26, 2026
0a8e34a
add hazard issue for DebugResume for flushing appropriately
stineje Mar 1, 2026
a0416e5
add comments to csrd.sv
stineje Mar 3, 2026
e37ac98
fix InstrValid as confusing
stineje Mar 3, 2026
e585408
move state info and clean up
stineje Mar 3, 2026
9cfb3c0
remove non-tested item - think we need an ebreak that fires when EBRE…
stineje Mar 3, 2026
9d41615
fix minor typo
stineje Mar 3, 2026
b24ceff
put back but dont like InstrValidE - change
stineje Mar 3, 2026
9545293
remove InstrValidE from csrd.sv to make agnostic
stineje Mar 3, 2026
51cc339
feat: better Resume ack handling with states.
JacobPease Mar 3, 2026
2973b5d
clean up old code and add comment on new ResumeAck sequence
Mar 3, 2026
c98551e
update some minor comments + fixing structure
stineje Mar 4, 2026
6d60503
fix tabs and definitions
stineje Mar 4, 2026
af1a928
beautify of comments
stineje Mar 4, 2026
0ff1b02
beautify of comments
stineje Mar 4, 2026
8305d24
beautify of comments
stineje Mar 4, 2026
1039ea0
beautify of comments
stineje Mar 4, 2026
af15ed9
add comment for dcsr
stineje Mar 4, 2026
a9fcb0e
fix always_ff coding style
stineje Mar 4, 2026
4722927
fix: added reading trigger module registers to known exceptions until…
JacobPease Mar 6, 2026
ef06150
feat: added stepping. Hacky solution, need to revisit.
JacobPease Mar 7, 2026
69570f6
feat: added WALLY-debug-step test to tests.vh
JacobPease Mar 7, 2026
4c095d1
feat: forgot to add WALLY-debug-step test.
JacobPease Mar 7, 2026
ee61e38
fix: made the memory signature change if stepping doesn't work properly.
JacobPease Mar 7, 2026
379ec6c
fix: moved ResumeAck to debug module, it's proper location. Fixes Res…
JacobPease Mar 9, 2026
faab640
feat: Skeleton Trigger Module to fix testvector mismatches.
JacobPease Mar 11, 2026
9dda4ca
fix: DPC now points to next instruction for steps and to the address …
JacobPease Mar 12, 2026
8a35ecb
fix: Removed DPC reading after reset halt, preventing testvector mism…
JacobPease Mar 12, 2026
89d5387
chore: added stepping through branching test.
JacobPease Mar 14, 2026
a7de902
fix: stepping works through branches now, though there appears to be …
JacobPease Mar 14, 2026
1bc7a44
fix: stepping now halts on branch instructions. Now to grab the right…
JacobPease Mar 14, 2026
4427a3c
fix: DPC now points to destination address on Branches and Jumps when…
JacobPease Mar 17, 2026
637d204
cleanup of input/output
stineje Mar 18, 2026
e89b2da
fix: Fixed mismatched width in csrd.sv. Also added a stepping through…
JacobPease Mar 18, 2026
9114f1a
Merge branch 'debug' of github.com:JacobPease/cvw into debug
JacobPease Mar 18, 2026
6566c4c
add headers for Python debug programs
stineje Mar 18, 2026
81cd259
fix: DPC now uses NextValidPCE. Also, a variety of fixes and cleanup …
JacobPease Mar 24, 2026
5fe1c9f
update 'Putting it All Together' tests and associated tcl commands
stineje Mar 26, 2026
9d115d9
update 'Putting it All Together' tests and associated tcl commands
stineje Mar 26, 2026
1a7513b
delete tv
stineje Mar 26, 2026
20a86b6
update tests.vh
stineje Mar 26, 2026
f85d2da
fix WALLY-debug-ex3
stineje Mar 26, 2026
2946c6c
update README.md with repo for openocd + some extra info
stineje Mar 27, 2026
b3b4460
update README.md with repo for openocd + some extra info
stineje Mar 27, 2026
ab43036
update README.md with repo for openocd + some extra info
stineje Mar 27, 2026
99b7952
feat: Abstract Read command reads more CSRs. Needs counter csrs still…
JacobPease Apr 9, 2026
504c016
update comment header on ex?.S
stineje Apr 10, 2026
6af0b6e
fix: Trigger module signal fixed. No longer drives IllegalCSRAccessM …
JacobPease Apr 15, 2026
51dfa37
Merge branch 'debug' of github.com:JacobPease/cvw into debug
JacobPease Apr 15, 2026
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58 changes: 58 additions & 0 deletions bin/installation/openocd-install.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
#!/bin/bash
###########################################
## openocd debug install script.
##
## Written: James Stine, james.stine@okstate.edu
## Created: Oct 16, 2025
##
## Purpose: openocd installation script
##
## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw
##
## Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################

OPENOCD_VERSION=eb01c632a4bb1c07d2bddb008d6987c809f1c496 # Last commit as of 2025-10-09T10:08:18Z

set -e # break on error
# If run standalone, check environment. Otherwise, use info from main install script
if [ -z "$FAMILY" ]; then
dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
WALLY="$(dirname $(dirname "$dir"))"
export WALLY
source "${dir}"/../wally-environment-check.sh
fi

# openocd (https://github.com/riscv-collab/riscv-openocd)
# openocd is OpenOCD stands for Open On-Chip Debugger and is an open-source tool that provides
# on-chip programming, debugging, and boundary-scan testing for embedded systems.
section_header "Installing/Updating OpenOCD"
STATUS="openocd"
cd "$RISCV"
if check_tool_version $OPENOCD_VERSION; then
git_checkout "riscv-openocd" "https://github.com/riscv-collab/riscv-openocd.git" "$OPENOCD_VERSION"
cd "$RISCV"/riscv-openocd
git submodule update --init --recursive
./bootstrap
./configure --enable-ftdi --enable-dummy --enable-jimtcl --prefix="$RISCV"
make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
sudo make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
echo "$OPENOCD_VERSION" > "$RISCV"/versions/$STATUS.version # Record installed version
echo -e "${SUCCESS_COLOR}openocd successfully installed/updated!${ENDC}"
else
echo -e "${SUCCESS_COLOR}openocd already up to date.${ENDC}"
fi
21 changes: 18 additions & 3 deletions bin/wally-package-install.sh
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
## Written: Jordan Carlin, jcarlin@hmc.edu
## Created: 30 June 2024
## Modified: May 30 2025
## Modified: 24 Jan 2026, James Stine james.stine@okstate.edu
##
## Purpose: Package manager installation for open source tool chain installation script
##
Expand Down Expand Up @@ -48,6 +49,20 @@ SAIL_PACKAGES+=(cmake)
VERILATOR_PACKAGES+=(autoconf flex bison help2man perl ccache numactl gtkwave) # gtkwave is not needed for verilator, but useful for viewing waveforms
BUILDROOT_PACKAGES+=(patchutils perl cpio bc)

# OPENOCD packages are distro-specific
# OpenOCD build dependencies (Jim Tcl + FTDI + USB)
case "$FAMILY" in
rhel)
OPENOCD_PACKAGES+=(jimtcl jimtcl-devel libftdi-devel libusb1-devel pkgconf-pkg-config)
;;
ubuntu|debian)
OPENOCD_PACKAGES+=(libjim-dev libftdi1-dev libusb-1.0-0-dev pkg-config)
;;
suse)
OPENOCD_PACKAGES+=(jimtcl jimtcl-devel libftdi-devel libusb-1_0-devel pkg-config)
;;
esac

# Distro specific packages and package manager
case "$FAMILY" in
rhel)
Expand Down Expand Up @@ -121,11 +136,11 @@ esac
if [ "${1}" == "--check" ]; then
section_header "Checking Dependencies from Package Manager"
if [[ "$FAMILY" == rhel || "$FAMILY" == suse ]]; then
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}"; do
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OPENOCD_PACKAGES[@]}"; do
rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1)
done
elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}"; do
for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OPENOCD_PACKAGES[@]}"; do
dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1)
done
fi
Expand Down Expand Up @@ -155,7 +170,7 @@ else
# Update and Upgrade tools
eval "$UPDATE_COMMAND"
# Install packages listed above using appropriate package manager
eval $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}"
eval $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OPENOCD_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}"

# Post install steps
# Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6
Expand Down
7 changes: 7 additions & 0 deletions bin/wally-tool-chain-install.sh
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@
## Written: Rose Thompson rose@rosethompson.net
## Modified: 30 June 2024, Jordan Carlin jcarlin@hmc.edu
## Modified: 30 May 2025
## Modified: 24 Jan 2206, James Stine james.stine@okstate.edu
##
## Purpose: Open source tool chain installation script
##
Expand Down Expand Up @@ -110,6 +111,12 @@ source "$WALLY"/bin/installation/verilator-install.sh
source "$WALLY"/bin/installation/skywater-lib-install.sh


# OpenOCD installation for RISC-V debug support
# OpenOCD is used to provide JTAG-based debugging and programming support
# for the Wally RISC-V processor during bring-up and validation.
source "$WALLY"/bin/installation/openocd-install.sh


# Buildroot and Linux testvectors
# Buildroot is used to boot a minimal version of Linux on Wally.
# Testvectors are generated using QEMU.
Expand Down
12 changes: 12 additions & 0 deletions config/derivlist.txt
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,18 @@ EXT_MEM_RANGE 64'h7FFFFFFF
SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12
DEBUG_SUPPORTED 1
TRIG_SUPPORTED 1

# RV32GC with Debug Mode supported
deriv debug32 rv32gc
DEBUG_SUPPORTED 1
TRIG_SUPPORTED 1

# RV64GC with Debug Mode supported
deriv debug64 rv64gc
DEBUG_SUPPORTED 1
TRIG_SUPPORTED 1

deriv fpgaArtyA7 fpga
EXT_MEM_RANGE 64'h0FFFFFFF
Expand Down
6 changes: 6 additions & 0 deletions config/rv32e/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -225,4 +225,10 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
6 changes: 6 additions & 0 deletions config/rv32gc/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -227,4 +227,10 @@ localparam DIVCOPIES = 32'd2;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
6 changes: 6 additions & 0 deletions config/rv32i/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -225,4 +225,10 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
6 changes: 6 additions & 0 deletions config/rv32imc/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -225,4 +225,10 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
6 changes: 6 additions & 0 deletions config/rv64gc/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -228,4 +228,10 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
6 changes: 6 additions & 0 deletions config/rv64i/config.vh
Original file line number Diff line number Diff line change
Expand Up @@ -225,4 +225,10 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;

// Debug
localparam logic DEBUG_SUPPORTED = 0;

// Trig
localparam logic TRIG_SUPPORTED = 0;

`include "config-shared.vh"
5 changes: 5 additions & 0 deletions config/shared/config-shared.vh
Original file line number Diff line number Diff line change
Expand Up @@ -122,3 +122,8 @@ localparam FMALEN = 3*NF + 6;
localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));

localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)

// Debug Specification (if enabled)
localparam JEDEC = 32'h1002ac05;
localparam ABITS = 6'd7;
localparam DTM_INSTR_WIDTH = 32'd5;
7 changes: 6 additions & 1 deletion config/shared/parameter-defs.vh
Original file line number Diff line number Diff line change
Expand Up @@ -197,5 +197,10 @@ localparam cvw_t P = '{
DURLEN : DURLEN,
DIVb : DIVb,
DIVBLEN : DIVBLEN,
INTDIVb : INTDIVb
INTDIVb : INTDIVb,
DEBUG_SUPPORTED : DEBUG_SUPPORTED,
JEDEC : JEDEC,
ABITS : ABITS,
DTM_INSTR_WIDTH : DTM_INSTR_WIDTH,
TRIG_SUPPORTED : TRIG_SUPPORTED
};
124 changes: 124 additions & 0 deletions docs/debug/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,124 @@
# Wally Debug Support

This repository documents debug support for **Wally**, an open-source RISC-V processor platform. The goal of this effort is to support the RISC-V Debug Specification while enabling reliable debugging in both simulation and hardware environments. Wally integrates debug functionality compatible with OpenOCD, Spike remote bitbang simulation, and physical JTAG debug adapters.

## OpenOCD for RISC-V

This repository uses a separate fork of OpenOCD maintained by the RISC-V
community, available at:
```
https://github.com/riscv/riscv-openocd
```
## Installation

OpenOCD for RISC-V is installed as part of the Wally toolchain. To install,
run the provided installation script:
```bash
$RISCV/bin/wally-tool-chain-install.sh
```

This script will automatically download, build, and install `riscv-openocd`
along with the rest of the Wally toolchain components. The `$RISCV` environment
variable should be set per `setup.sh` to your toolchain installation directory
before running the script.

### Why a Separate Fork?

The official OpenOCD mainline was slow to merge RISC-V support, so the
RISC-V community (primarily SiFive) maintained an independent fork to track
the evolving RISC-V debug specification. Key reasons the fork exists:

- **Evolving debug spec** — the RISC-V External Debug Support specification
went through significant revisions (0.11 → 0.13 → 1.0) while hardware was
already being shipped, requiring frequent implementation updates that
mainline OpenOCD could not absorb quickly enough
- **Hardware availability** — SiFive and others were shipping silicon that
needed a working debugger before upstream review cycles could complete
- **Slow upstream process** — mainline OpenOCD has a small maintainer team
and large feature sets take considerable time to review and merge

RISC-V support has since been progressively upstreamed into mainline OpenOCD,
so the gap between the two has narrowed. However, `riscv-openocd` may still
carry newer debug spec features or bug fixes ahead of mainline.

### Key Components

**DTM (Debug Transport Module)** — sits between JTAG and the debug module.
It exposes a small set of JTAG registers (`dtmcs`, `dmi`) that OpenOCD uses
to issue DMI transactions. The DTM handles the clock domain crossing between
the JTAG TCK domain and the core's system clock domain.

**DMI (Debug Module Interface)** — a simple address/data/op bus. OpenOCD
reads and writes DMI registers to control the debug module. Key registers
include `dmcontrol` (halt/resume), `dmstatus` (hart state), `abstractcs`
(abstract command control), `data0`/`data1` (data exchange), and
`progbuf0`–`progbufN` (program buffer for executing arbitrary instructions).

**Debug Module (DM)** — the on-chip hardware block that implements the debug
spec. It can:
- Halt and resume harts
- Reset harts or the whole system
- Execute abstract commands (read/write GPRs and CSRs directly)
- Execute arbitrary instructions via the Program Buffer
- Trigger hardware breakpoints via the Trigger Module

**Program Buffer** — a small instruction memory (typically 2–16 instructions)
that the debug module can fill with arbitrary RISC-V instructions and execute
on the halted hart. This is the mechanism used to access Debug Mode-only CSRs
(`dcsr`, `dscratch0`, `dscratch1`) and to perform memory access, since those
CSRs are only accessible when the hart is in Debug Mode.

**Trigger Module** — a set of hardware comparators that can fire on
instruction addresses (breakpoints) or data addresses/values (watchpoints),
causing the hart to enter Debug Mode without software intervention. Configured
via the `tselect`, `tdata1`, and `tdata2` CSRs from M-mode.


## Supported RISC-V Debug Specification

Wally currently targets:

**RISC-V Debug Specification — Version 1.0 (Revised 2025-02-21)**

Development continues toward expanded functionality and improved
tool interoperability.

---

## Note on Spike Debug Compatibility

The current Wally debug implementation does **not** include an initial Debug Module *program buffer* (`progbufsize = 0`). While this is allowed by the RISC-V Debug Specification (which permits implementations to rely on abstract register access instead of a program buffer), some debugger workflows assume program-buffer execution is available.

A recent Spike update (https://github.com/riscv-software-src/riscv-isa-sim/commit/5397899bb9eddba8c2f87d7d62e6303629ebed90) introduced stricter debug checks, including an assertion (around line 122 of riscv/debug_module.cc) that may trigger when debugging a target that does not implement a program buffer.

As a result, users may observe assertion failures or unexpected debugger behavior when using newer versions of Spike together with Wally debug.

This limitation is temporary. Future Wally debug revisions will include program buffer support, improving compatibility with Spike, OpenOCD, and standard RISC-V debug workflows.

---

## OpenOCD udev Rules Installation (Linux)

USB debug adapters typically require root privileges. Installing the OpenOCD udev rules allows OpenOCD to access supported debug probes without using `sudo`.

The rules file is provided with OpenOCD:

```
contrib/60-openocd.rules
```

Install it with:

```bash
sudo cp openocd-code/contrib/60-openocd.rules /etc/udev/rules.d/
sudo udevadm control --reload-rules
sudo udevadm trigger
```

After installation, unplug and reconnect the debug adapter. You may also need to log out and back in if group permissions change.

OpenOCD should then run normally as a user as an example here:

```bash
openocd -f tests/debug/openocd.cfg
```
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