Bump addins/riscv-arch-test-cvw from 82cc96e to fd83fd8#1716
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Bump addins/riscv-arch-test-cvw from 82cc96e to fd83fd8#1716dependabot[bot] wants to merge 1 commit intomainfrom
82cc96e to fd83fd8#1716dependabot[bot] wants to merge 1 commit intomainfrom
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Bumps [addins/riscv-arch-test-cvw](https://github.com/riscv-non-isa/riscv-arch-test) from `82cc96e` to `fd83fd8`. - [Release notes](https://github.com/riscv-non-isa/riscv-arch-test/releases) - [Commits](riscv/riscv-arch-test@82cc96e...fd83fd8) --- updated-dependencies: - dependency-name: addins/riscv-arch-test-cvw dependency-version: fd83fd8ed187b163c39ad1f25eb8b822ec493c01 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps addins/riscv-arch-test-cvw from
82cc96etofd83fd8.Commits
fd83fd8Changes to sv_area_sz offset for S-mode without H-extension (#1156)b058c01Zicbop & SvPMPZicbo ACTs (#1177)4bab1ebfix broken UDB profile links in CTP section 4.2.1 (#1128)cd1c1ccInterruptsU Python Tests (#1061)b27b0cdBump ruff from 0.15.7 to 0.15.8 (#1163)8975f23Bump docs/docs-resources fromb387152toa88e6af(#1165)def37d6Bump actions/deploy-pages from 4 to 5 (#1162)682213cRv64 vector selfcheck (#1160)921a35aremoved stale rvmodel_data_section (#1158)ae17370Ensure fp initialization only runs when F is supported (#1157)Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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