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[ci] Add slang lint #445

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3eee8f4
[ci] Add slang lint action
micprog Apr 10, 2026
deaade6
[ci] Update ubuntu to latest
micprog Apr 10, 2026
5184b1a
[hardware] Fix slang warnings
micprog Apr 10, 2026
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61 changes: 44 additions & 17 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ jobs:
#####################

tc-llvm:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
- name: Recover the submodule commit hash
Expand Down Expand Up @@ -82,7 +82,7 @@ jobs:
path: tc-llvm.tar

tc-gcc:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
- name: Recover the submodule commit hash
Expand Down Expand Up @@ -134,7 +134,7 @@ jobs:
path: tc-gcc.tar

tc-isa-sim:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
- name: Recover the submodule commit hash
Expand Down Expand Up @@ -169,7 +169,7 @@ jobs:
path: tc-isa-sim.tar

tc-verilator:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
- name: Recover the submodule commit hash
Expand Down Expand Up @@ -208,8 +208,35 @@ jobs:
# Compile stage #
###################

compile-slang:
runs-on: ubuntu-latest
permissions:
contents: read
checks: write
pull-requests: write
steps:
- name: Checkout
uses: actions/checkout@v6
with:
submodules: recursive
- name: Download RTL submodules
run: |
make -C hardware checkout
make -C hardware apply-patches
- name: Generate flist
run: make -C hardware spyglass/tmp/files
- name: Run slang
uses: pulp-platform/pulp-actions/slang@v2.5.0 # update version as needed, not autoupdated
with:
token: ${{ secrets.GITHUB_TOKEN }}
slang-flags: >-
-f hardware/spyglass/tmp/files --top ara_soc_wrap
-Wextra -Wno-width-trunc -Wno-case-redundant-default -Wno-case-enum -Wno-incomplete-return -Wno-dup-import
--ignore-unknown-modules
--suppress-warnings .bender/...,hardware/deps/...

compile-apps:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -241,7 +268,7 @@ jobs:
path: apps/bin

compile-riscv-tests:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -280,7 +307,7 @@ jobs:
path: apps/bin

compile-ara:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -324,7 +351,7 @@ jobs:
####################

simulate:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -358,7 +385,7 @@ jobs:
########################

riscv-tests-simv:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -387,7 +414,7 @@ jobs:
run: config=${{ matrix.ara_config }} make -C hardware -j8 riscv_tests_simv

riscv-tests-spike:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
needs: ["tc-isa-sim", "compile-riscv-tests"]
steps:
- uses: actions/checkout@v6
Expand Down Expand Up @@ -426,7 +453,7 @@ jobs:
###################

check-license:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
- uses: actions/setup-python@v6
Expand All @@ -438,7 +465,7 @@ jobs:
run: python scripts/licence-checker.py --config scripts/licence-checker.hjson hardware

check-clang-format:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
needs: ['tc-llvm']
steps:
- uses: actions/checkout@v6
Expand All @@ -464,7 +491,7 @@ jobs:
exit $EXIT_STATUS

check-trailing-whitespaces:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v6
with:
Expand Down Expand Up @@ -492,7 +519,7 @@ jobs:
#####################

benchmark:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down Expand Up @@ -544,7 +571,7 @@ jobs:
path: benchmarks-${{ matrix.ara_config }}.tar

roofline:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
needs: benchmark
steps:
- uses: actions/checkout@v6
Expand Down Expand Up @@ -700,7 +727,7 @@ jobs:
####################

clean-up:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
if: always()
needs: ["simulate", "riscv-tests-spike", "riscv-tests-simv"]
steps:
Expand All @@ -716,7 +743,7 @@ jobs:
riscv-tests-spike

clean-up-compile-runs:
runs-on: ubuntu-22.04
runs-on: ubuntu-latest
strategy:
max-parallel: 1
matrix:
Expand Down
12 changes: 9 additions & 3 deletions hardware/spyglass/src/ara_soc_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,6 @@ module ara_soc_wrap (
localparam int unsigned AxiUserWidth = 1;
localparam int unsigned AxiIdWidth = 5;

logic clk_i, rst_ni;

ara_soc #(
.NrLanes (NrLanes ),
.VLEN (VLEN ),
Expand All @@ -33,7 +31,15 @@ module ara_soc_wrap (
.scan_data_i (1'b0 ),
.uart_prdata_i ('0 ),
.uart_pready_i ('0 ),
.uart_pslverr_i('0 )
.uart_pslverr_i('0 ),
.exit_o(),
.hw_cnt_en_o(),
.scan_data_o(),
.uart_penable_o(),
.uart_pwrite_o(),
.uart_paddr_o(),
.uart_psel_o(),
.uart_pwdata_o()
);

endmodule
2 changes: 1 addition & 1 deletion hardware/src/ara.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -491,7 +491,7 @@ module ara import ara_pkg::*; #(

// Break path for acc_mmu_en. This signal can afford some additional latency
// since vector mem ops take multiple cycles to reach the addrgen
`FF(acc_mmu_en_q, acc_mmu_en, '0, clk_i, rst_ni);
`FF(acc_mmu_en_q, acc_mmu_en, '0, clk_i, rst_ni)

vlsu #(
.NrLanes (NrLanes ),
Expand Down
2 changes: 1 addition & 1 deletion hardware/src/ara_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -341,7 +341,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
logic running_mask_insn_d, running_mask_insn_q;

logic lsu_current_burst_exception_q;
`FF(lsu_current_burst_exception_q, lsu_current_burst_exception_i, 1'b0, clk_i, rst_ni);
`FF(lsu_current_burst_exception_q, lsu_current_burst_exception_i, 1'b0, clk_i, rst_ni)

// pe_req_ready_i comes from all the lanes
// It is deasserted if the current request is stuck
Expand Down
16 changes: 8 additions & 8 deletions hardware/src/ara_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -259,7 +259,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
`endif

// One-cycle latency
`FF(l2_rvalid, l2_req, 1'b0);
`FF(l2_rvalid, l2_req, 1'b0)

////////////
// UART //
Expand Down Expand Up @@ -482,17 +482,17 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
localparam config_pkg::cva6_cfg_t CVA6AraConfig = build_config_pkg::build_config(CVA6AraConfig_user);

// Define the exception type
`CVA6_TYPEDEF_EXCEPTION(exception_t, CVA6AraConfig);
`CVA6_TYPEDEF_EXCEPTION(exception_t, CVA6AraConfig)

// Standard interface
`CVA6_INTF_TYPEDEF_ACC_REQ(accelerator_req_t, CVA6AraConfig, fpnew_pkg::roundmode_e);
`CVA6_INTF_TYPEDEF_ACC_RESP(accelerator_resp_t, CVA6AraConfig, exception_t);
`CVA6_INTF_TYPEDEF_ACC_REQ(accelerator_req_t, CVA6AraConfig, fpnew_pkg::roundmode_e)
`CVA6_INTF_TYPEDEF_ACC_RESP(accelerator_resp_t, CVA6AraConfig, exception_t)
// MMU interface
`CVA6_INTF_TYPEDEF_MMU_REQ(acc_mmu_req_t, CVA6AraConfig);
`CVA6_INTF_TYPEDEF_MMU_RESP(acc_mmu_resp_t, CVA6AraConfig, exception_t);
`CVA6_INTF_TYPEDEF_MMU_REQ(acc_mmu_req_t, CVA6AraConfig)
`CVA6_INTF_TYPEDEF_MMU_RESP(acc_mmu_resp_t, CVA6AraConfig, exception_t)
// Accelerator - CVA6's top-level interface
`CVA6_INTF_TYPEDEF_CVA6_TO_ACC(cva6_to_acc_t, accelerator_req_t, acc_mmu_resp_t);
`CVA6_INTF_TYPEDEF_ACC_TO_CVA6(acc_to_cva6_t, accelerator_resp_t, acc_mmu_req_t);
`CVA6_INTF_TYPEDEF_CVA6_TO_ACC(cva6_to_acc_t, accelerator_req_t, acc_mmu_resp_t)
`CVA6_INTF_TYPEDEF_ACC_TO_CVA6(acc_to_cva6_t, accelerator_resp_t, acc_mmu_req_t)

`ifndef TARGET_GATESIM
ara_system #(
Expand Down
2 changes: 1 addition & 1 deletion hardware/src/ara_system.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(

// Support max 8 cores, for now
logic [63:0] hart_id;
assign hart_id = {'0, hart_id_i};
assign hart_id = 64'(hart_id_i);

// Pack invalidation interface into acc interface
acc_to_cva6_t acc_resp_pack;
Expand Down
4 changes: 2 additions & 2 deletions hardware/src/ctrl_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,7 @@ module ctrl_registers #(
.reg_q_o ({hw_cnt_en, event_trigger, dram_end_address, dram_base_address, exit})
);

`FF(wr_active_q, wr_active_d, '0);
`FF(wr_active_q, wr_active_d, '0)

/////////////////
// Signals //
Expand All @@ -105,6 +105,6 @@ module ctrl_registers #(
assign event_trigger_o = event_trigger;
assign dram_base_addr_o = dram_base_address;
assign dram_end_addr_o = dram_end_address;
assign exit_o = {exit, logic'(|wr_active_q[7:0])};
assign exit_o = {exit, |wr_active_q[7:0]};

endmodule : ctrl_registers
10 changes: 5 additions & 5 deletions hardware/src/lane/lane.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -222,12 +222,12 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
logic [NrVInsn-1:0] mfpu_vinsn_done;
// Interface with the MaskB operand queue (VRGATHER/VCOMPRESS)
logic mask_b_cmd_pop_d, mask_b_cmd_pop_q;
`FF(mask_b_cmd_pop_q, mask_b_cmd_pop_d, 1'b0, clk_i, rst_ni);
`FF(mask_b_cmd_pop_q, mask_b_cmd_pop_d, 1'b0, clk_i, rst_ni)


// Support for store exception flush
logic lsu_ex_flush_op_req_d, lsu_ex_flush_op_req_q;
`FF(lsu_ex_flush_op_req_q, lsu_ex_flush_op_req_d, 1'b0, clk_i, rst_ni);
`FF(lsu_ex_flush_op_req_q, lsu_ex_flush_op_req_d, 1'b0, clk_i, rst_ni)

// Additional signals to please Verilator's hierarchical verilation
pe_req_t pe_req;
Expand Down Expand Up @@ -310,7 +310,7 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
logic sldu_result_gnt_opqueues;
// Support for store exception flush
logic lsu_ex_flush_op_queues_d, lsu_ex_flush_op_queues_q;
`FF(lsu_ex_flush_op_queues_q, lsu_ex_flush_op_queues_d, 1'b0, clk_i, rst_ni);
`FF(lsu_ex_flush_op_queues_q, lsu_ex_flush_op_queues_d, 1'b0, clk_i, rst_ni)

operand_requester #(
.NrLanes (NrLanes ),
Expand Down Expand Up @@ -609,8 +609,8 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
);

// Break timing path
`FF(vfu_operation_valid_q, vfu_operation_valid, 1'b0, clk_i, rst_ni);
`FF(vfu_operation_op_q, vfu_operation.op, VADD, clk_i, rst_ni);
`FF(vfu_operation_valid_q, vfu_operation_valid, 1'b0, clk_i, rst_ni)
`FF(vfu_operation_op_q, vfu_operation.op, VADD, clk_i, rst_ni)

always_comb begin
sldu_addrgen_sel_d = SLDU_SEL;
Expand Down
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