dt-bindings: soc: qcom: stats: Support fallback compatible for RPM targets - #1788
Open
smankad-oss wants to merge 189 commits into
Open
dt-bindings: soc: qcom: stats: Support fallback compatible for RPM targets#1788smankad-oss wants to merge 189 commits into
smankad-oss wants to merge 189 commits into
Conversation
…fault for ARCH_QCOM Interconnect drivers provide fundamental NoC bandwidth management required for correct system behavior. Although systems can boot without them, power and performance are impacted. These drivers need to enabled irresepective of the board variant, design or configuration. Enable the Shikra interconnect driver by default on ARCH_QCOM by setting "default ARCH_QCOM". Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260526-shikra_icc_kconfig-v1-1-c589db2d023c@oss.qualcomm.com
Add bindings documentation for RPM clock controller on Qualcomm Shikra SoC. The Qualcomm Shikra RPMCC has the clocks same as Agatti (QCM2290) RPMCC. Hence, add support to use the QCM2290 RPMCC compatible as fallback for Shikra RPMCC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-1-94cefe092ee3@oss.qualcomm.com
…ck Controller Add device tree bindings for the global clock controller on Qualcomm Shikra SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com
…rt on Agatti Add support for missing RF_CLK1/RF_CLK2 clocks on Qualcomm Agatti (QCM2290) SoC. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-3-94cefe092ee3@oss.qualcomm.com
…hikra SoC Add support for Global clock controller (GCC) on Qualcomm Shikra SoC. Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-4-94cefe092ee3@oss.qualcomm.com
Add compatible for the Qualcomm Shikra rpm-smd device. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260508-shikra_mailbox_and_rpm_changes-v3-1-698f8e5fb339@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Update dt-bindings to add Shikra to QUSB2 Phy list. Shikra SoC has two High Speed QUSB2 Phys. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260712-usb-shikra-phy-v6-v6-1-1b3e51bf1541@oss.qualcomm.com
Declare the USB-C QMP PHY present on the Qualcomm Shikra SoC. Shikra uses 3 resets to be programmed before initialising the phy. As per the hardware documentation, the third reset is PHY_PRIM_SP0_BCR, hence naming it "phy". Also, add remote endpoints and orientation switch support for getting Type-C orientation information. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260712-usb-shikra-phy-v6-v6-2-1b3e51bf1541@oss.qualcomm.com
Add init sequence and phy configuration for Shikra. Since the init sequence is same as that of QCS615, reuse the existing init table in Shikra. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260712-usb-shikra-phy-v6-v6-3-1b3e51bf1541@oss.qualcomm.com
Add init sequence and phy configuration for the Super Speed port on Shikra SoC. Also since Shikra uses 3 resets, add support for the third reset and configure Shikra platform data to use 3 resets. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260712-usb-shikra-phy-v6-v6-4-1b3e51bf1541@oss.qualcomm.com
Introduce the compatible definition for Shikra QCOM SNPS DWC3. Shikra SoC has two usb controllers and the secondary controller is high-speed only capable. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260711-usb-shikra-v4-v4-1-9d59b9d9aff7@oss.qualcomm.com
Add compatible for Shikra SoC IMEM. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260430-shikra-imem-binding-v1-1-c6976239f90f@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the SCM compatible for the Shikra SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260501-shikra-scm-binding-v1-1-93d7faf1b784@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document the qcom,shikra-tcsr compatible. Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260501-shikra-tcsr-binding-v1-1-0c136d193634@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Document compatible string for the QFPROM on Qualcomm Shikra SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260508-shikra-qfprom-binding-v2-1-a75174c8a580@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Shikra is a Qualcomm IoT SoC available in a System-on-Module (SoM) form factor. The SoM integrates the Shikra SoC, PMICs, and essential passives, and is designed to be mounted on carrier boards. Three eSoM variant are introduced: - CQM: retail variant with integrated modem (PM4125 and PM8005 PMIC) - CQS: retail variant without modem (PM4125 and PM8005 PMIC) - IQS: industrial-grade variant without modem (PM8150 PMIC) Each SoM variant pairs with a common EVK carrier board provides debug UART, USB, and other peripheral interfaces. Add compatible strings for the CQ2390M, CQ2390S, IQ2390S SoM variant and its corresponding EVK boards. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-shikra-dt-v7-1-977b65a300c1@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform built around a heterogeneous CPU cluster (Cortex-A55 + Cortex-A78C) with RPM-based power and clock management. Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - System timer and watchdog Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-shikra-dt-v7-2-977b65a300c1@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device tree include for the CQ2390M variant of the Shikra System-on-Module, a compact compute module integrating the Shikra SoC and PMIC for IoT applications, designed to mount on carrier boards. - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC) The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC peripheral definitions specific to this variant. Since PM8005 regulators are controlled by rpmpd, so disabling the pm8005 regulators. Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-shikra-dt-v7-3-977b65a300c1@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device tree include for the IQ2390S variant of the Shikra System-on-Module, an industrial compute module integrating the Shikra SoC and PMIC for industrial IoT applications, designed to mount on carrier boards. - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC) The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator definitions specific to this variant. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-shikra-dt-v7-4-977b65a300c1@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device trees for the Shikra EVK platform, which combines each of Shikra SoM variant with a common carrier board. Three EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQ2390M SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQ2390S SoM (retail, without modem) - shikra-iqs-evk.dts: pairs with IQ2390S SoM (industrial, without modem) Also add shikra-evk.dtsi, it represents the common carrier-board and daughter-card configuration shared across all Shikra EVK variants. Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260708-shikra-dt-v7-5-977b65a300c1@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add Last Level Cache table and configs for the Shikra SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260531-shikra_llcc_conf-v1-1-fa405f5a2404@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
…4125-vbus-reg The pm4125 PMIC uses a different USB VBUS register layout than pm8150b. It uses a 2-bit VBOOST voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V and 5.0 V, instead of a current-limit selector. Move qcom,pm4125-vbus-reg from the pm8150b fallback items list into the standalone enum since the driver handles it with its own match-data and register layout. Make regulator-min/max-microamp conditional so they are only required for current-limit variants (pm8150b, pm6150, pm7250b, pmi632). Add an if/then condition for qcom,pm4125-vbus-reg requiring regulator-min/ max-microvolt instead, and update the pm4125 example accordingly. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-1-999d78a87b81@oss.qualcomm.com
…0B support Introduce per-compatible regulator descriptor data via struct qcom_usb_vbus_reg_data to abstract register layout differences between PMICs. This allows the probe function to dynamically populate the regulator_desc fields rather than relying on compile-time constants. Refactor the existing PM8150B support to use this abstraction, wiring in its CMD_OTG, OTG_CFG, and current-limit registers through pm8150b_data. No functional change is intended for PM8150B. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-2-999d78a87b81@oss.qualcomm.com
The PM4125 PMIC uses a different register layout for USB VBUS control compared to PM8150B. On PM4125, CMD_OTG is at offset 0x50, OTG_CFG is at 0x56, and offset 0x52 is a 2-bit VBOOST voltage selector rather than a current-limit selector. Add pm4125_data using the abstraction introduced for PM8150B, along with dedicated voltage-selector ops and the pm4125_vboost_table covering the four supported boost voltages: 4.25 V, 4.5 V, 4.75 V, and 5.0 V. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-3-999d78a87b81@oss.qualcomm.com
…onstraints Remove pm8150b fallback compatible from pm4125_vbus and fix regulator constraints in qrb2210 DTS files to use microvolt instead of microamp. Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-4-999d78a87b81@oss.qualcomm.com
…ng for Qualcomm Shikra SoC Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260603-shikra_epss_l3-v3-1-3c2e0b796e78@oss.qualcomm.com
Add Epoch Subsystem (EPSS) L3 interconnect provider support on Qualcomm Shikra SoC. The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Reading beyond the supported LUT entries can expose incorrect frequencies. Add shikra-specific EPSS descriptor shikra_epss_l3_perf_state that reuses existing EPSS configuration with appropriate LUT entries limit. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260603-shikra_epss_l3-v3-2-3c2e0b796e78@oss.qualcomm.com
…d by DSF On Shikra, the DDR System Firmware (DSF) configures ECC interrupt routing before the kernel driver probes — it enables Tag/Data RAM interrupts and programs error thresholds in the LLCC interrupt-enable registers. Set irq_configured in shikra_cfg so that qcom_llcc_edac_probe() skips calling qcom_llcc_core_setup(), which would otherwise overwrite the firmware-managed register state with redundant writes. Signed-off-by: Faiyaz Mohammed <faiyaz.mohammed@oss.qualcomm.com> Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-shikra-edac-v2-1-22fcb3ca9fb9@qti.qualcomm.com
…compatible Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR bandwidth monitor. Shikra has a BWMONv5 for CPU. Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-shikra-dt-m1-v6-1-bee265d3499b@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260720-shikra-dt-m1-v7-1-7dc99100c6dd@oss.qualcomm.com Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
…orm register Register the ASoC component, request the QAIF interrupt and add trigger handling to enable or disable DMA and its interrupt sources. Dispatch the top-level IRQ status to the AIF and CIF DMA handlers, report period elapsed events to ALSA, warn on xrun conditions and stop the stream on bus errors. Link: https://lore.kernel.org/all/20260824063627.3595610-8-harendra.gautam@oss.qualcomm.com/ Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
Provide the Shikra DMA-to-DAI mappings, DMA and SHRAM layout, clock names, DAI driver data and power-management hooks required by the QAIF driver. Add the Kconfig symbol and Makefile entries needed to build the new variant. Link: https://lore.kernel.org/all/20260824063627.3595610-9-harendra.gautam@oss.qualcomm.com/ Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
…tibles Add Shikra sound-card compatible strings to the Qualcomm sound card binding so DT can describe board-specific audio topologies: - qcom,shikra-cqm-sndcard - qcom,shikra-cqs-sndcard - qcom,shikra-iqs-sndcard Shikra EVK variants use different codec/interface combinations and DSP processing paths. Describing these variants explicitly in DT allows the machine driver to select the correct DAPM routes, controls, and clocking behavior for each board. Link: https://lore.kernel.org/all/20260611112946.954172-2-ajay.nandam@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add machine-driver support for Qualcomm Shikra EVK variants by matching dedicated compatible strings and applying board-specific audio behavior. Shikra platforms are available as CQM, CQS, and IQS variants with different audio components and processing architectures: - CQM/CQS use an I2S-based path with WSA885x amplifiers and PM4125 + Rouleur codec components. - CQM runs in DSP-bypass mode, where the complete audio pipeline runs on CPU only and no DSP is involved. - CQS uses modem-DSP based audio processing. - IQS uses a third-party MAX98091 codec with modem-DSP support. Introduce variant-specific handling so codec controls, DAPM widgets, and clock programming match the board design and avoid invalid clock setup on variants where it is not applicable. Link: https://lore.kernel.org/all/20260611112946.954172-3-ajay.nandam@oss.qualcomm.com/ Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add bindings for Qualcomm shikra rx and va macro codec. Link: https://lore.kernel.org/all/20260608172023.2965292-2-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add shikra RX macro compatible data and hook it into the existing LPASS codec v4.0 flow. Map codec v4.0 to the 2.5+ RX register handling paths, and enable the FS counter bypass bit during MCLK enable when the platform requests LPASS_MACRO_FLAG_BYPASS_FS_CONTROL. Link: https://lore.kernel.org/all/20260608172023.2965292-3-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add shikra specific VA macro data and register programming needed by the LPASS codec v4.0 implementation. This adds a shikra regmap/default table covering the ADPT register range, wires new match data flags (bypass FS control and ADPT block presence), and enables the ADPT control programming path during TX decimator bring-up. Link: https://lore.kernel.org/all/20260608172023.2965292-4-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…operty Add documentation for the qcom,swr-master-ee-val Device Tree property used by Qualcomm SoundWire masters to describe the execution-environment value for interrupt routing. This property allows platform DTs to specify the EE value used to direct SoundWire master interrupts to the appropriate CPU target. Link: https://lore.kernel.org/all/20260608175345.3118060-2-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…tion Some Qualcomm SoundWire masters expose interrupt, FIFO and status registers in EE-specific register windows on v2.0 and newer hardware. Add support for selecting the SoundWire execution environment from DT and use it to program the correct register window for the active EE. The driver now reads the EE value from the new qcom,swr-master-ee-val property, with qcom,ee as a fallback for backward compatibility. For v2.0+ hardware, the IRQ/FIFO/status register layout is adjusted by the EE window stride so the driver programs the correct bank for the selected EE. The interrupt enable path is also updated to always use the selected EE window. This change allows SoundWire interrupt routing and register accesses to work correctly on platforms where the master is not mapped to the default EE1 window. In Shikra, the soundwire execution environment is set to 0 unlike other Qualcomm boards. Link: https://lore.kernel.org/all/20260608175345.3118060-3-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…or shikra Add support for the modem_apps GLINK channel on Shikra, as audio processing is handled through the modem DSP. Link: https://lore.kernel.org/all/20260616201315.2565115-2-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add the QAIF CPU endpoint in shikra.dtsi so board files can connect LPASS front-end links to backend codecs. Describe the MMIO region, interrupt, IOMMU mapping and required clocks for the QAIF block. Keep the node disabled at SoC level; board dts files enable and consume it in subsequent patches. Link: https://lore.kernel.org/all/20260616201315.2565115-3-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com> Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Link: https://lore.kernel.org/all/20260616201315.2565115-4-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add SoC-level SoundWire masters and LPASS RX/VA macro nodes, along with DMIC and SWR pinctrl states required by the audio data path. Keep these nodes disabled in shikra.dtsi so board dts files can selectively enable and configure them. Link: https://lore.kernel.org/all/20260616201315.2565115-5-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable the sound card on the shikra-cqm-evk platform, including the PM4125 (Rouleur) headset codec, WSA885x external speaker path, and QAIF backend links. Also enable the required LPASS macro and SoundWire nodes, along with the necessary pinctrl configurations for DMIC and I2S interfaces. Link: https://lore.kernel.org/all/20260616201315.2565115-6-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable the sound card on the shikra-cqs-evk platform, including WSA885x external speaker path and DMIC via VA macro Also enable the required LPASS macro along with the necessary pinctrl configurations for DMIC and I2S interfaces. Link: https://lore.kernel.org/all/20260616201315.2565115-7-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable the IQS EVK audio card using MAX98091 on I2S0 for primary playback/capture and VA DMIC capture through q6apm backend links. Add board clock and pinctrl states required for codec IRQ, external mclk and digital mic routing. Link: https://lore.kernel.org/all/20260616201315.2565115-8-mohammad.rafi.shaik@oss.qualcomm.com/ Co-developed-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable the QAIF CPU DAI and WSA885X I2C codec as modules in arm64 defconfig. These options are required to exercise the Shikra EVK audio paths enabled by the preceding DTS changes. Link: https://lore.kernel.org/all/20260616201315.2565115-9-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable the Qualcomm PM4125 audio codec as a loadable module, as it is now required on the Shikra evk platform. Link: https://lore.kernel.org/all/20260620070442.3908242-1-mohammad.rafi.shaik@oss.qualcomm.com/ Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…k IDs The QAIF clock IDs were introduced with a LAPSS prefix typo. Rename them to use the existing LPASS naming convention and update all corresponding in-tree users. Since these IDs are new, rename them directly instead of keeping backward-compatible aliases. Reported-by: Sashiko <sashiko-bot@kernel.org> Link: https://sashiko.dev/#/patchset/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260818084655.3240284-2-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
q6apm_dai_prepare() and q6apm_dai_compr_set_params() build an AudioReach module config on the stack and populate only the fields needed for the stream type. Audio IF media-format setup treats zero slot_mask, nslots_per_frame and slot_width as a request to use the topology defaults. Leave those fields uninitialized and random stack data can override the topology values sent to the DSP. Initialize the whole config structure so omitted fields reliably retain their zero/default meaning. Reported-by: Sashiko <sashiko-bot@kernel.org> Link: https://sashiko.dev/#/patchset/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260818084655.3240284-3-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
… configuration qcom_snd_parse_dai_tdm_slots() uses -EINVAL for both missing DAI-link TDM configuration and malformed TDM slot properties. As a result, qcom_snd_apply_dai_tdm_slots() silently ignores configuration errors. Return -ENOENT for missing DAI-link configuration and preserve -EINVAL for malformed TDM slot properties. Reported-by: Sashiko <sashiko-bot@kernel.org> Link: https://sashiko.dev/#/patchset/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260818084655.3240284-4-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
Treat -ENOENT from TDM slot parsing as the optional "configuration not present" case and continue to propagate real configuration errors. Also ignore -ENOTSUPP from optional DAI format and codec sysclk callbacks, apply codec_dai_fmt to codec DAIs on TDM links, and use a signed bclk_freq variable so errors from snd_soc_tdm_params_to_bclk() are handled correctly. Reported-by: Sashiko <sashiko-bot@kernel.org> Link: https://sashiko.dev/#/patchset/20260804070307.117119-1-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> Link: https://patch.msgid.link/20260818084655.3240284-5-prasad.kumpatla@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
…access model The APM DAIs expose PCM buffers that the backing DSP must be able to reach. On existing targets the DSP runs in a stage-1 context and the buffers are described to the SMMU via the iommus property. On platforms such as Qualcomm Shikra, where audio is served by the modem DSP (mDSP) rather than the ADSP, the DSP runs in a stage-2 protected context and cannot use the SMMU. The buffers are reachable only after hypervisor (SCM) memory assignment to the fixed set of consumer Virtual Machine IDs (VMIDs) that own that protected context. Describe those consumers with a new qcom,vmids property. The two access models are mutually exclusive: a node carries either iommus (stage-1/SMMU) or qcom,vmids (stage-2/SCM), expressed with a oneOf constraint. iommus is therefore no longer unconditionally required. SCM assignment replaces the buffer's current owners with the supplied destination set, so the driver always adds HLOS to that set itself to retain host access; HLOS must not be listed in qcom,vmids. When qcom,vmids is present the PCM buffers must reside in reserved-memory carveouts that are SCM-assigned to the consumer VMIDs. Add an optional memory-region property listing those carveouts. The first entry is the control-path buffer and subsequent entries are data-path buffers. memory-region is only meaningful alongside qcom,vmids, enforced via dependentRequired. Link: https://lore.kernel.org/all/20260826-a2a-shikra-vmid-v5-v2-1-c3dc62354eee@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
…SP buffers On platforms such as Qualcomm Shikra, audio is served by the modem DSP (mDSP) which runs in a stage-2 protected context. Unlike ADSP targets where SMMU-mapped system RAM is directly accessible, the mDSP cannot reach the PCM buffers unless they are explicitly SCM-assigned to the appropriate Virtual Machine IDs (VMIDs). Without this assignment, audio does not function on these platforms. Parse the qcom,vmids DT property and, when present, SCM-assign all memory regions to HLOS (retained as source owner, RW) plus the listed consumer VMIDs (all RW). The two access models are mutually exclusive: a node uses the SMMU path (iommus) or the SCM path (qcom,vmids), never both. Memory assignment follows the upstream pattern used by rmtfs_mem and qcom_q6v5_pas: reserved-memory carveouts are SCM-assigned once at probe() time and restored to HLOS-only ownership via devm_add_action_or_reset() at device removal. For the non-reserved-mem path (qcom,vmids without memory-region), the fixed DMA buffer is assigned at pcm_new() time since its address is only known after allocation. When memory-region is present (has_reserved_mem), the data-path carveout is attached as a DMA pool via of_reserved_mem_device_init_by_idx() and PCM buffers allocate directly from the carveout instead of system RAM. Buffer constraints are capped at reserved_buf_size and snd_pcm_set_managed_buffer_all() replaces snd_pcm_set_fixed_buffer_all(). All new code paths are gated on use_scm_assign (false when qcom,vmids is absent), ensuring existing ADSP/iommus targets are completely unaffected. Link: https://lore.kernel.org/all/20260826-a2a-shikra-vmid-v5-v2-2-c3dc62354eee@oss.qualcomm.com/ Co-developed-by: Mohit Sharma <mohit.sharma@oss.qualcomm.com> Signed-off-by: Mohit Sharma <mohit.sharma@oss.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
AudioReach builds APM and PRM command packets with the GPR destination domain hardcoded to GPR_DOMAIN_ID_ADSP. This assumes audio is always served by the ADSP, which is true for all currently supported targets. On platforms such as Qualcomm Shikra, audio is served by the modem DSP (mDSP) instead. The GPR node in DT already describes which DSP backs the service via its qcom,domain property (e.g. GPR_DOMAIN_ID_MODEM), and the GPR core exposes it as gdev->domain_id. But the AudioReach packet builders ignore this and always target the ADSP, so every APM/PRM command is routed to the wrong DSP on mDSP targets and audio does not function. Fix this by reading the GPR destination domain from gdev->domain_id and stamping it in the send helpers (q6apm_send_cmd_sync, audioreach_graph_send_cmd_sync, q6prm_send_cmd_sync) just before dispatch. This centralizes the domain decision at the send layer rather than threading it through every packet-allocation call site. For the small number of async data-path sends that bypass the sync helpers (write, read, compr, EOS), the domain is stamped inline before gpr_send_port_pkt(). When no domain is available the helper falls back to GPR_DOMAIN_ID_ADSP, so all existing ADSP targets remain unchanged. Link: https://lore.kernel.org/all/20260826-a2a-shikra-vmid-v5-v2-3-c3dc62354eee@oss.qualcomm.com/ Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com> Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
…te APM DAIs memory regions Add a dedicated MDSP carveout memory region for audio usecases on Shikra and mark both existing audio heap and MDSP carveout regions as shared DMA pools. Update the Q6 APM DAI node to reference multiple memory regions, where index 0 is used for control path buffers and index 1 is used for MDSP data path buffers. This separation ensures proper memory allocation and access for APM communication between APSS and MDSP. Also add shared-dma-pool compatibility to the existing audio heap region to align with upstream DMA pool usage. Link: https://lore.kernel.org/all/20260618113509.2025881-3-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…for RPM targets Keep "qcom,rpm-stats" as a fallback for RPM targets, so that SoC level stats are still shown even without subsystem level stats support. A plain enum can't express that, since it caps compatible at one item. Add a oneOf branch with items for this pattern. Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260907-shikra_stats-v4-1-3825351f9740@oss.qualcomm.com
smankad-oss
force-pushed
the
tech/all/shikra
branch
from
September 9, 2026 06:48
f1015f7 to
84c860a
Compare
Komal Bajaj (Komal-Bajaj)
force-pushed
the
tech/all/shikra
branch
from
September 10, 2026 18:30
d2b0b30 to
bba7654
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
20 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Keep "qcom,rpm-stats" as a fallback for RPM targets, so that SoC level stats are still shown even without subsystem level stats support. A plain enum can't express that, since it caps compatible at one item. Add a oneOf branch with items for this pattern.
CRs-fixed: 4539405