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V_CMP_U64 fix #4130

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georgemoralis wants to merge 13 commits into from
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V_CMP_U64 fix #4130

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65c1a7b
handle src1 as VectorGPR in cmp_u64
georgemoralis Mar 16, 2026
ab8f4fd
exec is not permitted
georgemoralis Mar 16, 2026
760133c
made cmp_u64 a real u64 compare use it at your own risk
georgemoralis Mar 16, 2026
221629b
Select for U64 constants
StevenMiller123 Mar 16, 2026
ff40a92
SignedConstIntNeg values are encoded relative to a base value
georgemoralis Mar 16, 2026
5535b3f
brackets
georgemoralis Mar 16, 2026
6ea8587
fixed typo
georgemoralis Mar 16, 2026
17b38ed
avoid using u64 emmiter
georgemoralis Mar 17, 2026
46ad72c
fixed vcclo
georgemoralis Mar 17, 2026
80e1c29
cleanup
georgemoralis Mar 17, 2026
20db2f7
fixed main
georgemoralis Mar 18, 2026
1b6e309
Merge branch 'main' into rec_fixes1
georgemoralis Mar 18, 2026
192519a
Merge branch 'main' into rec_fixes1
georgemoralis Apr 1, 2026
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89 changes: 71 additions & 18 deletions src/shader_recompiler/frontend/translate/vector_alu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1136,52 +1136,105 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
}

void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
const bool is_zero = inst.src[1].field == OperandField::ConstZero;
const bool is_neg_one = inst.src[1].field == OperandField::SignedConstIntNeg;
ASSERT(is_zero || is_neg_one);
if (is_neg_one) {
ASSERT_MSG(-s32(inst.src[1].code) + SignedConstIntNegMin - 1 == -1,
"SignedConstIntNeg must be -1");
}

const IR::U1 src0 = [&] {
const IR::U64 src0 = [&]() -> IR::U64 {
switch (inst.src[0].field) {
case OperandField::ScalarGPR:
return ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code));
case OperandField::VccLo:
return ir.GetVcc();
case OperandField::ScalarGPR: {
IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code));
IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code + 1));
return ir.PackUint2x32(ir.CompositeConstruct(low, high));
}
case OperandField::VectorGPR: {
IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[0].code + 1));
return ir.PackUint2x32(ir.CompositeConstruct(low, high));
}
case OperandField::VccLo: {
IR::U1 vcc_bit = ir.GetVcc();
// Fix: Cast both Imm64 calls to avoid ambiguity
IR::Value vcc_val =
ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
return IR::U64{vcc_val};
}
case OperandField::ConstZero:
return ir.Imm64(static_cast<u64>(0));
case OperandField::SignedConstIntPos:
return ir.Imm64(static_cast<u64>(inst.src[0].code));
case OperandField::SignedConstIntNeg:
return ir.Imm64(static_cast<u64>(-s32(inst.src[0].code)));
default:
UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field));
}
}();

const IR::U64 src1 = [&]() -> IR::U64 {
switch (inst.src[1].field) {
case OperandField::ScalarGPR: {
IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code));
IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code + 1));
return ir.PackUint2x32(ir.CompositeConstruct(low, high));
}
case OperandField::VectorGPR: {
IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[1].code));
IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[1].code + 1));
return ir.PackUint2x32(ir.CompositeConstruct(low, high));
}
case OperandField::VccLo: {
IR::U1 vcc_bit = ir.GetVcc();
IR::Value vcc_val =
ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
return IR::U64{vcc_val};
}
case OperandField::ConstZero:
return ir.Imm64(static_cast<u64>(0));
case OperandField::SignedConstIntPos:
return ir.Imm64(static_cast<u64>(inst.src[1].code));
case OperandField::SignedConstIntNeg:
return ir.Imm64(static_cast<u64>(-s32(inst.src[1].code)));
default:
UNREACHABLE_MSG("Unsupported src[1] operand field: {}", u32(inst.src[1].field));
}
}();

// Perform the 64-bit comparison
const IR::U1 result = [&] {
switch (op) {
case ConditionOp::EQ:
return is_zero ? ir.LogicalNot(src0) : src0;
return ir.IEqual(src0, src1);
case ConditionOp::LG: // NE
return is_zero ? src0 : ir.LogicalNot(src0);
return ir.INotEqual(src0, src1);
case ConditionOp::GT:
ASSERT(is_zero);
return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)));
return ir.IGreaterThan(src0, src1, false); // false = unsigned
case ConditionOp::LT:
return ir.ILessThan(src0, src1, false);
case ConditionOp::GE:
return ir.IGreaterThanEqual(src0, src1, false);
case ConditionOp::LE:
return ir.ILessThanEqual(src0, src1, false);
default:
UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
}
}();

// Handle flags
if (is_signed) {
UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported");
}
if (set_exec) {
UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported");
}

// Write result (1-bit boolean) to destination
switch (inst.dst[1].field) {
case OperandField::VccLo:
return ir.SetVcc(result);
case OperandField::ScalarGPR:
return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
case OperandField::VectorGPR: {
IR::Value result_val = ir.Select(result, ir.Imm32(1), ir.Imm32(0));
ir.SetVectorReg(IR::VectorReg(inst.dst[1].code), IR::U32{result_val});
} break;
default:
UNREACHABLE();
UNREACHABLE_MSG("Unsupported dst field: {}", u32(inst.dst[1].field));
}
}

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