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Merged
shufps merged 7 commits into from
Apr 12, 2026
Merged

Draft: control nonce space and timeouts for all all chip topologies #546

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ffa1f90
add dynamic ASIC nonce space calculation (needs review)
warioishere Apr 4, 2026
6574a80
add Bitaxe-style chip IDs, nonce mapping and VR-disable
warioishere Apr 5, 2026
ec0ad41
add calculateSearchSpaceMs for dynamic ntime rolling
warioishere Apr 5, 2026
44518e0
use next_power_of_two for address_interval calculation
warioishere Apr 7, 2026
27e37f0
use address_interval instead of asic_count for HCN calculation
warioishere Apr 8, 2026
254f4d2
fix HCN core nonce overlap: subtract 268 from hcn_max
warioishere Apr 9, 2026
ba5178a
remove version rolling frequency, use HCN nonce space calculation only
Pmaxsd Apr 10, 2026
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2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -39,3 +39,5 @@ components/components/*
config.bin
config.cvs
managed_components/*
release/
esp-miner-*.bin
42 changes: 19 additions & 23 deletions components/bm1397/asic.cpp
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Expand Up @@ -167,13 +167,7 @@ int Asic::setMaxBaud(void)
return 1000000;
}

// set version rolling frequency
constexpr uint32_t ASIC_IO_CLK_HZ_U32 = 15'000'000u; // 15 MHz
constexpr uint32_t VR_TICK_DIV_U32 = 5000u; // VR counter increments every 5000 IO clock cycles
constexpr uint32_t VR_TICK_HZ_U32 = ASIC_IO_CLK_HZ_U32 / VR_TICK_DIV_U32; // 3000 Hz
constexpr uint64_t VR_REG_PER_HZ_U64 = 65536ull * VR_TICK_HZ_U32; // 196,608,000

// Version rolling frequency register @0x10 (MSB -> LSB)
// Register 0x10 write (MSB -> LSB)
void Asic::setVrFreqReg(uint32_t value) {
ESP_LOGI(TAG, "setting 0x10 to %08lx", value);
send6(CMD_WRITE_ALL, 0x00, 0x10,
Expand All @@ -183,29 +177,29 @@ void Asic::setVrFreqReg(uint32_t value) {
static_cast<uint8_t>((value >> 0) & 0xFF));
}

// Convert desired VR frequency (Hz, integer) to register value for 0x10
uint32_t Asic::vrFreqToReg(uint32_t freq_hz) {
// reg = round(VR_REG_PER_HZ / freq_hz) using integer division with rounding
return static_cast<uint32_t>((VR_REG_PER_HZ_U64 + (freq_hz / 2)) / freq_hz);
}
void Asic::setNonceSpace(float frequency, uint16_t asic_count, uint16_t cores) {
int cores_up = next_power_of_two(cores);
int chips_from_interval = (m_addressInterval > 0) ? (256 / m_addressInterval) : next_power_of_two(asic_count);

// Convert 0x10 register value back to VR frequency (Hz, integer)
uint32_t Asic::vrRegToFreq(uint32_t reg) {
// freq = round(VR_REG_PER_HZ / reg) using integer division with rounding
return static_cast<uint32_t>((VR_REG_PER_HZ_U64 + (reg / 2)) / reg);
}
float hcn_space = (float)NONCE_SPACE / cores_up / chips_from_interval;
double hcn_max = hcn_space * (double)FREQ_MULT / frequency * 0.5;
// HW errata: 134 per half clock cycle = 268 overlap between cores
uint32_t hcn = (uint32_t)hcn_max;
if (hcn > 268) hcn -= 268;

ESP_LOGI(TAG, "Setting nonce space: cores=%d(%d) chips=%d(interval=%d) freq=%.0f HCN=%lu (max=%lu)",
cores, cores_up, chips_from_interval, m_addressInterval, frequency, (unsigned long)hcn, (unsigned long)(uint32_t)hcn_max);

void Asic::setVrFrequency(uint32_t freq_hz) {
setVrFreqReg(vrFreqToReg(freq_hz));
setVrFreqReg(hcn);
}

// default calculation
// default calculation using address_interval
uint8_t Asic::chipIndexFromAddr(uint8_t addr) {
return addr >> 1;
return (m_addressInterval > 0) ? (addr / m_addressInterval) : 0;
}

uint8_t Asic::addrFromChipIndex(uint8_t idx) {
return idx << 1;
return idx * m_addressInterval;
}

void Asic::requestChipTemp() {
Expand Down Expand Up @@ -390,7 +384,9 @@ bool Asic::processWork(task_result *result)

uint32_t rolled_version = (reverseUint16(asic_result.version) << 13); // shift the 16 bit value left 13

int asic_nr = nonceToAsicNr(asic_result.nonce);
// Extract ASIC number from nonce using address_interval (Bitaxe-style)
uint32_t nonce_h = __bswap32(asic_result.nonce);
int asic_nr = (m_addressInterval > 0) ? ((uint8_t)((nonce_h >> 17) & 0xff) / m_addressInterval) : 0;

result->job_id = job_id;
result->asic_nr = asic_nr;
Expand Down
26 changes: 12 additions & 14 deletions components/bm1397/bm1366.cpp
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Expand Up @@ -33,11 +33,7 @@ const uint8_t* BM1366::getChipId() {
return (uint8_t*) chip_id;
}

uint32_t BM1366::getDefaultVrFrequency() {
return vrRegToFreq(0x151c);
};

uint8_t BM1366::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency)
uint8_t BM1366::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty)
{
// reset is done externally to not have board dependencies

Expand Down Expand Up @@ -68,9 +64,10 @@ uint8_t BM1366::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
// chain inactive
sendChainInactive();

// set chip address
// set chip address - distribute evenly across 0-255 range
m_addressInterval = (chip_counter > 0) ? (256 / next_power_of_two(chip_counter)) : 2;
for (uint8_t i = 0; i < chip_counter; i++) {
setChipAddress(i * 2);
setChipAddress(i * m_addressInterval);
}

// Core Register Control
Expand All @@ -88,22 +85,23 @@ uint8_t BM1366::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
send6(CMD_WRITE_ALL, 0x00, 0x58, 0x02, 0x11, 0x11, 0x11);

for (uint8_t i = 0; i < chip_counter; i++) {
uint8_t addr = i * m_addressInterval;
// Reg_A8
send6(CMD_WRITE_SINGLE, i * 2, 0xA8, 0x00, 0x07, 0x01, 0xF0);
send6(CMD_WRITE_SINGLE, addr, 0xA8, 0x00, 0x07, 0x01, 0xF0);
// Misc Control
send6(CMD_WRITE_SINGLE, i * 2, 0x18, 0xF0, 0x00, 0xC1, 0x00);
send6(CMD_WRITE_SINGLE, addr, 0x18, 0xF0, 0x00, 0xC1, 0x00);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x85, 0x40);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x85, 0x40);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x80, 0x20);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x80, 0x20);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x82, 0xAA);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x82, 0xAA);
}

doFrequencyTransition(frequency);

// set 0x10
setVrFrequency(vrFrequency);
// set nonce search space (register 0x10) based on frequency and core count
setNonceSpace((float)frequency, asic_count, getCoreCount());

send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);

Expand Down
27 changes: 12 additions & 15 deletions components/bm1397/bm1368.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,12 +33,7 @@ const uint8_t* BM1368::getChipId() {
return (uint8_t*) chip_id;
}

uint32_t BM1368::getDefaultVrFrequency() {
return vrRegToFreq(0x15a4);
};


uint8_t BM1368::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency)
uint8_t BM1368::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty)
{
// reset is done externally to not have board dependencies

Expand Down Expand Up @@ -69,9 +64,10 @@ uint8_t BM1368::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
// chain inactive
sendChainInactive();

// set chip address
// set chip address - distribute evenly across 0-255 range
m_addressInterval = (chip_counter > 0) ? (256 / next_power_of_two(chip_counter)) : 2;
for (uint8_t i = 0; i < chip_counter; i++) {
setChipAddress(i * 2);
setChipAddress(i * m_addressInterval);
}

// Core Register Control
Expand All @@ -89,22 +85,23 @@ uint8_t BM1368::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
send6(CMD_WRITE_ALL, 0x00, 0x58, 0x02, 0x11, 0x11, 0x11);

for (uint8_t i = 0; i < chip_counter; i++) {
uint8_t addr = i * m_addressInterval;
// Reg_A8
send6(CMD_WRITE_SINGLE, i * 2, 0xA8, 0x00, 0x07, 0x01, 0xF0);
send6(CMD_WRITE_SINGLE, addr, 0xA8, 0x00, 0x07, 0x01, 0xF0);
// Misc Control
send6(CMD_WRITE_SINGLE, i * 2, 0x18, 0xF0, 0x00, 0xC1, 0x00);
send6(CMD_WRITE_SINGLE, addr, 0x18, 0xF0, 0x00, 0xC1, 0x00);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x8B, 0x00);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x8B, 0x00);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x80, 0x18);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x80, 0x18);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 2, 0x3C, 0x80, 0x00, 0x82, 0xAA);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x82, 0xAA);
}

doFrequencyTransition(frequency);

// set 0x10
setVrFrequency(vrFrequency);
// set nonce search space (register 0x10) based on frequency and core count
setNonceSpace((float)frequency, asic_count, getCoreCount());

send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);

Expand Down
35 changes: 14 additions & 21 deletions components/bm1397/bm1370.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -36,11 +36,7 @@ const uint8_t* BM1370::getChipId() {
return (uint8_t*) chip_id;
}

uint32_t BM1370::getDefaultVrFrequency() {
return vrRegToFreq(0x1eb5);
};

uint8_t BM1370::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency)
uint8_t BM1370::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty)
{
// reset is done externally to not have board dependencies

Expand Down Expand Up @@ -72,9 +68,10 @@ uint8_t BM1370::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
// chain inactive
sendChainInactive();

// set chip address
// set chip address - distribute evenly across 0-255 range
m_addressInterval = (chip_counter > 0) ? (256 / next_power_of_two(chip_counter)) : 4;
for (uint8_t i = 0; i < chip_counter; i++) {
setChipAddress(i * 4);
setChipAddress(i * m_addressInterval);
}

// Core Register Control
Expand All @@ -96,16 +93,17 @@ uint8_t BM1370::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult
//send6(CMD_WRITE_ALL, 0x00, 0x28, 0x01, 0x30, 0x00, 0x00);

for (uint8_t i = 0; i < chip_counter; i++) {
uint8_t addr = i * m_addressInterval;
// Reg_A8
send6(CMD_WRITE_SINGLE, i * 4, 0xA8, 0x00, 0x07, 0x01, 0xF0);
send6(CMD_WRITE_SINGLE, addr, 0xA8, 0x00, 0x07, 0x01, 0xF0);
// Misc Control
send6(CMD_WRITE_SINGLE, i * 4, 0x18, 0xF0, 0x00, 0xC1, 0x00);
send6(CMD_WRITE_SINGLE, addr, 0x18, 0xF0, 0x00, 0xC1, 0x00);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 4, 0x3C, 0x80, 0x00, 0x8B, 0x00);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x8B, 0x00);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 4, 0x3C, 0x80, 0x00, 0x80, 0x0C);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x80, 0x0C);
// Core Register Control
send6(CMD_WRITE_SINGLE, i * 4, 0x3C, 0x80, 0x00, 0x82, 0xAA);
send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x82, 0xAA);
}

// ?
Expand All @@ -122,8 +120,8 @@ uint8_t BM1370::init(uint64_t frequency, uint16_t asic_count, uint32_t difficult

doFrequencyTransition(frequency);

// set 0x10
setVrFrequency(vrFrequency);
// set nonce search space (register 0x10) based on frequency and core count
setNonceSpace((float)frequency, asic_count, getCoreCount());

send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);

Expand All @@ -143,13 +141,8 @@ uint8_t BM1370::nonceToAsicNr(uint32_t nonce) {
return (uint8_t) ((nonce & 0x0000fc00) >> 11);
}

uint8_t BM1370::chipIndexFromAddr(uint8_t addr) {
return addr >> 2;
}

uint8_t BM1370::addrFromChipIndex(uint8_t idx) {
return idx << 2;
}
// chipIndexFromAddr and addrFromChipIndex now use base class
// implementation with m_addressInterval (set during init)

uint16_t BM1370::getSmallCoreCount() {
return BM1370_SMALL_CORE_COUNT;
Expand Down
19 changes: 12 additions & 7 deletions components/bm1397/include/asic.h
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Expand Up @@ -34,6 +34,14 @@

#define SLEEP_TIME 20
#define FREQ_MULT 25.0
#define NONCE_SPACE 4294967296.0 // 2^32

static inline int next_power_of_two(int num) {
if (num <= 1) return 1;
int power = 1;
while (power < num) power <<= 1;
return power;
}

#define CLOCK_ORDER_CONTROL_0 0x80
#define CLOCK_ORDER_CONTROL_1 0x84
Expand Down Expand Up @@ -79,6 +87,7 @@ class Asic {
float m_current_frequency;
float m_actual_current_frequency;
uint32_t m_asicDifficulty;
uint8_t m_addressInterval = 2; ///< Chip address spacing (set during init)

void send(uint8_t header, uint8_t *data, uint8_t data_len);
void send2(uint8_t header, uint8_t b0, uint8_t b1);
Expand All @@ -100,10 +109,6 @@ class Asic {
virtual uint8_t chipIndexFromAddr(uint8_t addr);
virtual uint8_t addrFromChipIndex(uint8_t idx);

// helper functions
uint32_t vrFreqToReg(uint32_t freq_hz);
uint32_t vrRegToFreq(uint32_t reg);

virtual uint8_t nonceToAsicNr(uint32_t nonce) = 0;

public:
Expand All @@ -118,10 +123,10 @@ class Asic {
virtual void readCounter(uint8_t reg);
virtual uint16_t getSmallCoreCount() = 0;

void setVrFrequency(uint32_t freq);
virtual uint32_t getDefaultVrFrequency() = 0;
void setNonceSpace(float frequency, uint16_t asic_count, uint16_t cores);
virtual uint16_t getCoreCount() = 0;

virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency) = 0;
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty) = 0;
virtual int setMaxBaud(void);
};

Expand Down
4 changes: 2 additions & 2 deletions components/bm1397/include/bm1366.h
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Expand Up @@ -8,7 +8,6 @@
class BM1366 : public Asic {
protected:
virtual const uint8_t* getChipId();
virtual uint32_t getDefaultVrFrequency();

virtual uint8_t jobToAsicId(uint8_t job_id);
virtual uint8_t asicToJobId(uint8_t asic_id);
Expand All @@ -17,7 +16,8 @@ class BM1366 : public Asic {
public:
BM1366();
virtual const char* getName() { return "BM1366"; };
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency);
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty);
virtual uint16_t getSmallCoreCount();
virtual uint16_t getCoreCount() { return 112; }
};

4 changes: 2 additions & 2 deletions components/bm1397/include/bm1368.h
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Expand Up @@ -8,7 +8,6 @@
class BM1368 : public Asic {
protected:
virtual const uint8_t* getChipId();
virtual uint32_t getDefaultVrFrequency();

virtual uint8_t jobToAsicId(uint8_t job_id);
virtual uint8_t asicToJobId(uint8_t asic_id);
Expand All @@ -17,8 +16,9 @@ class BM1368 : public Asic {
public:
BM1368();
virtual const char* getName() { return "BM1368"; };
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency);
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty);
virtual void requestChipTemp();
virtual uint16_t getSmallCoreCount();
virtual uint16_t getCoreCount() { return 80; }
};

6 changes: 2 additions & 4 deletions components/bm1397/include/bm1370.h
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Expand Up @@ -8,18 +8,16 @@
class BM1370 : public Asic {
protected:
virtual const uint8_t* getChipId();
virtual uint32_t getDefaultVrFrequency();

virtual uint8_t jobToAsicId(uint8_t job_id);
virtual uint8_t asicToJobId(uint8_t asic_id);

virtual uint8_t nonceToAsicNr(uint32_t nonce);
virtual uint8_t chipIndexFromAddr(uint8_t addr);
virtual uint8_t addrFromChipIndex(uint8_t idx);
public:
BM1370();
virtual const char* getName() { return "BM1370"; };
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency);
virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty);
virtual uint16_t getSmallCoreCount();
virtual uint16_t getCoreCount() { return 128; }
};

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