[Attention] TRITON_MLA_SPARSE backend for SM80/SM121 sparse MLA (rebase & takeover of #38476)

[thomaslwang]

[Attention] TRITON_MLA_SPARSE backend for SM80/SM121 sparse MLA (rebase & takeover of #38476)

Purpose

Rebase and continuation of #38476 by @haosdent, which adds a Triton-based sparse MLA
attention backend (TRITON_MLA_SPARSE) so DSA sparse-MLA models (DeepSeek-V3.2,
GLM-5.x) can run on GPUs where DeepGEMM and FlashMLA-Sparse are unavailable —
SM80 (A100/A800) and SM121 (GB10/DGX Spark).

Per the discussion in #38476 (see comments from 2026-06-29 onward): #43477 has merged,
maintainers indicated openness to merging this backend after a rebase, and the original
author has been inactive since mid-May. This PR takes over that work as invited in the
thread, crediting the original author (the main commit retains @haosdent's authorship).

Changes vs the original #38476

• Rebased onto current main. The indexer dispatch in sparse_attn_indexer.py is now a
  three-way is_xpu() → DeepGEMM → Triton fallback chain, preserving main's XPU path,
  skip_topk_buffer_clear optimization, and DCP handling.
• Backend priority (maintainer request): TRITON_MLA_SPARSE is appended after
  FLASH_ATTN_MLA_SPARSE and FLASHMLA_SPARSE in the SM8x/9x candidate list, so SM90+
  keeps native sparse backends and only SM80/SM121 fall through to Triton.
• New fix: gate use_fused_indexer_q (from [GLM5.2 Perf] fused_indexer_q_rope_quant triton kernel, 1.9% ~ 3.3% E2E Throughput improvement. #46862) on SM89+ — its Triton kernel
  stores fp8e4nv, which does not compile on SM80; older archs use the pre-existing
  unfused rope + per_token_group_quant_fp8 path.

Relationship to other PRs

• [bugfix]: support deepseek sparse attention on unsupported targets #39594 forces dense attention on unsupported targets via an env var (a correctness
  workaround that gives up sparse attention); this PR keeps sparse attention with Triton
  kernels. The two are complementary.
• [WIP]Support DeepSeek V4 flash on SM120 with Triton fallback #40929 / [New Model][Nvidia] Add SM12x support for DeepSeek V4 Flash with essential fixes #41834 target DeepSeek-V4 on SM120 specifically; this PR is about the
  DSA sparse-MLA indexer/attention path for V3.2/GLM-5.x on SM80/SM121.

Test Plan / Test Result

All on 8× NVIDIA A800-80GB PCIe (SM80), driver 580.95.05, this branch installed with
VLLM_USE_PRECOMPILED=1:

• pytest tests/kernels/attention/test_mqa_logits_triton.py — 41 passed (24.8s)
• pytest tests/kernels/attention/test_triton_mla_sparse_kernel.py — 53 passed (100.4s)
• End-to-end serve of GLM-5.2 NVFP4 (nvidia/GLM-5.2-NVFP4), TP=8, EP,
  bf16 KV cache, --max-model-len 131072:
  • Backend selection: Using TRITON_MLA_SPARSE attention backend out of potential backends: ['TRITON_MLA_SPARSE'] + DeepGEMM-fallback warning as expected
  • CUDA graph capture clean under default FULL_AND_PIECEWISE
    (mixed PIECEWISE 4/4 + decode FULL 3/3, 10s) — no Triton
    compile-during-capture issues; the backend's built-in autotune warmup covers it
  • GPU KV cache size: 202,688 tokens; default block size works (no
    --block-size override needed)
  • Correctness spot checks: math prompt correct; tool calling via glm47 parser
    produces well-formed tool_calls with finish_reason=tool_calls
  • Throughput: 32.3 tok/s single-stream decode, 100.3 tok/s aggregate at
    4-way concurrency (256-token completions)
• Regression guard: SM90+ candidate order keeps FLASH_ATTN_MLA_SPARSE and
  FLASHMLA_SPARSE ahead of TRITON_MLA_SPARSE (Triton is last-resort only).
• Pipeline parallelism (single node, TP=2 × PP=4, --block-size 128):
  • Tool/reasoning parsers work under PP (glm47/glm45): correct tool_calls
    after long contexts; needle retrieval accurate at 79k prompt tokens; two
    concurrent 53k-token tool-call requests both correct
  • bf16 KV capacity: 524,288 boots at TP=2×PP=4; full 1M
    (max-model-len 1048576) boots at TP=1×PP=8 with
    VLLM_PP_LAYER_PARTITION="11,10,10,10,10,10,10,7" (the default even
    split leaves the last stage — LM head + sampler activations — short) and
    --gpu-memory-utilization 0.96: KV cache 1,062,656 tokens, needle
    retrieval exact at 250k prompt tokens (with [Bugfix][Core] Sync reused pinned input buffers under PP batch queue (fixes IMA with sparse MLA + PP) #47644 applied; without it,
    a single long chunked prefill hits the pinned-buffer race)
  • The No common block size for 16. PP startup failure is fixed by the
    MultipleOf(64) declaration in this PR

Known issues

• PP + concurrent long prefills can nondeterministically hit an illegal
  memory access Root-caused and fixed in [Bugfix][Core] Sync reused pinned input buffers under PP batch queue (fixes IMA with sparse MLA + PP) #47644 (core model-runner race:
  reused pinned input buffers are unguarded under the PP batch queue without
  async scheduling; not specific to this backend). With that fix applied, the
  previously-crashing 9-concurrent-long-prefill stress passes 27/27 on
  TP=2×PP=4.
• Inherited from the original PR thread: sporadic NaN logits under sustained
  high load reported by one user on a hand-patched June build; not yet
  reproduced on this branch. Will track in a follow-up issue if it reproduces.

Notes

• AI assistance was used for the rebase and conflict resolution (Claude Code); every
  changed line has been reviewed by the submitter, who ran the tests above.

Co-authored-by: haosdent haosdent@gmail.com

🤖 Generated with Claude Code

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[mergify]

Documentation preview: https://vllm--47629.org.readthedocs.build/en/47629/

[halexan]

Great job!

[claude]

Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

[jharmon96]

Thanks for this! I spent the last couple days trying to get it all running on my own heterogenous hardware. I worked off this PR to patch bits and pieces until it landed at a decent spot. I used claude Fable to assist heavily. I'm a long time dev, but never contributed to open source or AI related work, so I hope this is helpful...

Field report: TRITON_MLA_SPARSE running GLM-5.2 744B (AWQ INT4) on a mixed
SM86+SM120 fleet, TP2×PP6 — including working MTP speculative decoding under
pipeline parallelism

Thanks for this backend — it resurrected DSA models on hardware the DeepGEMM
path can't serve. We have GLM-5.2 (AWQ INT4, compressed-tensors) in
production on 12 mixed GPUs (2× RTX PRO 6000 Blackwell, 2× RTX 5090, 8× RTX
3090), TP2×PP6, with --attention-backend TRITON_MLA_SPARSE: 904 tok/s
prefill, 14.8 tok/s decode with MTP spec decode (~80% acceptance, k=1),
40–62k context, output-validated to 25k+ context. Sharing the bugs we hit —
the first two are one-line kernel fixes in this PR's Triton path that
affect ANY spec-decode user, the rest are generic vLLM issues this backend
newly exposes.

Two Triton-path kernel bugs (spec decode only, one-line fixes)

Both are invisible at next_n == 1 and below index_topk (2048) context —
which is why plain decode looks perfect and why they survive short tests.
With MTP (next_n == 2) output corrupts progressively beyond ~2048 total
context (word doubling → repetition loops → garbage). Empirically isolated
and fixed; both validated together (3400-token generations flawless, 25k
prompts clean):

A. 2D seq_lens fed to a kernel that indexes it 1D. The decode caller
passes the raw (B, next_n) seq_lens to fp8_paged_mqa_logits_triton, but
_fp8_paged_mqa_logits_kernel loads context_lens_ptr + batch_id (1D, full
length expected — it derives per-row causal offsets itself via
q_offset = L - next_n + next_n_id). Every request reads a wrong length
(and at B>1, other requests' lengths). The sibling XPU branch already
flattens with seq_lens[:, -1]; the Triton branch misses it. Fix: same
flatten at the Triton call site in sparse_attn_indexer.py.

B. Unmasked OOB store spills -inf into the next logits row. The
kernel's last block stores k_offset up to 128*ceil(L/128)-1 masked only
by mask_n, while the logits row stride is the ACTIVE batch max_seq_len
(not block-aligned). Up to 127 columns of -inf land in the next row's
oldest positions — with spec decode, the base row erases the bonus row's
oldest context (including the prompt), and past index_topk the value-based
top-k then drops those positions. (Below 2048 the trivial top-k branch
selects by position and hides it.) Also writes past the allocation on the
last row. Fix: mask=mask_n & (k_offset < context_len) on the store.

Happy to PR both (they're one line each plus comments).

Portability fixes needed for mixed-capability fleets

1. Device-0-scoped capability gates. use_fused_indexer_q gates on
   current_platform.has_device_capability(89), which checks device 0. On a
   heterogeneous fleet, SM86 workers then compile the fp8e4nv Triton indexer
   kernel and die. Fixed locally by gating on
   torch.cuda.get_device_capability() (the worker's own device). Backend
   auto-selection has the same device-0 scoping (we force the backend
   explicitly as a workaround).

2. safetensors lazy load + dispatch modes. In worker context,
   safe_open.get_tensor intermittently fails with "could not determine the
   shape of object type 'torch.storage.UntypedStorage'" (a leaked torch
   function/dispatch mode routes it into torch._refs). Guarded retry under
   DisableTorchFunction + _disable_current_modes fixes it. (Will file
   separately — unrelated to this PR.)

MTP speculative decoding: draft-config inheritance bug family

We got MTP working with a separate draft checkpoint
(method:"mtp", num_speculative_tokens:1). Every failure below traces to
the same root pattern: the draft model's config is derived from the
target's and is only correct for vanilla single-node TP. Together with
local-inference-lab#72 (draft config doesn't inherit
decode_context_parallel_size under DCP), that's four confirmed members:

3. SpeculativeConfig doesn't inherit attention_backend. The draft
   auto-selects independently (device-0-scoped again) and can pick a backend
   with an incompatible KV spec: we got fp8_ds_mla (656B/token) allocation
   vs a bf16 (1152B/token) reshape —
   shape '[730, 64, 576]' invalid for input of size 15324160. Workaround:
   "attention_backend": "TRITON_MLA_SPARSE" inside --speculative-config.

4. Draft inherits the target's quant_config.
   _create_draft_vllm_config keeps base.quant_config. When the draft
   checkpoint's compressed-tensors ignore-list differs from the target's
   (ours: draft quantizes attention, target doesn't; draft ignores
   layer-scoped indexer/gate projections the target's list doesn't name),
   layer-78 modules are built with the wrong scheme. Fix: derive
   quant_config from the draft's own model config when the draft is a
   separate checkpoint.

5. MTP embedding sharing is gated pp_group().world_size == 1
   (_maybe_share_embeddings), while _maybe_share_lm_head has no PP guard.
   Under PP the drafter's embed_tokens is silently left at random init
   (DeepSeek-style MTP checkpoints intentionally omit it, and
   DeepSeekMTP.load_weights drops any tensor without a spec-layer index,
   so nothing loads it). Result: the drafter reproduces the target's own
   prediction — exactly-0% acceptance that looks like an echo bug.
   Workaround: re-export the draft checkpoint with the target's embedding
   spliced in as model.layers.<n>.embed_tokens.weight (top-level
   naming is silently dropped by the loader). Proper fix: share/load the
   embedding on the drafter's rank under PP.

Sync-PP scheduler races (spec decode + batch queue)

With PP>1 and --no-async-scheduling, three interlocking races made spec
decode produce 0% acceptance and corrupted output streams. All three are in
core vLLM, not this PR, but they're only reachable once a backend like this
one makes PP spec decode viable on such fleets:

6. Batch queue schedules a spec request's next step before
   update_from_output processes its verification — stale
   num_computed_tokens, empty payloads, worker-side
   IndexError: list index out of range in _update_states, silent KV
   desync. Notably the prefill→first-verify boundary: the first verify can
   be scheduled before the prefill's sampled token is appended, which puts
   the draft token at the base KV position (one-position verify shift; a
   token vanishes from the emitted stream).

7. Drafts produced by verify steps are dropped. post_step gates
   take_draft_token_ids on the schedule phase's model_executed; when
   the spec request is (correctly) not re-scheduled until its verification
   is processed, that phase is empty and the freshly proposed drafts are
   never collected — the scheduler then schedules stale/zero draft ids (the
   rejection sampler reads draft ids positionally from input_ids, so this
   also manifests as draft_token_ids == 0 worker-side).

8. Accepted draft tokens are never delivered to non-last PP ranks. They
   reach the last rank as spec inputs, but the next step's payload
   (_make_cached_request_data) starts at num_computed_tokens, so ranks
   0..N-2 never see them — their token streams shift one position per
   acceptance and verify verdicts drift progressively (accumulating
   wrongful rejections, output corruption).

Our fixes for 6–8 (scheduler-side serialization of spec-request steps under
sync-PP, forced draft collection after processing spec-carrying batches, and
payload over-delivery of accepted tokens — the worker's
num_computed + len(new) - req_state.num_tokens reconciliation dedups the
overlap) are small and validated: 83% acceptance, byte-correct output over
long multi-turn/streaming/concurrent sessions. Happy to open PRs / share
diffs if there's interest — or if the newer runner path already restructures
this, pointers appreciated.

Environment: vLLM @ bbe2ab4 (this PR's head, pinned) + PR #47644
cherry-picked, VLLM_USE_PRECOMPILED=1, CUDA graphs off,
--disable-custom-all-reduce, blocks=128.