[Bugfix][Core] Sync reused pinned input buffers under PP batch queue (fixes IMA with sparse MLA + PP)#47644
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prepare_inputs_event was only created with async scheduling, but the PP batch queue creates the same overlap: input prep for step N+1 rewrites the reused pinned CPU tensors (seq_lens_cpu, query_start_loc_cpu, ...) while step N's non_blocking H2D copies from those buffers may still be pending, so step N's kernels can consume step N+1's values. Observed as nondeterministic illegal memory accesses with DSA sparse-MLA models under PP with --no-async-scheduling (kernels index with device seq_lens into buffers sized from the CPU values of the earlier step); disappears under CUDA_LAUNCH_BLOCKING=1 and with TP-only. Create the event whenever max_concurrent_batches > 1 so synchronize_input_prep() guards every overlapped-step configuration. Repro: GLM-5.2 NVFP4 on 8xA800 (SM80, vllm-project#47629), TP=2 PP=4, 9 concurrent 50-90k-token prefills crashed within ~2 min; with this fix 27/27 requests across 3 rounds complete with correct outputs. Signed-off-by: Thomas Wang <thomas.l.wang@gmail.com>
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Production data point from a large A100 (sm80) deployment, in case it helps — we run the For the "is sm80 sparse-MLA worth supporting?" question upstream: GLM-5.2 on A100 is only possible via the Triton sparse-MLA path, and it's been serving a multi-day batch-generation workload for us — so there's at least one real production user depending on it. Setup
Symptom
Because CUDA errors are reported asynchronously, the watchdog stacktrace only shows where the error surfaced (the next NCCL collective), not the faulting kernel — so I can't prove from the trace alone that it's the reused-pinned-buffer race described here. But the trigger conditions match this PR's analysis exactly: PP batch queue ( Offer: since our serves cycle frequently anyway, I can apply this PR across the fleet and report whether the decode-time IMA rate drops from ~13/381 to zero over comparable serve-hours — a clean before/after on real sm80 hardware. Happy to test against whatever commit / combination with #47629 is most useful. |
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Purpose
Fix a race on reused pinned CPU input buffers when engine steps overlap under the PP batch queue.
prepare_inputs_event(consumed bysynchronize_input_prep()) was only created when async scheduling is enabled. But the PP batch queue creates exactly the same overlap (max_concurrent_batches == pp_size): input prep for step N+1 rewrites the reused pinned CPU tensors (seq_lens_cpu,query_start_loc_cpu, block-table staging, …) while step N'snon_blockingH2D copies from those same buffers may not have executed yet. When the copy engine finally runs, step N's kernels consume step N+1's values.For DSA sparse-MLA models this is fatal rather than silent: the indexer sizes its prefill-chunk buffers from step N's CPU values but its GPU kernels index with the (now newer, possibly larger) device
seq_lens— out-of-bounds scatter →Triton Error [CUDA]: an illegal memory access was encountered. Reported in the field in #38476 (multi-node TP×PP, and single-node repro below). For dense models the same race can silently corrupt inputs.The fix creates the event whenever
max_concurrent_batches > 1, sosynchronize_input_prep()guards every overlapped-step configuration (async scheduling ⇒ ≥ 2; PP ⇒ pp_size). Single-batch configurations are unchanged.Why the symptom is so elusive
CUDA_LAUNCH_BLOCKING=1makes every H2D copy synchronous → pinned buffers are always consumed before reuse → 100% stable (verified). This masks the bug in exactly the debugging mode people reach for.max_concurrent_batches == 1→ unaffected.Test Plan / Test Result
Repro hardware: 8×A800-80G PCIe (SM80), GLM-5.2 NVFP4 via #47629, TP=2 × PP=4,
--no-async-scheduling, bf16 KV:illegal memory access, surfacing at the indexer'sbuild_prefill_chunk_metadatakernel launch). Reproduced twice; also reproduced by @Ph0enix89 on multi-node in [Feature] TRITON_MLA_SPARSE backend for SM8x/11x/12x DSA Sparse MLA Support #38476.Notes
prepare_inputs_event).🤖 Generated with Claude Code