[testing] Move D/I Mem tests to MemorySpec

src/test/scala-2/chiselTests/Mem.scala

@@ -3,8 +3,10 @@
 package chiselTests
 
 import chisel3._
+import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 import chisel3.simulator.scalatest.ChiselSim
 import chisel3.simulator.stimulus.RunUntilFinished
+import chisel3.testing.scalatest.FileCheck
 import chisel3.util.{is, switch, Counter, SRAM}
 import circt.stage.ChiselStage
 import org.scalatest.propspec.AnyPropSpec
@@ -342,7 +344,13 @@ class MemMaskedReadWriteTester extends Module {
   }
 }
 
-class MemorySpec extends AnyPropSpec with Matchers with ChiselSim {
+@instantiable
+class HasMems() extends Module {
+  @public val mem = Mem(8, UInt(32.W))
+  @public val syncReadMem = SyncReadMem(8, UInt(32.W))
+}
+
+class MemorySpec extends AnyPropSpec with Matchers with ChiselSim with FileCheck {
   property("Mem of Vec should work") {
     simulate(new MemVecTester)(RunUntilFinished(3))
   }
@@ -450,8 +458,38 @@ class MemorySpec extends AnyPropSpec with Matchers with ChiselSim {
     }
     ChiselStage.emitSystemVerilog(new TestModule)
   }
-}
 
+  property("Definition/Instance should work with Mems/SyncReadMems") {
+    import chiselTests.experimental.hierarchy.Annotations._
+    class Top() extends Module {
+      val i = Definition(new HasMems())
+      mark(i.mem, "Mem")
+      mark(i.syncReadMem, "SyncReadMem")
+      ChiselStage
+        .emitCHIRRTL(new Top)
+        .fileCheck()(
+          """|CHECK:      "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
+             |CHECK-NEXT: "target":"~|HasMems>mem"
+             |CHECK-NEXT: "tag":"Mem"
+             |CHECK:      "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
+             |CHECK-NEXT: "target":"~|HasMems>syncReadMem"
+             |CHECK-NEXT: "tag":"SyncReadMem"
+             |""".stripMargin
+        )
+    }
+  }
+  property("Definition/Instance with Mems should not create memory ports") {
+    class Top() extends Module {
+      val i = Definition(new HasMems())
+      i.mem(0) := 100.U // should be illegal!
+    }
+    intercept[ChiselException] {
+      ChiselStage.elaborate(new Top)
+    }.getMessage should include(
+      "Cannot create a memory port in a different module (Top) than where the memory is (HasMems)."
+    )
+  }
+}
 class SRAMSpec extends AnyFunSpec with Matchers {
   describe("SRAM") {
     val portCombos: Seq[(Int, Int, Int)] =

src/test/scala-2/chiselTests/experimental/hierarchy/DefinitionSpec.scala

@@ -569,36 +569,8 @@ class DefinitionSpec extends AnyFunSpec with Matchers with FileCheck {
              |""".stripMargin
         )
     }
-    it("(3.n): should work on Mems/SyncReadMems") {
-      class Top() extends Module {
-        val i = Definition(new HasMems())
-        mark(i.mem, "Mem")
-        mark(i.syncReadMem, "SyncReadMem")
-      }
-      ChiselStage
-        .emitCHIRRTL(new Top)
-        .fileCheck()(
-          """|CHECK:      "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
-             |CHECK-NEXT: "target":"~|HasMems>mem"
-             |CHECK-NEXT: "tag":"Mem"
-             |CHECK:      "class":"chiselTests.experimental.hierarchy.Annotations$MarkAnnotation"
-             |CHECK-NEXT: "target":"~|HasMems>syncReadMem"
-             |CHECK-NEXT: "tag":"SyncReadMem"
-             |""".stripMargin
-        )
-    }
-    it("(3.o): should not create memory ports") {
-      class Top() extends Module {
-        val i = Definition(new HasMems())
-        i.mem(0) := 100.U // should be illegal!
-      }
-      intercept[ChiselException] {
-        ChiselStage.elaborate(new Top)
-      }.getMessage should include(
-        "Cannot create a memory port in a different module (Top) than where the memory is (HasMems)."
-      )
-    }
-    it("(3.p): should work on HasTarget") {
+
+    it("(3.n): should work on HasTarget") {
       class Top() extends Module {
         val i = Definition(new HasHasTarget)
         mark(i.x, "x")
@@ -612,7 +584,7 @@ class DefinitionSpec extends AnyFunSpec with Matchers with FileCheck {
              |""".stripMargin
         )
     }
-    it("(3.q): should work on Tuple5 with a Module in it") {
+    it("(3.o): should work on Tuple5 with a Module in it") {
       class Top() extends Module {
         val defn = Definition(new HasTuple5())
         val (3, w: UInt, "hi", inst: Instance[AddOne], l) = defn.tup

src/test/scala-2/chiselTests/experimental/hierarchy/Examples.scala

@@ -288,12 +288,6 @@ object Examples {
     val i11 = Instance(tpDef1)
   }
 
-  @instantiable
-  class HasMems() extends Module {
-    @public val mem = Mem(8, UInt(32.W))
-    @public val syncReadMem = SyncReadMem(8, UInt(32.W))
-  }
-
   @instantiable
   class LeafInstantiable(val bundle: Data) {
     @public val bundle = bundle

src/test/scala/chiselTests/experimental/hierarchy/Annotations.scala

@@ -8,7 +8,7 @@ import chisel3.{Data, HasTarget, MemBase}
 import chisel3.experimental.hierarchy.{Definition, Hierarchy, Instance}
 
 // These annotations exist purely for testing purposes
-private[hierarchy] object Annotations {
+object Annotations {
   case class MarkAnnotation(target: IsMember, tag: String) extends SingleTargetAnnotation[IsMember] {
     def duplicate(n: IsMember): Annotation = this.copy(target = n)
   }