Debug spec v1.0 implementation #1590
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| Original file line number | Diff line number | Diff line change |
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| # Wally Debug List | ||
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| It is our hope that we will get to many of these items for Wally with | ||
| the RISC-V Debug specification. We have posted a MarkDown file that lists | ||
| the capabilities we have implemented including the items we hope to | ||
| implement soon. | ||
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| ### Supported RISC-V Debug Specification | ||
| We are currently using the Debug specification with | ||
| Version 1.0, Revised 2025-02-21 |
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| # Wally Debug Feature List | ||
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| :x: means we currently have no intention of implementing this feature. | ||
| 🔶 means we intend to implement this in the future at some point but it is not immediately imperative. | ||
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| Anything else is intended to be implemented and will be implemented as soon as possible. | ||
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| General Overview of Implemented Features: | ||
| - [x] Halting and Resuming | ||
| - [x] Abstract GPR read and write access. | ||
| - [x] Abstract CSR read and write access. | ||
| - [ ] Stepping | ||
| - [x] Resetting from Debug Module | ||
| - [x] Halt on Reset | ||
| - [ ] Trigger Modules 🔶 | ||
| - [ ] Program buffer 🔶 | ||
| - [ ] System bus access 🔶 | ||
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| DTM Registers | ||
| - [x] idcode | ||
| - [x] dtmcs | ||
| - [x] dmi | ||
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| Debug Module | ||
| - [x] DMControl | ||
| - [x] haltreq | ||
| - [x] resumereq | ||
| - [ ] hartreset | ||
| - [x] ackhavereset | ||
| - [ ] ackunavail :x: | ||
| - I can't imagine there's a scenario where the only hart that exists wouldn't be available, but I need to investigate further, just in case. | ||
| - [ ] hasel :x: | ||
| - By hardcoding this to `0` as well as the hardcoding `hartsello` and `hartselhi` to 0 indicates to the debugger that there is only one hart. If Wally becomes multicore, this will need to be expanded so that we can select many harts. For now, it's not important to implement. | ||
| - [ ] hartsello :x: | ||
| - [ ] hartselhi :x: | ||
| - [ ] setkeepalive | ||
| - [ ] clrkeepalive | ||
| - [x] setresethaltreq | ||
| - [x] clrresethaltreq | ||
| - [x] ndmreset | ||
| - [x] dmactive. Note: Partially implemented. It needs to actually block writes to other debug module registers when set low. | ||
| - [x] DMStatus | ||
| - [x] ndmresetpending | ||
| - [ ] stickyunavail 🔶 | ||
| - [ ] impebreak 🔶 | ||
| - [x] allhavereset | ||
| - [x] anyhavereset | ||
| - [x] allresumeack | ||
| - [x] anyresumeack | ||
| - [ ] allnonexistent | ||
| - [ ] anynonexistent | ||
| - [ ] allunavail :x: | ||
| - [ ] anyunavail :x: | ||
| - [x] allrunning | ||
| - [x] anyrunning | ||
| - [x] allhalted | ||
| - [x] anyhalted | ||
| - [ ] authenticated 🔶 | ||
| - [ ] authbusy 🔶 | ||
| - [ ] hasresethaltreq | ||
| - [ ] confstrptrvalid :x: | ||
| - [x] version | ||
| - [x] Command | ||
| - [x] AbstractCS | ||
| - [ ] progbufsize 🔶 | ||
| - [ ] busy | ||
| - For clarification, abstract access are near immediate currently, so there are no busy cycles. This is subject to change. | ||
| - [ ] relaxedpriv 🔶 | ||
| - [x] cmderr | ||
| - [x] datacount | ||
| - [x] Data0 | ||
| - [x] Data1 (`if XLEN == 64`) | ||
| - [ ] HartInfo | ||
| - [ ] Hart Array Window Select | ||
| - [ ] Hart | ||
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| Debug Extension | ||
| - [x] DCSR | ||
| - [x] Halting | ||
| - [x] Resuming | ||
| - [x] Version field | ||
| - [x] Halt cause updating | ||
| - [ ] Stepping | ||
| - [ ] Stepie 🔶 | ||
| - This is for enabling interrupts during stepping. Not as important as implementing stepping itself for now. | ||
| - [ ] Ebreak to Debug mode in all modes | ||
| - [ ] Stop counters 🔶 | ||
| - [ ] Stop time 🔶 | ||
| - [ ] extcause :x: | ||
| - Can just be set to 0 for not being implemented and also stays 0 even if cetrig is implemented which is partly what it's needed for. All other values are reserved for future version of the RISCV debug spec. | ||
| - [ ] nmip 🔶 | ||
| - [ ] prv | ||
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Contributor
There was a problem hiding this comment. These three are important. |
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| - [ ] mprven | ||
| - [ ] v 🔶 | ||
| - [x] DPC | ||
| - [x] Grabs PC + 4 on Halt | ||
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Contributor
There was a problem hiding this comment. Or PC+2. Could get from the IFU PC logic. |
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| - [ ] Resumes at DPC value on Resume | ||
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| - [ ] Sdtrig 🔶 | ||
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| Original file line number | Diff line number | Diff line change |
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| /////////////////////////////////////////// | ||
| // bsr.sv | ||
| // | ||
| // Written: Jacob Pease jacobpease@protonmail.com, | ||
| // James E. Stine james.stine@okstate.edu | ||
| // Created: August 4th, 2025 | ||
| // Modified: | ||
| // | ||
| // Purpose: Boundary Scan Register with load on reset | ||
| // | ||
| // A component of the CORE-V-WALLY configurable RISC-V project. | ||
| // https://github.com/openhwgroup/cvw | ||
| // | ||
| // Copyright (C) 2021-25 Harvey Mudd College & Oklahoma State University | ||
| // | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 | ||
| // | ||
| // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file | ||
| // except in compliance with the License, or, at your option, the Apache License version 2.0. You | ||
| // may obtain a copy of the License at | ||
| // | ||
| // https://solderpad.org/licenses/SHL-2.1/ | ||
| // | ||
| // Unless required by applicable law or agreed to in writing, any work distributed under the | ||
| // License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, | ||
| // either express or implied. See the License for the specific language governing permissions | ||
| // and limitations under the License. | ||
| //////////////////////////////////////////////////////////////////////////////////////////////// | ||
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| module bsr #(parameter WIDTH=8) ( | ||
| input logic [WIDTH-1:0] DataIn, | ||
| input logic ScanIn, | ||
| input logic ShiftDR, ClockDR, UpdateDR, Mode, | ||
| output logic [WIDTH-1:0] Qout, | ||
| output logic ScanOut | ||
| ); | ||
| logic [WIDTH-1:0] shiftreg; | ||
| logic [WIDTH-1:0] y; | ||
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| always @(posedge ClockDR) | ||
| shiftreg <= ShiftDR ? {ScanIn, shiftreg[WIDTH-1:1]} : DataIn; | ||
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| always @(posedge UpdateDR) | ||
| y <= shiftreg; | ||
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| assign Qout = Mode ? y : DataIn; | ||
| assign ScanOut = shiftreg[0]; | ||
| endmodule // bsr |
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change to - for not planned
indicate x means done
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High level comment that debugger halts pipeline and takes abstract commands.
Indicate that "Minimal Debug Spec" is implemented with just abstract read/write of GPRs, FPRs, almost all CSRs (which ones not?