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Fixed #1725 cbo.zero #1735

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jordancarlin merged 1 commit intoopenhwgroup:mainfrom
davidharrishmc:dev
Apr 14, 2026
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Fixed #1725 cbo.zero #1735
jordancarlin merged 1 commit intoopenhwgroup:mainfrom
davidharrishmc:dev

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@davidharrishmc
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bug found and fixed by Claude looking at code and Verilator waveforms; checked new code works. Without waveforms, Claude timed out.

… and Verilator waveforms; checked new code works. Without waveforms, Claude timed out.
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Pull request overview

This PR addresses a cbo.zero (Zicboz) corner case in the cache FSM where a zeroing operation with no dirty eviction needs to stall and force an SRAM re-read on the following cycle to ensure correct behavior.

Changes:

  • Add an explicit STATE_ACCESS -> STATE_ADDRESS_SETUP transition for CMOZeroNoEviction (cbo.zero with no dirty writeback needed).
  • Extend StallConditions (and therefore CacheStall) to include CMOZeroNoEviction so the pipeline is stalled for the required extra cycle.

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@jordancarlin jordancarlin linked an issue Apr 13, 2026 that may be closed by this pull request
@jordancarlin jordancarlin merged commit 67f1a35 into openhwgroup:main Apr 14, 2026
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ACT4 Zicboz test case fails on rv32gc and rv64gc

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