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@libresilicon Libre Silicon Alliance

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    25 repositories

    • rocket-chip

      Public
      Rocket Chip Generator
      Scala
      •
      Other
      •1.3k•0•0•0•Updated Aug 22, 2024Aug 22, 2024

    • pythondata-cpu-rocket

      Public
      Python module containing verilog files for rocket cpu (for use with LiteX).
      Verilog
      •
      Other
      •8•0•0•0•Updated Jun 5, 2024Jun 5, 2024

    • magic-8.2

      Public
      Magic VLSI Layout Tool
      C
      •3•21•0•0•Updated Oct 10, 2019Oct 10, 2019

    • qtflow

      Public
      Free open source EDA tools
      C++
      •
      GNU Lesser General Public License v3.0
      •19•66•1•2•Updated Oct 1, 2019Oct 1, 2019

    • process

      Public
      TeX
      •12•92•0•2•Updated Aug 17, 2019Aug 17, 2019

    • PearlRiver

      Public
      1st Testwafer for LibreSilicon
      TeX
      •9•28•0•0•Updated Aug 2, 2019Aug 2, 2019

    • lsc

      Public
      Libre Silicon Compiler
      Haskell
      •
      GNU General Public License v3.0
      •4•0•0•0•Updated Jun 12, 2019Jun 12, 2019

    • libresilicon.github.io

      Public
      The project page for #LibreSilicon
      HTML
      •
      MIT License
      •2•0•0•0•Updated Jun 2, 2019Jun 2, 2019

    • Keysight

      Public
      Python
      •0•0•0•0•Updated May 31, 2019May 31, 2019

    • CMOS-555

      Public
      LibreSilicon 1 um Technology clone of the well-known CMOS "triple-5"
      Makefile
      •2•3•0•0•Updated May 28, 2019May 28, 2019

    • libresilicontalk

      Public
      TeX
      •1•4•0•0•Updated Dec 27, 2018Dec 27, 2018

    • QtProcessPlanner

      Public
      The QtProcessPlanner suppsed to be used on tablets in clean rooms
      androidtabletcleanroom
      androidtabletcleanroom
      QML
      •0•0•0•0•Updated Dec 6, 2018Dec 6, 2018

    • SauMauPing1

      Public
      SauMauPing SoC rev.1
      C
      •1•0•0•0•Updated Jul 18, 2018Jul 18, 2018

    • firviewer

      Public
      A viewer for the FIR format for showing what Chisel spits out
      Scala
      •0•0•0•0•Updated Jul 18, 2018Jul 18, 2018

    • fir2dot

      Public
      A quick and dirty block diagram generator for FIRRTL
      Scala
      •1•0•0•0•Updated Jul 13, 2018Jul 13, 2018

    • fpga-shells

      Public
      Scala
      •65•1•0•0•Updated Jun 27, 2018Jun 27, 2018

    • lefdef_parser

      Public
      lefdef parser implementation
      ANTLR
      •
      GNU General Public License v3.0
      •1•2•1•0•Updated Jun 23, 2018Jun 23, 2018

    • riscv-boom

      Public
      Berkeley Out-of-Order Machine
      Scala
      •
      Other
      •524•1•0•0•Updated Jun 20, 2018Jun 20, 2018

    • sifive-blocks

      Public
      Common RTL blocks used in SiFive's projects
      Scala
      •
      Apache License 2.0
      •81•0•0•0•Updated Jun 13, 2018Jun 13, 2018

    • ansible-coriolis

      Public
      ansible script installing coriolis with all dependencies
      0•0•0•0•Updated May 21, 2018May 21, 2018

    • ansible-qtflow

      Public
      sets up qtflow in a vm
      0•0•0•0•Updated May 21, 2018May 21, 2018

    • alf_parser

      Public
      ALF parser implementation
      ANTLR
      •
      GNU General Public License v3.0
      •5•8•3•0•Updated May 21, 2018May 21, 2018

    • coriolis

      Public
      autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
      C++
      •4•15•0•0•Updated May 21, 2018May 21, 2018

    • hyperram

      Public
      Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
      Verilog
      •22•1•0•0•Updated May 16, 2018May 16, 2018

    • chisel-wishbone

      Public
      WIP (not ready for use)
      Scala
      •2•1•0•0•Updated Dec 1, 2016Dec 1, 2016
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