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QCLINUX: arm64: dts: qcom: lemans and monaco: Rework RTSS Mailbox DT to use syscon and staging overlays #1768

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QCLINUX: arm64: dts: qcom: lemans and monaco: Rework RTSS Mailbox DT to use syscon and staging overlays #1768

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cf357d5
Revert "QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tr…
sargarram7 Sep 5, 2026
d99e8d6
Revert "QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tr…
sargarram7 Sep 5, 2026
e26d1ac
arm64: dts: qcom: lemans: Add IPCC and syscon nodes for RTSS Mailbox
sargarram7 Sep 9, 2026
931186f
arm64: dts: qcom: lemans-staging: Add rtss-mailbox node
sargarram7 Sep 9, 2026
4ecfab3
arm64: dts: qcom: monaco: Add IPCC, syscon, and reserved-memory nodes…
sargarram7 Sep 9, 2026
7543ed2
arm64: dts: qcom: monaco-staging: Add rtss-mailbox node
sargarram7 Sep 9, 2026
8bffa16
dt-bindings: mailbox: Add qcom,rtss-mailbox schema
sargarram7 Sep 9, 2026
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2 changes: 0 additions & 2 deletions arch/arm64/boot/dts/qcom/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -525,7 +525,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtbo

dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo

dtb-$(CONFIG_ARCH_QCOM) += lemans-rtss-mb.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo

monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo
Expand All @@ -539,7 +538,6 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtbo

dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-rtss-mb.dtbo

dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo

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65 changes: 0 additions & 65 deletions arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso
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45 changes: 45 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans-staging.dtso
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Expand Up @@ -7,6 +7,51 @@

/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>

&{/} {

@lumag Dmitry Baryshkov (lumag) Sep 11, 2026

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Add rtss_mailbox device node for Lemans platform, syscon-based, using
ipcc1-ipcc4 and the apss_tcsr_req/apss_tcsr_resp/apss_shared_ipc
syscon nodes.

You are not.

rtss_mailbox: rtss-ipcc-mailbox {
compatible = "qcom,sa8775p-rtss-mailbox", "qcom,rtss-mailbox";
qcom,syscon-tcsr-req = <&tcsr 0x3e02c>;
qcom,syscon-tcsr-resp = <&tcsr 0x3d018>;
qcom,syscon-ipc = <&apss_shared_ipc 0x0>;
mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10>;
interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>;
memory-region = <&sail_mailbox_mem>,
<&sail_ota_mem>;
};
};

&soc {
tgu@4b0e000 {
Expand Down
43 changes: 42 additions & 1 deletion arch/arm64/boot/dts/qcom/lemans.dtsi
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Expand Up @@ -1018,6 +1018,42 @@
#mbox-cells = <2>;
};

ipcc1: mailbox@488000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x00488000 0x0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc2: mailbox@4a1000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a1000 0x0 0x1000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc3: mailbox@4a2000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a2000 0x0 0x1000>;
interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc4: mailbox@4a3000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a3000 0x0 0x1000>;
interrupts = <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

qfprom: efuse@784000 {
compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
reg = <0x0 0x00784000 0x0 0x3000>;
Expand Down Expand Up @@ -4635,7 +4671,7 @@

tcsr: syscon@1fc0000 {
compatible = "qcom,sa8775p-tcsr", "syscon";
reg = <0x0 0x1fc0000 0x0 0x30000>;
reg = <0x0 0x1fc0000 0x0 0x40000>;
};

gpu: gpu@3d00000 {
Expand Down Expand Up @@ -7058,6 +7094,11 @@
redistributor-stride = <0x0 0x20000>;
};

apss_shared_ipc: syscon@17c0000c {
compatible = "qcom,sa8775p-tcsr", "syscon";

@lumag Dmitry Baryshkov (lumag) Sep 11, 2026

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What exactly is behind this address? TCSR is at the other address, so it can't be TCSR.

reg = <0x0 0x17c0000c 0x0 0x4>;
};

watchdog@17c10000 {
compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
Expand Down
65 changes: 0 additions & 65 deletions arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso
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58 changes: 57 additions & 1 deletion arch/arm64/boot/dts/qcom/monaco.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -748,6 +748,21 @@
hwlocks = <&tcsr_mutex 3>;
};

tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
reg = <0x0 0x90c00000 0x0 0x100000>;
no-map;
};

sail_mailbox_mem: sail-ss@90d00000 {
reg = <0x0 0x90d00000 0x0 0x100000>;
no-map;
};

sail_ota_mem: sail-ss@90e00000 {
reg = <0x0 0x90e00000 0x0 0x300000>;
no-map;
};

gunyah_md_mem: gunyah-md-region@91a80000 {
reg = <0x0 0x91a80000 0x0 0x80000>;
no-map;
Expand Down Expand Up @@ -919,6 +934,42 @@
#mbox-cells = <2>;
};

ipcc1: mailbox@488000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x00488000 0x0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc2: mailbox@4a1000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a1000 0x0 0x1000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc3: mailbox@4a2000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a2000 0x0 0x1000>;
interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc4: mailbox@4a3000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a3000 0x0 0x1000>;
interrupts = <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

qfprom: efuse@784000 {
compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
reg = <0x0 0x00784000 0x0 0x2410>;
Expand Down Expand Up @@ -2745,7 +2796,7 @@

tcsr: syscon@1fc0000 {
compatible = "qcom,qcs8300-tcsr", "syscon";
reg = <0x0 0x1fc0000 0x0 0x30000>;
reg = <0x0 0x1fc0000 0x0 0x40000>;
};

remoteproc_adsp: remoteproc@3000000 {
Expand Down Expand Up @@ -7401,6 +7452,11 @@
#address-cells = <0>;
};

apss_shared_ipc: syscon@17c0000c {
compatible = "qcom,qcs8300-tcsr", "syscon";

@lumag Dmitry Baryshkov (lumag) Sep 11, 2026

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Same question. Is it really TCSR?

reg = <0x0 0x17c0000c 0x0 0x4>;
};

watchdog@17c10000 {
compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
Expand Down